2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_mdio.h>
56 #include <linux/of_net.h>
57 #include <linux/regulator/consumer.h>
58 #include <linux/if_vlan.h>
59 #include <linux/pinctrl/consumer.h>
60 #include <linux/prefetch.h>
62 #include <asm/cacheflush.h>
66 static void set_multicast_list(struct net_device *ndev);
67 static void fec_enet_itr_coal_init(struct net_device *ndev);
69 #define DRIVER_NAME "fec"
71 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 static struct platform_device_id fec_devtype[] = {
83 /* keep it for coldfire */
88 .driver_data = FEC_QUIRK_USE_GASKET,
94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
98 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
99 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
101 .name = "mvf600-fec",
102 .driver_data = FEC_QUIRK_ENET_MAC,
104 .name = "imx6sx-fec",
105 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
106 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
107 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
108 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE,
113 MODULE_DEVICE_TABLE(platform, fec_devtype);
116 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
117 IMX27_FEC, /* runs on i.mx27/35/51 */
124 static const struct of_device_id fec_dt_ids[] = {
125 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
126 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
127 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
128 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
129 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
130 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
133 MODULE_DEVICE_TABLE(of, fec_dt_ids);
135 static unsigned char macaddr[ETH_ALEN];
136 module_param_array(macaddr, byte, NULL, 0);
137 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
139 #if defined(CONFIG_M5272)
141 * Some hardware gets it MAC address out of local flash memory.
142 * if this is non-zero then assume it is the address to get MAC from.
144 #if defined(CONFIG_NETtel)
145 #define FEC_FLASHMAC 0xf0006006
146 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
147 #define FEC_FLASHMAC 0xf0006000
148 #elif defined(CONFIG_CANCam)
149 #define FEC_FLASHMAC 0xf0020000
150 #elif defined (CONFIG_M5272C3)
151 #define FEC_FLASHMAC (0xffe04000 + 4)
152 #elif defined(CONFIG_MOD5272)
153 #define FEC_FLASHMAC 0xffc0406b
155 #define FEC_FLASHMAC 0
157 #endif /* CONFIG_M5272 */
159 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
161 #define PKT_MAXBUF_SIZE 1522
162 #define PKT_MINBUF_SIZE 64
163 #define PKT_MAXBLR_SIZE 1536
165 /* FEC receive acceleration */
166 #define FEC_RACC_IPDIS (1 << 1)
167 #define FEC_RACC_PRODIS (1 << 2)
168 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
171 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
172 * size bits. Other FEC hardware does not, so we need to take that into
173 * account when setting it.
175 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
176 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
177 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
179 #define OPT_FRAME_SIZE 0
182 /* FEC MII MMFR bits definition */
183 #define FEC_MMFR_ST (1 << 30)
184 #define FEC_MMFR_OP_READ (2 << 28)
185 #define FEC_MMFR_OP_WRITE (1 << 28)
186 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
187 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
188 #define FEC_MMFR_TA (2 << 16)
189 #define FEC_MMFR_DATA(v) (v & 0xffff)
191 #define FEC_MII_TIMEOUT 30000 /* us */
193 /* Transmitter timeout */
194 #define TX_TIMEOUT (2 * HZ)
196 #define FEC_PAUSE_FLAG_AUTONEG 0x1
197 #define FEC_PAUSE_FLAG_ENABLE 0x2
199 #define COPYBREAK_DEFAULT 256
201 #define TSO_HEADER_SIZE 128
202 /* Max number of allowed TCP segments for software TSO */
203 #define FEC_MAX_TSO_SEGS 100
204 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
206 #define IS_TSO_HEADER(txq, addr) \
207 ((addr >= txq->tso_hdrs_dma) && \
208 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
213 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
214 struct fec_enet_private *fep,
217 struct bufdesc *new_bd = bdp + 1;
218 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
219 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
220 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
221 struct bufdesc_ex *ex_base;
222 struct bufdesc *base;
225 if (bdp >= txq->tx_bd_base) {
226 base = txq->tx_bd_base;
227 ring_size = txq->tx_ring_size;
228 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
230 base = rxq->rx_bd_base;
231 ring_size = rxq->rx_ring_size;
232 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
236 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
237 ex_base : ex_new_bd);
239 return (new_bd >= (base + ring_size)) ?
244 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
245 struct fec_enet_private *fep,
248 struct bufdesc *new_bd = bdp - 1;
249 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
250 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
251 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
252 struct bufdesc_ex *ex_base;
253 struct bufdesc *base;
256 if (bdp >= txq->tx_bd_base) {
257 base = txq->tx_bd_base;
258 ring_size = txq->tx_ring_size;
259 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
261 base = rxq->rx_bd_base;
262 ring_size = rxq->rx_ring_size;
263 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
267 return (struct bufdesc *)((ex_new_bd < ex_base) ?
268 (ex_new_bd + ring_size) : ex_new_bd);
270 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
273 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
274 struct fec_enet_private *fep)
276 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
279 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
280 struct fec_enet_priv_tx_q *txq)
284 entries = ((const char *)txq->dirty_tx -
285 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
287 return entries > 0 ? entries : entries + txq->tx_ring_size;
290 static void swap_buffer(void *bufaddr, int len)
293 unsigned int *buf = bufaddr;
295 for (i = 0; i < len; i += 4, buf++)
299 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
302 unsigned int *src = src_buf;
303 unsigned int *dst = dst_buf;
305 for (i = 0; i < len; i += 4, src++, dst++)
309 static void fec_dump(struct net_device *ndev)
311 struct fec_enet_private *fep = netdev_priv(ndev);
313 struct fec_enet_priv_tx_q *txq;
316 netdev_info(ndev, "TX ring dump\n");
317 pr_info("Nr SC addr len SKB\n");
319 txq = fep->tx_queue[0];
320 bdp = txq->tx_bd_base;
323 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
325 bdp == txq->cur_tx ? 'S' : ' ',
326 bdp == txq->dirty_tx ? 'H' : ' ',
327 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
328 txq->tx_skbuff[index]);
329 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
331 } while (bdp != txq->tx_bd_base);
334 static inline bool is_ipv4_pkt(struct sk_buff *skb)
336 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
340 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
342 /* Only run for packets requiring a checksum. */
343 if (skb->ip_summed != CHECKSUM_PARTIAL)
346 if (unlikely(skb_cow_head(skb, 0)))
349 if (is_ipv4_pkt(skb))
350 ip_hdr(skb)->check = 0;
351 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
357 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
359 struct net_device *ndev)
361 struct fec_enet_private *fep = netdev_priv(ndev);
362 struct bufdesc *bdp = txq->cur_tx;
363 struct bufdesc_ex *ebdp;
364 int nr_frags = skb_shinfo(skb)->nr_frags;
365 unsigned short queue = skb_get_queue_mapping(skb);
367 unsigned short status;
368 unsigned int estatus = 0;
369 skb_frag_t *this_frag;
375 for (frag = 0; frag < nr_frags; frag++) {
376 this_frag = &skb_shinfo(skb)->frags[frag];
377 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
378 ebdp = (struct bufdesc_ex *)bdp;
380 status = bdp->cbd_sc;
381 status &= ~BD_ENET_TX_STATS;
382 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
383 frag_len = skb_shinfo(skb)->frags[frag].size;
385 /* Handle the last BD specially */
386 if (frag == nr_frags - 1) {
387 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
388 if (fep->bufdesc_ex) {
389 estatus |= BD_ENET_TX_INT;
390 if (unlikely(skb_shinfo(skb)->tx_flags &
391 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
392 estatus |= BD_ENET_TX_TS;
396 if (fep->bufdesc_ex) {
397 if (fep->quirks & FEC_QUIRK_HAS_AVB)
398 estatus |= FEC_TX_BD_FTYPE(queue);
399 if (skb->ip_summed == CHECKSUM_PARTIAL)
400 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
402 ebdp->cbd_esc = estatus;
405 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
407 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
408 if (((unsigned long) bufaddr) & fep->tx_align ||
409 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
410 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
411 bufaddr = txq->tx_bounce[index];
413 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
414 swap_buffer(bufaddr, frag_len);
417 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
419 if (dma_mapping_error(&fep->pdev->dev, addr)) {
420 dev_kfree_skb_any(skb);
422 netdev_err(ndev, "Tx DMA memory map failed\n");
423 goto dma_mapping_error;
426 bdp->cbd_bufaddr = addr;
427 bdp->cbd_datlen = frag_len;
428 bdp->cbd_sc = status;
437 for (i = 0; i < frag; i++) {
438 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
439 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
440 bdp->cbd_datlen, DMA_TO_DEVICE);
445 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
446 struct sk_buff *skb, struct net_device *ndev)
448 struct fec_enet_private *fep = netdev_priv(ndev);
449 int nr_frags = skb_shinfo(skb)->nr_frags;
450 struct bufdesc *bdp, *last_bdp;
453 unsigned short status;
454 unsigned short buflen;
455 unsigned short queue;
456 unsigned int estatus = 0;
461 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
462 if (entries_free < MAX_SKB_FRAGS + 1) {
463 dev_kfree_skb_any(skb);
465 netdev_err(ndev, "NOT enough BD for SG!\n");
469 /* Protocol checksum off-load for TCP and UDP. */
470 if (fec_enet_clear_csum(skb, ndev)) {
471 dev_kfree_skb_any(skb);
475 /* Fill in a Tx ring entry */
477 status = bdp->cbd_sc;
478 status &= ~BD_ENET_TX_STATS;
480 /* Set buffer length and buffer pointer */
482 buflen = skb_headlen(skb);
484 queue = skb_get_queue_mapping(skb);
485 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
486 if (((unsigned long) bufaddr) & fep->tx_align ||
487 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
488 memcpy(txq->tx_bounce[index], skb->data, buflen);
489 bufaddr = txq->tx_bounce[index];
491 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
492 swap_buffer(bufaddr, buflen);
495 /* Push the data cache so the CPM does not get stale memory data. */
496 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
497 if (dma_mapping_error(&fep->pdev->dev, addr)) {
498 dev_kfree_skb_any(skb);
500 netdev_err(ndev, "Tx DMA memory map failed\n");
505 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
509 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
510 if (fep->bufdesc_ex) {
511 estatus = BD_ENET_TX_INT;
512 if (unlikely(skb_shinfo(skb)->tx_flags &
513 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
514 estatus |= BD_ENET_TX_TS;
518 if (fep->bufdesc_ex) {
520 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
522 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
524 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
526 if (fep->quirks & FEC_QUIRK_HAS_AVB)
527 estatus |= FEC_TX_BD_FTYPE(queue);
529 if (skb->ip_summed == CHECKSUM_PARTIAL)
530 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
533 ebdp->cbd_esc = estatus;
536 last_bdp = txq->cur_tx;
537 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
538 /* Save skb pointer */
539 txq->tx_skbuff[index] = skb;
541 bdp->cbd_datlen = buflen;
542 bdp->cbd_bufaddr = addr;
544 /* Send it on its way. Tell FEC it's ready, interrupt when done,
545 * it's the last BD of the frame, and to put the CRC on the end.
547 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
548 bdp->cbd_sc = status;
550 /* If this was the last BD in the ring, start at the beginning again. */
551 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
553 skb_tx_timestamp(skb);
557 /* Trigger transmission start */
558 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
564 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
565 struct net_device *ndev,
566 struct bufdesc *bdp, int index, char *data,
567 int size, bool last_tcp, bool is_last)
569 struct fec_enet_private *fep = netdev_priv(ndev);
570 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
571 unsigned short queue = skb_get_queue_mapping(skb);
572 unsigned short status;
573 unsigned int estatus = 0;
576 status = bdp->cbd_sc;
577 status &= ~BD_ENET_TX_STATS;
579 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
581 if (((unsigned long) data) & fep->tx_align ||
582 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
583 memcpy(txq->tx_bounce[index], data, size);
584 data = txq->tx_bounce[index];
586 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
587 swap_buffer(data, size);
590 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
591 if (dma_mapping_error(&fep->pdev->dev, addr)) {
592 dev_kfree_skb_any(skb);
594 netdev_err(ndev, "Tx DMA memory map failed\n");
595 return NETDEV_TX_BUSY;
598 bdp->cbd_datlen = size;
599 bdp->cbd_bufaddr = addr;
601 if (fep->bufdesc_ex) {
602 if (fep->quirks & FEC_QUIRK_HAS_AVB)
603 estatus |= FEC_TX_BD_FTYPE(queue);
604 if (skb->ip_summed == CHECKSUM_PARTIAL)
605 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
607 ebdp->cbd_esc = estatus;
610 /* Handle the last BD specially */
612 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
614 status |= BD_ENET_TX_INTR;
616 ebdp->cbd_esc |= BD_ENET_TX_INT;
619 bdp->cbd_sc = status;
625 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
626 struct sk_buff *skb, struct net_device *ndev,
627 struct bufdesc *bdp, int index)
629 struct fec_enet_private *fep = netdev_priv(ndev);
630 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
631 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
632 unsigned short queue = skb_get_queue_mapping(skb);
634 unsigned long dmabuf;
635 unsigned short status;
636 unsigned int estatus = 0;
638 status = bdp->cbd_sc;
639 status &= ~BD_ENET_TX_STATS;
640 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
642 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
643 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
644 if (((unsigned long)bufaddr) & fep->tx_align ||
645 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
646 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
647 bufaddr = txq->tx_bounce[index];
649 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
650 swap_buffer(bufaddr, hdr_len);
652 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
653 hdr_len, DMA_TO_DEVICE);
654 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
655 dev_kfree_skb_any(skb);
657 netdev_err(ndev, "Tx DMA memory map failed\n");
658 return NETDEV_TX_BUSY;
662 bdp->cbd_bufaddr = dmabuf;
663 bdp->cbd_datlen = hdr_len;
665 if (fep->bufdesc_ex) {
666 if (fep->quirks & FEC_QUIRK_HAS_AVB)
667 estatus |= FEC_TX_BD_FTYPE(queue);
668 if (skb->ip_summed == CHECKSUM_PARTIAL)
669 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
671 ebdp->cbd_esc = estatus;
674 bdp->cbd_sc = status;
679 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
681 struct net_device *ndev)
683 struct fec_enet_private *fep = netdev_priv(ndev);
684 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
685 int total_len, data_left;
686 struct bufdesc *bdp = txq->cur_tx;
687 unsigned short queue = skb_get_queue_mapping(skb);
689 unsigned int index = 0;
692 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
693 dev_kfree_skb_any(skb);
695 netdev_err(ndev, "NOT enough BD for TSO!\n");
699 /* Protocol checksum off-load for TCP and UDP. */
700 if (fec_enet_clear_csum(skb, ndev)) {
701 dev_kfree_skb_any(skb);
705 /* Initialize the TSO handler, and prepare the first payload */
706 tso_start(skb, &tso);
708 total_len = skb->len - hdr_len;
709 while (total_len > 0) {
712 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
713 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
714 total_len -= data_left;
716 /* prepare packet headers: MAC + IP + TCP */
717 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
718 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
719 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
723 while (data_left > 0) {
726 size = min_t(int, tso.size, data_left);
727 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
728 index = fec_enet_get_bd_index(txq->tx_bd_base,
730 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
739 tso_build_data(skb, &tso, size);
742 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
745 /* Save skb pointer */
746 txq->tx_skbuff[index] = skb;
748 skb_tx_timestamp(skb);
751 /* Trigger transmission start */
752 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
753 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
754 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
755 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
756 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
757 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
762 /* TODO: Release all used data descriptors for TSO */
767 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
769 struct fec_enet_private *fep = netdev_priv(ndev);
771 unsigned short queue;
772 struct fec_enet_priv_tx_q *txq;
773 struct netdev_queue *nq;
776 queue = skb_get_queue_mapping(skb);
777 txq = fep->tx_queue[queue];
778 nq = netdev_get_tx_queue(ndev, queue);
781 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
783 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
787 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
788 if (entries_free <= txq->tx_stop_threshold)
789 netif_tx_stop_queue(nq);
794 /* Init RX & TX buffer descriptors
796 static void fec_enet_bd_init(struct net_device *dev)
798 struct fec_enet_private *fep = netdev_priv(dev);
799 struct fec_enet_priv_tx_q *txq;
800 struct fec_enet_priv_rx_q *rxq;
805 for (q = 0; q < fep->num_rx_queues; q++) {
806 /* Initialize the receive buffer descriptors. */
807 rxq = fep->rx_queue[q];
808 bdp = rxq->rx_bd_base;
810 for (i = 0; i < rxq->rx_ring_size; i++) {
812 /* Initialize the BD for every fragment in the page. */
813 if (bdp->cbd_bufaddr)
814 bdp->cbd_sc = BD_ENET_RX_EMPTY;
817 bdp = fec_enet_get_nextdesc(bdp, fep, q);
820 /* Set the last buffer to wrap */
821 bdp = fec_enet_get_prevdesc(bdp, fep, q);
822 bdp->cbd_sc |= BD_SC_WRAP;
824 rxq->cur_rx = rxq->rx_bd_base;
827 for (q = 0; q < fep->num_tx_queues; q++) {
828 /* ...and the same for transmit */
829 txq = fep->tx_queue[q];
830 bdp = txq->tx_bd_base;
833 for (i = 0; i < txq->tx_ring_size; i++) {
834 /* Initialize the BD for every fragment in the page. */
836 if (txq->tx_skbuff[i]) {
837 dev_kfree_skb_any(txq->tx_skbuff[i]);
838 txq->tx_skbuff[i] = NULL;
840 bdp->cbd_bufaddr = 0;
841 bdp = fec_enet_get_nextdesc(bdp, fep, q);
844 /* Set the last buffer to wrap */
845 bdp = fec_enet_get_prevdesc(bdp, fep, q);
846 bdp->cbd_sc |= BD_SC_WRAP;
851 static void fec_enet_active_rxring(struct net_device *ndev)
853 struct fec_enet_private *fep = netdev_priv(ndev);
856 for (i = 0; i < fep->num_rx_queues; i++)
857 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
860 static void fec_enet_enable_ring(struct net_device *ndev)
862 struct fec_enet_private *fep = netdev_priv(ndev);
863 struct fec_enet_priv_tx_q *txq;
864 struct fec_enet_priv_rx_q *rxq;
867 for (i = 0; i < fep->num_rx_queues; i++) {
868 rxq = fep->rx_queue[i];
869 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
870 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
874 writel(RCMR_MATCHEN | RCMR_CMP(i),
875 fep->hwp + FEC_RCMR(i));
878 for (i = 0; i < fep->num_tx_queues; i++) {
879 txq = fep->tx_queue[i];
880 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
884 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
885 fep->hwp + FEC_DMA_CFG(i));
889 static void fec_enet_reset_skb(struct net_device *ndev)
891 struct fec_enet_private *fep = netdev_priv(ndev);
892 struct fec_enet_priv_tx_q *txq;
895 for (i = 0; i < fep->num_tx_queues; i++) {
896 txq = fep->tx_queue[i];
898 for (j = 0; j < txq->tx_ring_size; j++) {
899 if (txq->tx_skbuff[j]) {
900 dev_kfree_skb_any(txq->tx_skbuff[j]);
901 txq->tx_skbuff[j] = NULL;
908 * This function is called to start or restart the FEC during a link
909 * change, transmit timeout, or to reconfigure the FEC. The network
910 * packet processing for this device must be stopped before this call.
913 fec_restart(struct net_device *ndev)
915 struct fec_enet_private *fep = netdev_priv(ndev);
918 u32 rcntl = OPT_FRAME_SIZE | 0x04;
919 u32 ecntl = 0x2; /* ETHEREN */
921 /* Whack a reset. We should wait for this.
922 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
923 * instead of reset MAC itself.
925 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
926 writel(0, fep->hwp + FEC_ECNTRL);
928 writel(1, fep->hwp + FEC_ECNTRL);
933 * enet-mac reset will reset mac address registers too,
934 * so need to reconfigure it.
936 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
937 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
938 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
939 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
942 /* Clear any outstanding interrupt. */
943 writel(0xffc00000, fep->hwp + FEC_IEVENT);
945 fec_enet_bd_init(ndev);
947 fec_enet_enable_ring(ndev);
949 /* Reset tx SKB buffers. */
950 fec_enet_reset_skb(ndev);
952 /* Enable MII mode */
953 if (fep->full_duplex == DUPLEX_FULL) {
955 writel(0x04, fep->hwp + FEC_X_CNTRL);
959 writel(0x0, fep->hwp + FEC_X_CNTRL);
963 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
965 #if !defined(CONFIG_M5272)
966 /* set RX checksum */
967 val = readl(fep->hwp + FEC_RACC);
968 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
969 val |= FEC_RACC_OPTIONS;
971 val &= ~FEC_RACC_OPTIONS;
972 writel(val, fep->hwp + FEC_RACC);
976 * The phy interface and speed need to get configured
977 * differently on enet-mac.
979 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
980 /* Enable flow control and length check */
981 rcntl |= 0x40000000 | 0x00000020;
983 /* RGMII, RMII or MII */
984 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
986 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
991 /* 1G, 100M or 10M */
993 if (fep->phy_dev->speed == SPEED_1000)
995 else if (fep->phy_dev->speed == SPEED_100)
1001 #ifdef FEC_MIIGSK_ENR
1002 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1004 /* disable the gasket and wait */
1005 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1006 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1010 * configure the gasket:
1011 * RMII, 50 MHz, no loopback, no echo
1012 * MII, 25 MHz, no loopback, no echo
1014 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1015 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1016 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1017 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1018 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1020 /* re-enable the gasket */
1021 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1026 #if !defined(CONFIG_M5272)
1027 /* enable pause frame*/
1028 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1029 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1030 fep->phy_dev && fep->phy_dev->pause)) {
1031 rcntl |= FEC_ENET_FCE;
1033 /* set FIFO threshold parameter to reduce overrun */
1034 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1035 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1036 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1037 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1040 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1042 rcntl &= ~FEC_ENET_FCE;
1044 #endif /* !defined(CONFIG_M5272) */
1046 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1048 /* Setup multicast filter. */
1049 set_multicast_list(ndev);
1050 #ifndef CONFIG_M5272
1051 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1052 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1055 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1056 /* enable ENET endian swap */
1058 /* enable ENET store and forward mode */
1059 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1062 if (fep->bufdesc_ex)
1065 #ifndef CONFIG_M5272
1066 /* Enable the MIB statistic event counters */
1067 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1070 /* And last, enable the transmit and receive processing */
1071 writel(ecntl, fep->hwp + FEC_ECNTRL);
1072 fec_enet_active_rxring(ndev);
1074 if (fep->bufdesc_ex)
1075 fec_ptp_start_cyclecounter(ndev);
1077 /* Enable interrupts we wish to service */
1078 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1080 /* Init the interrupt coalescing */
1081 fec_enet_itr_coal_init(ndev);
1086 fec_stop(struct net_device *ndev)
1088 struct fec_enet_private *fep = netdev_priv(ndev);
1089 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1091 /* We cannot expect a graceful transmit stop without link !!! */
1093 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1095 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1096 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1099 /* Whack a reset. We should wait for this.
1100 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1101 * instead of reset MAC itself.
1103 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1104 writel(0, fep->hwp + FEC_ECNTRL);
1106 writel(1, fep->hwp + FEC_ECNTRL);
1109 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1110 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1112 /* We have to keep ENET enabled to have MII interrupt stay working */
1113 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1114 writel(2, fep->hwp + FEC_ECNTRL);
1115 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1121 fec_timeout(struct net_device *ndev)
1123 struct fec_enet_private *fep = netdev_priv(ndev);
1127 ndev->stats.tx_errors++;
1129 schedule_work(&fep->tx_timeout_work);
1132 static void fec_enet_timeout_work(struct work_struct *work)
1134 struct fec_enet_private *fep =
1135 container_of(work, struct fec_enet_private, tx_timeout_work);
1136 struct net_device *ndev = fep->netdev;
1139 if (netif_device_present(ndev) || netif_running(ndev)) {
1140 napi_disable(&fep->napi);
1141 netif_tx_lock_bh(ndev);
1143 netif_wake_queue(ndev);
1144 netif_tx_unlock_bh(ndev);
1145 napi_enable(&fep->napi);
1151 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1152 struct skb_shared_hwtstamps *hwtstamps)
1154 unsigned long flags;
1157 spin_lock_irqsave(&fep->tmreg_lock, flags);
1158 ns = timecounter_cyc2time(&fep->tc, ts);
1159 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1161 memset(hwtstamps, 0, sizeof(*hwtstamps));
1162 hwtstamps->hwtstamp = ns_to_ktime(ns);
1166 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1168 struct fec_enet_private *fep;
1169 struct bufdesc *bdp;
1170 unsigned short status;
1171 struct sk_buff *skb;
1172 struct fec_enet_priv_tx_q *txq;
1173 struct netdev_queue *nq;
1177 fep = netdev_priv(ndev);
1179 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1181 txq = fep->tx_queue[queue_id];
1182 /* get next bdp of dirty_tx */
1183 nq = netdev_get_tx_queue(ndev, queue_id);
1184 bdp = txq->dirty_tx;
1186 /* get next bdp of dirty_tx */
1187 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1189 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1191 /* current queue is empty */
1192 if (bdp == txq->cur_tx)
1195 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1197 skb = txq->tx_skbuff[index];
1198 txq->tx_skbuff[index] = NULL;
1199 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1200 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1201 bdp->cbd_datlen, DMA_TO_DEVICE);
1202 bdp->cbd_bufaddr = 0;
1204 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1208 /* Check for errors. */
1209 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1210 BD_ENET_TX_RL | BD_ENET_TX_UN |
1212 ndev->stats.tx_errors++;
1213 if (status & BD_ENET_TX_HB) /* No heartbeat */
1214 ndev->stats.tx_heartbeat_errors++;
1215 if (status & BD_ENET_TX_LC) /* Late collision */
1216 ndev->stats.tx_window_errors++;
1217 if (status & BD_ENET_TX_RL) /* Retrans limit */
1218 ndev->stats.tx_aborted_errors++;
1219 if (status & BD_ENET_TX_UN) /* Underrun */
1220 ndev->stats.tx_fifo_errors++;
1221 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1222 ndev->stats.tx_carrier_errors++;
1224 ndev->stats.tx_packets++;
1225 ndev->stats.tx_bytes += skb->len;
1228 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1230 struct skb_shared_hwtstamps shhwtstamps;
1231 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1233 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
1234 skb_tstamp_tx(skb, &shhwtstamps);
1237 /* Deferred means some collisions occurred during transmit,
1238 * but we eventually sent the packet OK.
1240 if (status & BD_ENET_TX_DEF)
1241 ndev->stats.collisions++;
1243 /* Free the sk buffer associated with this last transmit */
1244 dev_kfree_skb_any(skb);
1246 txq->dirty_tx = bdp;
1248 /* Update pointer to next buffer descriptor to be transmitted */
1249 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1251 /* Since we have freed up a buffer, the ring is no longer full
1253 if (netif_queue_stopped(ndev)) {
1254 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1255 if (entries_free >= txq->tx_wake_threshold)
1256 netif_tx_wake_queue(nq);
1260 /* ERR006538: Keep the transmitter going */
1261 if (bdp != txq->cur_tx &&
1262 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1263 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1267 fec_enet_tx(struct net_device *ndev)
1269 struct fec_enet_private *fep = netdev_priv(ndev);
1271 /* First process class A queue, then Class B and Best Effort queue */
1272 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1273 clear_bit(queue_id, &fep->work_tx);
1274 fec_enet_tx_queue(ndev, queue_id);
1280 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1282 struct fec_enet_private *fep = netdev_priv(ndev);
1285 off = ((unsigned long)skb->data) & fep->rx_align;
1287 skb_reserve(skb, fep->rx_align + 1 - off);
1289 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1290 FEC_ENET_RX_FRSIZE - fep->rx_align,
1292 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1293 if (net_ratelimit())
1294 netdev_err(ndev, "Rx DMA memory map failed\n");
1301 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1302 struct bufdesc *bdp, u32 length, bool swap)
1304 struct fec_enet_private *fep = netdev_priv(ndev);
1305 struct sk_buff *new_skb;
1307 if (length > fep->rx_copybreak)
1310 new_skb = netdev_alloc_skb(ndev, length);
1314 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1315 FEC_ENET_RX_FRSIZE - fep->rx_align,
1318 memcpy(new_skb->data, (*skb)->data, length);
1320 swap_buffer2(new_skb->data, (*skb)->data, length);
1326 /* During a receive, the cur_rx points to the current incoming buffer.
1327 * When we update through the ring, if the next incoming buffer has
1328 * not been given to the system, we just set the empty indicator,
1329 * effectively tossing the packet.
1332 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1334 struct fec_enet_private *fep = netdev_priv(ndev);
1335 struct fec_enet_priv_rx_q *rxq;
1336 struct bufdesc *bdp;
1337 unsigned short status;
1338 struct sk_buff *skb_new = NULL;
1339 struct sk_buff *skb;
1342 int pkt_received = 0;
1343 struct bufdesc_ex *ebdp = NULL;
1344 bool vlan_packet_rcvd = false;
1348 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1353 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1354 rxq = fep->rx_queue[queue_id];
1356 /* First, grab all of the stats for the incoming packet.
1357 * These get messed up if we get called due to a busy condition.
1361 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1363 if (pkt_received >= budget)
1367 /* Since we have allocated space to hold a complete frame,
1368 * the last indicator should be set.
1370 if ((status & BD_ENET_RX_LAST) == 0)
1371 netdev_err(ndev, "rcv is not +last\n");
1374 /* Check for errors. */
1375 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1376 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1377 ndev->stats.rx_errors++;
1378 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1379 /* Frame too long or too short. */
1380 ndev->stats.rx_length_errors++;
1382 if (status & BD_ENET_RX_NO) /* Frame alignment */
1383 ndev->stats.rx_frame_errors++;
1384 if (status & BD_ENET_RX_CR) /* CRC Error */
1385 ndev->stats.rx_crc_errors++;
1386 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1387 ndev->stats.rx_fifo_errors++;
1390 /* Report late collisions as a frame error.
1391 * On this error, the BD is closed, but we don't know what we
1392 * have in the buffer. So, just drop this frame on the floor.
1394 if (status & BD_ENET_RX_CL) {
1395 ndev->stats.rx_errors++;
1396 ndev->stats.rx_frame_errors++;
1397 goto rx_processing_done;
1400 /* Process the incoming frame. */
1401 ndev->stats.rx_packets++;
1402 pkt_len = bdp->cbd_datlen;
1403 ndev->stats.rx_bytes += pkt_len;
1405 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1406 skb = rxq->rx_skbuff[index];
1408 /* The packet length includes FCS, but we don't want to
1409 * include that when passing upstream as it messes up
1410 * bridging applications.
1412 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1414 if (!is_copybreak) {
1415 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1416 if (unlikely(!skb_new)) {
1417 ndev->stats.rx_dropped++;
1418 goto rx_processing_done;
1420 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1421 FEC_ENET_RX_FRSIZE - fep->rx_align,
1425 prefetch(skb->data - NET_IP_ALIGN);
1426 skb_put(skb, pkt_len - 4);
1428 if (!is_copybreak && need_swap)
1429 swap_buffer(data, pkt_len);
1431 /* Extract the enhanced buffer descriptor */
1433 if (fep->bufdesc_ex)
1434 ebdp = (struct bufdesc_ex *)bdp;
1436 /* If this is a VLAN packet remove the VLAN Tag */
1437 vlan_packet_rcvd = false;
1438 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1439 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1440 /* Push and remove the vlan tag */
1441 struct vlan_hdr *vlan_header =
1442 (struct vlan_hdr *) (data + ETH_HLEN);
1443 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1445 vlan_packet_rcvd = true;
1447 skb_copy_to_linear_data_offset(skb, VLAN_HLEN,
1448 data, (2 * ETH_ALEN));
1449 skb_pull(skb, VLAN_HLEN);
1452 skb->protocol = eth_type_trans(skb, ndev);
1454 /* Get receive timestamp from the skb */
1455 if (fep->hwts_rx_en && fep->bufdesc_ex)
1456 fec_enet_hwtstamp(fep, ebdp->ts,
1457 skb_hwtstamps(skb));
1459 if (fep->bufdesc_ex &&
1460 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1461 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1462 /* don't check it */
1463 skb->ip_summed = CHECKSUM_UNNECESSARY;
1465 skb_checksum_none_assert(skb);
1469 /* Handle received VLAN packets */
1470 if (vlan_packet_rcvd)
1471 __vlan_hwaccel_put_tag(skb,
1475 napi_gro_receive(&fep->napi, skb);
1478 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1479 FEC_ENET_RX_FRSIZE - fep->rx_align,
1482 rxq->rx_skbuff[index] = skb_new;
1483 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1487 /* Clear the status flags for this buffer */
1488 status &= ~BD_ENET_RX_STATS;
1490 /* Mark the buffer empty */
1491 status |= BD_ENET_RX_EMPTY;
1492 bdp->cbd_sc = status;
1494 if (fep->bufdesc_ex) {
1495 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1497 ebdp->cbd_esc = BD_ENET_RX_INT;
1502 /* Update BD pointer to next entry */
1503 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1505 /* Doing this here will keep the FEC running while we process
1506 * incoming frames. On a heavily loaded network, we should be
1507 * able to keep up at the expense of system resources.
1509 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1512 return pkt_received;
1516 fec_enet_rx(struct net_device *ndev, int budget)
1518 int pkt_received = 0;
1520 struct fec_enet_private *fep = netdev_priv(ndev);
1522 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1523 clear_bit(queue_id, &fep->work_rx);
1524 pkt_received += fec_enet_rx_queue(ndev,
1525 budget - pkt_received, queue_id);
1527 return pkt_received;
1531 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1533 if (int_events == 0)
1536 if (int_events & FEC_ENET_RXF)
1537 fep->work_rx |= (1 << 2);
1538 if (int_events & FEC_ENET_RXF_1)
1539 fep->work_rx |= (1 << 0);
1540 if (int_events & FEC_ENET_RXF_2)
1541 fep->work_rx |= (1 << 1);
1543 if (int_events & FEC_ENET_TXF)
1544 fep->work_tx |= (1 << 2);
1545 if (int_events & FEC_ENET_TXF_1)
1546 fep->work_tx |= (1 << 0);
1547 if (int_events & FEC_ENET_TXF_2)
1548 fep->work_tx |= (1 << 1);
1554 fec_enet_interrupt(int irq, void *dev_id)
1556 struct net_device *ndev = dev_id;
1557 struct fec_enet_private *fep = netdev_priv(ndev);
1558 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
1560 irqreturn_t ret = IRQ_NONE;
1562 int_events = readl(fep->hwp + FEC_IEVENT);
1563 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
1564 fec_enet_collect_events(fep, int_events);
1566 if (int_events & napi_mask) {
1569 /* Disable the NAPI interrupts */
1570 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1571 napi_schedule(&fep->napi);
1574 if (int_events & FEC_ENET_MII) {
1576 complete(&fep->mdio_done);
1580 fec_ptp_check_pps_event(fep);
1585 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1587 struct net_device *ndev = napi->dev;
1588 struct fec_enet_private *fep = netdev_priv(ndev);
1592 * Clear any pending transmit or receive interrupts before
1593 * processing the rings to avoid racing with the hardware.
1595 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1597 pkts = fec_enet_rx(ndev, budget);
1601 if (pkts < budget) {
1602 napi_complete(napi);
1603 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1608 /* ------------------------------------------------------------------------- */
1609 static void fec_get_mac(struct net_device *ndev)
1611 struct fec_enet_private *fep = netdev_priv(ndev);
1612 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1613 unsigned char *iap, tmpaddr[ETH_ALEN];
1616 * try to get mac address in following order:
1618 * 1) module parameter via kernel command line in form
1619 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1624 * 2) from device tree data
1626 if (!is_valid_ether_addr(iap)) {
1627 struct device_node *np = fep->pdev->dev.of_node;
1629 const char *mac = of_get_mac_address(np);
1631 iap = (unsigned char *) mac;
1636 * 3) from flash or fuse (via platform data)
1638 if (!is_valid_ether_addr(iap)) {
1641 iap = (unsigned char *)FEC_FLASHMAC;
1644 iap = (unsigned char *)&pdata->mac;
1649 * 4) FEC mac registers set by bootloader
1651 if (!is_valid_ether_addr(iap)) {
1652 *((__be32 *) &tmpaddr[0]) =
1653 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1654 *((__be16 *) &tmpaddr[4]) =
1655 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1660 * 5) random mac address
1662 if (!is_valid_ether_addr(iap)) {
1663 /* Report it and use a random ethernet address instead */
1664 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1665 eth_hw_addr_random(ndev);
1666 netdev_info(ndev, "Using random MAC address: %pM\n",
1671 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1673 /* Adjust MAC if using macaddr */
1675 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1678 /* ------------------------------------------------------------------------- */
1683 static void fec_enet_adjust_link(struct net_device *ndev)
1685 struct fec_enet_private *fep = netdev_priv(ndev);
1686 struct phy_device *phy_dev = fep->phy_dev;
1687 int status_change = 0;
1689 /* Prevent a state halted on mii error */
1690 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1691 phy_dev->state = PHY_RESUMING;
1696 * If the netdev is down, or is going down, we're not interested
1697 * in link state events, so just mark our idea of the link as down
1698 * and ignore the event.
1700 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1702 } else if (phy_dev->link) {
1704 fep->link = phy_dev->link;
1708 if (fep->full_duplex != phy_dev->duplex) {
1709 fep->full_duplex = phy_dev->duplex;
1713 if (phy_dev->speed != fep->speed) {
1714 fep->speed = phy_dev->speed;
1718 /* if any of the above changed restart the FEC */
1719 if (status_change) {
1720 napi_disable(&fep->napi);
1721 netif_tx_lock_bh(ndev);
1723 netif_wake_queue(ndev);
1724 netif_tx_unlock_bh(ndev);
1725 napi_enable(&fep->napi);
1729 napi_disable(&fep->napi);
1730 netif_tx_lock_bh(ndev);
1732 netif_tx_unlock_bh(ndev);
1733 napi_enable(&fep->napi);
1734 fep->link = phy_dev->link;
1740 phy_print_status(phy_dev);
1743 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1745 struct fec_enet_private *fep = bus->priv;
1746 unsigned long time_left;
1748 fep->mii_timeout = 0;
1749 init_completion(&fep->mdio_done);
1751 /* start a read op */
1752 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1753 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1754 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1756 /* wait for end of transfer */
1757 time_left = wait_for_completion_timeout(&fep->mdio_done,
1758 usecs_to_jiffies(FEC_MII_TIMEOUT));
1759 if (time_left == 0) {
1760 fep->mii_timeout = 1;
1761 netdev_err(fep->netdev, "MDIO read timeout\n");
1766 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1769 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1772 struct fec_enet_private *fep = bus->priv;
1773 unsigned long time_left;
1775 fep->mii_timeout = 0;
1776 init_completion(&fep->mdio_done);
1778 /* start a write op */
1779 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1780 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1781 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1782 fep->hwp + FEC_MII_DATA);
1784 /* wait for end of transfer */
1785 time_left = wait_for_completion_timeout(&fep->mdio_done,
1786 usecs_to_jiffies(FEC_MII_TIMEOUT));
1787 if (time_left == 0) {
1788 fep->mii_timeout = 1;
1789 netdev_err(fep->netdev, "MDIO write timeout\n");
1796 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1798 struct fec_enet_private *fep = netdev_priv(ndev);
1802 ret = clk_prepare_enable(fep->clk_ahb);
1805 ret = clk_prepare_enable(fep->clk_ipg);
1807 goto failed_clk_ipg;
1808 if (fep->clk_enet_out) {
1809 ret = clk_prepare_enable(fep->clk_enet_out);
1811 goto failed_clk_enet_out;
1814 mutex_lock(&fep->ptp_clk_mutex);
1815 ret = clk_prepare_enable(fep->clk_ptp);
1817 mutex_unlock(&fep->ptp_clk_mutex);
1818 goto failed_clk_ptp;
1820 fep->ptp_clk_on = true;
1822 mutex_unlock(&fep->ptp_clk_mutex);
1825 ret = clk_prepare_enable(fep->clk_ref);
1827 goto failed_clk_ref;
1830 clk_disable_unprepare(fep->clk_ahb);
1831 clk_disable_unprepare(fep->clk_ipg);
1832 if (fep->clk_enet_out)
1833 clk_disable_unprepare(fep->clk_enet_out);
1835 mutex_lock(&fep->ptp_clk_mutex);
1836 clk_disable_unprepare(fep->clk_ptp);
1837 fep->ptp_clk_on = false;
1838 mutex_unlock(&fep->ptp_clk_mutex);
1841 clk_disable_unprepare(fep->clk_ref);
1848 clk_disable_unprepare(fep->clk_ref);
1850 if (fep->clk_enet_out)
1851 clk_disable_unprepare(fep->clk_enet_out);
1852 failed_clk_enet_out:
1853 clk_disable_unprepare(fep->clk_ipg);
1855 clk_disable_unprepare(fep->clk_ahb);
1860 static int fec_enet_mii_probe(struct net_device *ndev)
1862 struct fec_enet_private *fep = netdev_priv(ndev);
1863 struct phy_device *phy_dev = NULL;
1864 char mdio_bus_id[MII_BUS_ID_SIZE];
1865 char phy_name[MII_BUS_ID_SIZE + 3];
1867 int dev_id = fep->dev_id;
1869 fep->phy_dev = NULL;
1871 if (fep->phy_node) {
1872 phy_dev = of_phy_connect(ndev, fep->phy_node,
1873 &fec_enet_adjust_link, 0,
1874 fep->phy_interface);
1876 /* check for attached phy */
1877 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1878 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1880 if (fep->mii_bus->phy_map[phy_id] == NULL)
1882 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1886 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1890 if (phy_id >= PHY_MAX_ADDR) {
1891 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1892 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1896 snprintf(phy_name, sizeof(phy_name),
1897 PHY_ID_FMT, mdio_bus_id, phy_id);
1898 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1899 fep->phy_interface);
1902 if (IS_ERR(phy_dev)) {
1903 netdev_err(ndev, "could not attach to PHY\n");
1904 return PTR_ERR(phy_dev);
1907 /* mask with MAC supported features */
1908 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1909 phy_dev->supported &= PHY_GBIT_FEATURES;
1910 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1911 #if !defined(CONFIG_M5272)
1912 phy_dev->supported |= SUPPORTED_Pause;
1916 phy_dev->supported &= PHY_BASIC_FEATURES;
1918 phy_dev->advertising = phy_dev->supported;
1920 fep->phy_dev = phy_dev;
1922 fep->full_duplex = 0;
1924 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1925 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1931 static int fec_enet_mii_init(struct platform_device *pdev)
1933 static struct mii_bus *fec0_mii_bus;
1934 struct net_device *ndev = platform_get_drvdata(pdev);
1935 struct fec_enet_private *fep = netdev_priv(ndev);
1936 struct device_node *node;
1937 int err = -ENXIO, i;
1940 * The dual fec interfaces are not equivalent with enet-mac.
1941 * Here are the differences:
1943 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1944 * - fec0 acts as the 1588 time master while fec1 is slave
1945 * - external phys can only be configured by fec0
1947 * That is to say fec1 can not work independently. It only works
1948 * when fec0 is working. The reason behind this design is that the
1949 * second interface is added primarily for Switch mode.
1951 * Because of the last point above, both phys are attached on fec0
1952 * mdio interface in board design, and need to be configured by
1955 if ((fep->quirks & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1956 /* fec1 uses fec0 mii_bus */
1957 if (mii_cnt && fec0_mii_bus) {
1958 fep->mii_bus = fec0_mii_bus;
1965 fep->mii_timeout = 0;
1968 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1970 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1971 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1972 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1975 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1976 if (fep->quirks & FEC_QUIRK_ENET_MAC)
1978 fep->phy_speed <<= 1;
1979 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1981 fep->mii_bus = mdiobus_alloc();
1982 if (fep->mii_bus == NULL) {
1987 fep->mii_bus->name = "fec_enet_mii_bus";
1988 fep->mii_bus->read = fec_enet_mdio_read;
1989 fep->mii_bus->write = fec_enet_mdio_write;
1990 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1991 pdev->name, fep->dev_id + 1);
1992 fep->mii_bus->priv = fep;
1993 fep->mii_bus->parent = &pdev->dev;
1995 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1996 if (!fep->mii_bus->irq) {
1998 goto err_out_free_mdiobus;
2001 for (i = 0; i < PHY_MAX_ADDR; i++)
2002 fep->mii_bus->irq[i] = PHY_POLL;
2004 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2006 err = of_mdiobus_register(fep->mii_bus, node);
2009 err = mdiobus_register(fep->mii_bus);
2013 goto err_out_free_mdio_irq;
2017 /* save fec0 mii_bus */
2018 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2019 fec0_mii_bus = fep->mii_bus;
2023 err_out_free_mdio_irq:
2024 kfree(fep->mii_bus->irq);
2025 err_out_free_mdiobus:
2026 mdiobus_free(fep->mii_bus);
2031 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2033 if (--mii_cnt == 0) {
2034 mdiobus_unregister(fep->mii_bus);
2035 kfree(fep->mii_bus->irq);
2036 mdiobus_free(fep->mii_bus);
2040 static int fec_enet_get_settings(struct net_device *ndev,
2041 struct ethtool_cmd *cmd)
2043 struct fec_enet_private *fep = netdev_priv(ndev);
2044 struct phy_device *phydev = fep->phy_dev;
2049 return phy_ethtool_gset(phydev, cmd);
2052 static int fec_enet_set_settings(struct net_device *ndev,
2053 struct ethtool_cmd *cmd)
2055 struct fec_enet_private *fep = netdev_priv(ndev);
2056 struct phy_device *phydev = fep->phy_dev;
2061 return phy_ethtool_sset(phydev, cmd);
2064 static void fec_enet_get_drvinfo(struct net_device *ndev,
2065 struct ethtool_drvinfo *info)
2067 struct fec_enet_private *fep = netdev_priv(ndev);
2069 strlcpy(info->driver, fep->pdev->dev.driver->name,
2070 sizeof(info->driver));
2071 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2072 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2075 static int fec_enet_get_ts_info(struct net_device *ndev,
2076 struct ethtool_ts_info *info)
2078 struct fec_enet_private *fep = netdev_priv(ndev);
2080 if (fep->bufdesc_ex) {
2082 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2083 SOF_TIMESTAMPING_RX_SOFTWARE |
2084 SOF_TIMESTAMPING_SOFTWARE |
2085 SOF_TIMESTAMPING_TX_HARDWARE |
2086 SOF_TIMESTAMPING_RX_HARDWARE |
2087 SOF_TIMESTAMPING_RAW_HARDWARE;
2089 info->phc_index = ptp_clock_index(fep->ptp_clock);
2091 info->phc_index = -1;
2093 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2094 (1 << HWTSTAMP_TX_ON);
2096 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2097 (1 << HWTSTAMP_FILTER_ALL);
2100 return ethtool_op_get_ts_info(ndev, info);
2104 #if !defined(CONFIG_M5272)
2106 static void fec_enet_get_pauseparam(struct net_device *ndev,
2107 struct ethtool_pauseparam *pause)
2109 struct fec_enet_private *fep = netdev_priv(ndev);
2111 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2112 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2113 pause->rx_pause = pause->tx_pause;
2116 static int fec_enet_set_pauseparam(struct net_device *ndev,
2117 struct ethtool_pauseparam *pause)
2119 struct fec_enet_private *fep = netdev_priv(ndev);
2124 if (pause->tx_pause != pause->rx_pause) {
2126 "hardware only support enable/disable both tx and rx");
2130 fep->pause_flag = 0;
2132 /* tx pause must be same as rx pause */
2133 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2134 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2136 if (pause->rx_pause || pause->autoneg) {
2137 fep->phy_dev->supported |= ADVERTISED_Pause;
2138 fep->phy_dev->advertising |= ADVERTISED_Pause;
2140 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2141 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2144 if (pause->autoneg) {
2145 if (netif_running(ndev))
2147 phy_start_aneg(fep->phy_dev);
2149 if (netif_running(ndev)) {
2150 napi_disable(&fep->napi);
2151 netif_tx_lock_bh(ndev);
2153 netif_wake_queue(ndev);
2154 netif_tx_unlock_bh(ndev);
2155 napi_enable(&fep->napi);
2161 static const struct fec_stat {
2162 char name[ETH_GSTRING_LEN];
2166 { "tx_dropped", RMON_T_DROP },
2167 { "tx_packets", RMON_T_PACKETS },
2168 { "tx_broadcast", RMON_T_BC_PKT },
2169 { "tx_multicast", RMON_T_MC_PKT },
2170 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2171 { "tx_undersize", RMON_T_UNDERSIZE },
2172 { "tx_oversize", RMON_T_OVERSIZE },
2173 { "tx_fragment", RMON_T_FRAG },
2174 { "tx_jabber", RMON_T_JAB },
2175 { "tx_collision", RMON_T_COL },
2176 { "tx_64byte", RMON_T_P64 },
2177 { "tx_65to127byte", RMON_T_P65TO127 },
2178 { "tx_128to255byte", RMON_T_P128TO255 },
2179 { "tx_256to511byte", RMON_T_P256TO511 },
2180 { "tx_512to1023byte", RMON_T_P512TO1023 },
2181 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2182 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2183 { "tx_octets", RMON_T_OCTETS },
2186 { "IEEE_tx_drop", IEEE_T_DROP },
2187 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2188 { "IEEE_tx_1col", IEEE_T_1COL },
2189 { "IEEE_tx_mcol", IEEE_T_MCOL },
2190 { "IEEE_tx_def", IEEE_T_DEF },
2191 { "IEEE_tx_lcol", IEEE_T_LCOL },
2192 { "IEEE_tx_excol", IEEE_T_EXCOL },
2193 { "IEEE_tx_macerr", IEEE_T_MACERR },
2194 { "IEEE_tx_cserr", IEEE_T_CSERR },
2195 { "IEEE_tx_sqe", IEEE_T_SQE },
2196 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2197 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2200 { "rx_packets", RMON_R_PACKETS },
2201 { "rx_broadcast", RMON_R_BC_PKT },
2202 { "rx_multicast", RMON_R_MC_PKT },
2203 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2204 { "rx_undersize", RMON_R_UNDERSIZE },
2205 { "rx_oversize", RMON_R_OVERSIZE },
2206 { "rx_fragment", RMON_R_FRAG },
2207 { "rx_jabber", RMON_R_JAB },
2208 { "rx_64byte", RMON_R_P64 },
2209 { "rx_65to127byte", RMON_R_P65TO127 },
2210 { "rx_128to255byte", RMON_R_P128TO255 },
2211 { "rx_256to511byte", RMON_R_P256TO511 },
2212 { "rx_512to1023byte", RMON_R_P512TO1023 },
2213 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2214 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2215 { "rx_octets", RMON_R_OCTETS },
2218 { "IEEE_rx_drop", IEEE_R_DROP },
2219 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2220 { "IEEE_rx_crc", IEEE_R_CRC },
2221 { "IEEE_rx_align", IEEE_R_ALIGN },
2222 { "IEEE_rx_macerr", IEEE_R_MACERR },
2223 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2224 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2227 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2228 struct ethtool_stats *stats, u64 *data)
2230 struct fec_enet_private *fep = netdev_priv(dev);
2233 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2234 data[i] = readl(fep->hwp + fec_stats[i].offset);
2237 static void fec_enet_get_strings(struct net_device *netdev,
2238 u32 stringset, u8 *data)
2241 switch (stringset) {
2243 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2244 memcpy(data + i * ETH_GSTRING_LEN,
2245 fec_stats[i].name, ETH_GSTRING_LEN);
2250 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2254 return ARRAY_SIZE(fec_stats);
2259 #endif /* !defined(CONFIG_M5272) */
2261 static int fec_enet_nway_reset(struct net_device *dev)
2263 struct fec_enet_private *fep = netdev_priv(dev);
2264 struct phy_device *phydev = fep->phy_dev;
2269 return genphy_restart_aneg(phydev);
2272 /* ITR clock source is enet system clock (clk_ahb).
2273 * TCTT unit is cycle_ns * 64 cycle
2274 * So, the ICTT value = X us / (cycle_ns * 64)
2276 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2278 struct fec_enet_private *fep = netdev_priv(ndev);
2280 return us * (fep->itr_clk_rate / 64000) / 1000;
2283 /* Set threshold for interrupt coalescing */
2284 static void fec_enet_itr_coal_set(struct net_device *ndev)
2286 struct fec_enet_private *fep = netdev_priv(ndev);
2289 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2292 /* Must be greater than zero to avoid unpredictable behavior */
2293 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2294 !fep->tx_time_itr || !fep->tx_pkts_itr)
2297 /* Select enet system clock as Interrupt Coalescing
2298 * timer Clock Source
2300 rx_itr = FEC_ITR_CLK_SEL;
2301 tx_itr = FEC_ITR_CLK_SEL;
2303 /* set ICFT and ICTT */
2304 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2305 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2306 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2307 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2309 rx_itr |= FEC_ITR_EN;
2310 tx_itr |= FEC_ITR_EN;
2312 writel(tx_itr, fep->hwp + FEC_TXIC0);
2313 writel(rx_itr, fep->hwp + FEC_RXIC0);
2314 writel(tx_itr, fep->hwp + FEC_TXIC1);
2315 writel(rx_itr, fep->hwp + FEC_RXIC1);
2316 writel(tx_itr, fep->hwp + FEC_TXIC2);
2317 writel(rx_itr, fep->hwp + FEC_RXIC2);
2321 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2323 struct fec_enet_private *fep = netdev_priv(ndev);
2325 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2328 ec->rx_coalesce_usecs = fep->rx_time_itr;
2329 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2331 ec->tx_coalesce_usecs = fep->tx_time_itr;
2332 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2338 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2340 struct fec_enet_private *fep = netdev_priv(ndev);
2343 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2346 if (ec->rx_max_coalesced_frames > 255) {
2347 pr_err("Rx coalesced frames exceed hardware limiation");
2351 if (ec->tx_max_coalesced_frames > 255) {
2352 pr_err("Tx coalesced frame exceed hardware limiation");
2356 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2357 if (cycle > 0xFFFF) {
2358 pr_err("Rx coalesed usec exceeed hardware limiation");
2362 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2363 if (cycle > 0xFFFF) {
2364 pr_err("Rx coalesed usec exceeed hardware limiation");
2368 fep->rx_time_itr = ec->rx_coalesce_usecs;
2369 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2371 fep->tx_time_itr = ec->tx_coalesce_usecs;
2372 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2374 fec_enet_itr_coal_set(ndev);
2379 static void fec_enet_itr_coal_init(struct net_device *ndev)
2381 struct ethtool_coalesce ec;
2383 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2384 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2386 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2387 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2389 fec_enet_set_coalesce(ndev, &ec);
2392 static int fec_enet_get_tunable(struct net_device *netdev,
2393 const struct ethtool_tunable *tuna,
2396 struct fec_enet_private *fep = netdev_priv(netdev);
2400 case ETHTOOL_RX_COPYBREAK:
2401 *(u32 *)data = fep->rx_copybreak;
2411 static int fec_enet_set_tunable(struct net_device *netdev,
2412 const struct ethtool_tunable *tuna,
2415 struct fec_enet_private *fep = netdev_priv(netdev);
2419 case ETHTOOL_RX_COPYBREAK:
2420 fep->rx_copybreak = *(u32 *)data;
2430 static const struct ethtool_ops fec_enet_ethtool_ops = {
2431 .get_settings = fec_enet_get_settings,
2432 .set_settings = fec_enet_set_settings,
2433 .get_drvinfo = fec_enet_get_drvinfo,
2434 .nway_reset = fec_enet_nway_reset,
2435 .get_link = ethtool_op_get_link,
2436 .get_coalesce = fec_enet_get_coalesce,
2437 .set_coalesce = fec_enet_set_coalesce,
2438 #ifndef CONFIG_M5272
2439 .get_pauseparam = fec_enet_get_pauseparam,
2440 .set_pauseparam = fec_enet_set_pauseparam,
2441 .get_strings = fec_enet_get_strings,
2442 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2443 .get_sset_count = fec_enet_get_sset_count,
2445 .get_ts_info = fec_enet_get_ts_info,
2446 .get_tunable = fec_enet_get_tunable,
2447 .set_tunable = fec_enet_set_tunable,
2450 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2452 struct fec_enet_private *fep = netdev_priv(ndev);
2453 struct phy_device *phydev = fep->phy_dev;
2455 if (!netif_running(ndev))
2461 if (fep->bufdesc_ex) {
2462 if (cmd == SIOCSHWTSTAMP)
2463 return fec_ptp_set(ndev, rq);
2464 if (cmd == SIOCGHWTSTAMP)
2465 return fec_ptp_get(ndev, rq);
2468 return phy_mii_ioctl(phydev, rq, cmd);
2471 static void fec_enet_free_buffers(struct net_device *ndev)
2473 struct fec_enet_private *fep = netdev_priv(ndev);
2475 struct sk_buff *skb;
2476 struct bufdesc *bdp;
2477 struct fec_enet_priv_tx_q *txq;
2478 struct fec_enet_priv_rx_q *rxq;
2481 for (q = 0; q < fep->num_rx_queues; q++) {
2482 rxq = fep->rx_queue[q];
2483 bdp = rxq->rx_bd_base;
2484 for (i = 0; i < rxq->rx_ring_size; i++) {
2485 skb = rxq->rx_skbuff[i];
2486 rxq->rx_skbuff[i] = NULL;
2488 dma_unmap_single(&fep->pdev->dev,
2490 FEC_ENET_RX_FRSIZE - fep->rx_align,
2494 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2498 for (q = 0; q < fep->num_tx_queues; q++) {
2499 txq = fep->tx_queue[q];
2500 bdp = txq->tx_bd_base;
2501 for (i = 0; i < txq->tx_ring_size; i++) {
2502 kfree(txq->tx_bounce[i]);
2503 txq->tx_bounce[i] = NULL;
2504 skb = txq->tx_skbuff[i];
2505 txq->tx_skbuff[i] = NULL;
2511 static void fec_enet_free_queue(struct net_device *ndev)
2513 struct fec_enet_private *fep = netdev_priv(ndev);
2515 struct fec_enet_priv_tx_q *txq;
2517 for (i = 0; i < fep->num_tx_queues; i++)
2518 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2519 txq = fep->tx_queue[i];
2520 dma_free_coherent(NULL,
2521 txq->tx_ring_size * TSO_HEADER_SIZE,
2526 for (i = 0; i < fep->num_rx_queues; i++)
2527 if (fep->rx_queue[i])
2528 kfree(fep->rx_queue[i]);
2530 for (i = 0; i < fep->num_tx_queues; i++)
2531 if (fep->tx_queue[i])
2532 kfree(fep->tx_queue[i]);
2535 static int fec_enet_alloc_queue(struct net_device *ndev)
2537 struct fec_enet_private *fep = netdev_priv(ndev);
2540 struct fec_enet_priv_tx_q *txq;
2542 for (i = 0; i < fep->num_tx_queues; i++) {
2543 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2549 fep->tx_queue[i] = txq;
2550 txq->tx_ring_size = TX_RING_SIZE;
2551 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2553 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2554 txq->tx_wake_threshold =
2555 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2557 txq->tso_hdrs = dma_alloc_coherent(NULL,
2558 txq->tx_ring_size * TSO_HEADER_SIZE,
2561 if (!txq->tso_hdrs) {
2567 for (i = 0; i < fep->num_rx_queues; i++) {
2568 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2570 if (!fep->rx_queue[i]) {
2575 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2576 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2581 fec_enet_free_queue(ndev);
2586 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2588 struct fec_enet_private *fep = netdev_priv(ndev);
2590 struct sk_buff *skb;
2591 struct bufdesc *bdp;
2592 struct fec_enet_priv_rx_q *rxq;
2594 rxq = fep->rx_queue[queue];
2595 bdp = rxq->rx_bd_base;
2596 for (i = 0; i < rxq->rx_ring_size; i++) {
2597 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2601 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2606 rxq->rx_skbuff[i] = skb;
2607 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2609 if (fep->bufdesc_ex) {
2610 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2611 ebdp->cbd_esc = BD_ENET_RX_INT;
2614 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2617 /* Set the last buffer to wrap. */
2618 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2619 bdp->cbd_sc |= BD_SC_WRAP;
2623 fec_enet_free_buffers(ndev);
2628 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2630 struct fec_enet_private *fep = netdev_priv(ndev);
2632 struct bufdesc *bdp;
2633 struct fec_enet_priv_tx_q *txq;
2635 txq = fep->tx_queue[queue];
2636 bdp = txq->tx_bd_base;
2637 for (i = 0; i < txq->tx_ring_size; i++) {
2638 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2639 if (!txq->tx_bounce[i])
2643 bdp->cbd_bufaddr = 0;
2645 if (fep->bufdesc_ex) {
2646 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2647 ebdp->cbd_esc = BD_ENET_TX_INT;
2650 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2653 /* Set the last buffer to wrap. */
2654 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2655 bdp->cbd_sc |= BD_SC_WRAP;
2660 fec_enet_free_buffers(ndev);
2664 static int fec_enet_alloc_buffers(struct net_device *ndev)
2666 struct fec_enet_private *fep = netdev_priv(ndev);
2669 for (i = 0; i < fep->num_rx_queues; i++)
2670 if (fec_enet_alloc_rxq_buffers(ndev, i))
2673 for (i = 0; i < fep->num_tx_queues; i++)
2674 if (fec_enet_alloc_txq_buffers(ndev, i))
2680 fec_enet_open(struct net_device *ndev)
2682 struct fec_enet_private *fep = netdev_priv(ndev);
2685 pinctrl_pm_select_default_state(&fep->pdev->dev);
2686 ret = fec_enet_clk_enable(ndev, true);
2690 /* I should reset the ring buffers here, but I don't yet know
2691 * a simple way to do that.
2694 ret = fec_enet_alloc_buffers(ndev);
2696 goto err_enet_alloc;
2698 /* Probe and connect to PHY when open the interface */
2699 ret = fec_enet_mii_probe(ndev);
2701 goto err_enet_mii_probe;
2704 napi_enable(&fep->napi);
2705 phy_start(fep->phy_dev);
2706 netif_tx_start_all_queues(ndev);
2711 fec_enet_free_buffers(ndev);
2713 fec_enet_clk_enable(ndev, false);
2714 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2719 fec_enet_close(struct net_device *ndev)
2721 struct fec_enet_private *fep = netdev_priv(ndev);
2723 phy_stop(fep->phy_dev);
2725 if (netif_device_present(ndev)) {
2726 napi_disable(&fep->napi);
2727 netif_tx_disable(ndev);
2731 phy_disconnect(fep->phy_dev);
2732 fep->phy_dev = NULL;
2734 fec_enet_clk_enable(ndev, false);
2735 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2736 fec_enet_free_buffers(ndev);
2741 /* Set or clear the multicast filter for this adaptor.
2742 * Skeleton taken from sunlance driver.
2743 * The CPM Ethernet implementation allows Multicast as well as individual
2744 * MAC address filtering. Some of the drivers check to make sure it is
2745 * a group multicast address, and discard those that are not. I guess I
2746 * will do the same for now, but just remove the test if you want
2747 * individual filtering as well (do the upper net layers want or support
2748 * this kind of feature?).
2751 #define HASH_BITS 6 /* #bits in hash */
2752 #define CRC32_POLY 0xEDB88320
2754 static void set_multicast_list(struct net_device *ndev)
2756 struct fec_enet_private *fep = netdev_priv(ndev);
2757 struct netdev_hw_addr *ha;
2758 unsigned int i, bit, data, crc, tmp;
2761 if (ndev->flags & IFF_PROMISC) {
2762 tmp = readl(fep->hwp + FEC_R_CNTRL);
2764 writel(tmp, fep->hwp + FEC_R_CNTRL);
2768 tmp = readl(fep->hwp + FEC_R_CNTRL);
2770 writel(tmp, fep->hwp + FEC_R_CNTRL);
2772 if (ndev->flags & IFF_ALLMULTI) {
2773 /* Catch all multicast addresses, so set the
2776 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2777 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2782 /* Clear filter and add the addresses in hash register
2784 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2785 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2787 netdev_for_each_mc_addr(ha, ndev) {
2788 /* calculate crc32 value of mac address */
2791 for (i = 0; i < ndev->addr_len; i++) {
2793 for (bit = 0; bit < 8; bit++, data >>= 1) {
2795 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2799 /* only upper 6 bits (HASH_BITS) are used
2800 * which point to specific bit in he hash registers
2802 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2805 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2806 tmp |= 1 << (hash - 32);
2807 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2809 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2811 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2816 /* Set a MAC change in hardware. */
2818 fec_set_mac_address(struct net_device *ndev, void *p)
2820 struct fec_enet_private *fep = netdev_priv(ndev);
2821 struct sockaddr *addr = p;
2824 if (!is_valid_ether_addr(addr->sa_data))
2825 return -EADDRNOTAVAIL;
2826 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2829 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2830 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2831 fep->hwp + FEC_ADDR_LOW);
2832 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2833 fep->hwp + FEC_ADDR_HIGH);
2837 #ifdef CONFIG_NET_POLL_CONTROLLER
2839 * fec_poll_controller - FEC Poll controller function
2840 * @dev: The FEC network adapter
2842 * Polled functionality used by netconsole and others in non interrupt mode
2845 static void fec_poll_controller(struct net_device *dev)
2848 struct fec_enet_private *fep = netdev_priv(dev);
2850 for (i = 0; i < FEC_IRQ_NUM; i++) {
2851 if (fep->irq[i] > 0) {
2852 disable_irq(fep->irq[i]);
2853 fec_enet_interrupt(fep->irq[i], dev);
2854 enable_irq(fep->irq[i]);
2860 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
2861 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
2862 netdev_features_t features)
2864 struct fec_enet_private *fep = netdev_priv(netdev);
2865 netdev_features_t changed = features ^ netdev->features;
2867 netdev->features = features;
2869 /* Receive checksum has been changed */
2870 if (changed & NETIF_F_RXCSUM) {
2871 if (features & NETIF_F_RXCSUM)
2872 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2874 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2878 static int fec_set_features(struct net_device *netdev,
2879 netdev_features_t features)
2881 struct fec_enet_private *fep = netdev_priv(netdev);
2882 netdev_features_t changed = features ^ netdev->features;
2884 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
2885 napi_disable(&fep->napi);
2886 netif_tx_lock_bh(netdev);
2888 fec_enet_set_netdev_features(netdev, features);
2889 fec_restart(netdev);
2890 netif_tx_wake_all_queues(netdev);
2891 netif_tx_unlock_bh(netdev);
2892 napi_enable(&fep->napi);
2894 fec_enet_set_netdev_features(netdev, features);
2900 static const struct net_device_ops fec_netdev_ops = {
2901 .ndo_open = fec_enet_open,
2902 .ndo_stop = fec_enet_close,
2903 .ndo_start_xmit = fec_enet_start_xmit,
2904 .ndo_set_rx_mode = set_multicast_list,
2905 .ndo_change_mtu = eth_change_mtu,
2906 .ndo_validate_addr = eth_validate_addr,
2907 .ndo_tx_timeout = fec_timeout,
2908 .ndo_set_mac_address = fec_set_mac_address,
2909 .ndo_do_ioctl = fec_enet_ioctl,
2910 #ifdef CONFIG_NET_POLL_CONTROLLER
2911 .ndo_poll_controller = fec_poll_controller,
2913 .ndo_set_features = fec_set_features,
2917 * XXX: We need to clean up on failure exits here.
2920 static int fec_enet_init(struct net_device *ndev)
2922 struct fec_enet_private *fep = netdev_priv(ndev);
2923 struct fec_enet_priv_tx_q *txq;
2924 struct fec_enet_priv_rx_q *rxq;
2925 struct bufdesc *cbd_base;
2930 #if defined(CONFIG_ARM)
2931 fep->rx_align = 0xf;
2932 fep->tx_align = 0xf;
2934 fep->rx_align = 0x3;
2935 fep->tx_align = 0x3;
2938 fec_enet_alloc_queue(ndev);
2940 if (fep->bufdesc_ex)
2941 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2943 fep->bufdesc_size = sizeof(struct bufdesc);
2944 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
2947 /* Allocate memory for buffer descriptors. */
2948 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
2954 memset(cbd_base, 0, bd_size);
2956 /* Get the Ethernet address */
2958 /* make sure MAC we just acquired is programmed into the hw */
2959 fec_set_mac_address(ndev, NULL);
2961 /* Set receive and transmit descriptor base. */
2962 for (i = 0; i < fep->num_rx_queues; i++) {
2963 rxq = fep->rx_queue[i];
2965 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
2966 rxq->bd_dma = bd_dma;
2967 if (fep->bufdesc_ex) {
2968 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
2969 cbd_base = (struct bufdesc *)
2970 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
2972 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
2973 cbd_base += rxq->rx_ring_size;
2977 for (i = 0; i < fep->num_tx_queues; i++) {
2978 txq = fep->tx_queue[i];
2980 txq->tx_bd_base = (struct bufdesc *)cbd_base;
2981 txq->bd_dma = bd_dma;
2982 if (fep->bufdesc_ex) {
2983 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
2984 cbd_base = (struct bufdesc *)
2985 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
2987 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
2988 cbd_base += txq->tx_ring_size;
2993 /* The FEC Ethernet specific entries in the device structure */
2994 ndev->watchdog_timeo = TX_TIMEOUT;
2995 ndev->netdev_ops = &fec_netdev_ops;
2996 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2998 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2999 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3001 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3002 /* enable hw VLAN support */
3003 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3005 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3006 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3008 /* enable hw accelerator */
3009 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3010 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3011 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3014 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3016 fep->rx_align = 0x3f;
3019 ndev->hw_features = ndev->features;
3027 static void fec_reset_phy(struct platform_device *pdev)
3031 struct device_node *np = pdev->dev.of_node;
3036 of_property_read_u32(np, "phy-reset-duration", &msec);
3037 /* A sane reset duration should not be longer than 1s */
3041 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3042 if (!gpio_is_valid(phy_reset))
3045 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3046 GPIOF_OUT_INIT_LOW, "phy-reset");
3048 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3052 gpio_set_value(phy_reset, 1);
3054 #else /* CONFIG_OF */
3055 static void fec_reset_phy(struct platform_device *pdev)
3058 * In case of platform probe, the reset has been done
3062 #endif /* CONFIG_OF */
3065 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3067 struct device_node *np = pdev->dev.of_node;
3070 *num_tx = *num_rx = 1;
3072 if (!np || !of_device_is_available(np))
3075 /* parse the num of tx and rx queues */
3076 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3080 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3084 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3085 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3091 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3092 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3101 fec_probe(struct platform_device *pdev)
3103 struct fec_enet_private *fep;
3104 struct fec_platform_data *pdata;
3105 struct net_device *ndev;
3106 int i, irq, ret = 0;
3108 const struct of_device_id *of_id;
3110 struct device_node *np = pdev->dev.of_node, *phy_node;
3114 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3116 /* Init network device */
3117 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3118 num_tx_qs, num_rx_qs);
3122 SET_NETDEV_DEV(ndev, &pdev->dev);
3124 /* setup board info structure */
3125 fep = netdev_priv(ndev);
3127 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3129 pdev->id_entry = of_id->data;
3130 fep->quirks = pdev->id_entry->driver_data;
3132 fep->num_rx_queues = num_rx_qs;
3133 fep->num_tx_queues = num_tx_qs;
3135 #if !defined(CONFIG_M5272)
3136 /* default enable pause frame auto negotiation */
3137 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3138 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3141 /* Select default pin state */
3142 pinctrl_pm_select_default_state(&pdev->dev);
3144 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3145 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3146 if (IS_ERR(fep->hwp)) {
3147 ret = PTR_ERR(fep->hwp);
3148 goto failed_ioremap;
3152 fep->dev_id = dev_id++;
3154 platform_set_drvdata(pdev, ndev);
3156 phy_node = of_parse_phandle(np, "phy-handle", 0);
3157 if (!phy_node && of_phy_is_fixed_link(np)) {
3158 ret = of_phy_register_fixed_link(np);
3161 "broken fixed-link specification\n");
3164 phy_node = of_node_get(np);
3166 fep->phy_node = phy_node;
3168 ret = of_get_phy_mode(pdev->dev.of_node);
3170 pdata = dev_get_platdata(&pdev->dev);
3172 fep->phy_interface = pdata->phy;
3174 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3176 fep->phy_interface = ret;
3179 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3180 if (IS_ERR(fep->clk_ipg)) {
3181 ret = PTR_ERR(fep->clk_ipg);
3185 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3186 if (IS_ERR(fep->clk_ahb)) {
3187 ret = PTR_ERR(fep->clk_ahb);
3191 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3193 /* enet_out is optional, depends on board */
3194 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3195 if (IS_ERR(fep->clk_enet_out))
3196 fep->clk_enet_out = NULL;
3198 fep->ptp_clk_on = false;
3199 mutex_init(&fep->ptp_clk_mutex);
3201 /* clk_ref is optional, depends on board */
3202 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3203 if (IS_ERR(fep->clk_ref))
3204 fep->clk_ref = NULL;
3206 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3207 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3208 if (IS_ERR(fep->clk_ptp)) {
3209 fep->clk_ptp = NULL;
3210 fep->bufdesc_ex = false;
3213 ret = fec_enet_clk_enable(ndev, true);
3217 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3218 if (!IS_ERR(fep->reg_phy)) {
3219 ret = regulator_enable(fep->reg_phy);
3222 "Failed to enable phy regulator: %d\n", ret);
3223 goto failed_regulator;
3226 fep->reg_phy = NULL;
3229 fec_reset_phy(pdev);
3231 if (fep->bufdesc_ex)
3234 ret = fec_enet_init(ndev);
3238 for (i = 0; i < FEC_IRQ_NUM; i++) {
3239 irq = platform_get_irq(pdev, i);
3246 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3247 0, pdev->name, ndev);
3252 init_completion(&fep->mdio_done);
3253 ret = fec_enet_mii_init(pdev);
3255 goto failed_mii_init;
3257 /* Carrier starts down, phylib will bring it up */
3258 netif_carrier_off(ndev);
3259 fec_enet_clk_enable(ndev, false);
3260 pinctrl_pm_select_sleep_state(&pdev->dev);
3262 ret = register_netdev(ndev);
3264 goto failed_register;
3266 if (fep->bufdesc_ex && fep->ptp_clock)
3267 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3269 fep->rx_copybreak = COPYBREAK_DEFAULT;
3270 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3274 fec_enet_mii_remove(fep);
3279 regulator_disable(fep->reg_phy);
3281 fec_enet_clk_enable(ndev, false);
3284 of_node_put(phy_node);
3292 fec_drv_remove(struct platform_device *pdev)
3294 struct net_device *ndev = platform_get_drvdata(pdev);
3295 struct fec_enet_private *fep = netdev_priv(ndev);
3297 cancel_delayed_work_sync(&fep->time_keep);
3298 cancel_work_sync(&fep->tx_timeout_work);
3299 unregister_netdev(ndev);
3300 fec_enet_mii_remove(fep);
3302 regulator_disable(fep->reg_phy);
3304 ptp_clock_unregister(fep->ptp_clock);
3305 fec_enet_clk_enable(ndev, false);
3306 of_node_put(fep->phy_node);
3312 static int __maybe_unused fec_suspend(struct device *dev)
3314 struct net_device *ndev = dev_get_drvdata(dev);
3315 struct fec_enet_private *fep = netdev_priv(ndev);
3318 if (netif_running(ndev)) {
3319 phy_stop(fep->phy_dev);
3320 napi_disable(&fep->napi);
3321 netif_tx_lock_bh(ndev);
3322 netif_device_detach(ndev);
3323 netif_tx_unlock_bh(ndev);
3325 fec_enet_clk_enable(ndev, false);
3326 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3331 regulator_disable(fep->reg_phy);
3336 static int __maybe_unused fec_resume(struct device *dev)
3338 struct net_device *ndev = dev_get_drvdata(dev);
3339 struct fec_enet_private *fep = netdev_priv(ndev);
3343 ret = regulator_enable(fep->reg_phy);
3349 if (netif_running(ndev)) {
3350 pinctrl_pm_select_default_state(&fep->pdev->dev);
3351 ret = fec_enet_clk_enable(ndev, true);
3357 netif_tx_lock_bh(ndev);
3358 netif_device_attach(ndev);
3359 netif_tx_unlock_bh(ndev);
3360 napi_enable(&fep->napi);
3361 phy_start(fep->phy_dev);
3369 regulator_disable(fep->reg_phy);
3373 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
3375 static struct platform_driver fec_driver = {
3377 .name = DRIVER_NAME,
3378 .owner = THIS_MODULE,
3380 .of_match_table = fec_dt_ids,
3382 .id_table = fec_devtype,
3384 .remove = fec_drv_remove,
3387 module_platform_driver(fec_driver);
3389 MODULE_ALIAS("platform:"DRIVER_NAME);
3390 MODULE_LICENSE("GPL");