2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
39 #include <linux/tcp.h>
40 #include <linux/udp.h>
41 #include <linux/icmp.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/bitops.h>
46 #include <linux/irq.h>
47 #include <linux/clk.h>
48 #include <linux/platform_device.h>
49 #include <linux/phy.h>
50 #include <linux/fec.h>
52 #include <linux/of_device.h>
53 #include <linux/of_gpio.h>
54 #include <linux/of_net.h>
55 #include <linux/regulator/consumer.h>
56 #include <linux/if_vlan.h>
57 #include <linux/pinctrl/consumer.h>
59 #include <asm/cacheflush.h>
63 static void set_multicast_list(struct net_device *ndev);
65 #if defined(CONFIG_ARM)
66 #define FEC_ALIGNMENT 0xf
68 #define FEC_ALIGNMENT 0x3
71 #define DRIVER_NAME "fec"
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 /* Controller is ENET-MAC */
82 #define FEC_QUIRK_ENET_MAC (1 << 0)
83 /* Controller needs driver to swap frame */
84 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
85 /* Controller uses gasket */
86 #define FEC_QUIRK_USE_GASKET (1 << 2)
87 /* Controller has GBIT support */
88 #define FEC_QUIRK_HAS_GBIT (1 << 3)
89 /* Controller has extend desc buffer */
90 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
91 /* Controller has hardware checksum support */
92 #define FEC_QUIRK_HAS_CSUM (1 << 5)
93 /* Controller has hardware vlan support */
94 #define FEC_QUIRK_HAS_VLAN (1 << 6)
95 /* ENET IP errata ERR006358
97 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
98 * detected as not set during a prior frame transmission, then the
99 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
100 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
101 * frames not being transmitted until there is a 0-to-1 transition on
104 #define FEC_QUIRK_ERR006358 (1 << 7)
106 static struct platform_device_id fec_devtype[] = {
108 /* keep it for coldfire */
113 .driver_data = FEC_QUIRK_USE_GASKET,
119 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
122 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
126 .name = "mvf600-fec",
127 .driver_data = FEC_QUIRK_ENET_MAC,
132 MODULE_DEVICE_TABLE(platform, fec_devtype);
135 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
136 IMX27_FEC, /* runs on i.mx27/35/51 */
142 static const struct of_device_id fec_dt_ids[] = {
143 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
144 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
145 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
146 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
147 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
150 MODULE_DEVICE_TABLE(of, fec_dt_ids);
152 static unsigned char macaddr[ETH_ALEN];
153 module_param_array(macaddr, byte, NULL, 0);
154 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
156 #if defined(CONFIG_M5272)
158 * Some hardware gets it MAC address out of local flash memory.
159 * if this is non-zero then assume it is the address to get MAC from.
161 #if defined(CONFIG_NETtel)
162 #define FEC_FLASHMAC 0xf0006006
163 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
164 #define FEC_FLASHMAC 0xf0006000
165 #elif defined(CONFIG_CANCam)
166 #define FEC_FLASHMAC 0xf0020000
167 #elif defined (CONFIG_M5272C3)
168 #define FEC_FLASHMAC (0xffe04000 + 4)
169 #elif defined(CONFIG_MOD5272)
170 #define FEC_FLASHMAC 0xffc0406b
172 #define FEC_FLASHMAC 0
174 #endif /* CONFIG_M5272 */
176 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
177 #error "FEC: descriptor ring size constants too large"
180 /* Interrupt events/masks. */
181 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
182 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
183 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
184 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
185 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
186 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
187 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
188 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
189 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
190 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
192 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
193 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
195 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
197 #define PKT_MAXBUF_SIZE 1522
198 #define PKT_MINBUF_SIZE 64
199 #define PKT_MAXBLR_SIZE 1536
201 /* FEC receive acceleration */
202 #define FEC_RACC_IPDIS (1 << 1)
203 #define FEC_RACC_PRODIS (1 << 2)
204 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
207 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
208 * size bits. Other FEC hardware does not, so we need to take that into
209 * account when setting it.
211 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
212 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
213 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
215 #define OPT_FRAME_SIZE 0
218 /* FEC MII MMFR bits definition */
219 #define FEC_MMFR_ST (1 << 30)
220 #define FEC_MMFR_OP_READ (2 << 28)
221 #define FEC_MMFR_OP_WRITE (1 << 28)
222 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
223 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
224 #define FEC_MMFR_TA (2 << 16)
225 #define FEC_MMFR_DATA(v) (v & 0xffff)
227 #define FEC_MII_TIMEOUT 30000 /* us */
229 /* Transmitter timeout */
230 #define TX_TIMEOUT (2 * HZ)
232 #define FEC_PAUSE_FLAG_AUTONEG 0x1
233 #define FEC_PAUSE_FLAG_ENABLE 0x2
238 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
240 struct bufdesc *new_bd = bdp + 1;
241 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
242 struct bufdesc_ex *ex_base;
243 struct bufdesc *base;
246 if (bdp >= fep->tx_bd_base) {
247 base = fep->tx_bd_base;
248 ring_size = fep->tx_ring_size;
249 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
251 base = fep->rx_bd_base;
252 ring_size = fep->rx_ring_size;
253 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
257 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
258 ex_base : ex_new_bd);
260 return (new_bd >= (base + ring_size)) ?
265 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
267 struct bufdesc *new_bd = bdp - 1;
268 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
269 struct bufdesc_ex *ex_base;
270 struct bufdesc *base;
273 if (bdp >= fep->tx_bd_base) {
274 base = fep->tx_bd_base;
275 ring_size = fep->tx_ring_size;
276 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
278 base = fep->rx_bd_base;
279 ring_size = fep->rx_ring_size;
280 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
284 return (struct bufdesc *)((ex_new_bd < ex_base) ?
285 (ex_new_bd + ring_size) : ex_new_bd);
287 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
290 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
291 struct fec_enet_private *fep)
293 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
296 static void *swap_buffer(void *bufaddr, int len)
299 unsigned int *buf = bufaddr;
301 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
302 *buf = cpu_to_be32(*buf);
308 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
310 /* Only run for packets requiring a checksum. */
311 if (skb->ip_summed != CHECKSUM_PARTIAL)
314 if (unlikely(skb_cow_head(skb, 0)))
317 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
322 static int txq_submit_skb(struct sk_buff *skb, struct net_device *ndev)
324 struct fec_enet_private *fep = netdev_priv(ndev);
325 const struct platform_device_id *id_entry =
326 platform_get_device_id(fep->pdev);
327 struct bufdesc *bdp, *bdp_pre;
329 unsigned short status;
332 /* Fill in a Tx ring entry */
335 status = bdp->cbd_sc;
337 /* Protocol checksum off-load for TCP and UDP. */
338 if (fec_enet_clear_csum(skb, ndev)) {
339 dev_kfree_skb_any(skb);
343 /* Clear all of the status flags */
344 status &= ~BD_ENET_TX_STATS;
346 /* Set buffer length and buffer pointer */
348 bdp->cbd_datlen = skb->len;
350 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
352 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
353 memcpy(fep->tx_bounce[index], skb->data, skb->len);
354 bufaddr = fep->tx_bounce[index];
358 * Some design made an incorrect assumption on endian mode of
359 * the system that it's running on. As the result, driver has to
360 * swap every frame going to and coming from the controller.
362 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
363 swap_buffer(bufaddr, skb->len);
365 /* Save skb pointer */
366 fep->tx_skbuff[index] = skb;
368 /* Push the data cache so the CPM does not get stale memory
371 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
372 skb->len, DMA_TO_DEVICE);
373 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
374 bdp->cbd_bufaddr = 0;
375 fep->tx_skbuff[index] = NULL;
376 dev_kfree_skb_any(skb);
378 netdev_err(ndev, "Tx DMA memory map failed\n");
382 if (fep->bufdesc_ex) {
384 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
386 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
388 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
389 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
391 ebdp->cbd_esc = BD_ENET_TX_INT;
393 /* Enable protocol checksum flags
394 * We do not bother with the IP Checksum bits as they
395 * are done by the kernel
397 if (skb->ip_summed == CHECKSUM_PARTIAL)
398 ebdp->cbd_esc |= BD_ENET_TX_PINS;
402 /* Send it on its way. Tell FEC it's ready, interrupt when done,
403 * it's the last BD of the frame, and to put the CRC on the end.
405 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
406 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
407 bdp->cbd_sc = status;
409 bdp_pre = fec_enet_get_prevdesc(bdp, fep);
410 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
411 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
412 fep->delay_work.trig_tx = true;
413 schedule_delayed_work(&(fep->delay_work.delay_work),
414 msecs_to_jiffies(1));
417 /* If this was the last BD in the ring, start at the beginning again. */
418 bdp = fec_enet_get_nextdesc(bdp, fep);
420 skb_tx_timestamp(skb);
424 /* Trigger transmission start */
425 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
431 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
433 struct fec_enet_private *fep = netdev_priv(ndev);
435 unsigned short status;
438 /* Fill in a Tx ring entry */
441 status = bdp->cbd_sc;
443 if (status & BD_ENET_TX_READY) {
444 /* Ooops. All transmit buffers are full. Bail out.
445 * This should not happen, since ndev->tbusy should be set.
447 netdev_err(ndev, "tx queue full!\n");
448 return NETDEV_TX_BUSY;
451 ret = txq_submit_skb(skb, ndev);
453 return NETDEV_TX_BUSY;
455 if (fep->cur_tx == fep->dirty_tx)
456 netif_stop_queue(ndev);
461 /* Init RX & TX buffer descriptors
463 static void fec_enet_bd_init(struct net_device *dev)
465 struct fec_enet_private *fep = netdev_priv(dev);
469 /* Initialize the receive buffer descriptors. */
470 bdp = fep->rx_bd_base;
471 for (i = 0; i < fep->rx_ring_size; i++) {
473 /* Initialize the BD for every fragment in the page. */
474 if (bdp->cbd_bufaddr)
475 bdp->cbd_sc = BD_ENET_RX_EMPTY;
478 bdp = fec_enet_get_nextdesc(bdp, fep);
481 /* Set the last buffer to wrap */
482 bdp = fec_enet_get_prevdesc(bdp, fep);
483 bdp->cbd_sc |= BD_SC_WRAP;
485 fep->cur_rx = fep->rx_bd_base;
487 /* ...and the same for transmit */
488 bdp = fep->tx_bd_base;
490 for (i = 0; i < fep->tx_ring_size; i++) {
492 /* Initialize the BD for every fragment in the page. */
494 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
495 dev_kfree_skb_any(fep->tx_skbuff[i]);
496 fep->tx_skbuff[i] = NULL;
498 bdp->cbd_bufaddr = 0;
499 bdp = fec_enet_get_nextdesc(bdp, fep);
502 /* Set the last buffer to wrap */
503 bdp = fec_enet_get_prevdesc(bdp, fep);
504 bdp->cbd_sc |= BD_SC_WRAP;
508 /* This function is called to start or restart the FEC during a link
509 * change. This only happens when switching between half and full
513 fec_restart(struct net_device *ndev, int duplex)
515 struct fec_enet_private *fep = netdev_priv(ndev);
516 const struct platform_device_id *id_entry =
517 platform_get_device_id(fep->pdev);
521 u32 rcntl = OPT_FRAME_SIZE | 0x04;
522 u32 ecntl = 0x2; /* ETHEREN */
524 if (netif_running(ndev)) {
525 netif_device_detach(ndev);
526 napi_disable(&fep->napi);
527 netif_stop_queue(ndev);
528 netif_tx_lock_bh(ndev);
531 /* Whack a reset. We should wait for this. */
532 writel(1, fep->hwp + FEC_ECNTRL);
536 * enet-mac reset will reset mac address registers too,
537 * so need to reconfigure it.
539 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
540 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
541 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
542 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
545 /* Clear any outstanding interrupt. */
546 writel(0xffc00000, fep->hwp + FEC_IEVENT);
548 /* Set maximum receive buffer size. */
549 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
551 fec_enet_bd_init(ndev);
553 /* Set receive and transmit descriptor base. */
554 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
556 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
557 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
559 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
560 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
563 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
564 if (fep->tx_skbuff[i]) {
565 dev_kfree_skb_any(fep->tx_skbuff[i]);
566 fep->tx_skbuff[i] = NULL;
570 /* Enable MII mode */
573 writel(0x04, fep->hwp + FEC_X_CNTRL);
577 writel(0x0, fep->hwp + FEC_X_CNTRL);
580 fep->full_duplex = duplex;
583 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
585 #if !defined(CONFIG_M5272)
586 /* set RX checksum */
587 val = readl(fep->hwp + FEC_RACC);
588 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
589 val |= FEC_RACC_OPTIONS;
591 val &= ~FEC_RACC_OPTIONS;
592 writel(val, fep->hwp + FEC_RACC);
596 * The phy interface and speed need to get configured
597 * differently on enet-mac.
599 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
600 /* Enable flow control and length check */
601 rcntl |= 0x40000000 | 0x00000020;
603 /* RGMII, RMII or MII */
604 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
606 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
611 /* 1G, 100M or 10M */
613 if (fep->phy_dev->speed == SPEED_1000)
615 else if (fep->phy_dev->speed == SPEED_100)
621 #ifdef FEC_MIIGSK_ENR
622 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
624 /* disable the gasket and wait */
625 writel(0, fep->hwp + FEC_MIIGSK_ENR);
626 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
630 * configure the gasket:
631 * RMII, 50 MHz, no loopback, no echo
632 * MII, 25 MHz, no loopback, no echo
634 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
635 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
636 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
637 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
638 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
640 /* re-enable the gasket */
641 writel(2, fep->hwp + FEC_MIIGSK_ENR);
646 #if !defined(CONFIG_M5272)
647 /* enable pause frame*/
648 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
649 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
650 fep->phy_dev && fep->phy_dev->pause)) {
651 rcntl |= FEC_ENET_FCE;
653 /* set FIFO threshold parameter to reduce overrun */
654 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
655 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
656 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
657 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
660 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
662 rcntl &= ~FEC_ENET_FCE;
664 #endif /* !defined(CONFIG_M5272) */
666 writel(rcntl, fep->hwp + FEC_R_CNTRL);
668 /* Setup multicast filter. */
669 set_multicast_list(ndev);
671 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
672 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
675 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
676 /* enable ENET endian swap */
678 /* enable ENET store and forward mode */
679 writel(1 << 8, fep->hwp + FEC_X_WMRK);
686 /* Enable the MIB statistic event counters */
687 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
690 /* And last, enable the transmit and receive processing */
691 writel(ecntl, fep->hwp + FEC_ECNTRL);
692 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
695 fec_ptp_start_cyclecounter(ndev);
697 /* Enable interrupts we wish to service */
698 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
700 if (netif_running(ndev)) {
701 netif_tx_unlock_bh(ndev);
702 netif_wake_queue(ndev);
703 napi_enable(&fep->napi);
704 netif_device_attach(ndev);
709 fec_stop(struct net_device *ndev)
711 struct fec_enet_private *fep = netdev_priv(ndev);
712 const struct platform_device_id *id_entry =
713 platform_get_device_id(fep->pdev);
714 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
716 /* We cannot expect a graceful transmit stop without link !!! */
718 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
720 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
721 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
724 /* Whack a reset. We should wait for this. */
725 writel(1, fep->hwp + FEC_ECNTRL);
727 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
728 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
730 /* We have to keep ENET enabled to have MII interrupt stay working */
731 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
732 writel(2, fep->hwp + FEC_ECNTRL);
733 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
739 fec_timeout(struct net_device *ndev)
741 struct fec_enet_private *fep = netdev_priv(ndev);
743 ndev->stats.tx_errors++;
745 fep->delay_work.timeout = true;
746 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
749 static void fec_enet_work(struct work_struct *work)
751 struct fec_enet_private *fep =
753 struct fec_enet_private,
754 delay_work.delay_work.work);
756 if (fep->delay_work.timeout) {
757 fep->delay_work.timeout = false;
758 fec_restart(fep->netdev, fep->full_duplex);
759 netif_wake_queue(fep->netdev);
762 if (fep->delay_work.trig_tx) {
763 fep->delay_work.trig_tx = false;
764 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
769 fec_enet_tx(struct net_device *ndev)
771 struct fec_enet_private *fep;
773 unsigned short status;
777 fep = netdev_priv(ndev);
780 /* get next bdp of dirty_tx */
781 bdp = fec_enet_get_nextdesc(bdp, fep);
783 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
785 /* current queue is empty */
786 if (bdp == fep->cur_tx)
789 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
791 skb = fep->tx_skbuff[index];
792 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, skb->len,
794 bdp->cbd_bufaddr = 0;
796 /* Check for errors. */
797 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
798 BD_ENET_TX_RL | BD_ENET_TX_UN |
800 ndev->stats.tx_errors++;
801 if (status & BD_ENET_TX_HB) /* No heartbeat */
802 ndev->stats.tx_heartbeat_errors++;
803 if (status & BD_ENET_TX_LC) /* Late collision */
804 ndev->stats.tx_window_errors++;
805 if (status & BD_ENET_TX_RL) /* Retrans limit */
806 ndev->stats.tx_aborted_errors++;
807 if (status & BD_ENET_TX_UN) /* Underrun */
808 ndev->stats.tx_fifo_errors++;
809 if (status & BD_ENET_TX_CSL) /* Carrier lost */
810 ndev->stats.tx_carrier_errors++;
812 ndev->stats.tx_packets++;
813 ndev->stats.tx_bytes += bdp->cbd_datlen;
816 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
818 struct skb_shared_hwtstamps shhwtstamps;
820 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
822 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
823 spin_lock_irqsave(&fep->tmreg_lock, flags);
824 shhwtstamps.hwtstamp = ns_to_ktime(
825 timecounter_cyc2time(&fep->tc, ebdp->ts));
826 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
827 skb_tstamp_tx(skb, &shhwtstamps);
830 if (status & BD_ENET_TX_READY)
831 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
833 /* Deferred means some collisions occurred during transmit,
834 * but we eventually sent the packet OK.
836 if (status & BD_ENET_TX_DEF)
837 ndev->stats.collisions++;
839 /* Free the sk buffer associated with this last transmit */
840 dev_kfree_skb_any(skb);
841 fep->tx_skbuff[index] = NULL;
845 /* Update pointer to next buffer descriptor to be transmitted */
846 bdp = fec_enet_get_nextdesc(bdp, fep);
848 /* Since we have freed up a buffer, the ring is no longer full
850 if (fep->dirty_tx != fep->cur_tx) {
851 if (netif_queue_stopped(ndev))
852 netif_wake_queue(ndev);
859 /* During a receive, the cur_rx points to the current incoming buffer.
860 * When we update through the ring, if the next incoming buffer has
861 * not been given to the system, we just set the empty indicator,
862 * effectively tossing the packet.
865 fec_enet_rx(struct net_device *ndev, int budget)
867 struct fec_enet_private *fep = netdev_priv(ndev);
868 const struct platform_device_id *id_entry =
869 platform_get_device_id(fep->pdev);
871 unsigned short status;
875 int pkt_received = 0;
876 struct bufdesc_ex *ebdp = NULL;
877 bool vlan_packet_rcvd = false;
885 /* First, grab all of the stats for the incoming packet.
886 * These get messed up if we get called due to a busy condition.
890 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
892 if (pkt_received >= budget)
896 /* Since we have allocated space to hold a complete frame,
897 * the last indicator should be set.
899 if ((status & BD_ENET_RX_LAST) == 0)
900 netdev_err(ndev, "rcv is not +last\n");
903 goto rx_processing_done;
905 /* Check for errors. */
906 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
907 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
908 ndev->stats.rx_errors++;
909 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
910 /* Frame too long or too short. */
911 ndev->stats.rx_length_errors++;
913 if (status & BD_ENET_RX_NO) /* Frame alignment */
914 ndev->stats.rx_frame_errors++;
915 if (status & BD_ENET_RX_CR) /* CRC Error */
916 ndev->stats.rx_crc_errors++;
917 if (status & BD_ENET_RX_OV) /* FIFO overrun */
918 ndev->stats.rx_fifo_errors++;
921 /* Report late collisions as a frame error.
922 * On this error, the BD is closed, but we don't know what we
923 * have in the buffer. So, just drop this frame on the floor.
925 if (status & BD_ENET_RX_CL) {
926 ndev->stats.rx_errors++;
927 ndev->stats.rx_frame_errors++;
928 goto rx_processing_done;
931 /* Process the incoming frame. */
932 ndev->stats.rx_packets++;
933 pkt_len = bdp->cbd_datlen;
934 ndev->stats.rx_bytes += pkt_len;
936 index = fec_enet_get_bd_index(fep->rx_bd_base, bdp, fep);
937 data = fep->rx_skbuff[index]->data;
938 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
939 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
941 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
942 swap_buffer(data, pkt_len);
944 /* Extract the enhanced buffer descriptor */
947 ebdp = (struct bufdesc_ex *)bdp;
949 /* If this is a VLAN packet remove the VLAN Tag */
950 vlan_packet_rcvd = false;
951 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
952 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
953 /* Push and remove the vlan tag */
954 struct vlan_hdr *vlan_header =
955 (struct vlan_hdr *) (data + ETH_HLEN);
956 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
957 pkt_len -= VLAN_HLEN;
959 vlan_packet_rcvd = true;
962 /* This does 16 byte alignment, exactly what we need.
963 * The packet length includes FCS, but we don't want to
964 * include that when passing upstream as it messes up
965 * bridging applications.
967 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
969 if (unlikely(!skb)) {
970 ndev->stats.rx_dropped++;
972 int payload_offset = (2 * ETH_ALEN);
973 skb_reserve(skb, NET_IP_ALIGN);
974 skb_put(skb, pkt_len - 4); /* Make room */
976 /* Extract the frame data without the VLAN header. */
977 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
978 if (vlan_packet_rcvd)
979 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
980 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
981 data + payload_offset,
982 pkt_len - 4 - (2 * ETH_ALEN));
984 skb->protocol = eth_type_trans(skb, ndev);
986 /* Get receive timestamp from the skb */
987 if (fep->hwts_rx_en && fep->bufdesc_ex) {
988 struct skb_shared_hwtstamps *shhwtstamps =
992 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
994 spin_lock_irqsave(&fep->tmreg_lock, flags);
995 shhwtstamps->hwtstamp = ns_to_ktime(
996 timecounter_cyc2time(&fep->tc, ebdp->ts));
997 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1000 if (fep->bufdesc_ex &&
1001 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1002 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1003 /* don't check it */
1004 skb->ip_summed = CHECKSUM_UNNECESSARY;
1006 skb_checksum_none_assert(skb);
1010 /* Handle received VLAN packets */
1011 if (vlan_packet_rcvd)
1012 __vlan_hwaccel_put_tag(skb,
1016 napi_gro_receive(&fep->napi, skb);
1019 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1020 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1022 /* Clear the status flags for this buffer */
1023 status &= ~BD_ENET_RX_STATS;
1025 /* Mark the buffer empty */
1026 status |= BD_ENET_RX_EMPTY;
1027 bdp->cbd_sc = status;
1029 if (fep->bufdesc_ex) {
1030 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1032 ebdp->cbd_esc = BD_ENET_RX_INT;
1037 /* Update BD pointer to next entry */
1038 bdp = fec_enet_get_nextdesc(bdp, fep);
1040 /* Doing this here will keep the FEC running while we process
1041 * incoming frames. On a heavily loaded network, we should be
1042 * able to keep up at the expense of system resources.
1044 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1048 return pkt_received;
1052 fec_enet_interrupt(int irq, void *dev_id)
1054 struct net_device *ndev = dev_id;
1055 struct fec_enet_private *fep = netdev_priv(ndev);
1057 irqreturn_t ret = IRQ_NONE;
1060 int_events = readl(fep->hwp + FEC_IEVENT);
1061 writel(int_events, fep->hwp + FEC_IEVENT);
1063 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
1066 /* Disable the RX interrupt */
1067 if (napi_schedule_prep(&fep->napi)) {
1068 writel(FEC_RX_DISABLED_IMASK,
1069 fep->hwp + FEC_IMASK);
1070 __napi_schedule(&fep->napi);
1074 if (int_events & FEC_ENET_MII) {
1076 complete(&fep->mdio_done);
1078 } while (int_events);
1083 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1085 struct net_device *ndev = napi->dev;
1086 int pkts = fec_enet_rx(ndev, budget);
1087 struct fec_enet_private *fep = netdev_priv(ndev);
1091 if (pkts < budget) {
1092 napi_complete(napi);
1093 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1098 /* ------------------------------------------------------------------------- */
1099 static void fec_get_mac(struct net_device *ndev)
1101 struct fec_enet_private *fep = netdev_priv(ndev);
1102 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1103 unsigned char *iap, tmpaddr[ETH_ALEN];
1106 * try to get mac address in following order:
1108 * 1) module parameter via kernel command line in form
1109 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1114 * 2) from device tree data
1116 if (!is_valid_ether_addr(iap)) {
1117 struct device_node *np = fep->pdev->dev.of_node;
1119 const char *mac = of_get_mac_address(np);
1121 iap = (unsigned char *) mac;
1126 * 3) from flash or fuse (via platform data)
1128 if (!is_valid_ether_addr(iap)) {
1131 iap = (unsigned char *)FEC_FLASHMAC;
1134 iap = (unsigned char *)&pdata->mac;
1139 * 4) FEC mac registers set by bootloader
1141 if (!is_valid_ether_addr(iap)) {
1142 *((__be32 *) &tmpaddr[0]) =
1143 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1144 *((__be16 *) &tmpaddr[4]) =
1145 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1150 * 5) random mac address
1152 if (!is_valid_ether_addr(iap)) {
1153 /* Report it and use a random ethernet address instead */
1154 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1155 eth_hw_addr_random(ndev);
1156 netdev_info(ndev, "Using random MAC address: %pM\n",
1161 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1163 /* Adjust MAC if using macaddr */
1165 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1168 /* ------------------------------------------------------------------------- */
1173 static void fec_enet_adjust_link(struct net_device *ndev)
1175 struct fec_enet_private *fep = netdev_priv(ndev);
1176 struct phy_device *phy_dev = fep->phy_dev;
1177 int status_change = 0;
1179 /* Prevent a state halted on mii error */
1180 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1181 phy_dev->state = PHY_RESUMING;
1185 if (phy_dev->link) {
1187 fep->link = phy_dev->link;
1191 if (fep->full_duplex != phy_dev->duplex)
1194 if (phy_dev->speed != fep->speed) {
1195 fep->speed = phy_dev->speed;
1199 /* if any of the above changed restart the FEC */
1201 fec_restart(ndev, phy_dev->duplex);
1205 fep->link = phy_dev->link;
1211 phy_print_status(phy_dev);
1214 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1216 struct fec_enet_private *fep = bus->priv;
1217 unsigned long time_left;
1219 fep->mii_timeout = 0;
1220 init_completion(&fep->mdio_done);
1222 /* start a read op */
1223 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1224 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1225 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1227 /* wait for end of transfer */
1228 time_left = wait_for_completion_timeout(&fep->mdio_done,
1229 usecs_to_jiffies(FEC_MII_TIMEOUT));
1230 if (time_left == 0) {
1231 fep->mii_timeout = 1;
1232 netdev_err(fep->netdev, "MDIO read timeout\n");
1237 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1240 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1243 struct fec_enet_private *fep = bus->priv;
1244 unsigned long time_left;
1246 fep->mii_timeout = 0;
1247 init_completion(&fep->mdio_done);
1249 /* start a write op */
1250 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1251 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1252 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1253 fep->hwp + FEC_MII_DATA);
1255 /* wait for end of transfer */
1256 time_left = wait_for_completion_timeout(&fep->mdio_done,
1257 usecs_to_jiffies(FEC_MII_TIMEOUT));
1258 if (time_left == 0) {
1259 fep->mii_timeout = 1;
1260 netdev_err(fep->netdev, "MDIO write timeout\n");
1267 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1269 struct fec_enet_private *fep = netdev_priv(ndev);
1273 ret = clk_prepare_enable(fep->clk_ahb);
1276 ret = clk_prepare_enable(fep->clk_ipg);
1278 goto failed_clk_ipg;
1279 if (fep->clk_enet_out) {
1280 ret = clk_prepare_enable(fep->clk_enet_out);
1282 goto failed_clk_enet_out;
1285 ret = clk_prepare_enable(fep->clk_ptp);
1287 goto failed_clk_ptp;
1290 clk_disable_unprepare(fep->clk_ahb);
1291 clk_disable_unprepare(fep->clk_ipg);
1292 if (fep->clk_enet_out)
1293 clk_disable_unprepare(fep->clk_enet_out);
1295 clk_disable_unprepare(fep->clk_ptp);
1300 if (fep->clk_enet_out)
1301 clk_disable_unprepare(fep->clk_enet_out);
1302 failed_clk_enet_out:
1303 clk_disable_unprepare(fep->clk_ipg);
1305 clk_disable_unprepare(fep->clk_ahb);
1310 static int fec_enet_mii_probe(struct net_device *ndev)
1312 struct fec_enet_private *fep = netdev_priv(ndev);
1313 const struct platform_device_id *id_entry =
1314 platform_get_device_id(fep->pdev);
1315 struct phy_device *phy_dev = NULL;
1316 char mdio_bus_id[MII_BUS_ID_SIZE];
1317 char phy_name[MII_BUS_ID_SIZE + 3];
1319 int dev_id = fep->dev_id;
1321 fep->phy_dev = NULL;
1323 /* check for attached phy */
1324 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1325 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1327 if (fep->mii_bus->phy_map[phy_id] == NULL)
1329 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1333 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1337 if (phy_id >= PHY_MAX_ADDR) {
1338 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1339 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1343 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1344 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1345 fep->phy_interface);
1346 if (IS_ERR(phy_dev)) {
1347 netdev_err(ndev, "could not attach to PHY\n");
1348 return PTR_ERR(phy_dev);
1351 /* mask with MAC supported features */
1352 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1353 phy_dev->supported &= PHY_GBIT_FEATURES;
1354 #if !defined(CONFIG_M5272)
1355 phy_dev->supported |= SUPPORTED_Pause;
1359 phy_dev->supported &= PHY_BASIC_FEATURES;
1361 phy_dev->advertising = phy_dev->supported;
1363 fep->phy_dev = phy_dev;
1365 fep->full_duplex = 0;
1367 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1368 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1374 static int fec_enet_mii_init(struct platform_device *pdev)
1376 static struct mii_bus *fec0_mii_bus;
1377 struct net_device *ndev = platform_get_drvdata(pdev);
1378 struct fec_enet_private *fep = netdev_priv(ndev);
1379 const struct platform_device_id *id_entry =
1380 platform_get_device_id(fep->pdev);
1381 int err = -ENXIO, i;
1384 * The dual fec interfaces are not equivalent with enet-mac.
1385 * Here are the differences:
1387 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1388 * - fec0 acts as the 1588 time master while fec1 is slave
1389 * - external phys can only be configured by fec0
1391 * That is to say fec1 can not work independently. It only works
1392 * when fec0 is working. The reason behind this design is that the
1393 * second interface is added primarily for Switch mode.
1395 * Because of the last point above, both phys are attached on fec0
1396 * mdio interface in board design, and need to be configured by
1399 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1400 /* fec1 uses fec0 mii_bus */
1401 if (mii_cnt && fec0_mii_bus) {
1402 fep->mii_bus = fec0_mii_bus;
1409 fep->mii_timeout = 0;
1412 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1414 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1415 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1416 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1419 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1420 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1422 fep->phy_speed <<= 1;
1423 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1425 fep->mii_bus = mdiobus_alloc();
1426 if (fep->mii_bus == NULL) {
1431 fep->mii_bus->name = "fec_enet_mii_bus";
1432 fep->mii_bus->read = fec_enet_mdio_read;
1433 fep->mii_bus->write = fec_enet_mdio_write;
1434 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1435 pdev->name, fep->dev_id + 1);
1436 fep->mii_bus->priv = fep;
1437 fep->mii_bus->parent = &pdev->dev;
1439 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1440 if (!fep->mii_bus->irq) {
1442 goto err_out_free_mdiobus;
1445 for (i = 0; i < PHY_MAX_ADDR; i++)
1446 fep->mii_bus->irq[i] = PHY_POLL;
1448 if (mdiobus_register(fep->mii_bus))
1449 goto err_out_free_mdio_irq;
1453 /* save fec0 mii_bus */
1454 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1455 fec0_mii_bus = fep->mii_bus;
1459 err_out_free_mdio_irq:
1460 kfree(fep->mii_bus->irq);
1461 err_out_free_mdiobus:
1462 mdiobus_free(fep->mii_bus);
1467 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1469 if (--mii_cnt == 0) {
1470 mdiobus_unregister(fep->mii_bus);
1471 kfree(fep->mii_bus->irq);
1472 mdiobus_free(fep->mii_bus);
1476 static int fec_enet_get_settings(struct net_device *ndev,
1477 struct ethtool_cmd *cmd)
1479 struct fec_enet_private *fep = netdev_priv(ndev);
1480 struct phy_device *phydev = fep->phy_dev;
1485 return phy_ethtool_gset(phydev, cmd);
1488 static int fec_enet_set_settings(struct net_device *ndev,
1489 struct ethtool_cmd *cmd)
1491 struct fec_enet_private *fep = netdev_priv(ndev);
1492 struct phy_device *phydev = fep->phy_dev;
1497 return phy_ethtool_sset(phydev, cmd);
1500 static void fec_enet_get_drvinfo(struct net_device *ndev,
1501 struct ethtool_drvinfo *info)
1503 struct fec_enet_private *fep = netdev_priv(ndev);
1505 strlcpy(info->driver, fep->pdev->dev.driver->name,
1506 sizeof(info->driver));
1507 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1508 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1511 static int fec_enet_get_ts_info(struct net_device *ndev,
1512 struct ethtool_ts_info *info)
1514 struct fec_enet_private *fep = netdev_priv(ndev);
1516 if (fep->bufdesc_ex) {
1518 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1519 SOF_TIMESTAMPING_RX_SOFTWARE |
1520 SOF_TIMESTAMPING_SOFTWARE |
1521 SOF_TIMESTAMPING_TX_HARDWARE |
1522 SOF_TIMESTAMPING_RX_HARDWARE |
1523 SOF_TIMESTAMPING_RAW_HARDWARE;
1525 info->phc_index = ptp_clock_index(fep->ptp_clock);
1527 info->phc_index = -1;
1529 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1530 (1 << HWTSTAMP_TX_ON);
1532 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1533 (1 << HWTSTAMP_FILTER_ALL);
1536 return ethtool_op_get_ts_info(ndev, info);
1540 #if !defined(CONFIG_M5272)
1542 static void fec_enet_get_pauseparam(struct net_device *ndev,
1543 struct ethtool_pauseparam *pause)
1545 struct fec_enet_private *fep = netdev_priv(ndev);
1547 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1548 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1549 pause->rx_pause = pause->tx_pause;
1552 static int fec_enet_set_pauseparam(struct net_device *ndev,
1553 struct ethtool_pauseparam *pause)
1555 struct fec_enet_private *fep = netdev_priv(ndev);
1557 if (pause->tx_pause != pause->rx_pause) {
1559 "hardware only support enable/disable both tx and rx");
1563 fep->pause_flag = 0;
1565 /* tx pause must be same as rx pause */
1566 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1567 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1569 if (pause->rx_pause || pause->autoneg) {
1570 fep->phy_dev->supported |= ADVERTISED_Pause;
1571 fep->phy_dev->advertising |= ADVERTISED_Pause;
1573 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1574 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1577 if (pause->autoneg) {
1578 if (netif_running(ndev))
1580 phy_start_aneg(fep->phy_dev);
1582 if (netif_running(ndev))
1583 fec_restart(ndev, 0);
1588 static const struct fec_stat {
1589 char name[ETH_GSTRING_LEN];
1593 { "tx_dropped", RMON_T_DROP },
1594 { "tx_packets", RMON_T_PACKETS },
1595 { "tx_broadcast", RMON_T_BC_PKT },
1596 { "tx_multicast", RMON_T_MC_PKT },
1597 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1598 { "tx_undersize", RMON_T_UNDERSIZE },
1599 { "tx_oversize", RMON_T_OVERSIZE },
1600 { "tx_fragment", RMON_T_FRAG },
1601 { "tx_jabber", RMON_T_JAB },
1602 { "tx_collision", RMON_T_COL },
1603 { "tx_64byte", RMON_T_P64 },
1604 { "tx_65to127byte", RMON_T_P65TO127 },
1605 { "tx_128to255byte", RMON_T_P128TO255 },
1606 { "tx_256to511byte", RMON_T_P256TO511 },
1607 { "tx_512to1023byte", RMON_T_P512TO1023 },
1608 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1609 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1610 { "tx_octets", RMON_T_OCTETS },
1613 { "IEEE_tx_drop", IEEE_T_DROP },
1614 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1615 { "IEEE_tx_1col", IEEE_T_1COL },
1616 { "IEEE_tx_mcol", IEEE_T_MCOL },
1617 { "IEEE_tx_def", IEEE_T_DEF },
1618 { "IEEE_tx_lcol", IEEE_T_LCOL },
1619 { "IEEE_tx_excol", IEEE_T_EXCOL },
1620 { "IEEE_tx_macerr", IEEE_T_MACERR },
1621 { "IEEE_tx_cserr", IEEE_T_CSERR },
1622 { "IEEE_tx_sqe", IEEE_T_SQE },
1623 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1624 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1627 { "rx_packets", RMON_R_PACKETS },
1628 { "rx_broadcast", RMON_R_BC_PKT },
1629 { "rx_multicast", RMON_R_MC_PKT },
1630 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1631 { "rx_undersize", RMON_R_UNDERSIZE },
1632 { "rx_oversize", RMON_R_OVERSIZE },
1633 { "rx_fragment", RMON_R_FRAG },
1634 { "rx_jabber", RMON_R_JAB },
1635 { "rx_64byte", RMON_R_P64 },
1636 { "rx_65to127byte", RMON_R_P65TO127 },
1637 { "rx_128to255byte", RMON_R_P128TO255 },
1638 { "rx_256to511byte", RMON_R_P256TO511 },
1639 { "rx_512to1023byte", RMON_R_P512TO1023 },
1640 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1641 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1642 { "rx_octets", RMON_R_OCTETS },
1645 { "IEEE_rx_drop", IEEE_R_DROP },
1646 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1647 { "IEEE_rx_crc", IEEE_R_CRC },
1648 { "IEEE_rx_align", IEEE_R_ALIGN },
1649 { "IEEE_rx_macerr", IEEE_R_MACERR },
1650 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1651 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1654 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1655 struct ethtool_stats *stats, u64 *data)
1657 struct fec_enet_private *fep = netdev_priv(dev);
1660 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1661 data[i] = readl(fep->hwp + fec_stats[i].offset);
1664 static void fec_enet_get_strings(struct net_device *netdev,
1665 u32 stringset, u8 *data)
1668 switch (stringset) {
1670 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1671 memcpy(data + i * ETH_GSTRING_LEN,
1672 fec_stats[i].name, ETH_GSTRING_LEN);
1677 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1681 return ARRAY_SIZE(fec_stats);
1686 #endif /* !defined(CONFIG_M5272) */
1688 static int fec_enet_nway_reset(struct net_device *dev)
1690 struct fec_enet_private *fep = netdev_priv(dev);
1691 struct phy_device *phydev = fep->phy_dev;
1696 return genphy_restart_aneg(phydev);
1699 static const struct ethtool_ops fec_enet_ethtool_ops = {
1700 #if !defined(CONFIG_M5272)
1701 .get_pauseparam = fec_enet_get_pauseparam,
1702 .set_pauseparam = fec_enet_set_pauseparam,
1704 .get_settings = fec_enet_get_settings,
1705 .set_settings = fec_enet_set_settings,
1706 .get_drvinfo = fec_enet_get_drvinfo,
1707 .get_link = ethtool_op_get_link,
1708 .get_ts_info = fec_enet_get_ts_info,
1709 .nway_reset = fec_enet_nway_reset,
1710 #ifndef CONFIG_M5272
1711 .get_ethtool_stats = fec_enet_get_ethtool_stats,
1712 .get_strings = fec_enet_get_strings,
1713 .get_sset_count = fec_enet_get_sset_count,
1717 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1719 struct fec_enet_private *fep = netdev_priv(ndev);
1720 struct phy_device *phydev = fep->phy_dev;
1722 if (!netif_running(ndev))
1728 if (fep->bufdesc_ex) {
1729 if (cmd == SIOCSHWTSTAMP)
1730 return fec_ptp_set(ndev, rq);
1731 if (cmd == SIOCGHWTSTAMP)
1732 return fec_ptp_get(ndev, rq);
1735 return phy_mii_ioctl(phydev, rq, cmd);
1738 static void fec_enet_free_buffers(struct net_device *ndev)
1740 struct fec_enet_private *fep = netdev_priv(ndev);
1742 struct sk_buff *skb;
1743 struct bufdesc *bdp;
1745 bdp = fep->rx_bd_base;
1746 for (i = 0; i < fep->rx_ring_size; i++) {
1747 skb = fep->rx_skbuff[i];
1749 if (bdp->cbd_bufaddr)
1750 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1751 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1754 bdp = fec_enet_get_nextdesc(bdp, fep);
1757 bdp = fep->tx_bd_base;
1758 for (i = 0; i < fep->tx_ring_size; i++)
1759 kfree(fep->tx_bounce[i]);
1762 static int fec_enet_alloc_buffers(struct net_device *ndev)
1764 struct fec_enet_private *fep = netdev_priv(ndev);
1766 struct sk_buff *skb;
1767 struct bufdesc *bdp;
1769 bdp = fep->rx_bd_base;
1770 for (i = 0; i < fep->rx_ring_size; i++) {
1771 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1773 fec_enet_free_buffers(ndev);
1776 fep->rx_skbuff[i] = skb;
1778 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1779 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1780 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1781 fec_enet_free_buffers(ndev);
1782 if (net_ratelimit())
1783 netdev_err(ndev, "Rx DMA memory map failed\n");
1786 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1788 if (fep->bufdesc_ex) {
1789 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1790 ebdp->cbd_esc = BD_ENET_RX_INT;
1793 bdp = fec_enet_get_nextdesc(bdp, fep);
1796 /* Set the last buffer to wrap. */
1797 bdp = fec_enet_get_prevdesc(bdp, fep);
1798 bdp->cbd_sc |= BD_SC_WRAP;
1800 bdp = fep->tx_bd_base;
1801 for (i = 0; i < fep->tx_ring_size; i++) {
1802 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1805 bdp->cbd_bufaddr = 0;
1807 if (fep->bufdesc_ex) {
1808 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1809 ebdp->cbd_esc = BD_ENET_TX_INT;
1812 bdp = fec_enet_get_nextdesc(bdp, fep);
1815 /* Set the last buffer to wrap. */
1816 bdp = fec_enet_get_prevdesc(bdp, fep);
1817 bdp->cbd_sc |= BD_SC_WRAP;
1823 fec_enet_open(struct net_device *ndev)
1825 struct fec_enet_private *fep = netdev_priv(ndev);
1828 pinctrl_pm_select_default_state(&fep->pdev->dev);
1829 ret = fec_enet_clk_enable(ndev, true);
1833 /* I should reset the ring buffers here, but I don't yet know
1834 * a simple way to do that.
1837 ret = fec_enet_alloc_buffers(ndev);
1841 /* Probe and connect to PHY when open the interface */
1842 ret = fec_enet_mii_probe(ndev);
1844 fec_enet_free_buffers(ndev);
1848 napi_enable(&fep->napi);
1849 phy_start(fep->phy_dev);
1850 netif_start_queue(ndev);
1856 fec_enet_close(struct net_device *ndev)
1858 struct fec_enet_private *fep = netdev_priv(ndev);
1860 /* Don't know what to do yet. */
1861 napi_disable(&fep->napi);
1863 netif_stop_queue(ndev);
1867 phy_stop(fep->phy_dev);
1868 phy_disconnect(fep->phy_dev);
1871 fec_enet_clk_enable(ndev, false);
1872 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
1873 fec_enet_free_buffers(ndev);
1878 /* Set or clear the multicast filter for this adaptor.
1879 * Skeleton taken from sunlance driver.
1880 * The CPM Ethernet implementation allows Multicast as well as individual
1881 * MAC address filtering. Some of the drivers check to make sure it is
1882 * a group multicast address, and discard those that are not. I guess I
1883 * will do the same for now, but just remove the test if you want
1884 * individual filtering as well (do the upper net layers want or support
1885 * this kind of feature?).
1888 #define HASH_BITS 6 /* #bits in hash */
1889 #define CRC32_POLY 0xEDB88320
1891 static void set_multicast_list(struct net_device *ndev)
1893 struct fec_enet_private *fep = netdev_priv(ndev);
1894 struct netdev_hw_addr *ha;
1895 unsigned int i, bit, data, crc, tmp;
1898 if (ndev->flags & IFF_PROMISC) {
1899 tmp = readl(fep->hwp + FEC_R_CNTRL);
1901 writel(tmp, fep->hwp + FEC_R_CNTRL);
1905 tmp = readl(fep->hwp + FEC_R_CNTRL);
1907 writel(tmp, fep->hwp + FEC_R_CNTRL);
1909 if (ndev->flags & IFF_ALLMULTI) {
1910 /* Catch all multicast addresses, so set the
1913 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1914 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1919 /* Clear filter and add the addresses in hash register
1921 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1922 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1924 netdev_for_each_mc_addr(ha, ndev) {
1925 /* calculate crc32 value of mac address */
1928 for (i = 0; i < ndev->addr_len; i++) {
1930 for (bit = 0; bit < 8; bit++, data >>= 1) {
1932 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1936 /* only upper 6 bits (HASH_BITS) are used
1937 * which point to specific bit in he hash registers
1939 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1942 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1943 tmp |= 1 << (hash - 32);
1944 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1946 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1948 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1953 /* Set a MAC change in hardware. */
1955 fec_set_mac_address(struct net_device *ndev, void *p)
1957 struct fec_enet_private *fep = netdev_priv(ndev);
1958 struct sockaddr *addr = p;
1961 if (!is_valid_ether_addr(addr->sa_data))
1962 return -EADDRNOTAVAIL;
1963 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1966 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1967 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1968 fep->hwp + FEC_ADDR_LOW);
1969 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1970 fep->hwp + FEC_ADDR_HIGH);
1974 #ifdef CONFIG_NET_POLL_CONTROLLER
1976 * fec_poll_controller - FEC Poll controller function
1977 * @dev: The FEC network adapter
1979 * Polled functionality used by netconsole and others in non interrupt mode
1982 static void fec_poll_controller(struct net_device *dev)
1985 struct fec_enet_private *fep = netdev_priv(dev);
1987 for (i = 0; i < FEC_IRQ_NUM; i++) {
1988 if (fep->irq[i] > 0) {
1989 disable_irq(fep->irq[i]);
1990 fec_enet_interrupt(fep->irq[i], dev);
1991 enable_irq(fep->irq[i]);
1997 static int fec_set_features(struct net_device *netdev,
1998 netdev_features_t features)
2000 struct fec_enet_private *fep = netdev_priv(netdev);
2001 netdev_features_t changed = features ^ netdev->features;
2003 netdev->features = features;
2005 /* Receive checksum has been changed */
2006 if (changed & NETIF_F_RXCSUM) {
2007 if (features & NETIF_F_RXCSUM)
2008 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2010 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2012 if (netif_running(netdev)) {
2014 fec_restart(netdev, fep->phy_dev->duplex);
2015 netif_wake_queue(netdev);
2017 fec_restart(netdev, fep->phy_dev->duplex);
2024 static const struct net_device_ops fec_netdev_ops = {
2025 .ndo_open = fec_enet_open,
2026 .ndo_stop = fec_enet_close,
2027 .ndo_start_xmit = fec_enet_start_xmit,
2028 .ndo_set_rx_mode = set_multicast_list,
2029 .ndo_change_mtu = eth_change_mtu,
2030 .ndo_validate_addr = eth_validate_addr,
2031 .ndo_tx_timeout = fec_timeout,
2032 .ndo_set_mac_address = fec_set_mac_address,
2033 .ndo_do_ioctl = fec_enet_ioctl,
2034 #ifdef CONFIG_NET_POLL_CONTROLLER
2035 .ndo_poll_controller = fec_poll_controller,
2037 .ndo_set_features = fec_set_features,
2041 * XXX: We need to clean up on failure exits here.
2044 static int fec_enet_init(struct net_device *ndev)
2046 struct fec_enet_private *fep = netdev_priv(ndev);
2047 const struct platform_device_id *id_entry =
2048 platform_get_device_id(fep->pdev);
2049 struct bufdesc *cbd_base;
2051 /* Allocate memory for buffer descriptors. */
2052 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
2057 memset(cbd_base, 0, PAGE_SIZE);
2061 /* Get the Ethernet address */
2063 /* make sure MAC we just acquired is programmed into the hw */
2064 fec_set_mac_address(ndev, NULL);
2066 /* init the tx & rx ring size */
2067 fep->tx_ring_size = TX_RING_SIZE;
2068 fep->rx_ring_size = RX_RING_SIZE;
2070 /* Set receive and transmit descriptor base. */
2071 fep->rx_bd_base = cbd_base;
2072 if (fep->bufdesc_ex) {
2073 fep->tx_bd_base = (struct bufdesc *)
2074 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
2075 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2077 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
2078 fep->bufdesc_size = sizeof(struct bufdesc);
2081 /* The FEC Ethernet specific entries in the device structure */
2082 ndev->watchdog_timeo = TX_TIMEOUT;
2083 ndev->netdev_ops = &fec_netdev_ops;
2084 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2086 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2087 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
2089 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) {
2090 /* enable hw VLAN support */
2091 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2092 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2095 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
2096 /* enable hw accelerator */
2097 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2099 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2101 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2104 fec_restart(ndev, 0);
2110 static void fec_reset_phy(struct platform_device *pdev)
2114 struct device_node *np = pdev->dev.of_node;
2119 of_property_read_u32(np, "phy-reset-duration", &msec);
2120 /* A sane reset duration should not be longer than 1s */
2124 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2125 if (!gpio_is_valid(phy_reset))
2128 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2129 GPIOF_OUT_INIT_LOW, "phy-reset");
2131 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2135 gpio_set_value(phy_reset, 1);
2137 #else /* CONFIG_OF */
2138 static void fec_reset_phy(struct platform_device *pdev)
2141 * In case of platform probe, the reset has been done
2145 #endif /* CONFIG_OF */
2148 fec_probe(struct platform_device *pdev)
2150 struct fec_enet_private *fep;
2151 struct fec_platform_data *pdata;
2152 struct net_device *ndev;
2153 int i, irq, ret = 0;
2155 const struct of_device_id *of_id;
2158 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2160 pdev->id_entry = of_id->data;
2162 /* Init network device */
2163 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2167 SET_NETDEV_DEV(ndev, &pdev->dev);
2169 /* setup board info structure */
2170 fep = netdev_priv(ndev);
2172 #if !defined(CONFIG_M5272)
2173 /* default enable pause frame auto negotiation */
2174 if (pdev->id_entry &&
2175 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2176 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2179 /* Select default pin state */
2180 pinctrl_pm_select_default_state(&pdev->dev);
2182 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2183 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2184 if (IS_ERR(fep->hwp)) {
2185 ret = PTR_ERR(fep->hwp);
2186 goto failed_ioremap;
2190 fep->dev_id = dev_id++;
2192 fep->bufdesc_ex = 0;
2194 platform_set_drvdata(pdev, ndev);
2196 ret = of_get_phy_mode(pdev->dev.of_node);
2198 pdata = dev_get_platdata(&pdev->dev);
2200 fep->phy_interface = pdata->phy;
2202 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2204 fep->phy_interface = ret;
2207 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2208 if (IS_ERR(fep->clk_ipg)) {
2209 ret = PTR_ERR(fep->clk_ipg);
2213 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2214 if (IS_ERR(fep->clk_ahb)) {
2215 ret = PTR_ERR(fep->clk_ahb);
2219 /* enet_out is optional, depends on board */
2220 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2221 if (IS_ERR(fep->clk_enet_out))
2222 fep->clk_enet_out = NULL;
2224 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2226 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2227 if (IS_ERR(fep->clk_ptp)) {
2228 fep->clk_ptp = NULL;
2229 fep->bufdesc_ex = 0;
2232 ret = fec_enet_clk_enable(ndev, true);
2236 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2237 if (!IS_ERR(fep->reg_phy)) {
2238 ret = regulator_enable(fep->reg_phy);
2241 "Failed to enable phy regulator: %d\n", ret);
2242 goto failed_regulator;
2245 fep->reg_phy = NULL;
2248 fec_reset_phy(pdev);
2250 if (fep->bufdesc_ex)
2253 ret = fec_enet_init(ndev);
2257 for (i = 0; i < FEC_IRQ_NUM; i++) {
2258 irq = platform_get_irq(pdev, i);
2265 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2266 0, pdev->name, ndev);
2271 ret = fec_enet_mii_init(pdev);
2273 goto failed_mii_init;
2275 /* Carrier starts down, phylib will bring it up */
2276 netif_carrier_off(ndev);
2277 fec_enet_clk_enable(ndev, false);
2278 pinctrl_pm_select_sleep_state(&pdev->dev);
2280 ret = register_netdev(ndev);
2282 goto failed_register;
2284 if (fep->bufdesc_ex && fep->ptp_clock)
2285 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2287 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2291 fec_enet_mii_remove(fep);
2296 regulator_disable(fep->reg_phy);
2298 fec_enet_clk_enable(ndev, false);
2307 fec_drv_remove(struct platform_device *pdev)
2309 struct net_device *ndev = platform_get_drvdata(pdev);
2310 struct fec_enet_private *fep = netdev_priv(ndev);
2312 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2313 unregister_netdev(ndev);
2314 fec_enet_mii_remove(fep);
2315 del_timer_sync(&fep->time_keep);
2317 regulator_disable(fep->reg_phy);
2319 ptp_clock_unregister(fep->ptp_clock);
2320 fec_enet_clk_enable(ndev, false);
2326 #ifdef CONFIG_PM_SLEEP
2328 fec_suspend(struct device *dev)
2330 struct net_device *ndev = dev_get_drvdata(dev);
2331 struct fec_enet_private *fep = netdev_priv(ndev);
2333 if (netif_running(ndev)) {
2335 netif_device_detach(ndev);
2337 fec_enet_clk_enable(ndev, false);
2338 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2341 regulator_disable(fep->reg_phy);
2347 fec_resume(struct device *dev)
2349 struct net_device *ndev = dev_get_drvdata(dev);
2350 struct fec_enet_private *fep = netdev_priv(ndev);
2354 ret = regulator_enable(fep->reg_phy);
2359 pinctrl_pm_select_default_state(&fep->pdev->dev);
2360 ret = fec_enet_clk_enable(ndev, true);
2364 if (netif_running(ndev)) {
2365 fec_restart(ndev, fep->full_duplex);
2366 netif_device_attach(ndev);
2373 regulator_disable(fep->reg_phy);
2376 #endif /* CONFIG_PM_SLEEP */
2378 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2380 static struct platform_driver fec_driver = {
2382 .name = DRIVER_NAME,
2383 .owner = THIS_MODULE,
2385 .of_match_table = fec_dt_ids,
2387 .id_table = fec_devtype,
2389 .remove = fec_drv_remove,
2392 module_platform_driver(fec_driver);
2394 MODULE_ALIAS("platform:"DRIVER_NAME);
2395 MODULE_LICENSE("GPL");