1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/delay.h>
74 #include <linux/netdevice.h>
75 #include <linux/etherdevice.h>
76 #include <linux/skbuff.h>
77 #include <linux/if_vlan.h>
78 #include <linux/spinlock.h>
80 #include <linux/of_address.h>
81 #include <linux/of_irq.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
88 #include <linux/net_tstamp.h>
93 #include <asm/mpc85xx.h>
96 #include <asm/uaccess.h>
97 #include <linux/module.h>
98 #include <linux/dma-mapping.h>
99 #include <linux/crc32.h>
100 #include <linux/mii.h>
101 #include <linux/phy.h>
102 #include <linux/phy_fixed.h>
103 #include <linux/of.h>
104 #include <linux/of_net.h>
105 #include <linux/of_address.h>
106 #include <linux/of_irq.h>
110 #define TX_TIMEOUT (1*HZ)
112 const char gfar_driver_version[] = "2.0";
114 static int gfar_enet_open(struct net_device *dev);
115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
116 static void gfar_reset_task(struct work_struct *work);
117 static void gfar_timeout(struct net_device *dev);
118 static int gfar_close(struct net_device *dev);
119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
121 static int gfar_set_mac_address(struct net_device *dev);
122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123 static irqreturn_t gfar_error(int irq, void *dev_id);
124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
126 static void adjust_link(struct net_device *dev);
127 static noinline void gfar_update_link_state(struct gfar_private *priv);
128 static int init_phy(struct net_device *dev);
129 static int gfar_probe(struct platform_device *ofdev);
130 static int gfar_remove(struct platform_device *ofdev);
131 static void free_skb_resources(struct gfar_private *priv);
132 static void gfar_set_multi(struct net_device *dev);
133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134 static void gfar_configure_serdes(struct net_device *dev);
135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
139 #ifdef CONFIG_NET_POLL_CONTROLLER
140 static void gfar_netpoll(struct net_device *dev);
142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
145 static void gfar_halt_nodisable(struct gfar_private *priv);
146 static void gfar_clear_exact_match(struct net_device *dev);
147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
153 MODULE_LICENSE("GPL");
155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
160 bdp->bufPtr = cpu_to_be32(buf);
162 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
163 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
164 lstatus |= BD_LFLAG(RXBD_WRAP);
168 bdp->lstatus = cpu_to_be32(lstatus);
171 static void gfar_init_bds(struct net_device *ndev)
173 struct gfar_private *priv = netdev_priv(ndev);
174 struct gfar __iomem *regs = priv->gfargrp[0].regs;
175 struct gfar_priv_tx_q *tx_queue = NULL;
176 struct gfar_priv_rx_q *rx_queue = NULL;
181 for (i = 0; i < priv->num_tx_queues; i++) {
182 tx_queue = priv->tx_queue[i];
183 /* Initialize some variables in our dev structure */
184 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
185 tx_queue->dirty_tx = tx_queue->tx_bd_base;
186 tx_queue->cur_tx = tx_queue->tx_bd_base;
187 tx_queue->skb_curtx = 0;
188 tx_queue->skb_dirtytx = 0;
190 /* Initialize Transmit Descriptor Ring */
191 txbdp = tx_queue->tx_bd_base;
192 for (j = 0; j < tx_queue->tx_ring_size; j++) {
198 /* Set the last descriptor in the ring to indicate wrap */
200 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
204 rfbptr = ®s->rfbptr0;
205 for (i = 0; i < priv->num_rx_queues; i++) {
206 rx_queue = priv->rx_queue[i];
208 rx_queue->next_to_clean = 0;
209 rx_queue->next_to_use = 0;
210 rx_queue->next_to_alloc = 0;
212 /* make sure next_to_clean != next_to_use after this
213 * by leaving at least 1 unused descriptor
215 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
217 rx_queue->rfbptr = rfbptr;
222 static int gfar_alloc_skb_resources(struct net_device *ndev)
227 struct gfar_private *priv = netdev_priv(ndev);
228 struct device *dev = priv->dev;
229 struct gfar_priv_tx_q *tx_queue = NULL;
230 struct gfar_priv_rx_q *rx_queue = NULL;
232 priv->total_tx_ring_size = 0;
233 for (i = 0; i < priv->num_tx_queues; i++)
234 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
236 priv->total_rx_ring_size = 0;
237 for (i = 0; i < priv->num_rx_queues; i++)
238 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
240 /* Allocate memory for the buffer descriptors */
241 vaddr = dma_alloc_coherent(dev,
242 (priv->total_tx_ring_size *
243 sizeof(struct txbd8)) +
244 (priv->total_rx_ring_size *
245 sizeof(struct rxbd8)),
250 for (i = 0; i < priv->num_tx_queues; i++) {
251 tx_queue = priv->tx_queue[i];
252 tx_queue->tx_bd_base = vaddr;
253 tx_queue->tx_bd_dma_base = addr;
254 tx_queue->dev = ndev;
255 /* enet DMA only understands physical addresses */
256 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
257 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
260 /* Start the rx descriptor ring where the tx ring leaves off */
261 for (i = 0; i < priv->num_rx_queues; i++) {
262 rx_queue = priv->rx_queue[i];
263 rx_queue->rx_bd_base = vaddr;
264 rx_queue->rx_bd_dma_base = addr;
265 rx_queue->ndev = ndev;
267 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
268 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
271 /* Setup the skbuff rings */
272 for (i = 0; i < priv->num_tx_queues; i++) {
273 tx_queue = priv->tx_queue[i];
274 tx_queue->tx_skbuff =
275 kmalloc_array(tx_queue->tx_ring_size,
276 sizeof(*tx_queue->tx_skbuff),
278 if (!tx_queue->tx_skbuff)
281 for (j = 0; j < tx_queue->tx_ring_size; j++)
282 tx_queue->tx_skbuff[j] = NULL;
285 for (i = 0; i < priv->num_rx_queues; i++) {
286 rx_queue = priv->rx_queue[i];
287 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
288 sizeof(*rx_queue->rx_buff),
290 if (!rx_queue->rx_buff)
299 free_skb_resources(priv);
303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
305 struct gfar __iomem *regs = priv->gfargrp[0].regs;
309 baddr = ®s->tbase0;
310 for (i = 0; i < priv->num_tx_queues; i++) {
311 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
315 baddr = ®s->rbase0;
316 for (i = 0; i < priv->num_rx_queues; i++) {
317 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
322 static void gfar_init_rqprm(struct gfar_private *priv)
324 struct gfar __iomem *regs = priv->gfargrp[0].regs;
328 baddr = ®s->rqprm0;
329 for (i = 0; i < priv->num_rx_queues; i++) {
330 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
331 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
336 static void gfar_rx_offload_en(struct gfar_private *priv)
338 /* set this when rx hw offload (TOE) functions are being used */
339 priv->uses_rxfcb = 0;
341 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
342 priv->uses_rxfcb = 1;
344 if (priv->hwts_rx_en)
345 priv->uses_rxfcb = 1;
348 static void gfar_mac_rx_config(struct gfar_private *priv)
350 struct gfar __iomem *regs = priv->gfargrp[0].regs;
353 if (priv->rx_filer_enable) {
354 rctrl |= RCTRL_FILREN;
355 /* Program the RIR0 reg with the required distribution */
356 if (priv->poll_mode == GFAR_SQ_POLLING)
357 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
358 else /* GFAR_MQ_POLLING */
359 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
362 /* Restore PROMISC mode */
363 if (priv->ndev->flags & IFF_PROMISC)
366 if (priv->ndev->features & NETIF_F_RXCSUM)
367 rctrl |= RCTRL_CHECKSUMMING;
369 if (priv->extended_hash)
370 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
373 rctrl &= ~RCTRL_PAL_MASK;
374 rctrl |= RCTRL_PADDING(priv->padding);
377 /* Enable HW time stamping if requested from user space */
378 if (priv->hwts_rx_en)
379 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
381 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
382 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
384 /* Clear the LFC bit */
385 gfar_write(®s->rctrl, rctrl);
386 /* Init flow control threshold values */
387 gfar_init_rqprm(priv);
388 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL);
391 /* Init rctrl based on our settings */
392 gfar_write(®s->rctrl, rctrl);
395 static void gfar_mac_tx_config(struct gfar_private *priv)
397 struct gfar __iomem *regs = priv->gfargrp[0].regs;
400 if (priv->ndev->features & NETIF_F_IP_CSUM)
401 tctrl |= TCTRL_INIT_CSUM;
403 if (priv->prio_sched_en)
404 tctrl |= TCTRL_TXSCHED_PRIO;
406 tctrl |= TCTRL_TXSCHED_WRRS;
407 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
408 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
411 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
412 tctrl |= TCTRL_VLINS;
414 gfar_write(®s->tctrl, tctrl);
417 static void gfar_configure_coalescing(struct gfar_private *priv,
418 unsigned long tx_mask, unsigned long rx_mask)
420 struct gfar __iomem *regs = priv->gfargrp[0].regs;
423 if (priv->mode == MQ_MG_MODE) {
426 baddr = ®s->txic0;
427 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
428 gfar_write(baddr + i, 0);
429 if (likely(priv->tx_queue[i]->txcoalescing))
430 gfar_write(baddr + i, priv->tx_queue[i]->txic);
433 baddr = ®s->rxic0;
434 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
435 gfar_write(baddr + i, 0);
436 if (likely(priv->rx_queue[i]->rxcoalescing))
437 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
440 /* Backward compatible case -- even if we enable
441 * multiple queues, there's only single reg to program
443 gfar_write(®s->txic, 0);
444 if (likely(priv->tx_queue[0]->txcoalescing))
445 gfar_write(®s->txic, priv->tx_queue[0]->txic);
447 gfar_write(®s->rxic, 0);
448 if (unlikely(priv->rx_queue[0]->rxcoalescing))
449 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
453 void gfar_configure_coalescing_all(struct gfar_private *priv)
455 gfar_configure_coalescing(priv, 0xFF, 0xFF);
458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
460 struct gfar_private *priv = netdev_priv(dev);
461 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
462 unsigned long tx_packets = 0, tx_bytes = 0;
465 for (i = 0; i < priv->num_rx_queues; i++) {
466 rx_packets += priv->rx_queue[i]->stats.rx_packets;
467 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
468 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
471 dev->stats.rx_packets = rx_packets;
472 dev->stats.rx_bytes = rx_bytes;
473 dev->stats.rx_dropped = rx_dropped;
475 for (i = 0; i < priv->num_tx_queues; i++) {
476 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
477 tx_packets += priv->tx_queue[i]->stats.tx_packets;
480 dev->stats.tx_bytes = tx_bytes;
481 dev->stats.tx_packets = tx_packets;
486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
488 eth_mac_addr(dev, p);
490 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
495 static const struct net_device_ops gfar_netdev_ops = {
496 .ndo_open = gfar_enet_open,
497 .ndo_start_xmit = gfar_start_xmit,
498 .ndo_stop = gfar_close,
499 .ndo_change_mtu = gfar_change_mtu,
500 .ndo_set_features = gfar_set_features,
501 .ndo_set_rx_mode = gfar_set_multi,
502 .ndo_tx_timeout = gfar_timeout,
503 .ndo_do_ioctl = gfar_ioctl,
504 .ndo_get_stats = gfar_get_stats,
505 .ndo_set_mac_address = gfar_set_mac_addr,
506 .ndo_validate_addr = eth_validate_addr,
507 #ifdef CONFIG_NET_POLL_CONTROLLER
508 .ndo_poll_controller = gfar_netpoll,
512 static void gfar_ints_disable(struct gfar_private *priv)
515 for (i = 0; i < priv->num_grps; i++) {
516 struct gfar __iomem *regs = priv->gfargrp[i].regs;
518 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
520 /* Initialize IMASK */
521 gfar_write(®s->imask, IMASK_INIT_CLEAR);
525 static void gfar_ints_enable(struct gfar_private *priv)
528 for (i = 0; i < priv->num_grps; i++) {
529 struct gfar __iomem *regs = priv->gfargrp[i].regs;
530 /* Unmask the interrupts we look for */
531 gfar_write(®s->imask, IMASK_DEFAULT);
535 static int gfar_alloc_tx_queues(struct gfar_private *priv)
539 for (i = 0; i < priv->num_tx_queues; i++) {
540 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
542 if (!priv->tx_queue[i])
545 priv->tx_queue[i]->tx_skbuff = NULL;
546 priv->tx_queue[i]->qindex = i;
547 priv->tx_queue[i]->dev = priv->ndev;
548 spin_lock_init(&(priv->tx_queue[i]->txlock));
553 static int gfar_alloc_rx_queues(struct gfar_private *priv)
557 for (i = 0; i < priv->num_rx_queues; i++) {
558 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
560 if (!priv->rx_queue[i])
563 priv->rx_queue[i]->qindex = i;
564 priv->rx_queue[i]->ndev = priv->ndev;
569 static void gfar_free_tx_queues(struct gfar_private *priv)
573 for (i = 0; i < priv->num_tx_queues; i++)
574 kfree(priv->tx_queue[i]);
577 static void gfar_free_rx_queues(struct gfar_private *priv)
581 for (i = 0; i < priv->num_rx_queues; i++)
582 kfree(priv->rx_queue[i]);
585 static void unmap_group_regs(struct gfar_private *priv)
589 for (i = 0; i < MAXGROUPS; i++)
590 if (priv->gfargrp[i].regs)
591 iounmap(priv->gfargrp[i].regs);
594 static void free_gfar_dev(struct gfar_private *priv)
598 for (i = 0; i < priv->num_grps; i++)
599 for (j = 0; j < GFAR_NUM_IRQS; j++) {
600 kfree(priv->gfargrp[i].irqinfo[j]);
601 priv->gfargrp[i].irqinfo[j] = NULL;
604 free_netdev(priv->ndev);
607 static void disable_napi(struct gfar_private *priv)
611 for (i = 0; i < priv->num_grps; i++) {
612 napi_disable(&priv->gfargrp[i].napi_rx);
613 napi_disable(&priv->gfargrp[i].napi_tx);
617 static void enable_napi(struct gfar_private *priv)
621 for (i = 0; i < priv->num_grps; i++) {
622 napi_enable(&priv->gfargrp[i].napi_rx);
623 napi_enable(&priv->gfargrp[i].napi_tx);
627 static int gfar_parse_group(struct device_node *np,
628 struct gfar_private *priv, const char *model)
630 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
633 for (i = 0; i < GFAR_NUM_IRQS; i++) {
634 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
636 if (!grp->irqinfo[i])
640 grp->regs = of_iomap(np, 0);
644 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
646 /* If we aren't the FEC we have multiple interrupts */
647 if (model && strcasecmp(model, "FEC")) {
648 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
649 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
650 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
651 gfar_irq(grp, RX)->irq == NO_IRQ ||
652 gfar_irq(grp, ER)->irq == NO_IRQ)
657 spin_lock_init(&grp->grplock);
658 if (priv->mode == MQ_MG_MODE) {
659 u32 rxq_mask, txq_mask;
662 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
663 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
665 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
667 grp->rx_bit_map = rxq_mask ?
668 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
671 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
673 grp->tx_bit_map = txq_mask ?
674 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
677 if (priv->poll_mode == GFAR_SQ_POLLING) {
678 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
679 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
680 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
683 grp->rx_bit_map = 0xFF;
684 grp->tx_bit_map = 0xFF;
687 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
688 * right to left, so we need to revert the 8 bits to get the q index
690 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
691 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
693 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
694 * also assign queues to groups
696 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
698 grp->rx_queue = priv->rx_queue[i];
699 grp->num_rx_queues++;
700 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
701 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
702 priv->rx_queue[i]->grp = grp;
705 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
707 grp->tx_queue = priv->tx_queue[i];
708 grp->num_tx_queues++;
709 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
710 priv->tqueue |= (TQUEUE_EN0 >> i);
711 priv->tx_queue[i]->grp = grp;
719 static int gfar_of_group_count(struct device_node *np)
721 struct device_node *child;
724 for_each_available_child_of_node(np, child)
725 if (!of_node_cmp(child->name, "queue-group"))
731 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
735 const void *mac_addr;
737 struct net_device *dev = NULL;
738 struct gfar_private *priv = NULL;
739 struct device_node *np = ofdev->dev.of_node;
740 struct device_node *child = NULL;
741 struct property *stash;
744 unsigned int num_tx_qs, num_rx_qs;
745 unsigned short mode, poll_mode;
750 if (of_device_is_compatible(np, "fsl,etsec2")) {
752 poll_mode = GFAR_SQ_POLLING;
755 poll_mode = GFAR_SQ_POLLING;
758 if (mode == SQ_SG_MODE) {
761 } else { /* MQ_MG_MODE */
762 /* get the actual number of supported groups */
763 unsigned int num_grps = gfar_of_group_count(np);
765 if (num_grps == 0 || num_grps > MAXGROUPS) {
766 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
768 pr_err("Cannot do alloc_etherdev, aborting\n");
772 if (poll_mode == GFAR_SQ_POLLING) {
773 num_tx_qs = num_grps; /* one txq per int group */
774 num_rx_qs = num_grps; /* one rxq per int group */
775 } else { /* GFAR_MQ_POLLING */
776 u32 tx_queues, rx_queues;
779 /* parse the num of HW tx and rx queues */
780 ret = of_property_read_u32(np, "fsl,num_tx_queues",
782 num_tx_qs = ret ? 1 : tx_queues;
784 ret = of_property_read_u32(np, "fsl,num_rx_queues",
786 num_rx_qs = ret ? 1 : rx_queues;
790 if (num_tx_qs > MAX_TX_QS) {
791 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
792 num_tx_qs, MAX_TX_QS);
793 pr_err("Cannot do alloc_etherdev, aborting\n");
797 if (num_rx_qs > MAX_RX_QS) {
798 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
799 num_rx_qs, MAX_RX_QS);
800 pr_err("Cannot do alloc_etherdev, aborting\n");
804 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
809 priv = netdev_priv(dev);
813 priv->poll_mode = poll_mode;
815 priv->num_tx_queues = num_tx_qs;
816 netif_set_real_num_rx_queues(dev, num_rx_qs);
817 priv->num_rx_queues = num_rx_qs;
819 err = gfar_alloc_tx_queues(priv);
821 goto tx_alloc_failed;
823 err = gfar_alloc_rx_queues(priv);
825 goto rx_alloc_failed;
827 err = of_property_read_string(np, "model", &model);
829 pr_err("Device model property missing, aborting\n");
830 goto rx_alloc_failed;
833 /* Init Rx queue filer rule set linked list */
834 INIT_LIST_HEAD(&priv->rx_list.list);
835 priv->rx_list.count = 0;
836 mutex_init(&priv->rx_queue_access);
838 for (i = 0; i < MAXGROUPS; i++)
839 priv->gfargrp[i].regs = NULL;
841 /* Parse and initialize group specific information */
842 if (priv->mode == MQ_MG_MODE) {
843 for_each_available_child_of_node(np, child) {
844 if (of_node_cmp(child->name, "queue-group"))
847 err = gfar_parse_group(child, priv, model);
851 } else { /* SQ_SG_MODE */
852 err = gfar_parse_group(np, priv, model);
857 stash = of_find_property(np, "bd-stash", NULL);
860 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
861 priv->bd_stash_en = 1;
864 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
867 priv->rx_stash_size = stash_len;
869 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
872 priv->rx_stash_index = stash_idx;
874 if (stash_len || stash_idx)
875 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
877 mac_addr = of_get_mac_address(np);
880 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
882 if (model && !strcasecmp(model, "TSEC"))
883 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
884 FSL_GIANFAR_DEV_HAS_COALESCE |
885 FSL_GIANFAR_DEV_HAS_RMON |
886 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
888 if (model && !strcasecmp(model, "eTSEC"))
889 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
890 FSL_GIANFAR_DEV_HAS_COALESCE |
891 FSL_GIANFAR_DEV_HAS_RMON |
892 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
893 FSL_GIANFAR_DEV_HAS_CSUM |
894 FSL_GIANFAR_DEV_HAS_VLAN |
895 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
896 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
897 FSL_GIANFAR_DEV_HAS_TIMER;
899 err = of_property_read_string(np, "phy-connection-type", &ctype);
901 /* We only care about rgmii-id. The rest are autodetected */
902 if (err == 0 && !strcmp(ctype, "rgmii-id"))
903 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
905 priv->interface = PHY_INTERFACE_MODE_MII;
907 if (of_find_property(np, "fsl,magic-packet", NULL))
908 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
910 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
912 /* In the case of a fixed PHY, the DT node associated
913 * to the PHY is the Ethernet MAC DT node.
915 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
916 err = of_phy_register_fixed_link(np);
920 priv->phy_node = of_node_get(np);
923 /* Find the TBI PHY. If it's not there, we don't support SGMII */
924 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
929 unmap_group_regs(priv);
931 gfar_free_rx_queues(priv);
933 gfar_free_tx_queues(priv);
938 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
940 struct hwtstamp_config config;
941 struct gfar_private *priv = netdev_priv(netdev);
943 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
946 /* reserved for future extensions */
950 switch (config.tx_type) {
951 case HWTSTAMP_TX_OFF:
952 priv->hwts_tx_en = 0;
955 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
957 priv->hwts_tx_en = 1;
963 switch (config.rx_filter) {
964 case HWTSTAMP_FILTER_NONE:
965 if (priv->hwts_rx_en) {
966 priv->hwts_rx_en = 0;
971 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
973 if (!priv->hwts_rx_en) {
974 priv->hwts_rx_en = 1;
977 config.rx_filter = HWTSTAMP_FILTER_ALL;
981 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
985 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
987 struct hwtstamp_config config;
988 struct gfar_private *priv = netdev_priv(netdev);
991 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
992 config.rx_filter = (priv->hwts_rx_en ?
993 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
995 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
999 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1001 struct gfar_private *priv = netdev_priv(dev);
1003 if (!netif_running(dev))
1006 if (cmd == SIOCSHWTSTAMP)
1007 return gfar_hwtstamp_set(dev, rq);
1008 if (cmd == SIOCGHWTSTAMP)
1009 return gfar_hwtstamp_get(dev, rq);
1014 return phy_mii_ioctl(priv->phydev, rq, cmd);
1017 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1020 u32 rqfpr = FPR_FILER_MASK;
1024 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1025 priv->ftp_rqfpr[rqfar] = rqfpr;
1026 priv->ftp_rqfcr[rqfar] = rqfcr;
1027 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1030 rqfcr = RQFCR_CMP_NOMATCH;
1031 priv->ftp_rqfpr[rqfar] = rqfpr;
1032 priv->ftp_rqfcr[rqfar] = rqfcr;
1033 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1036 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1038 priv->ftp_rqfcr[rqfar] = rqfcr;
1039 priv->ftp_rqfpr[rqfar] = rqfpr;
1040 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1043 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1045 priv->ftp_rqfcr[rqfar] = rqfcr;
1046 priv->ftp_rqfpr[rqfar] = rqfpr;
1047 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1052 static void gfar_init_filer_table(struct gfar_private *priv)
1055 u32 rqfar = MAX_FILER_IDX;
1057 u32 rqfpr = FPR_FILER_MASK;
1060 rqfcr = RQFCR_CMP_MATCH;
1061 priv->ftp_rqfcr[rqfar] = rqfcr;
1062 priv->ftp_rqfpr[rqfar] = rqfpr;
1063 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1065 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1066 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1067 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1068 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1069 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1070 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1072 /* cur_filer_idx indicated the first non-masked rule */
1073 priv->cur_filer_idx = rqfar;
1075 /* Rest are masked rules */
1076 rqfcr = RQFCR_CMP_NOMATCH;
1077 for (i = 0; i < rqfar; i++) {
1078 priv->ftp_rqfcr[i] = rqfcr;
1079 priv->ftp_rqfpr[i] = rqfpr;
1080 gfar_write_filer(priv, i, rqfcr, rqfpr);
1085 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1087 unsigned int pvr = mfspr(SPRN_PVR);
1088 unsigned int svr = mfspr(SPRN_SVR);
1089 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1090 unsigned int rev = svr & 0xffff;
1092 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1093 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1094 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1095 priv->errata |= GFAR_ERRATA_74;
1097 /* MPC8313 and MPC837x all rev */
1098 if ((pvr == 0x80850010 && mod == 0x80b0) ||
1099 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1100 priv->errata |= GFAR_ERRATA_76;
1102 /* MPC8313 Rev < 2.0 */
1103 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1104 priv->errata |= GFAR_ERRATA_12;
1107 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1109 unsigned int svr = mfspr(SPRN_SVR);
1111 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1112 priv->errata |= GFAR_ERRATA_12;
1113 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1114 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1115 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1119 static void gfar_detect_errata(struct gfar_private *priv)
1121 struct device *dev = &priv->ofdev->dev;
1123 /* no plans to fix */
1124 priv->errata |= GFAR_ERRATA_A002;
1127 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1128 __gfar_detect_errata_85xx(priv);
1129 else /* non-mpc85xx parts, i.e. e300 core based */
1130 __gfar_detect_errata_83xx(priv);
1134 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1138 void gfar_mac_reset(struct gfar_private *priv)
1140 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1143 /* Reset MAC layer */
1144 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1146 /* We need to delay at least 3 TX clocks */
1149 /* the soft reset bit is not self-resetting, so we need to
1150 * clear it before resuming normal operation
1152 gfar_write(®s->maccfg1, 0);
1156 gfar_rx_offload_en(priv);
1158 /* Initialize the max receive frame/buffer lengths */
1159 gfar_write(®s->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1160 gfar_write(®s->mrblr, GFAR_RXB_SIZE);
1162 /* Initialize the Minimum Frame Length Register */
1163 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1165 /* Initialize MACCFG2. */
1166 tempval = MACCFG2_INIT_SETTINGS;
1168 /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1169 * are marked as truncated. Avoid this by MACCFG2[Huge Frame]=1,
1170 * and by checking RxBD[LG] and discarding larger than MAXFRM.
1172 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1173 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1175 gfar_write(®s->maccfg2, tempval);
1177 /* Clear mac addr hash registers */
1178 gfar_write(®s->igaddr0, 0);
1179 gfar_write(®s->igaddr1, 0);
1180 gfar_write(®s->igaddr2, 0);
1181 gfar_write(®s->igaddr3, 0);
1182 gfar_write(®s->igaddr4, 0);
1183 gfar_write(®s->igaddr5, 0);
1184 gfar_write(®s->igaddr6, 0);
1185 gfar_write(®s->igaddr7, 0);
1187 gfar_write(®s->gaddr0, 0);
1188 gfar_write(®s->gaddr1, 0);
1189 gfar_write(®s->gaddr2, 0);
1190 gfar_write(®s->gaddr3, 0);
1191 gfar_write(®s->gaddr4, 0);
1192 gfar_write(®s->gaddr5, 0);
1193 gfar_write(®s->gaddr6, 0);
1194 gfar_write(®s->gaddr7, 0);
1196 if (priv->extended_hash)
1197 gfar_clear_exact_match(priv->ndev);
1199 gfar_mac_rx_config(priv);
1201 gfar_mac_tx_config(priv);
1203 gfar_set_mac_address(priv->ndev);
1205 gfar_set_multi(priv->ndev);
1207 /* clear ievent and imask before configuring coalescing */
1208 gfar_ints_disable(priv);
1210 /* Configure the coalescing support */
1211 gfar_configure_coalescing_all(priv);
1214 static void gfar_hw_init(struct gfar_private *priv)
1216 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1219 /* Stop the DMA engine now, in case it was running before
1220 * (The firmware could have used it, and left it running).
1224 gfar_mac_reset(priv);
1226 /* Zero out the rmon mib registers if it has them */
1227 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1228 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1230 /* Mask off the CAM interrupts */
1231 gfar_write(®s->rmon.cam1, 0xffffffff);
1232 gfar_write(®s->rmon.cam2, 0xffffffff);
1235 /* Initialize ECNTRL */
1236 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1238 /* Set the extraction length and index */
1239 attrs = ATTRELI_EL(priv->rx_stash_size) |
1240 ATTRELI_EI(priv->rx_stash_index);
1242 gfar_write(®s->attreli, attrs);
1244 /* Start with defaults, and add stashing
1245 * depending on driver parameters
1247 attrs = ATTR_INIT_SETTINGS;
1249 if (priv->bd_stash_en)
1250 attrs |= ATTR_BDSTASH;
1252 if (priv->rx_stash_size != 0)
1253 attrs |= ATTR_BUFSTASH;
1255 gfar_write(®s->attr, attrs);
1258 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1259 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1260 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1262 /* Program the interrupt steering regs, only for MG devices */
1263 if (priv->num_grps > 1)
1264 gfar_write_isrg(priv);
1267 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1269 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1271 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1272 priv->extended_hash = 1;
1273 priv->hash_width = 9;
1275 priv->hash_regs[0] = ®s->igaddr0;
1276 priv->hash_regs[1] = ®s->igaddr1;
1277 priv->hash_regs[2] = ®s->igaddr2;
1278 priv->hash_regs[3] = ®s->igaddr3;
1279 priv->hash_regs[4] = ®s->igaddr4;
1280 priv->hash_regs[5] = ®s->igaddr5;
1281 priv->hash_regs[6] = ®s->igaddr6;
1282 priv->hash_regs[7] = ®s->igaddr7;
1283 priv->hash_regs[8] = ®s->gaddr0;
1284 priv->hash_regs[9] = ®s->gaddr1;
1285 priv->hash_regs[10] = ®s->gaddr2;
1286 priv->hash_regs[11] = ®s->gaddr3;
1287 priv->hash_regs[12] = ®s->gaddr4;
1288 priv->hash_regs[13] = ®s->gaddr5;
1289 priv->hash_regs[14] = ®s->gaddr6;
1290 priv->hash_regs[15] = ®s->gaddr7;
1293 priv->extended_hash = 0;
1294 priv->hash_width = 8;
1296 priv->hash_regs[0] = ®s->gaddr0;
1297 priv->hash_regs[1] = ®s->gaddr1;
1298 priv->hash_regs[2] = ®s->gaddr2;
1299 priv->hash_regs[3] = ®s->gaddr3;
1300 priv->hash_regs[4] = ®s->gaddr4;
1301 priv->hash_regs[5] = ®s->gaddr5;
1302 priv->hash_regs[6] = ®s->gaddr6;
1303 priv->hash_regs[7] = ®s->gaddr7;
1307 /* Set up the ethernet device structure, private data,
1308 * and anything else we need before we start
1310 static int gfar_probe(struct platform_device *ofdev)
1312 struct net_device *dev = NULL;
1313 struct gfar_private *priv = NULL;
1316 err = gfar_of_init(ofdev, &dev);
1321 priv = netdev_priv(dev);
1323 priv->ofdev = ofdev;
1324 priv->dev = &ofdev->dev;
1325 SET_NETDEV_DEV(dev, &ofdev->dev);
1327 INIT_WORK(&priv->reset_task, gfar_reset_task);
1329 platform_set_drvdata(ofdev, priv);
1331 gfar_detect_errata(priv);
1333 /* Set the dev->base_addr to the gfar reg region */
1334 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1336 /* Fill in the dev structure */
1337 dev->watchdog_timeo = TX_TIMEOUT;
1339 dev->netdev_ops = &gfar_netdev_ops;
1340 dev->ethtool_ops = &gfar_ethtool_ops;
1342 /* Register for napi ...We are registering NAPI for each grp */
1343 for (i = 0; i < priv->num_grps; i++) {
1344 if (priv->poll_mode == GFAR_SQ_POLLING) {
1345 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1346 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1347 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1348 gfar_poll_tx_sq, 2);
1350 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1351 gfar_poll_rx, GFAR_DEV_WEIGHT);
1352 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1357 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1358 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1360 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1361 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1364 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1365 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1366 NETIF_F_HW_VLAN_CTAG_RX;
1367 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1370 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1372 gfar_init_addr_hash_table(priv);
1374 /* Insert receive time stamps into padding alignment bytes */
1375 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1378 if (dev->features & NETIF_F_IP_CSUM ||
1379 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1380 dev->needed_headroom = GMAC_FCB_LEN;
1382 /* Initializing some of the rx/tx queue level parameters */
1383 for (i = 0; i < priv->num_tx_queues; i++) {
1384 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1385 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1386 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1387 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1390 for (i = 0; i < priv->num_rx_queues; i++) {
1391 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1392 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1393 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1396 /* always enable rx filer */
1397 priv->rx_filer_enable = 1;
1398 /* Enable most messages by default */
1399 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1400 /* use pritority h/w tx queue scheduling for single queue devices */
1401 if (priv->num_tx_queues == 1)
1402 priv->prio_sched_en = 1;
1404 set_bit(GFAR_DOWN, &priv->state);
1408 /* Carrier starts down, phylib will bring it up */
1409 netif_carrier_off(dev);
1411 err = register_netdev(dev);
1414 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1418 device_set_wakeup_capable(&dev->dev, priv->device_flags &
1419 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1421 /* fill out IRQ number and name fields */
1422 for (i = 0; i < priv->num_grps; i++) {
1423 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1424 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1425 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1426 dev->name, "_g", '0' + i, "_tx");
1427 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1428 dev->name, "_g", '0' + i, "_rx");
1429 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1430 dev->name, "_g", '0' + i, "_er");
1432 strcpy(gfar_irq(grp, TX)->name, dev->name);
1435 /* Initialize the filer table */
1436 gfar_init_filer_table(priv);
1438 /* Print out the device info */
1439 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1441 /* Even more device info helps when determining which kernel
1442 * provided which set of benchmarks.
1444 netdev_info(dev, "Running with NAPI enabled\n");
1445 for (i = 0; i < priv->num_rx_queues; i++)
1446 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1447 i, priv->rx_queue[i]->rx_ring_size);
1448 for (i = 0; i < priv->num_tx_queues; i++)
1449 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1450 i, priv->tx_queue[i]->tx_ring_size);
1455 unmap_group_regs(priv);
1456 gfar_free_rx_queues(priv);
1457 gfar_free_tx_queues(priv);
1458 of_node_put(priv->phy_node);
1459 of_node_put(priv->tbi_node);
1460 free_gfar_dev(priv);
1464 static int gfar_remove(struct platform_device *ofdev)
1466 struct gfar_private *priv = platform_get_drvdata(ofdev);
1468 of_node_put(priv->phy_node);
1469 of_node_put(priv->tbi_node);
1471 unregister_netdev(priv->ndev);
1472 unmap_group_regs(priv);
1473 gfar_free_rx_queues(priv);
1474 gfar_free_tx_queues(priv);
1475 free_gfar_dev(priv);
1482 static int gfar_suspend(struct device *dev)
1484 struct gfar_private *priv = dev_get_drvdata(dev);
1485 struct net_device *ndev = priv->ndev;
1486 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1488 int magic_packet = priv->wol_en &&
1489 (priv->device_flags &
1490 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1492 if (!netif_running(ndev))
1496 netif_tx_lock(ndev);
1497 netif_device_detach(ndev);
1498 netif_tx_unlock(ndev);
1503 /* Enable interrupt on Magic Packet */
1504 gfar_write(®s->imask, IMASK_MAG);
1506 /* Enable Magic Packet mode */
1507 tempval = gfar_read(®s->maccfg2);
1508 tempval |= MACCFG2_MPEN;
1509 gfar_write(®s->maccfg2, tempval);
1511 /* re-enable the Rx block */
1512 tempval = gfar_read(®s->maccfg1);
1513 tempval |= MACCFG1_RX_EN;
1514 gfar_write(®s->maccfg1, tempval);
1517 phy_stop(priv->phydev);
1523 static int gfar_resume(struct device *dev)
1525 struct gfar_private *priv = dev_get_drvdata(dev);
1526 struct net_device *ndev = priv->ndev;
1527 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1529 int magic_packet = priv->wol_en &&
1530 (priv->device_flags &
1531 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1533 if (!netif_running(ndev))
1537 /* Disable Magic Packet mode */
1538 tempval = gfar_read(®s->maccfg2);
1539 tempval &= ~MACCFG2_MPEN;
1540 gfar_write(®s->maccfg2, tempval);
1542 phy_start(priv->phydev);
1547 netif_device_attach(ndev);
1553 static int gfar_restore(struct device *dev)
1555 struct gfar_private *priv = dev_get_drvdata(dev);
1556 struct net_device *ndev = priv->ndev;
1558 if (!netif_running(ndev)) {
1559 netif_device_attach(ndev);
1564 gfar_init_bds(ndev);
1566 gfar_mac_reset(priv);
1568 gfar_init_tx_rx_base(priv);
1574 priv->oldduplex = -1;
1577 phy_start(priv->phydev);
1579 netif_device_attach(ndev);
1585 static struct dev_pm_ops gfar_pm_ops = {
1586 .suspend = gfar_suspend,
1587 .resume = gfar_resume,
1588 .freeze = gfar_suspend,
1589 .thaw = gfar_resume,
1590 .restore = gfar_restore,
1593 #define GFAR_PM_OPS (&gfar_pm_ops)
1597 #define GFAR_PM_OPS NULL
1601 /* Reads the controller's registers to determine what interface
1602 * connects it to the PHY.
1604 static phy_interface_t gfar_get_interface(struct net_device *dev)
1606 struct gfar_private *priv = netdev_priv(dev);
1607 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1610 ecntrl = gfar_read(®s->ecntrl);
1612 if (ecntrl & ECNTRL_SGMII_MODE)
1613 return PHY_INTERFACE_MODE_SGMII;
1615 if (ecntrl & ECNTRL_TBI_MODE) {
1616 if (ecntrl & ECNTRL_REDUCED_MODE)
1617 return PHY_INTERFACE_MODE_RTBI;
1619 return PHY_INTERFACE_MODE_TBI;
1622 if (ecntrl & ECNTRL_REDUCED_MODE) {
1623 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1624 return PHY_INTERFACE_MODE_RMII;
1627 phy_interface_t interface = priv->interface;
1629 /* This isn't autodetected right now, so it must
1630 * be set by the device tree or platform code.
1632 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1633 return PHY_INTERFACE_MODE_RGMII_ID;
1635 return PHY_INTERFACE_MODE_RGMII;
1639 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1640 return PHY_INTERFACE_MODE_GMII;
1642 return PHY_INTERFACE_MODE_MII;
1646 /* Initializes driver's PHY state, and attaches to the PHY.
1647 * Returns 0 on success.
1649 static int init_phy(struct net_device *dev)
1651 struct gfar_private *priv = netdev_priv(dev);
1652 uint gigabit_support =
1653 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1654 GFAR_SUPPORTED_GBIT : 0;
1655 phy_interface_t interface;
1659 priv->oldduplex = -1;
1661 interface = gfar_get_interface(dev);
1663 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1665 if (!priv->phydev) {
1666 dev_err(&dev->dev, "could not attach to PHY\n");
1670 if (interface == PHY_INTERFACE_MODE_SGMII)
1671 gfar_configure_serdes(dev);
1673 /* Remove any features not supported by the controller */
1674 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1675 priv->phydev->advertising = priv->phydev->supported;
1677 /* Add support for flow control, but don't advertise it by default */
1678 priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1683 /* Initialize TBI PHY interface for communicating with the
1684 * SERDES lynx PHY on the chip. We communicate with this PHY
1685 * through the MDIO bus on each controller, treating it as a
1686 * "normal" PHY at the address found in the TBIPA register. We assume
1687 * that the TBIPA register is valid. Either the MDIO bus code will set
1688 * it to a value that doesn't conflict with other PHYs on the bus, or the
1689 * value doesn't matter, as there are no other PHYs on the bus.
1691 static void gfar_configure_serdes(struct net_device *dev)
1693 struct gfar_private *priv = netdev_priv(dev);
1694 struct phy_device *tbiphy;
1696 if (!priv->tbi_node) {
1697 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1698 "device tree specify a tbi-handle\n");
1702 tbiphy = of_phy_find_device(priv->tbi_node);
1704 dev_err(&dev->dev, "error: Could not get TBI device\n");
1708 /* If the link is already up, we must already be ok, and don't need to
1709 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1710 * everything for us? Resetting it takes the link down and requires
1711 * several seconds for it to come back.
1713 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1716 /* Single clk mode, mii mode off(for serdes communication) */
1717 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1719 phy_write(tbiphy, MII_ADVERTISE,
1720 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1721 ADVERTISE_1000XPSE_ASYM);
1723 phy_write(tbiphy, MII_BMCR,
1724 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1728 static int __gfar_is_rx_idle(struct gfar_private *priv)
1732 /* Normaly TSEC should not hang on GRS commands, so we should
1733 * actually wait for IEVENT_GRSC flag.
1735 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1738 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1739 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1740 * and the Rx can be safely reset.
1742 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1744 if ((res & 0xffff) == (res >> 16))
1750 /* Halt the receive and transmit queues */
1751 static void gfar_halt_nodisable(struct gfar_private *priv)
1753 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1755 unsigned int timeout;
1758 gfar_ints_disable(priv);
1760 if (gfar_is_dma_stopped(priv))
1763 /* Stop the DMA, and wait for it to stop */
1764 tempval = gfar_read(®s->dmactrl);
1765 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1766 gfar_write(®s->dmactrl, tempval);
1770 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1776 stopped = gfar_is_dma_stopped(priv);
1778 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1779 !__gfar_is_rx_idle(priv))
1783 /* Halt the receive and transmit queues */
1784 void gfar_halt(struct gfar_private *priv)
1786 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1789 /* Dissable the Rx/Tx hw queues */
1790 gfar_write(®s->rqueue, 0);
1791 gfar_write(®s->tqueue, 0);
1795 gfar_halt_nodisable(priv);
1797 /* Disable Rx/Tx DMA */
1798 tempval = gfar_read(®s->maccfg1);
1799 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1800 gfar_write(®s->maccfg1, tempval);
1803 void stop_gfar(struct net_device *dev)
1805 struct gfar_private *priv = netdev_priv(dev);
1807 netif_tx_stop_all_queues(dev);
1809 smp_mb__before_atomic();
1810 set_bit(GFAR_DOWN, &priv->state);
1811 smp_mb__after_atomic();
1815 /* disable ints and gracefully shut down Rx/Tx DMA */
1818 phy_stop(priv->phydev);
1820 free_skb_resources(priv);
1823 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1825 struct txbd8 *txbdp;
1826 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1829 txbdp = tx_queue->tx_bd_base;
1831 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1832 if (!tx_queue->tx_skbuff[i])
1835 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1836 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1838 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1841 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1842 be16_to_cpu(txbdp->length),
1846 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1847 tx_queue->tx_skbuff[i] = NULL;
1849 kfree(tx_queue->tx_skbuff);
1850 tx_queue->tx_skbuff = NULL;
1853 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1857 struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1860 dev_kfree_skb(rx_queue->skb);
1862 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1863 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1872 dma_unmap_single(rx_queue->dev, rxb->dma,
1873 PAGE_SIZE, DMA_FROM_DEVICE);
1874 __free_page(rxb->page);
1879 kfree(rx_queue->rx_buff);
1880 rx_queue->rx_buff = NULL;
1883 /* If there are any tx skbs or rx skbs still around, free them.
1884 * Then free tx_skbuff and rx_skbuff
1886 static void free_skb_resources(struct gfar_private *priv)
1888 struct gfar_priv_tx_q *tx_queue = NULL;
1889 struct gfar_priv_rx_q *rx_queue = NULL;
1892 /* Go through all the buffer descriptors and free their data buffers */
1893 for (i = 0; i < priv->num_tx_queues; i++) {
1894 struct netdev_queue *txq;
1896 tx_queue = priv->tx_queue[i];
1897 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1898 if (tx_queue->tx_skbuff)
1899 free_skb_tx_queue(tx_queue);
1900 netdev_tx_reset_queue(txq);
1903 for (i = 0; i < priv->num_rx_queues; i++) {
1904 rx_queue = priv->rx_queue[i];
1905 if (rx_queue->rx_buff)
1906 free_skb_rx_queue(rx_queue);
1909 dma_free_coherent(priv->dev,
1910 sizeof(struct txbd8) * priv->total_tx_ring_size +
1911 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1912 priv->tx_queue[0]->tx_bd_base,
1913 priv->tx_queue[0]->tx_bd_dma_base);
1916 void gfar_start(struct gfar_private *priv)
1918 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1922 /* Enable Rx/Tx hw queues */
1923 gfar_write(®s->rqueue, priv->rqueue);
1924 gfar_write(®s->tqueue, priv->tqueue);
1926 /* Initialize DMACTRL to have WWR and WOP */
1927 tempval = gfar_read(®s->dmactrl);
1928 tempval |= DMACTRL_INIT_SETTINGS;
1929 gfar_write(®s->dmactrl, tempval);
1931 /* Make sure we aren't stopped */
1932 tempval = gfar_read(®s->dmactrl);
1933 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1934 gfar_write(®s->dmactrl, tempval);
1936 for (i = 0; i < priv->num_grps; i++) {
1937 regs = priv->gfargrp[i].regs;
1938 /* Clear THLT/RHLT, so that the DMA starts polling now */
1939 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1940 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1943 /* Enable Rx/Tx DMA */
1944 tempval = gfar_read(®s->maccfg1);
1945 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1946 gfar_write(®s->maccfg1, tempval);
1948 gfar_ints_enable(priv);
1950 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
1953 static void free_grp_irqs(struct gfar_priv_grp *grp)
1955 free_irq(gfar_irq(grp, TX)->irq, grp);
1956 free_irq(gfar_irq(grp, RX)->irq, grp);
1957 free_irq(gfar_irq(grp, ER)->irq, grp);
1960 static int register_grp_irqs(struct gfar_priv_grp *grp)
1962 struct gfar_private *priv = grp->priv;
1963 struct net_device *dev = priv->ndev;
1966 /* If the device has multiple interrupts, register for
1967 * them. Otherwise, only register for the one
1969 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1970 /* Install our interrupt handlers for Error,
1971 * Transmit, and Receive
1973 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1974 gfar_irq(grp, ER)->name, grp);
1976 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1977 gfar_irq(grp, ER)->irq);
1981 enable_irq_wake(gfar_irq(grp, ER)->irq);
1983 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1984 gfar_irq(grp, TX)->name, grp);
1986 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1987 gfar_irq(grp, TX)->irq);
1990 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1991 gfar_irq(grp, RX)->name, grp);
1993 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1994 gfar_irq(grp, RX)->irq);
1998 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1999 gfar_irq(grp, TX)->name, grp);
2001 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2002 gfar_irq(grp, TX)->irq);
2005 enable_irq_wake(gfar_irq(grp, TX)->irq);
2011 free_irq(gfar_irq(grp, TX)->irq, grp);
2013 free_irq(gfar_irq(grp, ER)->irq, grp);
2019 static void gfar_free_irq(struct gfar_private *priv)
2024 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2025 for (i = 0; i < priv->num_grps; i++)
2026 free_grp_irqs(&priv->gfargrp[i]);
2028 for (i = 0; i < priv->num_grps; i++)
2029 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2034 static int gfar_request_irq(struct gfar_private *priv)
2038 for (i = 0; i < priv->num_grps; i++) {
2039 err = register_grp_irqs(&priv->gfargrp[i]);
2041 for (j = 0; j < i; j++)
2042 free_grp_irqs(&priv->gfargrp[j]);
2050 /* Bring the controller up and running */
2051 int startup_gfar(struct net_device *ndev)
2053 struct gfar_private *priv = netdev_priv(ndev);
2056 gfar_mac_reset(priv);
2058 err = gfar_alloc_skb_resources(ndev);
2062 gfar_init_tx_rx_base(priv);
2064 smp_mb__before_atomic();
2065 clear_bit(GFAR_DOWN, &priv->state);
2066 smp_mb__after_atomic();
2068 /* Start Rx/Tx DMA and enable the interrupts */
2071 /* force link state update after mac reset */
2074 priv->oldduplex = -1;
2076 phy_start(priv->phydev);
2080 netif_tx_wake_all_queues(ndev);
2085 /* Called when something needs to use the ethernet device
2086 * Returns 0 for success.
2088 static int gfar_enet_open(struct net_device *dev)
2090 struct gfar_private *priv = netdev_priv(dev);
2093 err = init_phy(dev);
2097 err = gfar_request_irq(priv);
2101 err = startup_gfar(dev);
2108 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2110 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2112 memset(fcb, 0, GMAC_FCB_LEN);
2117 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2120 /* If we're here, it's a IP packet with a TCP or UDP
2121 * payload. We set it to checksum, using a pseudo-header
2124 u8 flags = TXFCB_DEFAULT;
2126 /* Tell the controller what the protocol is
2127 * And provide the already calculated phcs
2129 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2131 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2133 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2135 /* l3os is the distance between the start of the
2136 * frame (skb->data) and the start of the IP hdr.
2137 * l4os is the distance between the start of the
2138 * l3 hdr and the l4 hdr
2140 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2141 fcb->l4os = skb_network_header_len(skb);
2146 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2148 fcb->flags |= TXFCB_VLN;
2149 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2152 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2153 struct txbd8 *base, int ring_size)
2155 struct txbd8 *new_bd = bdp + stride;
2157 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2160 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2163 return skip_txbd(bdp, 1, base, ring_size);
2166 /* eTSEC12: csum generation not supported for some fcb offsets */
2167 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2168 unsigned long fcb_addr)
2170 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2171 (fcb_addr % 0x20) > 0x18);
2174 /* eTSEC76: csum generation for frames larger than 2500 may
2175 * cause excess delays before start of transmission
2177 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2180 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2184 /* This is called by the kernel when a frame is ready for transmission.
2185 * It is pointed to by the dev->hard_start_xmit function pointer
2187 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2189 struct gfar_private *priv = netdev_priv(dev);
2190 struct gfar_priv_tx_q *tx_queue = NULL;
2191 struct netdev_queue *txq;
2192 struct gfar __iomem *regs = NULL;
2193 struct txfcb *fcb = NULL;
2194 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2197 int do_tstamp, do_csum, do_vlan;
2199 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2201 rq = skb->queue_mapping;
2202 tx_queue = priv->tx_queue[rq];
2203 txq = netdev_get_tx_queue(dev, rq);
2204 base = tx_queue->tx_bd_base;
2205 regs = tx_queue->grp->regs;
2207 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2208 do_vlan = skb_vlan_tag_present(skb);
2209 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2212 if (do_csum || do_vlan)
2213 fcb_len = GMAC_FCB_LEN;
2215 /* check if time stamp should be generated */
2216 if (unlikely(do_tstamp))
2217 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2219 /* make space for additional header when fcb is needed */
2220 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2221 struct sk_buff *skb_new;
2223 skb_new = skb_realloc_headroom(skb, fcb_len);
2225 dev->stats.tx_errors++;
2226 dev_kfree_skb_any(skb);
2227 return NETDEV_TX_OK;
2231 skb_set_owner_w(skb_new, skb->sk);
2232 dev_consume_skb_any(skb);
2236 /* total number of fragments in the SKB */
2237 nr_frags = skb_shinfo(skb)->nr_frags;
2239 /* calculate the required number of TxBDs for this skb */
2240 if (unlikely(do_tstamp))
2241 nr_txbds = nr_frags + 2;
2243 nr_txbds = nr_frags + 1;
2245 /* check if there is space to queue this packet */
2246 if (nr_txbds > tx_queue->num_txbdfree) {
2247 /* no space, stop the queue */
2248 netif_tx_stop_queue(txq);
2249 dev->stats.tx_fifo_errors++;
2250 return NETDEV_TX_BUSY;
2253 /* Update transmit stats */
2254 bytes_sent = skb->len;
2255 tx_queue->stats.tx_bytes += bytes_sent;
2256 /* keep Tx bytes on wire for BQL accounting */
2257 GFAR_CB(skb)->bytes_sent = bytes_sent;
2258 tx_queue->stats.tx_packets++;
2260 txbdp = txbdp_start = tx_queue->cur_tx;
2261 lstatus = be32_to_cpu(txbdp->lstatus);
2263 /* Time stamp insertion requires one additional TxBD */
2264 if (unlikely(do_tstamp))
2265 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2266 tx_queue->tx_ring_size);
2268 if (nr_frags == 0) {
2269 if (unlikely(do_tstamp)) {
2270 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2272 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2273 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2275 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2278 /* Place the fragment addresses and lengths into the TxBDs */
2279 for (i = 0; i < nr_frags; i++) {
2280 unsigned int frag_len;
2281 /* Point at the next BD, wrapping as needed */
2282 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2284 frag_len = skb_shinfo(skb)->frags[i].size;
2286 lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
2287 BD_LFLAG(TXBD_READY);
2289 /* Handle the last BD specially */
2290 if (i == nr_frags - 1)
2291 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2293 bufaddr = skb_frag_dma_map(priv->dev,
2294 &skb_shinfo(skb)->frags[i],
2298 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2301 /* set the TxBD length and buffer pointer */
2302 txbdp->bufPtr = cpu_to_be32(bufaddr);
2303 txbdp->lstatus = cpu_to_be32(lstatus);
2306 lstatus = be32_to_cpu(txbdp_start->lstatus);
2309 /* Add TxPAL between FCB and frame if required */
2310 if (unlikely(do_tstamp)) {
2311 skb_push(skb, GMAC_TXPAL_LEN);
2312 memset(skb->data, 0, GMAC_TXPAL_LEN);
2315 /* Add TxFCB if required */
2317 fcb = gfar_add_fcb(skb);
2318 lstatus |= BD_LFLAG(TXBD_TOE);
2321 /* Set up checksumming */
2323 gfar_tx_checksum(skb, fcb, fcb_len);
2325 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2326 unlikely(gfar_csum_errata_76(priv, skb->len))) {
2327 __skb_pull(skb, GMAC_FCB_LEN);
2328 skb_checksum_help(skb);
2329 if (do_vlan || do_tstamp) {
2330 /* put back a new fcb for vlan/tstamp TOE */
2331 fcb = gfar_add_fcb(skb);
2333 /* Tx TOE not used */
2334 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2341 gfar_tx_vlan(skb, fcb);
2343 /* Setup tx hardware time stamping if requested */
2344 if (unlikely(do_tstamp)) {
2345 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2349 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2351 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2354 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2356 /* If time stamping is requested one additional TxBD must be set up. The
2357 * first TxBD points to the FCB and must have a data length of
2358 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2359 * the full frame length.
2361 if (unlikely(do_tstamp)) {
2362 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2364 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2366 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2367 (skb_headlen(skb) - fcb_len);
2369 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2370 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2371 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2373 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2376 netdev_tx_sent_queue(txq, bytes_sent);
2380 txbdp_start->lstatus = cpu_to_be32(lstatus);
2382 gfar_wmb(); /* force lstatus write before tx_skbuff */
2384 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2386 /* Update the current skb pointer to the next entry we will use
2387 * (wrapping if necessary)
2389 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2390 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2392 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2394 /* We can work in parallel with gfar_clean_tx_ring(), except
2395 * when modifying num_txbdfree. Note that we didn't grab the lock
2396 * when we were reading the num_txbdfree and checking for available
2397 * space, that's because outside of this function it can only grow.
2399 spin_lock_bh(&tx_queue->txlock);
2400 /* reduce TxBD free count */
2401 tx_queue->num_txbdfree -= (nr_txbds);
2402 spin_unlock_bh(&tx_queue->txlock);
2404 /* If the next BD still needs to be cleaned up, then the bds
2405 * are full. We need to tell the kernel to stop sending us stuff.
2407 if (!tx_queue->num_txbdfree) {
2408 netif_tx_stop_queue(txq);
2410 dev->stats.tx_fifo_errors++;
2413 /* Tell the DMA to go go go */
2414 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2416 return NETDEV_TX_OK;
2419 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2421 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2422 for (i = 0; i < nr_frags; i++) {
2423 lstatus = be32_to_cpu(txbdp->lstatus);
2424 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2427 lstatus &= ~BD_LFLAG(TXBD_READY);
2428 txbdp->lstatus = cpu_to_be32(lstatus);
2429 bufaddr = be32_to_cpu(txbdp->bufPtr);
2430 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2432 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2435 dev_kfree_skb_any(skb);
2436 return NETDEV_TX_OK;
2439 /* Stops the kernel queue, and halts the controller */
2440 static int gfar_close(struct net_device *dev)
2442 struct gfar_private *priv = netdev_priv(dev);
2444 cancel_work_sync(&priv->reset_task);
2447 /* Disconnect from the PHY */
2448 phy_disconnect(priv->phydev);
2449 priv->phydev = NULL;
2451 gfar_free_irq(priv);
2456 /* Changes the mac address if the controller is not running. */
2457 static int gfar_set_mac_address(struct net_device *dev)
2459 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2464 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2466 struct gfar_private *priv = netdev_priv(dev);
2467 int frame_size = new_mtu + ETH_HLEN;
2469 if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
2470 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2474 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2477 if (dev->flags & IFF_UP)
2482 if (dev->flags & IFF_UP)
2485 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2490 void reset_gfar(struct net_device *ndev)
2492 struct gfar_private *priv = netdev_priv(ndev);
2494 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2500 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2503 /* gfar_reset_task gets scheduled when a packet has not been
2504 * transmitted after a set amount of time.
2505 * For now, assume that clearing out all the structures, and
2506 * starting over will fix the problem.
2508 static void gfar_reset_task(struct work_struct *work)
2510 struct gfar_private *priv = container_of(work, struct gfar_private,
2512 reset_gfar(priv->ndev);
2515 static void gfar_timeout(struct net_device *dev)
2517 struct gfar_private *priv = netdev_priv(dev);
2519 dev->stats.tx_errors++;
2520 schedule_work(&priv->reset_task);
2523 /* Interrupt Handler for Transmit complete */
2524 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2526 struct net_device *dev = tx_queue->dev;
2527 struct netdev_queue *txq;
2528 struct gfar_private *priv = netdev_priv(dev);
2529 struct txbd8 *bdp, *next = NULL;
2530 struct txbd8 *lbdp = NULL;
2531 struct txbd8 *base = tx_queue->tx_bd_base;
2532 struct sk_buff *skb;
2534 int tx_ring_size = tx_queue->tx_ring_size;
2535 int frags = 0, nr_txbds = 0;
2538 int tqi = tx_queue->qindex;
2539 unsigned int bytes_sent = 0;
2543 txq = netdev_get_tx_queue(dev, tqi);
2544 bdp = tx_queue->dirty_tx;
2545 skb_dirtytx = tx_queue->skb_dirtytx;
2547 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2549 frags = skb_shinfo(skb)->nr_frags;
2551 /* When time stamping, one additional TxBD must be freed.
2552 * Also, we need to dma_unmap_single() the TxPAL.
2554 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2555 nr_txbds = frags + 2;
2557 nr_txbds = frags + 1;
2559 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2561 lstatus = be32_to_cpu(lbdp->lstatus);
2563 /* Only clean completed frames */
2564 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2565 (lstatus & BD_LENGTH_MASK))
2568 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2569 next = next_txbd(bdp, base, tx_ring_size);
2570 buflen = be16_to_cpu(next->length) +
2571 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2573 buflen = be16_to_cpu(bdp->length);
2575 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2576 buflen, DMA_TO_DEVICE);
2578 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2579 struct skb_shared_hwtstamps shhwtstamps;
2580 u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2583 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2584 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2585 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2586 skb_tstamp_tx(skb, &shhwtstamps);
2587 gfar_clear_txbd_status(bdp);
2591 gfar_clear_txbd_status(bdp);
2592 bdp = next_txbd(bdp, base, tx_ring_size);
2594 for (i = 0; i < frags; i++) {
2595 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2596 be16_to_cpu(bdp->length),
2598 gfar_clear_txbd_status(bdp);
2599 bdp = next_txbd(bdp, base, tx_ring_size);
2602 bytes_sent += GFAR_CB(skb)->bytes_sent;
2604 dev_kfree_skb_any(skb);
2606 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2608 skb_dirtytx = (skb_dirtytx + 1) &
2609 TX_RING_MOD_MASK(tx_ring_size);
2612 spin_lock(&tx_queue->txlock);
2613 tx_queue->num_txbdfree += nr_txbds;
2614 spin_unlock(&tx_queue->txlock);
2617 /* If we freed a buffer, we can restart transmission, if necessary */
2618 if (tx_queue->num_txbdfree &&
2619 netif_tx_queue_stopped(txq) &&
2620 !(test_bit(GFAR_DOWN, &priv->state)))
2621 netif_wake_subqueue(priv->ndev, tqi);
2623 /* Update dirty indicators */
2624 tx_queue->skb_dirtytx = skb_dirtytx;
2625 tx_queue->dirty_tx = bdp;
2627 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2630 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2635 page = dev_alloc_page();
2636 if (unlikely(!page))
2639 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2640 if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2648 rxb->page_offset = 0;
2653 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2655 struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2656 struct gfar_extra_stats *estats = &priv->extra_stats;
2658 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2659 atomic64_inc(&estats->rx_alloc_err);
2662 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2666 struct gfar_rx_buff *rxb;
2669 i = rx_queue->next_to_use;
2670 bdp = &rx_queue->rx_bd_base[i];
2671 rxb = &rx_queue->rx_buff[i];
2673 while (alloc_cnt--) {
2674 /* try reuse page */
2675 if (unlikely(!rxb->page)) {
2676 if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2677 gfar_rx_alloc_err(rx_queue);
2682 /* Setup the new RxBD */
2683 gfar_init_rxbdp(rx_queue, bdp,
2684 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2686 /* Update to the next pointer */
2690 if (unlikely(++i == rx_queue->rx_ring_size)) {
2692 bdp = rx_queue->rx_bd_base;
2693 rxb = rx_queue->rx_buff;
2697 rx_queue->next_to_use = i;
2698 rx_queue->next_to_alloc = i;
2701 static void count_errors(u32 lstatus, struct net_device *ndev)
2703 struct gfar_private *priv = netdev_priv(ndev);
2704 struct net_device_stats *stats = &ndev->stats;
2705 struct gfar_extra_stats *estats = &priv->extra_stats;
2707 /* If the packet was truncated, none of the other errors matter */
2708 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2709 stats->rx_length_errors++;
2711 atomic64_inc(&estats->rx_trunc);
2715 /* Count the errors, if there were any */
2716 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2717 stats->rx_length_errors++;
2719 if (lstatus & BD_LFLAG(RXBD_LARGE))
2720 atomic64_inc(&estats->rx_large);
2722 atomic64_inc(&estats->rx_short);
2724 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2725 stats->rx_frame_errors++;
2726 atomic64_inc(&estats->rx_nonoctet);
2728 if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2729 atomic64_inc(&estats->rx_crcerr);
2730 stats->rx_crc_errors++;
2732 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2733 atomic64_inc(&estats->rx_overrun);
2734 stats->rx_over_errors++;
2738 irqreturn_t gfar_receive(int irq, void *grp_id)
2740 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2741 unsigned long flags;
2744 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2745 spin_lock_irqsave(&grp->grplock, flags);
2746 imask = gfar_read(&grp->regs->imask);
2747 imask &= IMASK_RX_DISABLED;
2748 gfar_write(&grp->regs->imask, imask);
2749 spin_unlock_irqrestore(&grp->grplock, flags);
2750 __napi_schedule(&grp->napi_rx);
2752 /* Clear IEVENT, so interrupts aren't called again
2753 * because of the packets that have already arrived.
2755 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2761 /* Interrupt Handler for Transmit complete */
2762 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2764 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2765 unsigned long flags;
2768 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2769 spin_lock_irqsave(&grp->grplock, flags);
2770 imask = gfar_read(&grp->regs->imask);
2771 imask &= IMASK_TX_DISABLED;
2772 gfar_write(&grp->regs->imask, imask);
2773 spin_unlock_irqrestore(&grp->grplock, flags);
2774 __napi_schedule(&grp->napi_tx);
2776 /* Clear IEVENT, so interrupts aren't called again
2777 * because of the packets that have already arrived.
2779 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2785 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2786 struct sk_buff *skb, bool first)
2788 unsigned int size = lstatus & BD_LENGTH_MASK;
2789 struct page *page = rxb->page;
2791 /* Remove the FCS from the packet length */
2792 if (likely(lstatus & BD_LFLAG(RXBD_LAST)))
2793 size -= ETH_FCS_LEN;
2798 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2799 rxb->page_offset + RXBUF_ALIGNMENT,
2800 size, GFAR_RXB_TRUESIZE);
2802 /* try reuse page */
2803 if (unlikely(page_count(page) != 1))
2806 /* change offset to the other half */
2807 rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2809 atomic_inc(&page->_count);
2814 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2815 struct gfar_rx_buff *old_rxb)
2817 struct gfar_rx_buff *new_rxb;
2818 u16 nta = rxq->next_to_alloc;
2820 new_rxb = &rxq->rx_buff[nta];
2822 /* find next buf that can reuse a page */
2824 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2826 /* copy page reference */
2827 *new_rxb = *old_rxb;
2829 /* sync for use by the device */
2830 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2831 old_rxb->page_offset,
2832 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2835 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2836 u32 lstatus, struct sk_buff *skb)
2838 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2839 struct page *page = rxb->page;
2843 void *buff_addr = page_address(page) + rxb->page_offset;
2845 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2846 if (unlikely(!skb)) {
2847 gfar_rx_alloc_err(rx_queue);
2850 skb_reserve(skb, RXBUF_ALIGNMENT);
2854 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2855 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2857 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2858 /* reuse the free half of the page */
2859 gfar_reuse_rx_page(rx_queue, rxb);
2861 /* page cannot be reused, unmap it */
2862 dma_unmap_page(rx_queue->dev, rxb->dma,
2863 PAGE_SIZE, DMA_FROM_DEVICE);
2866 /* clear rxb content */
2872 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2874 /* If valid headers were found, and valid sums
2875 * were verified, then we tell the kernel that no
2876 * checksumming is necessary. Otherwise, it is [FIXME]
2878 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2879 (RXFCB_CIP | RXFCB_CTU))
2880 skb->ip_summed = CHECKSUM_UNNECESSARY;
2882 skb_checksum_none_assert(skb);
2885 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2886 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
2888 struct gfar_private *priv = netdev_priv(ndev);
2889 struct rxfcb *fcb = NULL;
2891 /* fcb is at the beginning if exists */
2892 fcb = (struct rxfcb *)skb->data;
2894 /* Remove the FCB from the skb
2895 * Remove the padded bytes, if there are any
2897 if (priv->uses_rxfcb)
2898 skb_pull(skb, GMAC_FCB_LEN);
2900 /* Get receive timestamp from the skb */
2901 if (priv->hwts_rx_en) {
2902 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2903 u64 *ns = (u64 *) skb->data;
2905 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2906 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2910 skb_pull(skb, priv->padding);
2912 if (ndev->features & NETIF_F_RXCSUM)
2913 gfar_rx_checksum(skb, fcb);
2915 /* Tell the skb what kind of packet this is */
2916 skb->protocol = eth_type_trans(skb, ndev);
2918 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2919 * Even if vlan rx accel is disabled, on some chips
2920 * RXFCB_VLN is pseudo randomly set.
2922 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2923 be16_to_cpu(fcb->flags) & RXFCB_VLN)
2924 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2925 be16_to_cpu(fcb->vlctl));
2928 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2929 * until the budget/quota has been reached. Returns the number
2932 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2934 struct net_device *ndev = rx_queue->ndev;
2935 struct gfar_private *priv = netdev_priv(ndev);
2938 struct sk_buff *skb = rx_queue->skb;
2939 int cleaned_cnt = gfar_rxbd_unused(rx_queue);
2940 unsigned int total_bytes = 0, total_pkts = 0;
2942 /* Get the first full descriptor */
2943 i = rx_queue->next_to_clean;
2945 while (rx_work_limit--) {
2948 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
2949 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2953 bdp = &rx_queue->rx_bd_base[i];
2954 lstatus = be32_to_cpu(bdp->lstatus);
2955 if (lstatus & BD_LFLAG(RXBD_EMPTY))
2958 /* order rx buffer descriptor reads */
2961 /* fetch next to clean buffer from the ring */
2962 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
2969 if (unlikely(++i == rx_queue->rx_ring_size))
2972 rx_queue->next_to_clean = i;
2974 /* fetch next buffer if not the last in frame */
2975 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
2978 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
2979 count_errors(lstatus, ndev);
2981 /* discard faulty buffer */
2984 rx_queue->stats.rx_dropped++;
2988 /* Increment the number of packets */
2990 total_bytes += skb->len;
2992 skb_record_rx_queue(skb, rx_queue->qindex);
2994 gfar_process_frame(ndev, skb);
2996 /* Send the packet up the stack */
2997 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3002 /* Store incomplete frames for completion */
3003 rx_queue->skb = skb;
3005 rx_queue->stats.rx_packets += total_pkts;
3006 rx_queue->stats.rx_bytes += total_bytes;
3009 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3011 /* Update Last Free RxBD pointer for LFC */
3012 if (unlikely(priv->tx_actual_en)) {
3013 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3015 gfar_write(rx_queue->rfbptr, bdp_dma);
3021 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3023 struct gfar_priv_grp *gfargrp =
3024 container_of(napi, struct gfar_priv_grp, napi_rx);
3025 struct gfar __iomem *regs = gfargrp->regs;
3026 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3029 /* Clear IEVENT, so interrupts aren't called again
3030 * because of the packets that have already arrived
3032 gfar_write(®s->ievent, IEVENT_RX_MASK);
3034 work_done = gfar_clean_rx_ring(rx_queue, budget);
3036 if (work_done < budget) {
3038 napi_complete(napi);
3039 /* Clear the halt bit in RSTAT */
3040 gfar_write(®s->rstat, gfargrp->rstat);
3042 spin_lock_irq(&gfargrp->grplock);
3043 imask = gfar_read(®s->imask);
3044 imask |= IMASK_RX_DEFAULT;
3045 gfar_write(®s->imask, imask);
3046 spin_unlock_irq(&gfargrp->grplock);
3052 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3054 struct gfar_priv_grp *gfargrp =
3055 container_of(napi, struct gfar_priv_grp, napi_tx);
3056 struct gfar __iomem *regs = gfargrp->regs;
3057 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3060 /* Clear IEVENT, so interrupts aren't called again
3061 * because of the packets that have already arrived
3063 gfar_write(®s->ievent, IEVENT_TX_MASK);
3065 /* run Tx cleanup to completion */
3066 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3067 gfar_clean_tx_ring(tx_queue);
3069 napi_complete(napi);
3071 spin_lock_irq(&gfargrp->grplock);
3072 imask = gfar_read(®s->imask);
3073 imask |= IMASK_TX_DEFAULT;
3074 gfar_write(®s->imask, imask);
3075 spin_unlock_irq(&gfargrp->grplock);
3080 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3082 struct gfar_priv_grp *gfargrp =
3083 container_of(napi, struct gfar_priv_grp, napi_rx);
3084 struct gfar_private *priv = gfargrp->priv;
3085 struct gfar __iomem *regs = gfargrp->regs;
3086 struct gfar_priv_rx_q *rx_queue = NULL;
3087 int work_done = 0, work_done_per_q = 0;
3088 int i, budget_per_q = 0;
3089 unsigned long rstat_rxf;
3092 /* Clear IEVENT, so interrupts aren't called again
3093 * because of the packets that have already arrived
3095 gfar_write(®s->ievent, IEVENT_RX_MASK);
3097 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
3099 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3101 budget_per_q = budget/num_act_queues;
3103 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3104 /* skip queue if not active */
3105 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3108 rx_queue = priv->rx_queue[i];
3110 gfar_clean_rx_ring(rx_queue, budget_per_q);
3111 work_done += work_done_per_q;
3113 /* finished processing this queue */
3114 if (work_done_per_q < budget_per_q) {
3115 /* clear active queue hw indication */
3116 gfar_write(®s->rstat,
3117 RSTAT_CLEAR_RXF0 >> i);
3120 if (!num_act_queues)
3125 if (!num_act_queues) {
3127 napi_complete(napi);
3129 /* Clear the halt bit in RSTAT */
3130 gfar_write(®s->rstat, gfargrp->rstat);
3132 spin_lock_irq(&gfargrp->grplock);
3133 imask = gfar_read(®s->imask);
3134 imask |= IMASK_RX_DEFAULT;
3135 gfar_write(®s->imask, imask);
3136 spin_unlock_irq(&gfargrp->grplock);
3142 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3144 struct gfar_priv_grp *gfargrp =
3145 container_of(napi, struct gfar_priv_grp, napi_tx);
3146 struct gfar_private *priv = gfargrp->priv;
3147 struct gfar __iomem *regs = gfargrp->regs;
3148 struct gfar_priv_tx_q *tx_queue = NULL;
3149 int has_tx_work = 0;
3152 /* Clear IEVENT, so interrupts aren't called again
3153 * because of the packets that have already arrived
3155 gfar_write(®s->ievent, IEVENT_TX_MASK);
3157 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3158 tx_queue = priv->tx_queue[i];
3159 /* run Tx cleanup to completion */
3160 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3161 gfar_clean_tx_ring(tx_queue);
3168 napi_complete(napi);
3170 spin_lock_irq(&gfargrp->grplock);
3171 imask = gfar_read(®s->imask);
3172 imask |= IMASK_TX_DEFAULT;
3173 gfar_write(®s->imask, imask);
3174 spin_unlock_irq(&gfargrp->grplock);
3181 #ifdef CONFIG_NET_POLL_CONTROLLER
3182 /* Polling 'interrupt' - used by things like netconsole to send skbs
3183 * without having to re-enable interrupts. It's not called while
3184 * the interrupt routine is executing.
3186 static void gfar_netpoll(struct net_device *dev)
3188 struct gfar_private *priv = netdev_priv(dev);
3191 /* If the device has multiple interrupts, run tx/rx */
3192 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3193 for (i = 0; i < priv->num_grps; i++) {
3194 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3196 disable_irq(gfar_irq(grp, TX)->irq);
3197 disable_irq(gfar_irq(grp, RX)->irq);
3198 disable_irq(gfar_irq(grp, ER)->irq);
3199 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3200 enable_irq(gfar_irq(grp, ER)->irq);
3201 enable_irq(gfar_irq(grp, RX)->irq);
3202 enable_irq(gfar_irq(grp, TX)->irq);
3205 for (i = 0; i < priv->num_grps; i++) {
3206 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3208 disable_irq(gfar_irq(grp, TX)->irq);
3209 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3210 enable_irq(gfar_irq(grp, TX)->irq);
3216 /* The interrupt handler for devices with one interrupt */
3217 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3219 struct gfar_priv_grp *gfargrp = grp_id;
3221 /* Save ievent for future reference */
3222 u32 events = gfar_read(&gfargrp->regs->ievent);
3224 /* Check for reception */
3225 if (events & IEVENT_RX_MASK)
3226 gfar_receive(irq, grp_id);
3228 /* Check for transmit completion */
3229 if (events & IEVENT_TX_MASK)
3230 gfar_transmit(irq, grp_id);
3232 /* Check for errors */
3233 if (events & IEVENT_ERR_MASK)
3234 gfar_error(irq, grp_id);
3239 /* Called every time the controller might need to be made
3240 * aware of new link state. The PHY code conveys this
3241 * information through variables in the phydev structure, and this
3242 * function converts those variables into the appropriate
3243 * register values, and can bring down the device if needed.
3245 static void adjust_link(struct net_device *dev)
3247 struct gfar_private *priv = netdev_priv(dev);
3248 struct phy_device *phydev = priv->phydev;
3250 if (unlikely(phydev->link != priv->oldlink ||
3251 (phydev->link && (phydev->duplex != priv->oldduplex ||
3252 phydev->speed != priv->oldspeed))))
3253 gfar_update_link_state(priv);
3256 /* Update the hash table based on the current list of multicast
3257 * addresses we subscribe to. Also, change the promiscuity of
3258 * the device based on the flags (this function is called
3259 * whenever dev->flags is changed
3261 static void gfar_set_multi(struct net_device *dev)
3263 struct netdev_hw_addr *ha;
3264 struct gfar_private *priv = netdev_priv(dev);
3265 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3268 if (dev->flags & IFF_PROMISC) {
3269 /* Set RCTRL to PROM */
3270 tempval = gfar_read(®s->rctrl);
3271 tempval |= RCTRL_PROM;
3272 gfar_write(®s->rctrl, tempval);
3274 /* Set RCTRL to not PROM */
3275 tempval = gfar_read(®s->rctrl);
3276 tempval &= ~(RCTRL_PROM);
3277 gfar_write(®s->rctrl, tempval);
3280 if (dev->flags & IFF_ALLMULTI) {
3281 /* Set the hash to rx all multicast frames */
3282 gfar_write(®s->igaddr0, 0xffffffff);
3283 gfar_write(®s->igaddr1, 0xffffffff);
3284 gfar_write(®s->igaddr2, 0xffffffff);
3285 gfar_write(®s->igaddr3, 0xffffffff);
3286 gfar_write(®s->igaddr4, 0xffffffff);
3287 gfar_write(®s->igaddr5, 0xffffffff);
3288 gfar_write(®s->igaddr6, 0xffffffff);
3289 gfar_write(®s->igaddr7, 0xffffffff);
3290 gfar_write(®s->gaddr0, 0xffffffff);
3291 gfar_write(®s->gaddr1, 0xffffffff);
3292 gfar_write(®s->gaddr2, 0xffffffff);
3293 gfar_write(®s->gaddr3, 0xffffffff);
3294 gfar_write(®s->gaddr4, 0xffffffff);
3295 gfar_write(®s->gaddr5, 0xffffffff);
3296 gfar_write(®s->gaddr6, 0xffffffff);
3297 gfar_write(®s->gaddr7, 0xffffffff);
3302 /* zero out the hash */
3303 gfar_write(®s->igaddr0, 0x0);
3304 gfar_write(®s->igaddr1, 0x0);
3305 gfar_write(®s->igaddr2, 0x0);
3306 gfar_write(®s->igaddr3, 0x0);
3307 gfar_write(®s->igaddr4, 0x0);
3308 gfar_write(®s->igaddr5, 0x0);
3309 gfar_write(®s->igaddr6, 0x0);
3310 gfar_write(®s->igaddr7, 0x0);
3311 gfar_write(®s->gaddr0, 0x0);
3312 gfar_write(®s->gaddr1, 0x0);
3313 gfar_write(®s->gaddr2, 0x0);
3314 gfar_write(®s->gaddr3, 0x0);
3315 gfar_write(®s->gaddr4, 0x0);
3316 gfar_write(®s->gaddr5, 0x0);
3317 gfar_write(®s->gaddr6, 0x0);
3318 gfar_write(®s->gaddr7, 0x0);
3320 /* If we have extended hash tables, we need to
3321 * clear the exact match registers to prepare for
3324 if (priv->extended_hash) {
3325 em_num = GFAR_EM_NUM + 1;
3326 gfar_clear_exact_match(dev);
3333 if (netdev_mc_empty(dev))
3336 /* Parse the list, and set the appropriate bits */
3337 netdev_for_each_mc_addr(ha, dev) {
3339 gfar_set_mac_for_addr(dev, idx, ha->addr);
3342 gfar_set_hash_for_addr(dev, ha->addr);
3348 /* Clears each of the exact match registers to zero, so they
3349 * don't interfere with normal reception
3351 static void gfar_clear_exact_match(struct net_device *dev)
3354 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3356 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3357 gfar_set_mac_for_addr(dev, idx, zero_arr);
3360 /* Set the appropriate hash bit for the given addr */
3361 /* The algorithm works like so:
3362 * 1) Take the Destination Address (ie the multicast address), and
3363 * do a CRC on it (little endian), and reverse the bits of the
3365 * 2) Use the 8 most significant bits as a hash into a 256-entry
3366 * table. The table is controlled through 8 32-bit registers:
3367 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3368 * gaddr7. This means that the 3 most significant bits in the
3369 * hash index which gaddr register to use, and the 5 other bits
3370 * indicate which bit (assuming an IBM numbering scheme, which
3371 * for PowerPC (tm) is usually the case) in the register holds
3374 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3377 struct gfar_private *priv = netdev_priv(dev);
3378 u32 result = ether_crc(ETH_ALEN, addr);
3379 int width = priv->hash_width;
3380 u8 whichbit = (result >> (32 - width)) & 0x1f;
3381 u8 whichreg = result >> (32 - width + 5);
3382 u32 value = (1 << (31-whichbit));
3384 tempval = gfar_read(priv->hash_regs[whichreg]);
3386 gfar_write(priv->hash_regs[whichreg], tempval);
3390 /* There are multiple MAC Address register pairs on some controllers
3391 * This function sets the numth pair to a given address
3393 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3396 struct gfar_private *priv = netdev_priv(dev);
3397 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3399 u32 __iomem *macptr = ®s->macstnaddr1;
3403 /* For a station address of 0x12345678ABCD in transmission
3404 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3405 * MACnADDR2 is set to 0x34120000.
3407 tempval = (addr[5] << 24) | (addr[4] << 16) |
3408 (addr[3] << 8) | addr[2];
3410 gfar_write(macptr, tempval);
3412 tempval = (addr[1] << 24) | (addr[0] << 16);
3414 gfar_write(macptr+1, tempval);
3417 /* GFAR error interrupt handler */
3418 static irqreturn_t gfar_error(int irq, void *grp_id)
3420 struct gfar_priv_grp *gfargrp = grp_id;
3421 struct gfar __iomem *regs = gfargrp->regs;
3422 struct gfar_private *priv= gfargrp->priv;
3423 struct net_device *dev = priv->ndev;
3425 /* Save ievent for future reference */
3426 u32 events = gfar_read(®s->ievent);
3429 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3431 /* Magic Packet is not an error. */
3432 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3433 (events & IEVENT_MAG))
3434 events &= ~IEVENT_MAG;
3437 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3439 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3440 events, gfar_read(®s->imask));
3442 /* Update the error counters */
3443 if (events & IEVENT_TXE) {
3444 dev->stats.tx_errors++;
3446 if (events & IEVENT_LC)
3447 dev->stats.tx_window_errors++;
3448 if (events & IEVENT_CRL)
3449 dev->stats.tx_aborted_errors++;
3450 if (events & IEVENT_XFUN) {
3451 netif_dbg(priv, tx_err, dev,
3452 "TX FIFO underrun, packet dropped\n");
3453 dev->stats.tx_dropped++;
3454 atomic64_inc(&priv->extra_stats.tx_underrun);
3456 schedule_work(&priv->reset_task);
3458 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3460 if (events & IEVENT_BSY) {
3461 dev->stats.rx_errors++;
3462 atomic64_inc(&priv->extra_stats.rx_bsy);
3464 gfar_receive(irq, grp_id);
3466 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3467 gfar_read(®s->rstat));
3469 if (events & IEVENT_BABR) {
3470 dev->stats.rx_errors++;
3471 atomic64_inc(&priv->extra_stats.rx_babr);
3473 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3475 if (events & IEVENT_EBERR) {
3476 atomic64_inc(&priv->extra_stats.eberr);
3477 netif_dbg(priv, rx_err, dev, "bus error\n");
3479 if (events & IEVENT_RXC)
3480 netif_dbg(priv, rx_status, dev, "control frame\n");
3482 if (events & IEVENT_BABT) {
3483 atomic64_inc(&priv->extra_stats.tx_babt);
3484 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3489 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3491 struct phy_device *phydev = priv->phydev;
3494 if (!phydev->duplex)
3497 if (!priv->pause_aneg_en) {
3498 if (priv->tx_pause_en)
3499 val |= MACCFG1_TX_FLOW;
3500 if (priv->rx_pause_en)
3501 val |= MACCFG1_RX_FLOW;
3503 u16 lcl_adv, rmt_adv;
3505 /* get link partner capabilities */
3508 rmt_adv = LPA_PAUSE_CAP;
3509 if (phydev->asym_pause)
3510 rmt_adv |= LPA_PAUSE_ASYM;
3513 if (phydev->advertising & ADVERTISED_Pause)
3514 lcl_adv |= ADVERTISE_PAUSE_CAP;
3515 if (phydev->advertising & ADVERTISED_Asym_Pause)
3516 lcl_adv |= ADVERTISE_PAUSE_ASYM;
3518 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3519 if (flowctrl & FLOW_CTRL_TX)
3520 val |= MACCFG1_TX_FLOW;
3521 if (flowctrl & FLOW_CTRL_RX)
3522 val |= MACCFG1_RX_FLOW;
3528 static noinline void gfar_update_link_state(struct gfar_private *priv)
3530 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3531 struct phy_device *phydev = priv->phydev;
3532 struct gfar_priv_rx_q *rx_queue = NULL;
3535 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3539 u32 tempval1 = gfar_read(®s->maccfg1);
3540 u32 tempval = gfar_read(®s->maccfg2);
3541 u32 ecntrl = gfar_read(®s->ecntrl);
3542 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3544 if (phydev->duplex != priv->oldduplex) {
3545 if (!(phydev->duplex))
3546 tempval &= ~(MACCFG2_FULL_DUPLEX);
3548 tempval |= MACCFG2_FULL_DUPLEX;
3550 priv->oldduplex = phydev->duplex;
3553 if (phydev->speed != priv->oldspeed) {
3554 switch (phydev->speed) {
3557 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3559 ecntrl &= ~(ECNTRL_R100);
3564 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3566 /* Reduced mode distinguishes
3567 * between 10 and 100
3569 if (phydev->speed == SPEED_100)
3570 ecntrl |= ECNTRL_R100;
3572 ecntrl &= ~(ECNTRL_R100);
3575 netif_warn(priv, link, priv->ndev,
3576 "Ack! Speed (%d) is not 10/100/1000!\n",
3581 priv->oldspeed = phydev->speed;
3584 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3585 tempval1 |= gfar_get_flowctrl_cfg(priv);
3587 /* Turn last free buffer recording on */
3588 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3589 for (i = 0; i < priv->num_rx_queues; i++) {
3592 rx_queue = priv->rx_queue[i];
3593 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3594 gfar_write(rx_queue->rfbptr, bdp_dma);
3597 priv->tx_actual_en = 1;
3600 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3601 priv->tx_actual_en = 0;
3603 gfar_write(®s->maccfg1, tempval1);
3604 gfar_write(®s->maccfg2, tempval);
3605 gfar_write(®s->ecntrl, ecntrl);
3610 } else if (priv->oldlink) {
3613 priv->oldduplex = -1;
3616 if (netif_msg_link(priv))
3617 phy_print_status(phydev);
3620 static const struct of_device_id gfar_match[] =
3624 .compatible = "gianfar",
3627 .compatible = "fsl,etsec2",
3631 MODULE_DEVICE_TABLE(of, gfar_match);
3633 /* Structure for a device driver */
3634 static struct platform_driver gfar_driver = {
3636 .name = "fsl-gianfar",
3638 .of_match_table = gfar_match,
3640 .probe = gfar_probe,
3641 .remove = gfar_remove,
3644 module_platform_driver(gfar_driver);