drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/of_mdio.h>
  82 #include <linux/of_platform.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87 #include <linux/net_tstamp.h>
  88
  89 #include <asm/io.h>
  90 #include <asm/reg.h>
  91 #include <asm/irq.h>
  92 #include <asm/uaccess.h>
  93 #include <linux/module.h>
  94 #include <linux/dma-mapping.h>
  95 #include <linux/crc32.h>
  96 #include <linux/mii.h>
  97 #include <linux/phy.h>
  98 #include <linux/phy_fixed.h>
  99 #include <linux/of.h>
 100 #include <linux/of_net.h>
 101
 102 #include "gianfar.h"
 103
 104 #define TX_TIMEOUT      (1*HZ)
 105
 106 const char gfar_driver_version[] = "1.3";
 107
 108 static int gfar_enet_open(struct net_device *dev);
 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 110 static void gfar_reset_task(struct work_struct *work);
 111 static void gfar_timeout(struct net_device *dev);
 112 static int gfar_close(struct net_device *dev);
 113 struct sk_buff *gfar_new_skb(struct net_device *dev);
 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 115                            struct sk_buff *skb);
 116 static int gfar_set_mac_address(struct net_device *dev);
 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 118 static irqreturn_t gfar_error(int irq, void *dev_id);
 119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 121 static void adjust_link(struct net_device *dev);
 122 static void init_registers(struct net_device *dev);
 123 static int init_phy(struct net_device *dev);
 124 static int gfar_probe(struct platform_device *ofdev);
 125 static int gfar_remove(struct platform_device *ofdev);
 126 static void free_skb_resources(struct gfar_private *priv);
 127 static void gfar_set_multi(struct net_device *dev);
 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 129 static void gfar_configure_serdes(struct net_device *dev);
 130 static int gfar_poll(struct napi_struct *napi, int budget);
 131 static int gfar_poll_sq(struct napi_struct *napi, int budget);
 132 #ifdef CONFIG_NET_POLL_CONTROLLER
 133 static void gfar_netpoll(struct net_device *dev);
 134 #endif
 135 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 136 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 137 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 138                                int amount_pull, struct napi_struct *napi);
 139 void gfar_halt(struct net_device *dev);
 140 static void gfar_halt_nodisable(struct net_device *dev);
 141 void gfar_start(struct net_device *dev);
 142 static void gfar_clear_exact_match(struct net_device *dev);
 143 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 144                                   const u8 *addr);
 145 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 146
 147 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 148 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 149 MODULE_LICENSE("GPL");
 150
 151 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 152                             dma_addr_t buf)
 153 {
 154         u32 lstatus;
 155
 156         bdp->bufPtr = buf;
 157
 158         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 159         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 160                 lstatus |= BD_LFLAG(RXBD_WRAP);
 161
 162         eieio();
 163
 164         bdp->lstatus = lstatus;
 165 }
 166
 167 static int gfar_init_bds(struct net_device *ndev)
 168 {
 169         struct gfar_private *priv = netdev_priv(ndev);
 170         struct gfar_priv_tx_q *tx_queue = NULL;
 171         struct gfar_priv_rx_q *rx_queue = NULL;
 172         struct txbd8 *txbdp;
 173         struct rxbd8 *rxbdp;
 174         int i, j;
 175
 176         for (i = 0; i < priv->num_tx_queues; i++) {
 177                 tx_queue = priv->tx_queue[i];
 178                 /* Initialize some variables in our dev structure */
 179                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 180                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 181                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 182                 tx_queue->skb_curtx = 0;
 183                 tx_queue->skb_dirtytx = 0;
 184
 185                 /* Initialize Transmit Descriptor Ring */
 186                 txbdp = tx_queue->tx_bd_base;
 187                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 188                         txbdp->lstatus = 0;
 189                         txbdp->bufPtr = 0;
 190                         txbdp++;
 191                 }
 192
 193                 /* Set the last descriptor in the ring to indicate wrap */
 194                 txbdp--;
 195                 txbdp->status |= TXBD_WRAP;
 196         }
 197
 198         for (i = 0; i < priv->num_rx_queues; i++) {
 199                 rx_queue = priv->rx_queue[i];
 200                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 201                 rx_queue->skb_currx = 0;
 202                 rxbdp = rx_queue->rx_bd_base;
 203
 204                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 205                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 206
 207                         if (skb) {
 208                                 gfar_init_rxbdp(rx_queue, rxbdp,
 209                                                 rxbdp->bufPtr);
 210                         } else {
 211                                 skb = gfar_new_skb(ndev);
 212                                 if (!skb) {
 213                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 214                                         return -ENOMEM;
 215                                 }
 216                                 rx_queue->rx_skbuff[j] = skb;
 217
 218                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 219                         }
 220
 221                         rxbdp++;
 222                 }
 223
 224         }
 225
 226         return 0;
 227 }
 228
 229 static int gfar_alloc_skb_resources(struct net_device *ndev)
 230 {
 231         void *vaddr;
 232         dma_addr_t addr;
 233         int i, j, k;
 234         struct gfar_private *priv = netdev_priv(ndev);
 235         struct device *dev = priv->dev;
 236         struct gfar_priv_tx_q *tx_queue = NULL;
 237         struct gfar_priv_rx_q *rx_queue = NULL;
 238
 239         priv->total_tx_ring_size = 0;
 240         for (i = 0; i < priv->num_tx_queues; i++)
 241                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 242
 243         priv->total_rx_ring_size = 0;
 244         for (i = 0; i < priv->num_rx_queues; i++)
 245                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 246
 247         /* Allocate memory for the buffer descriptors */
 248         vaddr = dma_alloc_coherent(dev,
 249                                    (priv->total_tx_ring_size *
 250                                     sizeof(struct txbd8)) +
 251                                    (priv->total_rx_ring_size *
 252                                     sizeof(struct rxbd8)),
 253                                    &addr, GFP_KERNEL);
 254         if (!vaddr)
 255                 return -ENOMEM;
 256
 257         for (i = 0; i < priv->num_tx_queues; i++) {
 258                 tx_queue = priv->tx_queue[i];
 259                 tx_queue->tx_bd_base = vaddr;
 260                 tx_queue->tx_bd_dma_base = addr;
 261                 tx_queue->dev = ndev;
 262                 /* enet DMA only understands physical addresses */
 263                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 264                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 265         }
 266
 267         /* Start the rx descriptor ring where the tx ring leaves off */
 268         for (i = 0; i < priv->num_rx_queues; i++) {
 269                 rx_queue = priv->rx_queue[i];
 270                 rx_queue->rx_bd_base = vaddr;
 271                 rx_queue->rx_bd_dma_base = addr;
 272                 rx_queue->dev = ndev;
 273                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 274                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 275         }
 276
 277         /* Setup the skbuff rings */
 278         for (i = 0; i < priv->num_tx_queues; i++) {
 279                 tx_queue = priv->tx_queue[i];
 280                 tx_queue->tx_skbuff =
 281                         kmalloc_array(tx_queue->tx_ring_size,
 282                                       sizeof(*tx_queue->tx_skbuff),
 283                                       GFP_KERNEL);
 284                 if (!tx_queue->tx_skbuff)
 285                         goto cleanup;
 286
 287                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 288                         tx_queue->tx_skbuff[k] = NULL;
 289         }
 290
 291         for (i = 0; i < priv->num_rx_queues; i++) {
 292                 rx_queue = priv->rx_queue[i];
 293                 rx_queue->rx_skbuff =
 294                         kmalloc_array(rx_queue->rx_ring_size,
 295                                       sizeof(*rx_queue->rx_skbuff),
 296                                       GFP_KERNEL);
 297                 if (!rx_queue->rx_skbuff)
 298                         goto cleanup;
 299
 300                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 301                         rx_queue->rx_skbuff[j] = NULL;
 302         }
 303
 304         if (gfar_init_bds(ndev))
 305                 goto cleanup;
 306
 307         return 0;
 308
 309 cleanup:
 310         free_skb_resources(priv);
 311         return -ENOMEM;
 312 }
 313
 314 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 315 {
 316         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 317         u32 __iomem *baddr;
 318         int i;
 319
 320         baddr = &regs->tbase0;
 321         for (i = 0; i < priv->num_tx_queues; i++) {
 322                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 323                 baddr += 2;
 324         }
 325
 326         baddr = &regs->rbase0;
 327         for (i = 0; i < priv->num_rx_queues; i++) {
 328                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 329                 baddr += 2;
 330         }
 331 }
 332
 333 static void gfar_init_mac(struct net_device *ndev)
 334 {
 335         struct gfar_private *priv = netdev_priv(ndev);
 336         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 337         u32 rctrl = 0;
 338         u32 tctrl = 0;
 339         u32 attrs = 0;
 340
 341         /* write the tx/rx base registers */
 342         gfar_init_tx_rx_base(priv);
 343
 344         /* Configure the coalescing support */
 345         gfar_configure_coalescing_all(priv);
 346
 347         /* set this when rx hw offload (TOE) functions are being used */
 348         priv->uses_rxfcb = 0;
 349
 350         if (priv->rx_filer_enable) {
 351                 rctrl |= RCTRL_FILREN;
 352                 /* Program the RIR0 reg with the required distribution */
 353                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 354         }
 355
 356         /* Restore PROMISC mode */
 357         if (ndev->flags & IFF_PROMISC)
 358                 rctrl |= RCTRL_PROM;
 359
 360         if (ndev->features & NETIF_F_RXCSUM) {
 361                 rctrl |= RCTRL_CHECKSUMMING;
 362                 priv->uses_rxfcb = 1;
 363         }
 364
 365         if (priv->extended_hash) {
 366                 rctrl |= RCTRL_EXTHASH;
 367
 368                 gfar_clear_exact_match(ndev);
 369                 rctrl |= RCTRL_EMEN;
 370         }
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Insert receive time stamps into padding alignment bytes */
 378         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 379                 rctrl &= ~RCTRL_PAL_MASK;
 380                 rctrl |= RCTRL_PADDING(8);
 381                 priv->padding = 8;
 382         }
 383
 384         /* Enable HW time stamping if requested from user space */
 385         if (priv->hwts_rx_en) {
 386                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 387                 priv->uses_rxfcb = 1;
 388         }
 389
 390         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
 391                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 392                 priv->uses_rxfcb = 1;
 393         }
 394
 395         /* Init rctrl based on our settings */
 396         gfar_write(&regs->rctrl, rctrl);
 397
 398         if (ndev->features & NETIF_F_IP_CSUM)
 399                 tctrl |= TCTRL_INIT_CSUM;
 400
 401         if (priv->prio_sched_en)
 402                 tctrl |= TCTRL_TXSCHED_PRIO;
 403         else {
 404                 tctrl |= TCTRL_TXSCHED_WRRS;
 405                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 406                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 407         }
 408
 409         gfar_write(&regs->tctrl, tctrl);
 410
 411         /* Set the extraction length and index */
 412         attrs = ATTRELI_EL(priv->rx_stash_size) |
 413                 ATTRELI_EI(priv->rx_stash_index);
 414
 415         gfar_write(&regs->attreli, attrs);
 416
 417         /* Start with defaults, and add stashing or locking
 418          * depending on the approprate variables
 419          */
 420         attrs = ATTR_INIT_SETTINGS;
 421
 422         if (priv->bd_stash_en)
 423                 attrs |= ATTR_BDSTASH;
 424
 425         if (priv->rx_stash_size != 0)
 426                 attrs |= ATTR_BUFSTASH;
 427
 428         gfar_write(&regs->attr, attrs);
 429
 430         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 431         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 432         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 433 }
 434
 435 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 436 {
 437         struct gfar_private *priv = netdev_priv(dev);
 438         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 439         unsigned long tx_packets = 0, tx_bytes = 0;
 440         int i;
 441
 442         for (i = 0; i < priv->num_rx_queues; i++) {
 443                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 444                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 445                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 446         }
 447
 448         dev->stats.rx_packets = rx_packets;
 449         dev->stats.rx_bytes   = rx_bytes;
 450         dev->stats.rx_dropped = rx_dropped;
 451
 452         for (i = 0; i < priv->num_tx_queues; i++) {
 453                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 454                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 455         }
 456
 457         dev->stats.tx_bytes   = tx_bytes;
 458         dev->stats.tx_packets = tx_packets;
 459
 460         return &dev->stats;
 461 }
 462
 463 static const struct net_device_ops gfar_netdev_ops = {
 464         .ndo_open = gfar_enet_open,
 465         .ndo_start_xmit = gfar_start_xmit,
 466         .ndo_stop = gfar_close,
 467         .ndo_change_mtu = gfar_change_mtu,
 468         .ndo_set_features = gfar_set_features,
 469         .ndo_set_rx_mode = gfar_set_multi,
 470         .ndo_tx_timeout = gfar_timeout,
 471         .ndo_do_ioctl = gfar_ioctl,
 472         .ndo_get_stats = gfar_get_stats,
 473         .ndo_set_mac_address = eth_mac_addr,
 474         .ndo_validate_addr = eth_validate_addr,
 475 #ifdef CONFIG_NET_POLL_CONTROLLER
 476         .ndo_poll_controller = gfar_netpoll,
 477 #endif
 478 };
 479
 480 void lock_rx_qs(struct gfar_private *priv)
 481 {
 482         int i;
 483
 484         for (i = 0; i < priv->num_rx_queues; i++)
 485                 spin_lock(&priv->rx_queue[i]->rxlock);
 486 }
 487
 488 void lock_tx_qs(struct gfar_private *priv)
 489 {
 490         int i;
 491
 492         for (i = 0; i < priv->num_tx_queues; i++)
 493                 spin_lock(&priv->tx_queue[i]->txlock);
 494 }
 495
 496 void unlock_rx_qs(struct gfar_private *priv)
 497 {
 498         int i;
 499
 500         for (i = 0; i < priv->num_rx_queues; i++)
 501                 spin_unlock(&priv->rx_queue[i]->rxlock);
 502 }
 503
 504 void unlock_tx_qs(struct gfar_private *priv)
 505 {
 506         int i;
 507
 508         for (i = 0; i < priv->num_tx_queues; i++)
 509                 spin_unlock(&priv->tx_queue[i]->txlock);
 510 }
 511
 512 static void free_tx_pointers(struct gfar_private *priv)
 513 {
 514         int i;
 515
 516         for (i = 0; i < priv->num_tx_queues; i++)
 517                 kfree(priv->tx_queue[i]);
 518 }
 519
 520 static void free_rx_pointers(struct gfar_private *priv)
 521 {
 522         int i;
 523
 524         for (i = 0; i < priv->num_rx_queues; i++)
 525                 kfree(priv->rx_queue[i]);
 526 }
 527
 528 static void unmap_group_regs(struct gfar_private *priv)
 529 {
 530         int i;
 531
 532         for (i = 0; i < MAXGROUPS; i++)
 533                 if (priv->gfargrp[i].regs)
 534                         iounmap(priv->gfargrp[i].regs);
 535 }
 536
 537 static void free_gfar_dev(struct gfar_private *priv)
 538 {
 539         int i, j;
 540
 541         for (i = 0; i < priv->num_grps; i++)
 542                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 543                         kfree(priv->gfargrp[i].irqinfo[j]);
 544                         priv->gfargrp[i].irqinfo[j] = NULL;
 545                 }
 546
 547         free_netdev(priv->ndev);
 548 }
 549
 550 static void disable_napi(struct gfar_private *priv)
 551 {
 552         int i;
 553
 554         for (i = 0; i < priv->num_grps; i++)
 555                 napi_disable(&priv->gfargrp[i].napi);
 556 }
 557
 558 static void enable_napi(struct gfar_private *priv)
 559 {
 560         int i;
 561
 562         for (i = 0; i < priv->num_grps; i++)
 563                 napi_enable(&priv->gfargrp[i].napi);
 564 }
 565
 566 static int gfar_parse_group(struct device_node *np,
 567                             struct gfar_private *priv, const char *model)
 568 {
 569         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 570         u32 *queue_mask;
 571         int i;
 572
 573         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 574                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 575                                           GFP_KERNEL);
 576                 if (!grp->irqinfo[i])
 577                         return -ENOMEM;
 578         }
 579
 580         grp->regs = of_iomap(np, 0);
 581         if (!grp->regs)
 582                 return -ENOMEM;
 583
 584         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 585
 586         /* If we aren't the FEC we have multiple interrupts */
 587         if (model && strcasecmp(model, "FEC")) {
 588                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 589                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 590                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 591                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 592                     gfar_irq(grp, ER)->irq == NO_IRQ)
 593                         return -EINVAL;
 594         }
 595
 596         grp->grp_id = priv->num_grps;
 597         grp->priv = priv;
 598         spin_lock_init(&grp->grplock);
 599         if (priv->mode == MQ_MG_MODE) {
 600                 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 601                 grp->rx_bit_map = queue_mask ?
 602                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 603                 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 604                 grp->tx_bit_map = queue_mask ?
 605                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 606         } else {
 607                 grp->rx_bit_map = 0xFF;
 608                 grp->tx_bit_map = 0xFF;
 609         }
 610         priv->num_grps++;
 611
 612         return 0;
 613 }
 614
 615 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 616 {
 617         const char *model;
 618         const char *ctype;
 619         const void *mac_addr;
 620         int err = 0, i;
 621         struct net_device *dev = NULL;
 622         struct gfar_private *priv = NULL;
 623         struct device_node *np = ofdev->dev.of_node;
 624         struct device_node *child = NULL;
 625         const u32 *stash;
 626         const u32 *stash_len;
 627         const u32 *stash_idx;
 628         unsigned int num_tx_qs, num_rx_qs;
 629         u32 *tx_queues, *rx_queues;
 630
 631         if (!np || !of_device_is_available(np))
 632                 return -ENODEV;
 633
 634         /* parse the num of tx and rx queues */
 635         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 636         num_tx_qs = tx_queues ? *tx_queues : 1;
 637
 638         if (num_tx_qs > MAX_TX_QS) {
 639                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 640                        num_tx_qs, MAX_TX_QS);
 641                 pr_err("Cannot do alloc_etherdev, aborting\n");
 642                 return -EINVAL;
 643         }
 644
 645         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 646         num_rx_qs = rx_queues ? *rx_queues : 1;
 647
 648         if (num_rx_qs > MAX_RX_QS) {
 649                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 650                        num_rx_qs, MAX_RX_QS);
 651                 pr_err("Cannot do alloc_etherdev, aborting\n");
 652                 return -EINVAL;
 653         }
 654
 655         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 656         dev = *pdev;
 657         if (NULL == dev)
 658                 return -ENOMEM;
 659
 660         priv = netdev_priv(dev);
 661         priv->ndev = dev;
 662
 663         priv->num_tx_queues = num_tx_qs;
 664         netif_set_real_num_rx_queues(dev, num_rx_qs);
 665         priv->num_rx_queues = num_rx_qs;
 666         priv->num_grps = 0x0;
 667
 668         /* Init Rx queue filer rule set linked list */
 669         INIT_LIST_HEAD(&priv->rx_list.list);
 670         priv->rx_list.count = 0;
 671         mutex_init(&priv->rx_queue_access);
 672
 673         model = of_get_property(np, "model", NULL);
 674
 675         for (i = 0; i < MAXGROUPS; i++)
 676                 priv->gfargrp[i].regs = NULL;
 677
 678         /* Parse and initialize group specific information */
 679         if (of_device_is_compatible(np, "fsl,etsec2")) {
 680                 priv->mode = MQ_MG_MODE;
 681                 for_each_child_of_node(np, child) {
 682                         err = gfar_parse_group(child, priv, model);
 683                         if (err)
 684                                 goto err_grp_init;
 685                 }
 686         } else {
 687                 priv->mode = SQ_SG_MODE;
 688                 err = gfar_parse_group(np, priv, model);
 689                 if (err)
 690                         goto err_grp_init;
 691         }
 692
 693         for (i = 0; i < priv->num_tx_queues; i++)
 694                 priv->tx_queue[i] = NULL;
 695         for (i = 0; i < priv->num_rx_queues; i++)
 696                 priv->rx_queue[i] = NULL;
 697
 698         for (i = 0; i < priv->num_tx_queues; i++) {
 699                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 700                                             GFP_KERNEL);
 701                 if (!priv->tx_queue[i]) {
 702                         err = -ENOMEM;
 703                         goto tx_alloc_failed;
 704                 }
 705                 priv->tx_queue[i]->tx_skbuff = NULL;
 706                 priv->tx_queue[i]->qindex = i;
 707                 priv->tx_queue[i]->dev = dev;
 708                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 709         }
 710
 711         for (i = 0; i < priv->num_rx_queues; i++) {
 712                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 713                                             GFP_KERNEL);
 714                 if (!priv->rx_queue[i]) {
 715                         err = -ENOMEM;
 716                         goto rx_alloc_failed;
 717                 }
 718                 priv->rx_queue[i]->rx_skbuff = NULL;
 719                 priv->rx_queue[i]->qindex = i;
 720                 priv->rx_queue[i]->dev = dev;
 721                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 722         }
 723
 724
 725         stash = of_get_property(np, "bd-stash", NULL);
 726
 727         if (stash) {
 728                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 729                 priv->bd_stash_en = 1;
 730         }
 731
 732         stash_len = of_get_property(np, "rx-stash-len", NULL);
 733
 734         if (stash_len)
 735                 priv->rx_stash_size = *stash_len;
 736
 737         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 738
 739         if (stash_idx)
 740                 priv->rx_stash_index = *stash_idx;
 741
 742         if (stash_len || stash_idx)
 743                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 744
 745         mac_addr = of_get_mac_address(np);
 746
 747         if (mac_addr)
 748                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 749
 750         if (model && !strcasecmp(model, "TSEC"))
 751                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 752                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 753                                      FSL_GIANFAR_DEV_HAS_RMON |
 754                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 755
 756         if (model && !strcasecmp(model, "eTSEC"))
 757                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 758                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 759                                      FSL_GIANFAR_DEV_HAS_RMON |
 760                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 761                                      FSL_GIANFAR_DEV_HAS_PADDING |
 762                                      FSL_GIANFAR_DEV_HAS_CSUM |
 763                                      FSL_GIANFAR_DEV_HAS_VLAN |
 764                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 765                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 766                                      FSL_GIANFAR_DEV_HAS_TIMER;
 767
 768         ctype = of_get_property(np, "phy-connection-type", NULL);
 769
 770         /* We only care about rgmii-id.  The rest are autodetected */
 771         if (ctype && !strcmp(ctype, "rgmii-id"))
 772                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 773         else
 774                 priv->interface = PHY_INTERFACE_MODE_MII;
 775
 776         if (of_get_property(np, "fsl,magic-packet", NULL))
 777                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 778
 779         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 780
 781         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 782         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 783
 784         return 0;
 785
 786 rx_alloc_failed:
 787         free_rx_pointers(priv);
 788 tx_alloc_failed:
 789         free_tx_pointers(priv);
 790 err_grp_init:
 791         unmap_group_regs(priv);
 792         free_gfar_dev(priv);
 793         return err;
 794 }
 795
 796 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 797                                struct ifreq *ifr, int cmd)
 798 {
 799         struct hwtstamp_config config;
 800         struct gfar_private *priv = netdev_priv(netdev);
 801
 802         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 803                 return -EFAULT;
 804
 805         /* reserved for future extensions */
 806         if (config.flags)
 807                 return -EINVAL;
 808
 809         switch (config.tx_type) {
 810         case HWTSTAMP_TX_OFF:
 811                 priv->hwts_tx_en = 0;
 812                 break;
 813         case HWTSTAMP_TX_ON:
 814                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 815                         return -ERANGE;
 816                 priv->hwts_tx_en = 1;
 817                 break;
 818         default:
 819                 return -ERANGE;
 820         }
 821
 822         switch (config.rx_filter) {
 823         case HWTSTAMP_FILTER_NONE:
 824                 if (priv->hwts_rx_en) {
 825                         stop_gfar(netdev);
 826                         priv->hwts_rx_en = 0;
 827                         startup_gfar(netdev);
 828                 }
 829                 break;
 830         default:
 831                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 832                         return -ERANGE;
 833                 if (!priv->hwts_rx_en) {
 834                         stop_gfar(netdev);
 835                         priv->hwts_rx_en = 1;
 836                         startup_gfar(netdev);
 837                 }
 838                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 839                 break;
 840         }
 841
 842         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 843                 -EFAULT : 0;
 844 }
 845
 846 /* Ioctl MII Interface */
 847 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 848 {
 849         struct gfar_private *priv = netdev_priv(dev);
 850
 851         if (!netif_running(dev))
 852                 return -EINVAL;
 853
 854         if (cmd == SIOCSHWTSTAMP)
 855                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 856
 857         if (!priv->phydev)
 858                 return -ENODEV;
 859
 860         return phy_mii_ioctl(priv->phydev, rq, cmd);
 861 }
 862
 863 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 864 {
 865         unsigned int new_bit_map = 0x0;
 866         int mask = 0x1 << (max_qs - 1), i;
 867
 868         for (i = 0; i < max_qs; i++) {
 869                 if (bit_map & mask)
 870                         new_bit_map = new_bit_map + (1 << i);
 871                 mask = mask >> 0x1;
 872         }
 873         return new_bit_map;
 874 }
 875
 876 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 877                                    u32 class)
 878 {
 879         u32 rqfpr = FPR_FILER_MASK;
 880         u32 rqfcr = 0x0;
 881
 882         rqfar--;
 883         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 884         priv->ftp_rqfpr[rqfar] = rqfpr;
 885         priv->ftp_rqfcr[rqfar] = rqfcr;
 886         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 887
 888         rqfar--;
 889         rqfcr = RQFCR_CMP_NOMATCH;
 890         priv->ftp_rqfpr[rqfar] = rqfpr;
 891         priv->ftp_rqfcr[rqfar] = rqfcr;
 892         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 893
 894         rqfar--;
 895         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 896         rqfpr = class;
 897         priv->ftp_rqfcr[rqfar] = rqfcr;
 898         priv->ftp_rqfpr[rqfar] = rqfpr;
 899         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 900
 901         rqfar--;
 902         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 903         rqfpr = class;
 904         priv->ftp_rqfcr[rqfar] = rqfcr;
 905         priv->ftp_rqfpr[rqfar] = rqfpr;
 906         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 907
 908         return rqfar;
 909 }
 910
 911 static void gfar_init_filer_table(struct gfar_private *priv)
 912 {
 913         int i = 0x0;
 914         u32 rqfar = MAX_FILER_IDX;
 915         u32 rqfcr = 0x0;
 916         u32 rqfpr = FPR_FILER_MASK;
 917
 918         /* Default rule */
 919         rqfcr = RQFCR_CMP_MATCH;
 920         priv->ftp_rqfcr[rqfar] = rqfcr;
 921         priv->ftp_rqfpr[rqfar] = rqfpr;
 922         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 923
 924         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 925         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 926         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 927         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 928         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 929         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 930
 931         /* cur_filer_idx indicated the first non-masked rule */
 932         priv->cur_filer_idx = rqfar;
 933
 934         /* Rest are masked rules */
 935         rqfcr = RQFCR_CMP_NOMATCH;
 936         for (i = 0; i < rqfar; i++) {
 937                 priv->ftp_rqfcr[i] = rqfcr;
 938                 priv->ftp_rqfpr[i] = rqfpr;
 939                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 940         }
 941 }
 942
 943 static void gfar_detect_errata(struct gfar_private *priv)
 944 {
 945         struct device *dev = &priv->ofdev->dev;
 946         unsigned int pvr = mfspr(SPRN_PVR);
 947         unsigned int svr = mfspr(SPRN_SVR);
 948         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 949         unsigned int rev = svr & 0xffff;
 950
 951         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 952         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 953             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 954                 priv->errata |= GFAR_ERRATA_74;
 955
 956         /* MPC8313 and MPC837x all rev */
 957         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 958             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 959                 priv->errata |= GFAR_ERRATA_76;
 960
 961         /* MPC8313 and MPC837x all rev */
 962         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 963             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 964                 priv->errata |= GFAR_ERRATA_A002;
 965
 966         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 967         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 968             (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 969                 priv->errata |= GFAR_ERRATA_12;
 970
 971         if (priv->errata)
 972                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 973                          priv->errata);
 974 }
 975
 976 /* Set up the ethernet device structure, private data,
 977  * and anything else we need before we start
 978  */
 979 static int gfar_probe(struct platform_device *ofdev)
 980 {
 981         u32 tempval;
 982         struct net_device *dev = NULL;
 983         struct gfar_private *priv = NULL;
 984         struct gfar __iomem *regs = NULL;
 985         int err = 0, i, grp_idx = 0;
 986         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 987         u32 isrg = 0;
 988         u32 __iomem *baddr;
 989
 990         err = gfar_of_init(ofdev, &dev);
 991
 992         if (err)
 993                 return err;
 994
 995         priv = netdev_priv(dev);
 996         priv->ndev = dev;
 997         priv->ofdev = ofdev;
 998         priv->dev = &ofdev->dev;
 999         SET_NETDEV_DEV(dev, &ofdev->dev);
1000
1001         spin_lock_init(&priv->bflock);
1002         INIT_WORK(&priv->reset_task, gfar_reset_task);
1003
1004         platform_set_drvdata(ofdev, priv);
1005         regs = priv->gfargrp[0].regs;
1006
1007         gfar_detect_errata(priv);
1008
1009         /* Stop the DMA engine now, in case it was running before
1010          * (The firmware could have used it, and left it running).
1011          */
1012         gfar_halt(dev);
1013
1014         /* Reset MAC layer */
1015         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1016
1017         /* We need to delay at least 3 TX clocks */
1018         udelay(2);
1019
1020         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1021         gfar_write(&regs->maccfg1, tempval);
1022
1023         /* Initialize MACCFG2. */
1024         tempval = MACCFG2_INIT_SETTINGS;
1025         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1026                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1027         gfar_write(&regs->maccfg2, tempval);
1028
1029         /* Initialize ECNTRL */
1030         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1031
1032         /* Set the dev->base_addr to the gfar reg region */
1033         dev->base_addr = (unsigned long) regs;
1034
1035         /* Fill in the dev structure */
1036         dev->watchdog_timeo = TX_TIMEOUT;
1037         dev->mtu = 1500;
1038         dev->netdev_ops = &gfar_netdev_ops;
1039         dev->ethtool_ops = &gfar_ethtool_ops;
1040
1041         /* Register for napi ...We are registering NAPI for each grp */
1042         if (priv->mode == SQ_SG_MODE)
1043                 netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
1044                                GFAR_DEV_WEIGHT);
1045         else
1046                 for (i = 0; i < priv->num_grps; i++)
1047                         netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1048                                        GFAR_DEV_WEIGHT);
1049
1050         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1051                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1052                                    NETIF_F_RXCSUM;
1053                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1054                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1055         }
1056
1057         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1058                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1059                                     NETIF_F_HW_VLAN_CTAG_RX;
1060                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1061         }
1062
1063         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1064                 priv->extended_hash = 1;
1065                 priv->hash_width = 9;
1066
1067                 priv->hash_regs[0] = &regs->igaddr0;
1068                 priv->hash_regs[1] = &regs->igaddr1;
1069                 priv->hash_regs[2] = &regs->igaddr2;
1070                 priv->hash_regs[3] = &regs->igaddr3;
1071                 priv->hash_regs[4] = &regs->igaddr4;
1072                 priv->hash_regs[5] = &regs->igaddr5;
1073                 priv->hash_regs[6] = &regs->igaddr6;
1074                 priv->hash_regs[7] = &regs->igaddr7;
1075                 priv->hash_regs[8] = &regs->gaddr0;
1076                 priv->hash_regs[9] = &regs->gaddr1;
1077                 priv->hash_regs[10] = &regs->gaddr2;
1078                 priv->hash_regs[11] = &regs->gaddr3;
1079                 priv->hash_regs[12] = &regs->gaddr4;
1080                 priv->hash_regs[13] = &regs->gaddr5;
1081                 priv->hash_regs[14] = &regs->gaddr6;
1082                 priv->hash_regs[15] = &regs->gaddr7;
1083
1084         } else {
1085                 priv->extended_hash = 0;
1086                 priv->hash_width = 8;
1087
1088                 priv->hash_regs[0] = &regs->gaddr0;
1089                 priv->hash_regs[1] = &regs->gaddr1;
1090                 priv->hash_regs[2] = &regs->gaddr2;
1091                 priv->hash_regs[3] = &regs->gaddr3;
1092                 priv->hash_regs[4] = &regs->gaddr4;
1093                 priv->hash_regs[5] = &regs->gaddr5;
1094                 priv->hash_regs[6] = &regs->gaddr6;
1095                 priv->hash_regs[7] = &regs->gaddr7;
1096         }
1097
1098         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1099                 priv->padding = DEFAULT_PADDING;
1100         else
1101                 priv->padding = 0;
1102
1103         if (dev->features & NETIF_F_IP_CSUM ||
1104             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1105                 dev->needed_headroom = GMAC_FCB_LEN;
1106
1107         /* Program the isrg regs only if number of grps > 1 */
1108         if (priv->num_grps > 1) {
1109                 baddr = &regs->isrg0;
1110                 for (i = 0; i < priv->num_grps; i++) {
1111                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1112                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1113                         gfar_write(baddr, isrg);
1114                         baddr++;
1115                         isrg = 0x0;
1116                 }
1117         }
1118
1119         /* Need to reverse the bit maps as  bit_map's MSB is q0
1120          * but, for_each_set_bit parses from right to left, which
1121          * basically reverses the queue numbers
1122          */
1123         for (i = 0; i< priv->num_grps; i++) {
1124                 priv->gfargrp[i].tx_bit_map =
1125                         reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1126                 priv->gfargrp[i].rx_bit_map =
1127                         reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1128         }
1129
1130         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1131          * also assign queues to groups
1132          */
1133         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1134                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1135
1136                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1137                                  priv->num_rx_queues) {
1138                         priv->gfargrp[grp_idx].num_rx_queues++;
1139                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1140                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1141                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1142                 }
1143                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1144
1145                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1146                                  priv->num_tx_queues) {
1147                         priv->gfargrp[grp_idx].num_tx_queues++;
1148                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1149                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1150                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1151                 }
1152                 priv->gfargrp[grp_idx].rstat = rstat;
1153                 priv->gfargrp[grp_idx].tstat = tstat;
1154                 rstat = tstat =0;
1155         }
1156
1157         gfar_write(&regs->rqueue, rqueue);
1158         gfar_write(&regs->tqueue, tqueue);
1159
1160         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1161
1162         /* Initializing some of the rx/tx queue level parameters */
1163         for (i = 0; i < priv->num_tx_queues; i++) {
1164                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1165                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1166                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1167                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1168         }
1169
1170         for (i = 0; i < priv->num_rx_queues; i++) {
1171                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1172                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1173                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1174         }
1175
1176         /* always enable rx filer */
1177         priv->rx_filer_enable = 1;
1178         /* Enable most messages by default */
1179         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1180         /* use pritority h/w tx queue scheduling for single queue devices */
1181         if (priv->num_tx_queues == 1)
1182                 priv->prio_sched_en = 1;
1183
1184         /* Carrier starts down, phylib will bring it up */
1185         netif_carrier_off(dev);
1186
1187         err = register_netdev(dev);
1188
1189         if (err) {
1190                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1191                 goto register_fail;
1192         }
1193
1194         device_init_wakeup(&dev->dev,
1195                            priv->device_flags &
1196                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1197
1198         /* fill out IRQ number and name fields */
1199         for (i = 0; i < priv->num_grps; i++) {
1200                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1201                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1202                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1203                                 dev->name, "_g", '0' + i, "_tx");
1204                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1205                                 dev->name, "_g", '0' + i, "_rx");
1206                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1207                                 dev->name, "_g", '0' + i, "_er");
1208                 } else
1209                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1210         }
1211
1212         /* Initialize the filer table */
1213         gfar_init_filer_table(priv);
1214
1215         /* Create all the sysfs files */
1216         gfar_init_sysfs(dev);
1217
1218         /* Print out the device info */
1219         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1220
1221         /* Even more device info helps when determining which kernel
1222          * provided which set of benchmarks.
1223          */
1224         netdev_info(dev, "Running with NAPI enabled\n");
1225         for (i = 0; i < priv->num_rx_queues; i++)
1226                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1227                             i, priv->rx_queue[i]->rx_ring_size);
1228         for (i = 0; i < priv->num_tx_queues; i++)
1229                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1230                             i, priv->tx_queue[i]->tx_ring_size);
1231
1232         return 0;
1233
1234 register_fail:
1235         unmap_group_regs(priv);
1236         free_tx_pointers(priv);
1237         free_rx_pointers(priv);
1238         if (priv->phy_node)
1239                 of_node_put(priv->phy_node);
1240         if (priv->tbi_node)
1241                 of_node_put(priv->tbi_node);
1242         free_gfar_dev(priv);
1243         return err;
1244 }
1245
1246 static int gfar_remove(struct platform_device *ofdev)
1247 {
1248         struct gfar_private *priv = platform_get_drvdata(ofdev);
1249
1250         if (priv->phy_node)
1251                 of_node_put(priv->phy_node);
1252         if (priv->tbi_node)
1253                 of_node_put(priv->tbi_node);
1254
1255         unregister_netdev(priv->ndev);
1256         unmap_group_regs(priv);
1257         free_gfar_dev(priv);
1258
1259         return 0;
1260 }
1261
1262 #ifdef CONFIG_PM
1263
1264 static int gfar_suspend(struct device *dev)
1265 {
1266         struct gfar_private *priv = dev_get_drvdata(dev);
1267         struct net_device *ndev = priv->ndev;
1268         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1269         unsigned long flags;
1270         u32 tempval;
1271
1272         int magic_packet = priv->wol_en &&
1273                            (priv->device_flags &
1274                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1275
1276         netif_device_detach(ndev);
1277
1278         if (netif_running(ndev)) {
1279
1280                 local_irq_save(flags);
1281                 lock_tx_qs(priv);
1282                 lock_rx_qs(priv);
1283
1284                 gfar_halt_nodisable(ndev);
1285
1286                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1287                 tempval = gfar_read(&regs->maccfg1);
1288
1289                 tempval &= ~MACCFG1_TX_EN;
1290
1291                 if (!magic_packet)
1292                         tempval &= ~MACCFG1_RX_EN;
1293
1294                 gfar_write(&regs->maccfg1, tempval);
1295
1296                 unlock_rx_qs(priv);
1297                 unlock_tx_qs(priv);
1298                 local_irq_restore(flags);
1299
1300                 disable_napi(priv);
1301
1302                 if (magic_packet) {
1303                         /* Enable interrupt on Magic Packet */
1304                         gfar_write(&regs->imask, IMASK_MAG);
1305
1306                         /* Enable Magic Packet mode */
1307                         tempval = gfar_read(&regs->maccfg2);
1308                         tempval |= MACCFG2_MPEN;
1309                         gfar_write(&regs->maccfg2, tempval);
1310                 } else {
1311                         phy_stop(priv->phydev);
1312                 }
1313         }
1314
1315         return 0;
1316 }
1317
1318 static int gfar_resume(struct device *dev)
1319 {
1320         struct gfar_private *priv = dev_get_drvdata(dev);
1321         struct net_device *ndev = priv->ndev;
1322         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1323         unsigned long flags;
1324         u32 tempval;
1325         int magic_packet = priv->wol_en &&
1326                            (priv->device_flags &
1327                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1328
1329         if (!netif_running(ndev)) {
1330                 netif_device_attach(ndev);
1331                 return 0;
1332         }
1333
1334         if (!magic_packet && priv->phydev)
1335                 phy_start(priv->phydev);
1336
1337         /* Disable Magic Packet mode, in case something
1338          * else woke us up.
1339          */
1340         local_irq_save(flags);
1341         lock_tx_qs(priv);
1342         lock_rx_qs(priv);
1343
1344         tempval = gfar_read(&regs->maccfg2);
1345         tempval &= ~MACCFG2_MPEN;
1346         gfar_write(&regs->maccfg2, tempval);
1347
1348         gfar_start(ndev);
1349
1350         unlock_rx_qs(priv);
1351         unlock_tx_qs(priv);
1352         local_irq_restore(flags);
1353
1354         netif_device_attach(ndev);
1355
1356         enable_napi(priv);
1357
1358         return 0;
1359 }
1360
1361 static int gfar_restore(struct device *dev)
1362 {
1363         struct gfar_private *priv = dev_get_drvdata(dev);
1364         struct net_device *ndev = priv->ndev;
1365
1366         if (!netif_running(ndev)) {
1367                 netif_device_attach(ndev);
1368
1369                 return 0;
1370         }
1371
1372         if (gfar_init_bds(ndev)) {
1373                 free_skb_resources(priv);
1374                 return -ENOMEM;
1375         }
1376
1377         init_registers(ndev);
1378         gfar_set_mac_address(ndev);
1379         gfar_init_mac(ndev);
1380         gfar_start(ndev);
1381
1382         priv->oldlink = 0;
1383         priv->oldspeed = 0;
1384         priv->oldduplex = -1;
1385
1386         if (priv->phydev)
1387                 phy_start(priv->phydev);
1388
1389         netif_device_attach(ndev);
1390         enable_napi(priv);
1391
1392         return 0;
1393 }
1394
1395 static struct dev_pm_ops gfar_pm_ops = {
1396         .suspend = gfar_suspend,
1397         .resume = gfar_resume,
1398         .freeze = gfar_suspend,
1399         .thaw = gfar_resume,
1400         .restore = gfar_restore,
1401 };
1402
1403 #define GFAR_PM_OPS (&gfar_pm_ops)
1404
1405 #else
1406
1407 #define GFAR_PM_OPS NULL
1408
1409 #endif
1410
1411 /* Reads the controller's registers to determine what interface
1412  * connects it to the PHY.
1413  */
1414 static phy_interface_t gfar_get_interface(struct net_device *dev)
1415 {
1416         struct gfar_private *priv = netdev_priv(dev);
1417         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1418         u32 ecntrl;
1419
1420         ecntrl = gfar_read(&regs->ecntrl);
1421
1422         if (ecntrl & ECNTRL_SGMII_MODE)
1423                 return PHY_INTERFACE_MODE_SGMII;
1424
1425         if (ecntrl & ECNTRL_TBI_MODE) {
1426                 if (ecntrl & ECNTRL_REDUCED_MODE)
1427                         return PHY_INTERFACE_MODE_RTBI;
1428                 else
1429                         return PHY_INTERFACE_MODE_TBI;
1430         }
1431
1432         if (ecntrl & ECNTRL_REDUCED_MODE) {
1433                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1434                         return PHY_INTERFACE_MODE_RMII;
1435                 }
1436                 else {
1437                         phy_interface_t interface = priv->interface;
1438
1439                         /* This isn't autodetected right now, so it must
1440                          * be set by the device tree or platform code.
1441                          */
1442                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1443                                 return PHY_INTERFACE_MODE_RGMII_ID;
1444
1445                         return PHY_INTERFACE_MODE_RGMII;
1446                 }
1447         }
1448
1449         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1450                 return PHY_INTERFACE_MODE_GMII;
1451
1452         return PHY_INTERFACE_MODE_MII;
1453 }
1454
1455
1456 /* Initializes driver's PHY state, and attaches to the PHY.
1457  * Returns 0 on success.
1458  */
1459 static int init_phy(struct net_device *dev)
1460 {
1461         struct gfar_private *priv = netdev_priv(dev);
1462         uint gigabit_support =
1463                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1464                 SUPPORTED_1000baseT_Full : 0;
1465         phy_interface_t interface;
1466
1467         priv->oldlink = 0;
1468         priv->oldspeed = 0;
1469         priv->oldduplex = -1;
1470
1471         interface = gfar_get_interface(dev);
1472
1473         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1474                                       interface);
1475         if (!priv->phydev)
1476                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1477                                                          interface);
1478         if (!priv->phydev) {
1479                 dev_err(&dev->dev, "could not attach to PHY\n");
1480                 return -ENODEV;
1481         }
1482
1483         if (interface == PHY_INTERFACE_MODE_SGMII)
1484                 gfar_configure_serdes(dev);
1485
1486         /* Remove any features not supported by the controller */
1487         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1488         priv->phydev->advertising = priv->phydev->supported;
1489
1490         return 0;
1491 }
1492
1493 /* Initialize TBI PHY interface for communicating with the
1494  * SERDES lynx PHY on the chip.  We communicate with this PHY
1495  * through the MDIO bus on each controller, treating it as a
1496  * "normal" PHY at the address found in the TBIPA register.  We assume
1497  * that the TBIPA register is valid.  Either the MDIO bus code will set
1498  * it to a value that doesn't conflict with other PHYs on the bus, or the
1499  * value doesn't matter, as there are no other PHYs on the bus.
1500  */
1501 static void gfar_configure_serdes(struct net_device *dev)
1502 {
1503         struct gfar_private *priv = netdev_priv(dev);
1504         struct phy_device *tbiphy;
1505
1506         if (!priv->tbi_node) {
1507                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1508                                     "device tree specify a tbi-handle\n");
1509                 return;
1510         }
1511
1512         tbiphy = of_phy_find_device(priv->tbi_node);
1513         if (!tbiphy) {
1514                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1515                 return;
1516         }
1517
1518         /* If the link is already up, we must already be ok, and don't need to
1519          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1520          * everything for us?  Resetting it takes the link down and requires
1521          * several seconds for it to come back.
1522          */
1523         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1524                 return;
1525
1526         /* Single clk mode, mii mode off(for serdes communication) */
1527         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1528
1529         phy_write(tbiphy, MII_ADVERTISE,
1530                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1531                   ADVERTISE_1000XPSE_ASYM);
1532
1533         phy_write(tbiphy, MII_BMCR,
1534                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1535                   BMCR_SPEED1000);
1536 }
1537
1538 static void init_registers(struct net_device *dev)
1539 {
1540         struct gfar_private *priv = netdev_priv(dev);
1541         struct gfar __iomem *regs = NULL;
1542         int i;
1543
1544         for (i = 0; i < priv->num_grps; i++) {
1545                 regs = priv->gfargrp[i].regs;
1546                 /* Clear IEVENT */
1547                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1548
1549                 /* Initialize IMASK */
1550                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1551         }
1552
1553         regs = priv->gfargrp[0].regs;
1554         /* Init hash registers to zero */
1555         gfar_write(&regs->igaddr0, 0);
1556         gfar_write(&regs->igaddr1, 0);
1557         gfar_write(&regs->igaddr2, 0);
1558         gfar_write(&regs->igaddr3, 0);
1559         gfar_write(&regs->igaddr4, 0);
1560         gfar_write(&regs->igaddr5, 0);
1561         gfar_write(&regs->igaddr6, 0);
1562         gfar_write(&regs->igaddr7, 0);
1563
1564         gfar_write(&regs->gaddr0, 0);
1565         gfar_write(&regs->gaddr1, 0);
1566         gfar_write(&regs->gaddr2, 0);
1567         gfar_write(&regs->gaddr3, 0);
1568         gfar_write(&regs->gaddr4, 0);
1569         gfar_write(&regs->gaddr5, 0);
1570         gfar_write(&regs->gaddr6, 0);
1571         gfar_write(&regs->gaddr7, 0);
1572
1573         /* Zero out the rmon mib registers if it has them */
1574         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1575                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1576
1577                 /* Mask off the CAM interrupts */
1578                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1579                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1580         }
1581
1582         /* Initialize the max receive buffer length */
1583         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1584
1585         /* Initialize the Minimum Frame Length Register */
1586         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1587 }
1588
1589 static int __gfar_is_rx_idle(struct gfar_private *priv)
1590 {
1591         u32 res;
1592
1593         /* Normaly TSEC should not hang on GRS commands, so we should
1594          * actually wait for IEVENT_GRSC flag.
1595          */
1596         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1597                 return 0;
1598
1599         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1600          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1601          * and the Rx can be safely reset.
1602          */
1603         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1604         res &= 0x7f807f80;
1605         if ((res & 0xffff) == (res >> 16))
1606                 return 1;
1607
1608         return 0;
1609 }
1610
1611 /* Halt the receive and transmit queues */
1612 static void gfar_halt_nodisable(struct net_device *dev)
1613 {
1614         struct gfar_private *priv = netdev_priv(dev);
1615         struct gfar __iomem *regs = NULL;
1616         u32 tempval;
1617         int i;
1618
1619         for (i = 0; i < priv->num_grps; i++) {
1620                 regs = priv->gfargrp[i].regs;
1621                 /* Mask all interrupts */
1622                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1623
1624                 /* Clear all interrupts */
1625                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1626         }
1627
1628         regs = priv->gfargrp[0].regs;
1629         /* Stop the DMA, and wait for it to stop */
1630         tempval = gfar_read(&regs->dmactrl);
1631         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1632             (DMACTRL_GRS | DMACTRL_GTS)) {
1633                 int ret;
1634
1635                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1636                 gfar_write(&regs->dmactrl, tempval);
1637
1638                 do {
1639                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1640                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1641                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1642                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1643                                 ret = __gfar_is_rx_idle(priv);
1644                 } while (!ret);
1645         }
1646 }
1647
1648 /* Halt the receive and transmit queues */
1649 void gfar_halt(struct net_device *dev)
1650 {
1651         struct gfar_private *priv = netdev_priv(dev);
1652         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1653         u32 tempval;
1654
1655         gfar_halt_nodisable(dev);
1656
1657         /* Disable Rx and Tx */
1658         tempval = gfar_read(&regs->maccfg1);
1659         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1660         gfar_write(&regs->maccfg1, tempval);
1661 }
1662
1663 static void free_grp_irqs(struct gfar_priv_grp *grp)
1664 {
1665         free_irq(gfar_irq(grp, TX)->irq, grp);
1666         free_irq(gfar_irq(grp, RX)->irq, grp);
1667         free_irq(gfar_irq(grp, ER)->irq, grp);
1668 }
1669
1670 void stop_gfar(struct net_device *dev)
1671 {
1672         struct gfar_private *priv = netdev_priv(dev);
1673         unsigned long flags;
1674         int i;
1675
1676         phy_stop(priv->phydev);
1677
1678
1679         /* Lock it down */
1680         local_irq_save(flags);
1681         lock_tx_qs(priv);
1682         lock_rx_qs(priv);
1683
1684         gfar_halt(dev);
1685
1686         unlock_rx_qs(priv);
1687         unlock_tx_qs(priv);
1688         local_irq_restore(flags);
1689
1690         /* Free the IRQs */
1691         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1692                 for (i = 0; i < priv->num_grps; i++)
1693                         free_grp_irqs(&priv->gfargrp[i]);
1694         } else {
1695                 for (i = 0; i < priv->num_grps; i++)
1696                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1697                                  &priv->gfargrp[i]);
1698         }
1699
1700         free_skb_resources(priv);
1701 }
1702
1703 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1704 {
1705         struct txbd8 *txbdp;
1706         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1707         int i, j;
1708
1709         txbdp = tx_queue->tx_bd_base;
1710
1711         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1712                 if (!tx_queue->tx_skbuff[i])
1713                         continue;
1714
1715                 dma_unmap_single(priv->dev, txbdp->bufPtr,
1716                                  txbdp->length, DMA_TO_DEVICE);
1717                 txbdp->lstatus = 0;
1718                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1719                      j++) {
1720                         txbdp++;
1721                         dma_unmap_page(priv->dev, txbdp->bufPtr,
1722                                        txbdp->length, DMA_TO_DEVICE);
1723                 }
1724                 txbdp++;
1725                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1726                 tx_queue->tx_skbuff[i] = NULL;
1727         }
1728         kfree(tx_queue->tx_skbuff);
1729         tx_queue->tx_skbuff = NULL;
1730 }
1731
1732 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1733 {
1734         struct rxbd8 *rxbdp;
1735         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1736         int i;
1737
1738         rxbdp = rx_queue->rx_bd_base;
1739
1740         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1741                 if (rx_queue->rx_skbuff[i]) {
1742                         dma_unmap_single(priv->dev, rxbdp->bufPtr,
1743                                          priv->rx_buffer_size,
1744                                          DMA_FROM_DEVICE);
1745                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1746                         rx_queue->rx_skbuff[i] = NULL;
1747                 }
1748                 rxbdp->lstatus = 0;
1749                 rxbdp->bufPtr = 0;
1750                 rxbdp++;
1751         }
1752         kfree(rx_queue->rx_skbuff);
1753         rx_queue->rx_skbuff = NULL;
1754 }
1755
1756 /* If there are any tx skbs or rx skbs still around, free them.
1757  * Then free tx_skbuff and rx_skbuff
1758  */
1759 static void free_skb_resources(struct gfar_private *priv)
1760 {
1761         struct gfar_priv_tx_q *tx_queue = NULL;
1762         struct gfar_priv_rx_q *rx_queue = NULL;
1763         int i;
1764
1765         /* Go through all the buffer descriptors and free their data buffers */
1766         for (i = 0; i < priv->num_tx_queues; i++) {
1767                 struct netdev_queue *txq;
1768
1769                 tx_queue = priv->tx_queue[i];
1770                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1771                 if (tx_queue->tx_skbuff)
1772                         free_skb_tx_queue(tx_queue);
1773                 netdev_tx_reset_queue(txq);
1774         }
1775
1776         for (i = 0; i < priv->num_rx_queues; i++) {
1777                 rx_queue = priv->rx_queue[i];
1778                 if (rx_queue->rx_skbuff)
1779                         free_skb_rx_queue(rx_queue);
1780         }
1781
1782         dma_free_coherent(priv->dev,
1783                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1784                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1785                           priv->tx_queue[0]->tx_bd_base,
1786                           priv->tx_queue[0]->tx_bd_dma_base);
1787 }
1788
1789 void gfar_start(struct net_device *dev)
1790 {
1791         struct gfar_private *priv = netdev_priv(dev);
1792         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1793         u32 tempval;
1794         int i = 0;
1795
1796         /* Enable Rx and Tx in MACCFG1 */
1797         tempval = gfar_read(&regs->maccfg1);
1798         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1799         gfar_write(&regs->maccfg1, tempval);
1800
1801         /* Initialize DMACTRL to have WWR and WOP */
1802         tempval = gfar_read(&regs->dmactrl);
1803         tempval |= DMACTRL_INIT_SETTINGS;
1804         gfar_write(&regs->dmactrl, tempval);
1805
1806         /* Make sure we aren't stopped */
1807         tempval = gfar_read(&regs->dmactrl);
1808         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1809         gfar_write(&regs->dmactrl, tempval);
1810
1811         for (i = 0; i < priv->num_grps; i++) {
1812                 regs = priv->gfargrp[i].regs;
1813                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1814                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1815                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1816                 /* Unmask the interrupts we look for */
1817                 gfar_write(&regs->imask, IMASK_DEFAULT);
1818         }
1819
1820         dev->trans_start = jiffies; /* prevent tx timeout */
1821 }
1822
1823 static void gfar_configure_coalescing(struct gfar_private *priv,
1824                                unsigned long tx_mask, unsigned long rx_mask)
1825 {
1826         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1827         u32 __iomem *baddr;
1828
1829         if (priv->mode == MQ_MG_MODE) {
1830                 int i = 0;
1831
1832                 baddr = &regs->txic0;
1833                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1834                         gfar_write(baddr + i, 0);
1835                         if (likely(priv->tx_queue[i]->txcoalescing))
1836                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1837                 }
1838
1839                 baddr = &regs->rxic0;
1840                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1841                         gfar_write(baddr + i, 0);
1842                         if (likely(priv->rx_queue[i]->rxcoalescing))
1843                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1844                 }
1845         } else {
1846                 /* Backward compatible case -- even if we enable
1847                  * multiple queues, there's only single reg to program
1848                  */
1849                 gfar_write(&regs->txic, 0);
1850                 if (likely(priv->tx_queue[0]->txcoalescing))
1851                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1852
1853                 gfar_write(&regs->rxic, 0);
1854                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1855                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1856         }
1857 }
1858
1859 void gfar_configure_coalescing_all(struct gfar_private *priv)
1860 {
1861         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1862 }
1863
1864 static int register_grp_irqs(struct gfar_priv_grp *grp)
1865 {
1866         struct gfar_private *priv = grp->priv;
1867         struct net_device *dev = priv->ndev;
1868         int err;
1869
1870         /* If the device has multiple interrupts, register for
1871          * them.  Otherwise, only register for the one
1872          */
1873         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1874                 /* Install our interrupt handlers for Error,
1875                  * Transmit, and Receive
1876                  */
1877                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1878                                   gfar_irq(grp, ER)->name, grp);
1879                 if (err < 0) {
1880                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1881                                   gfar_irq(grp, ER)->irq);
1882
1883                         goto err_irq_fail;
1884                 }
1885                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1886                                   gfar_irq(grp, TX)->name, grp);
1887                 if (err < 0) {
1888                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1889                                   gfar_irq(grp, TX)->irq);
1890                         goto tx_irq_fail;
1891                 }
1892                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1893                                   gfar_irq(grp, RX)->name, grp);
1894                 if (err < 0) {
1895                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1896                                   gfar_irq(grp, RX)->irq);
1897                         goto rx_irq_fail;
1898                 }
1899         } else {
1900                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1901                                   gfar_irq(grp, TX)->name, grp);
1902                 if (err < 0) {
1903                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1904                                   gfar_irq(grp, TX)->irq);
1905                         goto err_irq_fail;
1906                 }
1907         }
1908
1909         return 0;
1910
1911 rx_irq_fail:
1912         free_irq(gfar_irq(grp, TX)->irq, grp);
1913 tx_irq_fail:
1914         free_irq(gfar_irq(grp, ER)->irq, grp);
1915 err_irq_fail:
1916         return err;
1917
1918 }
1919
1920 /* Bring the controller up and running */
1921 int startup_gfar(struct net_device *ndev)
1922 {
1923         struct gfar_private *priv = netdev_priv(ndev);
1924         struct gfar __iomem *regs = NULL;
1925         int err, i, j;
1926
1927         for (i = 0; i < priv->num_grps; i++) {
1928                 regs= priv->gfargrp[i].regs;
1929                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1930         }
1931
1932         regs= priv->gfargrp[0].regs;
1933         err = gfar_alloc_skb_resources(ndev);
1934         if (err)
1935                 return err;
1936
1937         gfar_init_mac(ndev);
1938
1939         for (i = 0; i < priv->num_grps; i++) {
1940                 err = register_grp_irqs(&priv->gfargrp[i]);
1941                 if (err) {
1942                         for (j = 0; j < i; j++)
1943                                 free_grp_irqs(&priv->gfargrp[j]);
1944                         goto irq_fail;
1945                 }
1946         }
1947
1948         /* Start the controller */
1949         gfar_start(ndev);
1950
1951         phy_start(priv->phydev);
1952
1953         gfar_configure_coalescing_all(priv);
1954
1955         return 0;
1956
1957 irq_fail:
1958         free_skb_resources(priv);
1959         return err;
1960 }
1961
1962 /* Called when something needs to use the ethernet device
1963  * Returns 0 for success.
1964  */
1965 static int gfar_enet_open(struct net_device *dev)
1966 {
1967         struct gfar_private *priv = netdev_priv(dev);
1968         int err;
1969
1970         enable_napi(priv);
1971
1972         /* Initialize a bunch of registers */
1973         init_registers(dev);
1974
1975         gfar_set_mac_address(dev);
1976
1977         err = init_phy(dev);
1978
1979         if (err) {
1980                 disable_napi(priv);
1981                 return err;
1982         }
1983
1984         err = startup_gfar(dev);
1985         if (err) {
1986                 disable_napi(priv);
1987                 return err;
1988         }
1989
1990         netif_tx_start_all_queues(dev);
1991
1992         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1993
1994         return err;
1995 }
1996
1997 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1998 {
1999         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2000
2001         memset(fcb, 0, GMAC_FCB_LEN);
2002
2003         return fcb;
2004 }
2005
2006 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2007                                     int fcb_length)
2008 {
2009         /* If we're here, it's a IP packet with a TCP or UDP
2010          * payload.  We set it to checksum, using a pseudo-header
2011          * we provide
2012          */
2013         u8 flags = TXFCB_DEFAULT;
2014
2015         /* Tell the controller what the protocol is
2016          * And provide the already calculated phcs
2017          */
2018         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2019                 flags |= TXFCB_UDP;
2020                 fcb->phcs = udp_hdr(skb)->check;
2021         } else
2022                 fcb->phcs = tcp_hdr(skb)->check;
2023
2024         /* l3os is the distance between the start of the
2025          * frame (skb->data) and the start of the IP hdr.
2026          * l4os is the distance between the start of the
2027          * l3 hdr and the l4 hdr
2028          */
2029         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2030         fcb->l4os = skb_network_header_len(skb);
2031
2032         fcb->flags = flags;
2033 }
2034
2035 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2036 {
2037         fcb->flags |= TXFCB_VLN;
2038         fcb->vlctl = vlan_tx_tag_get(skb);
2039 }
2040
2041 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2042                                       struct txbd8 *base, int ring_size)
2043 {
2044         struct txbd8 *new_bd = bdp + stride;
2045
2046         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2047 }
2048
2049 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2050                                       int ring_size)
2051 {
2052         return skip_txbd(bdp, 1, base, ring_size);
2053 }
2054
2055 /* This is called by the kernel when a frame is ready for transmission.
2056  * It is pointed to by the dev->hard_start_xmit function pointer
2057  */
2058 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2059 {
2060         struct gfar_private *priv = netdev_priv(dev);
2061         struct gfar_priv_tx_q *tx_queue = NULL;
2062         struct netdev_queue *txq;
2063         struct gfar __iomem *regs = NULL;
2064         struct txfcb *fcb = NULL;
2065         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2066         u32 lstatus;
2067         int i, rq = 0, do_tstamp = 0;
2068         u32 bufaddr;
2069         unsigned long flags;
2070         unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2071
2072         /* TOE=1 frames larger than 2500 bytes may see excess delays
2073          * before start of transmission.
2074          */
2075         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2076                      skb->ip_summed == CHECKSUM_PARTIAL &&
2077                      skb->len > 2500)) {
2078                 int ret;
2079
2080                 ret = skb_checksum_help(skb);
2081                 if (ret)
2082                         return ret;
2083         }
2084
2085         rq = skb->queue_mapping;
2086         tx_queue = priv->tx_queue[rq];
2087         txq = netdev_get_tx_queue(dev, rq);
2088         base = tx_queue->tx_bd_base;
2089         regs = tx_queue->grp->regs;
2090
2091         /* check if time stamp should be generated */
2092         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2093                      priv->hwts_tx_en)) {
2094                 do_tstamp = 1;
2095                 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2096         }
2097
2098         /* make space for additional header when fcb is needed */
2099         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2100              vlan_tx_tag_present(skb) ||
2101              unlikely(do_tstamp)) &&
2102             (skb_headroom(skb) < fcb_length)) {
2103                 struct sk_buff *skb_new;
2104
2105                 skb_new = skb_realloc_headroom(skb, fcb_length);
2106                 if (!skb_new) {
2107                         dev->stats.tx_errors++;
2108                         kfree_skb(skb);
2109                         return NETDEV_TX_OK;
2110                 }
2111
2112                 if (skb->sk)
2113                         skb_set_owner_w(skb_new, skb->sk);
2114                 consume_skb(skb);
2115                 skb = skb_new;
2116         }
2117
2118         /* total number of fragments in the SKB */
2119         nr_frags = skb_shinfo(skb)->nr_frags;
2120
2121         /* calculate the required number of TxBDs for this skb */
2122         if (unlikely(do_tstamp))
2123                 nr_txbds = nr_frags + 2;
2124         else
2125                 nr_txbds = nr_frags + 1;
2126
2127         /* check if there is space to queue this packet */
2128         if (nr_txbds > tx_queue->num_txbdfree) {
2129                 /* no space, stop the queue */
2130                 netif_tx_stop_queue(txq);
2131                 dev->stats.tx_fifo_errors++;
2132                 return NETDEV_TX_BUSY;
2133         }
2134
2135         /* Update transmit stats */
2136         tx_queue->stats.tx_bytes += skb->len;
2137         tx_queue->stats.tx_packets++;
2138
2139         txbdp = txbdp_start = tx_queue->cur_tx;
2140         lstatus = txbdp->lstatus;
2141
2142         /* Time stamp insertion requires one additional TxBD */
2143         if (unlikely(do_tstamp))
2144                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2145                                                  tx_queue->tx_ring_size);
2146
2147         if (nr_frags == 0) {
2148                 if (unlikely(do_tstamp))
2149                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2150                                                           TXBD_INTERRUPT);
2151                 else
2152                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2153         } else {
2154                 /* Place the fragment addresses and lengths into the TxBDs */
2155                 for (i = 0; i < nr_frags; i++) {
2156                         /* Point at the next BD, wrapping as needed */
2157                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2158
2159                         length = skb_shinfo(skb)->frags[i].size;
2160
2161                         lstatus = txbdp->lstatus | length |
2162                                   BD_LFLAG(TXBD_READY);
2163
2164                         /* Handle the last BD specially */
2165                         if (i == nr_frags - 1)
2166                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2167
2168                         bufaddr = skb_frag_dma_map(priv->dev,
2169                                                    &skb_shinfo(skb)->frags[i],
2170                                                    0,
2171                                                    length,
2172                                                    DMA_TO_DEVICE);
2173
2174                         /* set the TxBD length and buffer pointer */
2175                         txbdp->bufPtr = bufaddr;
2176                         txbdp->lstatus = lstatus;
2177                 }
2178
2179                 lstatus = txbdp_start->lstatus;
2180         }
2181
2182         /* Add TxPAL between FCB and frame if required */
2183         if (unlikely(do_tstamp)) {
2184                 skb_push(skb, GMAC_TXPAL_LEN);
2185                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2186         }
2187
2188         /* Set up checksumming */
2189         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2190                 fcb = gfar_add_fcb(skb);
2191                 /* as specified by errata */
2192                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2193                              ((unsigned long)fcb % 0x20) > 0x18)) {
2194                         __skb_pull(skb, GMAC_FCB_LEN);
2195                         skb_checksum_help(skb);
2196                 } else {
2197                         lstatus |= BD_LFLAG(TXBD_TOE);
2198                         gfar_tx_checksum(skb, fcb, fcb_length);
2199                 }
2200         }
2201
2202         if (vlan_tx_tag_present(skb)) {
2203                 if (unlikely(NULL == fcb)) {
2204                         fcb = gfar_add_fcb(skb);
2205                         lstatus |= BD_LFLAG(TXBD_TOE);
2206                 }
2207
2208                 gfar_tx_vlan(skb, fcb);
2209         }
2210
2211         /* Setup tx hardware time stamping if requested */
2212         if (unlikely(do_tstamp)) {
2213                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2214                 if (fcb == NULL)
2215                         fcb = gfar_add_fcb(skb);
2216                 fcb->ptp = 1;
2217                 lstatus |= BD_LFLAG(TXBD_TOE);
2218         }
2219
2220         txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2221                                              skb_headlen(skb), DMA_TO_DEVICE);
2222
2223         /* If time stamping is requested one additional TxBD must be set up. The
2224          * first TxBD points to the FCB and must have a data length of
2225          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2226          * the full frame length.
2227          */
2228         if (unlikely(do_tstamp)) {
2229                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2230                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2231                                          (skb_headlen(skb) - fcb_length);
2232                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2233         } else {
2234                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2235         }
2236
2237         netdev_tx_sent_queue(txq, skb->len);
2238
2239         /* We can work in parallel with gfar_clean_tx_ring(), except
2240          * when modifying num_txbdfree. Note that we didn't grab the lock
2241          * when we were reading the num_txbdfree and checking for available
2242          * space, that's because outside of this function it can only grow,
2243          * and once we've got needed space, it cannot suddenly disappear.
2244          *
2245          * The lock also protects us from gfar_error(), which can modify
2246          * regs->tstat and thus retrigger the transfers, which is why we
2247          * also must grab the lock before setting ready bit for the first
2248          * to be transmitted BD.
2249          */
2250         spin_lock_irqsave(&tx_queue->txlock, flags);
2251
2252         /* The powerpc-specific eieio() is used, as wmb() has too strong
2253          * semantics (it requires synchronization between cacheable and
2254          * uncacheable mappings, which eieio doesn't provide and which we
2255          * don't need), thus requiring a more expensive sync instruction.  At
2256          * some point, the set of architecture-independent barrier functions
2257          * should be expanded to include weaker barriers.
2258          */
2259         eieio();
2260
2261         txbdp_start->lstatus = lstatus;
2262
2263         eieio(); /* force lstatus write before tx_skbuff */
2264
2265         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2266
2267         /* Update the current skb pointer to the next entry we will use
2268          * (wrapping if necessary)
2269          */
2270         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2271                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2272
2273         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2274
2275         /* reduce TxBD free count */
2276         tx_queue->num_txbdfree -= (nr_txbds);
2277
2278         /* If the next BD still needs to be cleaned up, then the bds
2279          * are full.  We need to tell the kernel to stop sending us stuff.
2280          */
2281         if (!tx_queue->num_txbdfree) {
2282                 netif_tx_stop_queue(txq);
2283
2284                 dev->stats.tx_fifo_errors++;
2285         }
2286
2287         /* Tell the DMA to go go go */
2288         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2289
2290         /* Unlock priv */
2291         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2292
2293         return NETDEV_TX_OK;
2294 }
2295
2296 /* Stops the kernel queue, and halts the controller */
2297 static int gfar_close(struct net_device *dev)
2298 {
2299         struct gfar_private *priv = netdev_priv(dev);
2300
2301         disable_napi(priv);
2302
2303         cancel_work_sync(&priv->reset_task);
2304         stop_gfar(dev);
2305
2306         /* Disconnect from the PHY */
2307         phy_disconnect(priv->phydev);
2308         priv->phydev = NULL;
2309
2310         netif_tx_stop_all_queues(dev);
2311
2312         return 0;
2313 }
2314
2315 /* Changes the mac address if the controller is not running. */
2316 static int gfar_set_mac_address(struct net_device *dev)
2317 {
2318         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2319
2320         return 0;
2321 }
2322
2323 /* Check if rx parser should be activated */
2324 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2325 {
2326         struct gfar __iomem *regs;
2327         u32 tempval;
2328
2329         regs = priv->gfargrp[0].regs;
2330
2331         tempval = gfar_read(&regs->rctrl);
2332         /* If parse is no longer required, then disable parser */
2333         if (tempval & RCTRL_REQ_PARSER) {
2334                 tempval |= RCTRL_PRSDEP_INIT;
2335                 priv->uses_rxfcb = 1;
2336         } else {
2337                 tempval &= ~RCTRL_PRSDEP_INIT;
2338                 priv->uses_rxfcb = 0;
2339         }
2340         gfar_write(&regs->rctrl, tempval);
2341 }
2342
2343 /* Enables and disables VLAN insertion/extraction */
2344 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2345 {
2346         struct gfar_private *priv = netdev_priv(dev);
2347         struct gfar __iomem *regs = NULL;
2348         unsigned long flags;
2349         u32 tempval;
2350
2351         regs = priv->gfargrp[0].regs;
2352         local_irq_save(flags);
2353         lock_rx_qs(priv);
2354
2355         if (features & NETIF_F_HW_VLAN_CTAG_TX) {
2356                 /* Enable VLAN tag insertion */
2357                 tempval = gfar_read(&regs->tctrl);
2358                 tempval |= TCTRL_VLINS;
2359                 gfar_write(&regs->tctrl, tempval);
2360         } else {
2361                 /* Disable VLAN tag insertion */
2362                 tempval = gfar_read(&regs->tctrl);
2363                 tempval &= ~TCTRL_VLINS;
2364                 gfar_write(&regs->tctrl, tempval);
2365         }
2366
2367         if (features & NETIF_F_HW_VLAN_CTAG_RX) {
2368                 /* Enable VLAN tag extraction */
2369                 tempval = gfar_read(&regs->rctrl);
2370                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2371                 gfar_write(&regs->rctrl, tempval);
2372                 priv->uses_rxfcb = 1;
2373         } else {
2374                 /* Disable VLAN tag extraction */
2375                 tempval = gfar_read(&regs->rctrl);
2376                 tempval &= ~RCTRL_VLEX;
2377                 gfar_write(&regs->rctrl, tempval);
2378
2379                 gfar_check_rx_parser_mode(priv);
2380         }
2381
2382         gfar_change_mtu(dev, dev->mtu);
2383
2384         unlock_rx_qs(priv);
2385         local_irq_restore(flags);
2386 }
2387
2388 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2389 {
2390         int tempsize, tempval;
2391         struct gfar_private *priv = netdev_priv(dev);
2392         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2393         int oldsize = priv->rx_buffer_size;
2394         int frame_size = new_mtu + ETH_HLEN;
2395
2396         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2397                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2398                 return -EINVAL;
2399         }
2400
2401         if (priv->uses_rxfcb)
2402                 frame_size += GMAC_FCB_LEN;
2403
2404         frame_size += priv->padding;
2405
2406         tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2407                    INCREMENTAL_BUFFER_SIZE;
2408
2409         /* Only stop and start the controller if it isn't already
2410          * stopped, and we changed something
2411          */
2412         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2413                 stop_gfar(dev);
2414
2415         priv->rx_buffer_size = tempsize;
2416
2417         dev->mtu = new_mtu;
2418
2419         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2420         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2421
2422         /* If the mtu is larger than the max size for standard
2423          * ethernet frames (ie, a jumbo frame), then set maccfg2
2424          * to allow huge frames, and to check the length
2425          */
2426         tempval = gfar_read(&regs->maccfg2);
2427
2428         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2429             gfar_has_errata(priv, GFAR_ERRATA_74))
2430                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2431         else
2432                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2433
2434         gfar_write(&regs->maccfg2, tempval);
2435
2436         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2437                 startup_gfar(dev);
2438
2439         return 0;
2440 }
2441
2442 /* gfar_reset_task gets scheduled when a packet has not been
2443  * transmitted after a set amount of time.
2444  * For now, assume that clearing out all the structures, and
2445  * starting over will fix the problem.
2446  */
2447 static void gfar_reset_task(struct work_struct *work)
2448 {
2449         struct gfar_private *priv = container_of(work, struct gfar_private,
2450                                                  reset_task);
2451         struct net_device *dev = priv->ndev;
2452
2453         if (dev->flags & IFF_UP) {
2454                 netif_tx_stop_all_queues(dev);
2455                 stop_gfar(dev);
2456                 startup_gfar(dev);
2457                 netif_tx_start_all_queues(dev);
2458         }
2459
2460         netif_tx_schedule_all(dev);
2461 }
2462
2463 static void gfar_timeout(struct net_device *dev)
2464 {
2465         struct gfar_private *priv = netdev_priv(dev);
2466
2467         dev->stats.tx_errors++;
2468         schedule_work(&priv->reset_task);
2469 }
2470
2471 static void gfar_align_skb(struct sk_buff *skb)
2472 {
2473         /* We need the data buffer to be aligned properly.  We will reserve
2474          * as many bytes as needed to align the data properly
2475          */
2476         skb_reserve(skb, RXBUF_ALIGNMENT -
2477                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2478 }
2479
2480 /* Interrupt Handler for Transmit complete */
2481 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2482 {
2483         struct net_device *dev = tx_queue->dev;
2484         struct netdev_queue *txq;
2485         struct gfar_private *priv = netdev_priv(dev);
2486         struct txbd8 *bdp, *next = NULL;
2487         struct txbd8 *lbdp = NULL;
2488         struct txbd8 *base = tx_queue->tx_bd_base;
2489         struct sk_buff *skb;
2490         int skb_dirtytx;
2491         int tx_ring_size = tx_queue->tx_ring_size;
2492         int frags = 0, nr_txbds = 0;
2493         int i;
2494         int howmany = 0;
2495         int tqi = tx_queue->qindex;
2496         unsigned int bytes_sent = 0;
2497         u32 lstatus;
2498         size_t buflen;
2499
2500         txq = netdev_get_tx_queue(dev, tqi);
2501         bdp = tx_queue->dirty_tx;
2502         skb_dirtytx = tx_queue->skb_dirtytx;
2503
2504         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2505                 unsigned long flags;
2506
2507                 frags = skb_shinfo(skb)->nr_frags;
2508
2509                 /* When time stamping, one additional TxBD must be freed.
2510                  * Also, we need to dma_unmap_single() the TxPAL.
2511                  */
2512                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2513                         nr_txbds = frags + 2;
2514                 else
2515                         nr_txbds = frags + 1;
2516
2517                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2518
2519                 lstatus = lbdp->lstatus;
2520
2521                 /* Only clean completed frames */
2522                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2523                     (lstatus & BD_LENGTH_MASK))
2524                         break;
2525
2526                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2527                         next = next_txbd(bdp, base, tx_ring_size);
2528                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2529                 } else
2530                         buflen = bdp->length;
2531
2532                 dma_unmap_single(priv->dev, bdp->bufPtr,
2533                                  buflen, DMA_TO_DEVICE);
2534
2535                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2536                         struct skb_shared_hwtstamps shhwtstamps;
2537                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2538
2539                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2540                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2541                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2542                         skb_tstamp_tx(skb, &shhwtstamps);
2543                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2544                         bdp = next;
2545                 }
2546
2547                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2548                 bdp = next_txbd(bdp, base, tx_ring_size);
2549
2550                 for (i = 0; i < frags; i++) {
2551                         dma_unmap_page(priv->dev, bdp->bufPtr,
2552                                        bdp->length, DMA_TO_DEVICE);
2553                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2554                         bdp = next_txbd(bdp, base, tx_ring_size);
2555                 }
2556
2557                 bytes_sent += skb->len;
2558
2559                 dev_kfree_skb_any(skb);
2560
2561                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2562
2563                 skb_dirtytx = (skb_dirtytx + 1) &
2564                               TX_RING_MOD_MASK(tx_ring_size);
2565
2566                 howmany++;
2567                 spin_lock_irqsave(&tx_queue->txlock, flags);
2568                 tx_queue->num_txbdfree += nr_txbds;
2569                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2570         }
2571
2572         /* If we freed a buffer, we can restart transmission, if necessary */
2573         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2574                 netif_wake_subqueue(dev, tqi);
2575
2576         /* Update dirty indicators */
2577         tx_queue->skb_dirtytx = skb_dirtytx;
2578         tx_queue->dirty_tx = bdp;
2579
2580         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2581 }
2582
2583 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2584 {
2585         unsigned long flags;
2586
2587         spin_lock_irqsave(&gfargrp->grplock, flags);
2588         if (napi_schedule_prep(&gfargrp->napi)) {
2589                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2590                 __napi_schedule(&gfargrp->napi);
2591         } else {
2592                 /* Clear IEVENT, so interrupts aren't called again
2593                  * because of the packets that have already arrived.
2594                  */
2595                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2596         }
2597         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2598
2599 }
2600
2601 /* Interrupt Handler for Transmit complete */
2602 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2603 {
2604         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2605         return IRQ_HANDLED;
2606 }
2607
2608 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2609                            struct sk_buff *skb)
2610 {
2611         struct net_device *dev = rx_queue->dev;
2612         struct gfar_private *priv = netdev_priv(dev);
2613         dma_addr_t buf;
2614
2615         buf = dma_map_single(priv->dev, skb->data,
2616                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2617         gfar_init_rxbdp(rx_queue, bdp, buf);
2618 }
2619
2620 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2621 {
2622         struct gfar_private *priv = netdev_priv(dev);
2623         struct sk_buff *skb;
2624
2625         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2626         if (!skb)
2627                 return NULL;
2628
2629         gfar_align_skb(skb);
2630
2631         return skb;
2632 }
2633
2634 struct sk_buff *gfar_new_skb(struct net_device *dev)
2635 {
2636         return gfar_alloc_skb(dev);
2637 }
2638
2639 static inline void count_errors(unsigned short status, struct net_device *dev)
2640 {
2641         struct gfar_private *priv = netdev_priv(dev);
2642         struct net_device_stats *stats = &dev->stats;
2643         struct gfar_extra_stats *estats = &priv->extra_stats;
2644
2645         /* If the packet was truncated, none of the other errors matter */
2646         if (status & RXBD_TRUNCATED) {
2647                 stats->rx_length_errors++;
2648
2649                 atomic64_inc(&estats->rx_trunc);
2650
2651                 return;
2652         }
2653         /* Count the errors, if there were any */
2654         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2655                 stats->rx_length_errors++;
2656
2657                 if (status & RXBD_LARGE)
2658                         atomic64_inc(&estats->rx_large);
2659                 else
2660                         atomic64_inc(&estats->rx_short);
2661         }
2662         if (status & RXBD_NONOCTET) {
2663                 stats->rx_frame_errors++;
2664                 atomic64_inc(&estats->rx_nonoctet);
2665         }
2666         if (status & RXBD_CRCERR) {
2667                 atomic64_inc(&estats->rx_crcerr);
2668                 stats->rx_crc_errors++;
2669         }
2670         if (status & RXBD_OVERRUN) {
2671                 atomic64_inc(&estats->rx_overrun);
2672                 stats->rx_crc_errors++;
2673         }
2674 }
2675
2676 irqreturn_t gfar_receive(int irq, void *grp_id)
2677 {
2678         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2679         return IRQ_HANDLED;
2680 }
2681
2682 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2683 {
2684         /* If valid headers were found, and valid sums
2685          * were verified, then we tell the kernel that no
2686          * checksumming is necessary.  Otherwise, it is [FIXME]
2687          */
2688         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2689                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2690         else
2691                 skb_checksum_none_assert(skb);
2692 }
2693
2694
2695 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2696 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2697                                int amount_pull, struct napi_struct *napi)
2698 {
2699         struct gfar_private *priv = netdev_priv(dev);
2700         struct rxfcb *fcb = NULL;
2701
2702         /* fcb is at the beginning if exists */
2703         fcb = (struct rxfcb *)skb->data;
2704
2705         /* Remove the FCB from the skb
2706          * Remove the padded bytes, if there are any
2707          */
2708         if (amount_pull) {
2709                 skb_record_rx_queue(skb, fcb->rq);
2710                 skb_pull(skb, amount_pull);
2711         }
2712
2713         /* Get receive timestamp from the skb */
2714         if (priv->hwts_rx_en) {
2715                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2716                 u64 *ns = (u64 *) skb->data;
2717
2718                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2719                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2720         }
2721
2722         if (priv->padding)
2723                 skb_pull(skb, priv->padding);
2724
2725         if (dev->features & NETIF_F_RXCSUM)
2726                 gfar_rx_checksum(skb, fcb);
2727
2728         /* Tell the skb what kind of packet this is */
2729         skb->protocol = eth_type_trans(skb, dev);
2730
2731         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2732          * Even if vlan rx accel is disabled, on some chips
2733          * RXFCB_VLN is pseudo randomly set.
2734          */
2735         if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2736             fcb->flags & RXFCB_VLN)
2737                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
2738
2739         /* Send the packet up the stack */
2740         napi_gro_receive(napi, skb);
2741
2742 }
2743
2744 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2745  * until the budget/quota has been reached. Returns the number
2746  * of frames handled
2747  */
2748 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2749 {
2750         struct net_device *dev = rx_queue->dev;
2751         struct rxbd8 *bdp, *base;
2752         struct sk_buff *skb;
2753         int pkt_len;
2754         int amount_pull;
2755         int howmany = 0;
2756         struct gfar_private *priv = netdev_priv(dev);
2757
2758         /* Get the first full descriptor */
2759         bdp = rx_queue->cur_rx;
2760         base = rx_queue->rx_bd_base;
2761
2762         amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2763
2764         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2765                 struct sk_buff *newskb;
2766
2767                 rmb();
2768
2769                 /* Add another skb for the future */
2770                 newskb = gfar_new_skb(dev);
2771
2772                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2773
2774                 dma_unmap_single(priv->dev, bdp->bufPtr,
2775                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2776
2777                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2778                              bdp->length > priv->rx_buffer_size))
2779                         bdp->status = RXBD_LARGE;
2780
2781                 /* We drop the frame if we failed to allocate a new buffer */
2782                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2783                              bdp->status & RXBD_ERR)) {
2784                         count_errors(bdp->status, dev);
2785
2786                         if (unlikely(!newskb))
2787                                 newskb = skb;
2788                         else if (skb)
2789                                 dev_kfree_skb(skb);
2790                 } else {
2791                         /* Increment the number of packets */
2792                         rx_queue->stats.rx_packets++;
2793                         howmany++;
2794
2795                         if (likely(skb)) {
2796                                 pkt_len = bdp->length - ETH_FCS_LEN;
2797                                 /* Remove the FCS from the packet length */
2798                                 skb_put(skb, pkt_len);
2799                                 rx_queue->stats.rx_bytes += pkt_len;
2800                                 skb_record_rx_queue(skb, rx_queue->qindex);
2801                                 gfar_process_frame(dev, skb, amount_pull,
2802                                                    &rx_queue->grp->napi);
2803
2804                         } else {
2805                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2806                                 rx_queue->stats.rx_dropped++;
2807                                 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2808                         }
2809
2810                 }
2811
2812                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2813
2814                 /* Setup the new bdp */
2815                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2816
2817                 /* Update to the next pointer */
2818                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2819
2820                 /* update to point at the next skb */
2821                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2822                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2823         }
2824
2825         /* Update the current rxbd pointer to be the next one */
2826         rx_queue->cur_rx = bdp;
2827
2828         return howmany;
2829 }
2830
2831 static int gfar_poll_sq(struct napi_struct *napi, int budget)
2832 {
2833         struct gfar_priv_grp *gfargrp =
2834                 container_of(napi, struct gfar_priv_grp, napi);
2835         struct gfar __iomem *regs = gfargrp->regs;
2836         struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0];
2837         struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0];
2838         int work_done = 0;
2839
2840         /* Clear IEVENT, so interrupts aren't called again
2841          * because of the packets that have already arrived
2842          */
2843         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2844
2845         /* run Tx cleanup to completion */
2846         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2847                 gfar_clean_tx_ring(tx_queue);
2848
2849         work_done = gfar_clean_rx_ring(rx_queue, budget);
2850
2851         if (work_done < budget) {
2852                 napi_complete(napi);
2853                 /* Clear the halt bit in RSTAT */
2854                 gfar_write(&regs->rstat, gfargrp->rstat);
2855
2856                 gfar_write(&regs->imask, IMASK_DEFAULT);
2857
2858                 /* If we are coalescing interrupts, update the timer
2859                  * Otherwise, clear it
2860                  */
2861                 gfar_write(&regs->txic, 0);
2862                 if (likely(tx_queue->txcoalescing))
2863                         gfar_write(&regs->txic, tx_queue->txic);
2864
2865                 gfar_write(&regs->rxic, 0);
2866                 if (unlikely(rx_queue->rxcoalescing))
2867                         gfar_write(&regs->rxic, rx_queue->rxic);
2868         }
2869
2870         return work_done;
2871 }
2872
2873 static int gfar_poll(struct napi_struct *napi, int budget)
2874 {
2875         struct gfar_priv_grp *gfargrp =
2876                 container_of(napi, struct gfar_priv_grp, napi);
2877         struct gfar_private *priv = gfargrp->priv;
2878         struct gfar __iomem *regs = gfargrp->regs;
2879         struct gfar_priv_tx_q *tx_queue = NULL;
2880         struct gfar_priv_rx_q *rx_queue = NULL;
2881         int work_done = 0, work_done_per_q = 0;
2882         int i, budget_per_q = 0;
2883         int has_tx_work;
2884         unsigned long rstat_rxf;
2885         int num_act_queues;
2886
2887         /* Clear IEVENT, so interrupts aren't called again
2888          * because of the packets that have already arrived
2889          */
2890         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2891
2892         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2893
2894         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2895         if (num_act_queues)
2896                 budget_per_q = budget/num_act_queues;
2897
2898         while (1) {
2899                 has_tx_work = 0;
2900                 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2901                         tx_queue = priv->tx_queue[i];
2902                         /* run Tx cleanup to completion */
2903                         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2904                                 gfar_clean_tx_ring(tx_queue);
2905                                 has_tx_work = 1;
2906                         }
2907                 }
2908
2909                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2910                         /* skip queue if not active */
2911                         if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2912                                 continue;
2913
2914                         rx_queue = priv->rx_queue[i];
2915                         work_done_per_q =
2916                                 gfar_clean_rx_ring(rx_queue, budget_per_q);
2917                         work_done += work_done_per_q;
2918
2919                         /* finished processing this queue */
2920                         if (work_done_per_q < budget_per_q) {
2921                                 /* clear active queue hw indication */
2922                                 gfar_write(&regs->rstat,
2923                                            RSTAT_CLEAR_RXF0 >> i);
2924                                 rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i);
2925                                 num_act_queues--;
2926
2927                                 if (!num_act_queues)
2928                                         break;
2929                                 /* recompute budget per Rx queue */
2930                                 budget_per_q =
2931                                         (budget - work_done) / num_act_queues;
2932                         }
2933                 }
2934
2935                 if (work_done >= budget)
2936                         break;
2937
2938                 if (!num_act_queues && !has_tx_work) {
2939
2940                         napi_complete(napi);
2941
2942                         /* Clear the halt bit in RSTAT */
2943                         gfar_write(&regs->rstat, gfargrp->rstat);
2944
2945                         gfar_write(&regs->imask, IMASK_DEFAULT);
2946
2947                         /* If we are coalescing interrupts, update the timer
2948                          * Otherwise, clear it
2949                          */
2950                         gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2951                                                   gfargrp->tx_bit_map);
2952                         break;
2953                 }
2954         }
2955
2956         return work_done;
2957 }
2958
2959 #ifdef CONFIG_NET_POLL_CONTROLLER
2960 /* Polling 'interrupt' - used by things like netconsole to send skbs
2961  * without having to re-enable interrupts. It's not called while
2962  * the interrupt routine is executing.
2963  */
2964 static void gfar_netpoll(struct net_device *dev)
2965 {
2966         struct gfar_private *priv = netdev_priv(dev);
2967         int i;
2968
2969         /* If the device has multiple interrupts, run tx/rx */
2970         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2971                 for (i = 0; i < priv->num_grps; i++) {
2972                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
2973
2974                         disable_irq(gfar_irq(grp, TX)->irq);
2975                         disable_irq(gfar_irq(grp, RX)->irq);
2976                         disable_irq(gfar_irq(grp, ER)->irq);
2977                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2978                         enable_irq(gfar_irq(grp, ER)->irq);
2979                         enable_irq(gfar_irq(grp, RX)->irq);
2980                         enable_irq(gfar_irq(grp, TX)->irq);
2981                 }
2982         } else {
2983                 for (i = 0; i < priv->num_grps; i++) {
2984                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
2985
2986                         disable_irq(gfar_irq(grp, TX)->irq);
2987                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2988                         enable_irq(gfar_irq(grp, TX)->irq);
2989                 }
2990         }
2991 }
2992 #endif
2993
2994 /* The interrupt handler for devices with one interrupt */
2995 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2996 {
2997         struct gfar_priv_grp *gfargrp = grp_id;
2998
2999         /* Save ievent for future reference */
3000         u32 events = gfar_read(&gfargrp->regs->ievent);
3001
3002         /* Check for reception */
3003         if (events & IEVENT_RX_MASK)
3004                 gfar_receive(irq, grp_id);
3005
3006         /* Check for transmit completion */
3007         if (events & IEVENT_TX_MASK)
3008                 gfar_transmit(irq, grp_id);
3009
3010         /* Check for errors */
3011         if (events & IEVENT_ERR_MASK)
3012                 gfar_error(irq, grp_id);
3013
3014         return IRQ_HANDLED;
3015 }
3016
3017 /* Called every time the controller might need to be made
3018  * aware of new link state.  The PHY code conveys this
3019  * information through variables in the phydev structure, and this
3020  * function converts those variables into the appropriate
3021  * register values, and can bring down the device if needed.
3022  */
3023 static void adjust_link(struct net_device *dev)
3024 {
3025         struct gfar_private *priv = netdev_priv(dev);
3026         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3027         unsigned long flags;
3028         struct phy_device *phydev = priv->phydev;
3029         int new_state = 0;
3030
3031         local_irq_save(flags);
3032         lock_tx_qs(priv);
3033
3034         if (phydev->link) {
3035                 u32 tempval = gfar_read(&regs->maccfg2);
3036                 u32 ecntrl = gfar_read(&regs->ecntrl);
3037
3038                 /* Now we make sure that we can be in full duplex mode.
3039                  * If not, we operate in half-duplex mode.
3040                  */
3041                 if (phydev->duplex != priv->oldduplex) {
3042                         new_state = 1;
3043                         if (!(phydev->duplex))
3044                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3045                         else
3046                                 tempval |= MACCFG2_FULL_DUPLEX;
3047
3048                         priv->oldduplex = phydev->duplex;
3049                 }
3050
3051                 if (phydev->speed != priv->oldspeed) {
3052                         new_state = 1;
3053                         switch (phydev->speed) {
3054                         case 1000:
3055                                 tempval =
3056                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3057
3058                                 ecntrl &= ~(ECNTRL_R100);
3059                                 break;
3060                         case 100:
3061                         case 10:
3062                                 tempval =
3063                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3064
3065                                 /* Reduced mode distinguishes
3066                                  * between 10 and 100
3067                                  */
3068                                 if (phydev->speed == SPEED_100)
3069                                         ecntrl |= ECNTRL_R100;
3070                                 else
3071                                         ecntrl &= ~(ECNTRL_R100);
3072                                 break;
3073                         default:
3074                                 netif_warn(priv, link, dev,
3075                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3076                                            phydev->speed);
3077                                 break;
3078                         }
3079
3080                         priv->oldspeed = phydev->speed;
3081                 }
3082
3083                 gfar_write(&regs->maccfg2, tempval);
3084                 gfar_write(&regs->ecntrl, ecntrl);
3085
3086                 if (!priv->oldlink) {
3087                         new_state = 1;
3088                         priv->oldlink = 1;
3089                 }
3090         } else if (priv->oldlink) {
3091                 new_state = 1;
3092                 priv->oldlink = 0;
3093                 priv->oldspeed = 0;
3094                 priv->oldduplex = -1;
3095         }
3096
3097         if (new_state && netif_msg_link(priv))
3098                 phy_print_status(phydev);
3099         unlock_tx_qs(priv);
3100         local_irq_restore(flags);
3101 }
3102
3103 /* Update the hash table based on the current list of multicast
3104  * addresses we subscribe to.  Also, change the promiscuity of
3105  * the device based on the flags (this function is called
3106  * whenever dev->flags is changed
3107  */
3108 static void gfar_set_multi(struct net_device *dev)
3109 {
3110         struct netdev_hw_addr *ha;
3111         struct gfar_private *priv = netdev_priv(dev);
3112         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3113         u32 tempval;
3114
3115         if (dev->flags & IFF_PROMISC) {
3116                 /* Set RCTRL to PROM */
3117                 tempval = gfar_read(&regs->rctrl);
3118                 tempval |= RCTRL_PROM;
3119                 gfar_write(&regs->rctrl, tempval);
3120         } else {
3121                 /* Set RCTRL to not PROM */
3122                 tempval = gfar_read(&regs->rctrl);
3123                 tempval &= ~(RCTRL_PROM);
3124                 gfar_write(&regs->rctrl, tempval);
3125         }
3126
3127         if (dev->flags & IFF_ALLMULTI) {
3128                 /* Set the hash to rx all multicast frames */
3129                 gfar_write(&regs->igaddr0, 0xffffffff);
3130                 gfar_write(&regs->igaddr1, 0xffffffff);
3131                 gfar_write(&regs->igaddr2, 0xffffffff);
3132                 gfar_write(&regs->igaddr3, 0xffffffff);
3133                 gfar_write(&regs->igaddr4, 0xffffffff);
3134                 gfar_write(&regs->igaddr5, 0xffffffff);
3135                 gfar_write(&regs->igaddr6, 0xffffffff);
3136                 gfar_write(&regs->igaddr7, 0xffffffff);
3137                 gfar_write(&regs->gaddr0, 0xffffffff);
3138                 gfar_write(&regs->gaddr1, 0xffffffff);
3139                 gfar_write(&regs->gaddr2, 0xffffffff);
3140                 gfar_write(&regs->gaddr3, 0xffffffff);
3141                 gfar_write(&regs->gaddr4, 0xffffffff);
3142                 gfar_write(&regs->gaddr5, 0xffffffff);
3143                 gfar_write(&regs->gaddr6, 0xffffffff);
3144                 gfar_write(&regs->gaddr7, 0xffffffff);
3145         } else {
3146                 int em_num;
3147                 int idx;
3148
3149                 /* zero out the hash */
3150                 gfar_write(&regs->igaddr0, 0x0);
3151                 gfar_write(&regs->igaddr1, 0x0);
3152                 gfar_write(&regs->igaddr2, 0x0);
3153                 gfar_write(&regs->igaddr3, 0x0);
3154                 gfar_write(&regs->igaddr4, 0x0);
3155                 gfar_write(&regs->igaddr5, 0x0);
3156                 gfar_write(&regs->igaddr6, 0x0);
3157                 gfar_write(&regs->igaddr7, 0x0);
3158                 gfar_write(&regs->gaddr0, 0x0);
3159                 gfar_write(&regs->gaddr1, 0x0);
3160                 gfar_write(&regs->gaddr2, 0x0);
3161                 gfar_write(&regs->gaddr3, 0x0);
3162                 gfar_write(&regs->gaddr4, 0x0);
3163                 gfar_write(&regs->gaddr5, 0x0);
3164                 gfar_write(&regs->gaddr6, 0x0);
3165                 gfar_write(&regs->gaddr7, 0x0);
3166
3167                 /* If we have extended hash tables, we need to
3168                  * clear the exact match registers to prepare for
3169                  * setting them
3170                  */
3171                 if (priv->extended_hash) {
3172                         em_num = GFAR_EM_NUM + 1;
3173                         gfar_clear_exact_match(dev);
3174                         idx = 1;
3175                 } else {
3176                         idx = 0;
3177                         em_num = 0;
3178                 }
3179
3180                 if (netdev_mc_empty(dev))
3181                         return;
3182
3183                 /* Parse the list, and set the appropriate bits */
3184                 netdev_for_each_mc_addr(ha, dev) {
3185                         if (idx < em_num) {
3186                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3187                                 idx++;
3188                         } else
3189                                 gfar_set_hash_for_addr(dev, ha->addr);
3190                 }
3191         }
3192 }
3193
3194
3195 /* Clears each of the exact match registers to zero, so they
3196  * don't interfere with normal reception
3197  */
3198 static void gfar_clear_exact_match(struct net_device *dev)
3199 {
3200         int idx;
3201         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3202
3203         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3204                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3205 }
3206
3207 /* Set the appropriate hash bit for the given addr */
3208 /* The algorithm works like so:
3209  * 1) Take the Destination Address (ie the multicast address), and
3210  * do a CRC on it (little endian), and reverse the bits of the
3211  * result.
3212  * 2) Use the 8 most significant bits as a hash into a 256-entry
3213  * table.  The table is controlled through 8 32-bit registers:
3214  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3215  * gaddr7.  This means that the 3 most significant bits in the
3216  * hash index which gaddr register to use, and the 5 other bits
3217  * indicate which bit (assuming an IBM numbering scheme, which
3218  * for PowerPC (tm) is usually the case) in the register holds
3219  * the entry.
3220  */
3221 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3222 {
3223         u32 tempval;
3224         struct gfar_private *priv = netdev_priv(dev);
3225         u32 result = ether_crc(ETH_ALEN, addr);
3226         int width = priv->hash_width;
3227         u8 whichbit = (result >> (32 - width)) & 0x1f;
3228         u8 whichreg = result >> (32 - width + 5);
3229         u32 value = (1 << (31-whichbit));
3230
3231         tempval = gfar_read(priv->hash_regs[whichreg]);
3232         tempval |= value;
3233         gfar_write(priv->hash_regs[whichreg], tempval);
3234 }
3235
3236
3237 /* There are multiple MAC Address register pairs on some controllers
3238  * This function sets the numth pair to a given address
3239  */
3240 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3241                                   const u8 *addr)
3242 {
3243         struct gfar_private *priv = netdev_priv(dev);
3244         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3245         int idx;
3246         char tmpbuf[ETH_ALEN];
3247         u32 tempval;
3248         u32 __iomem *macptr = &regs->macstnaddr1;
3249
3250         macptr += num*2;
3251
3252         /* Now copy it into the mac registers backwards, cuz
3253          * little endian is silly
3254          */
3255         for (idx = 0; idx < ETH_ALEN; idx++)
3256                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3257
3258         gfar_write(macptr, *((u32 *) (tmpbuf)));
3259
3260         tempval = *((u32 *) (tmpbuf + 4));
3261
3262         gfar_write(macptr+1, tempval);
3263 }
3264
3265 /* GFAR error interrupt handler */
3266 static irqreturn_t gfar_error(int irq, void *grp_id)
3267 {
3268         struct gfar_priv_grp *gfargrp = grp_id;
3269         struct gfar __iomem *regs = gfargrp->regs;
3270         struct gfar_private *priv= gfargrp->priv;
3271         struct net_device *dev = priv->ndev;
3272
3273         /* Save ievent for future reference */
3274         u32 events = gfar_read(&regs->ievent);
3275
3276         /* Clear IEVENT */
3277         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3278
3279         /* Magic Packet is not an error. */
3280         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3281             (events & IEVENT_MAG))
3282                 events &= ~IEVENT_MAG;
3283
3284         /* Hmm... */
3285         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3286                 netdev_dbg(dev,
3287                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3288                            events, gfar_read(&regs->imask));
3289
3290         /* Update the error counters */
3291         if (events & IEVENT_TXE) {
3292                 dev->stats.tx_errors++;
3293
3294                 if (events & IEVENT_LC)
3295                         dev->stats.tx_window_errors++;
3296                 if (events & IEVENT_CRL)
3297                         dev->stats.tx_aborted_errors++;
3298                 if (events & IEVENT_XFUN) {
3299                         unsigned long flags;
3300
3301                         netif_dbg(priv, tx_err, dev,
3302                                   "TX FIFO underrun, packet dropped\n");
3303                         dev->stats.tx_dropped++;
3304                         atomic64_inc(&priv->extra_stats.tx_underrun);
3305
3306                         local_irq_save(flags);
3307                         lock_tx_qs(priv);
3308
3309                         /* Reactivate the Tx Queues */
3310                         gfar_write(&regs->tstat, gfargrp->tstat);
3311
3312                         unlock_tx_qs(priv);
3313                         local_irq_restore(flags);
3314                 }
3315                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3316         }
3317         if (events & IEVENT_BSY) {
3318                 dev->stats.rx_errors++;
3319                 atomic64_inc(&priv->extra_stats.rx_bsy);
3320
3321                 gfar_receive(irq, grp_id);
3322
3323                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3324                           gfar_read(&regs->rstat));
3325         }
3326         if (events & IEVENT_BABR) {
3327                 dev->stats.rx_errors++;
3328                 atomic64_inc(&priv->extra_stats.rx_babr);
3329
3330                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3331         }
3332         if (events & IEVENT_EBERR) {
3333                 atomic64_inc(&priv->extra_stats.eberr);
3334                 netif_dbg(priv, rx_err, dev, "bus error\n");
3335         }
3336         if (events & IEVENT_RXC)
3337                 netif_dbg(priv, rx_status, dev, "control frame\n");
3338
3339         if (events & IEVENT_BABT) {
3340                 atomic64_inc(&priv->extra_stats.tx_babt);
3341                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3342         }
3343         return IRQ_HANDLED;
3344 }
3345
3346 static struct of_device_id gfar_match[] =
3347 {
3348         {
3349                 .type = "network",
3350                 .compatible = "gianfar",
3351         },
3352         {
3353                 .compatible = "fsl,etsec2",
3354         },
3355         {},
3356 };
3357 MODULE_DEVICE_TABLE(of, gfar_match);
3358
3359 /* Structure for a device driver */
3360 static struct platform_driver gfar_driver = {
3361         .driver = {
3362                 .name = "fsl-gianfar",
3363                 .owner = THIS_MODULE,
3364                 .pm = GFAR_PM_OPS,
3365                 .of_match_table = gfar_match,
3366         },
3367         .probe = gfar_probe,
3368         .remove = gfar_remove,
3369 };
3370
3371 module_platform_driver(gfar_driver);