1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/delay.h>
74 #include <linux/netdevice.h>
75 #include <linux/etherdevice.h>
76 #include <linux/skbuff.h>
77 #include <linux/if_vlan.h>
78 #include <linux/spinlock.h>
80 #include <linux/of_address.h>
81 #include <linux/of_irq.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
88 #include <linux/net_tstamp.h>
93 #include <asm/mpc85xx.h>
96 #include <asm/uaccess.h>
97 #include <linux/module.h>
98 #include <linux/dma-mapping.h>
99 #include <linux/crc32.h>
100 #include <linux/mii.h>
101 #include <linux/phy.h>
102 #include <linux/phy_fixed.h>
103 #include <linux/of.h>
104 #include <linux/of_net.h>
105 #include <linux/of_address.h>
106 #include <linux/of_irq.h>
110 #define TX_TIMEOUT (1*HZ)
112 const char gfar_driver_version[] = "1.3";
114 static int gfar_enet_open(struct net_device *dev);
115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
116 static void gfar_reset_task(struct work_struct *work);
117 static void gfar_timeout(struct net_device *dev);
118 static int gfar_close(struct net_device *dev);
119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
121 static int gfar_set_mac_address(struct net_device *dev);
122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123 static irqreturn_t gfar_error(int irq, void *dev_id);
124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
126 static void adjust_link(struct net_device *dev);
127 static noinline void gfar_update_link_state(struct gfar_private *priv);
128 static int init_phy(struct net_device *dev);
129 static int gfar_probe(struct platform_device *ofdev);
130 static int gfar_remove(struct platform_device *ofdev);
131 static void free_skb_resources(struct gfar_private *priv);
132 static void gfar_set_multi(struct net_device *dev);
133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134 static void gfar_configure_serdes(struct net_device *dev);
135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
139 #ifdef CONFIG_NET_POLL_CONTROLLER
140 static void gfar_netpoll(struct net_device *dev);
142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
144 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
145 struct napi_struct *napi);
146 static void gfar_halt_nodisable(struct gfar_private *priv);
147 static void gfar_clear_exact_match(struct net_device *dev);
148 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
150 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
152 MODULE_AUTHOR("Freescale Semiconductor, Inc");
153 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
154 MODULE_LICENSE("GPL");
156 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
161 bdp->bufPtr = cpu_to_be32(buf);
163 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
164 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
165 lstatus |= BD_LFLAG(RXBD_WRAP);
169 bdp->lstatus = cpu_to_be32(lstatus);
172 static void gfar_init_bds(struct net_device *ndev)
174 struct gfar_private *priv = netdev_priv(ndev);
175 struct gfar __iomem *regs = priv->gfargrp[0].regs;
176 struct gfar_priv_tx_q *tx_queue = NULL;
177 struct gfar_priv_rx_q *rx_queue = NULL;
182 for (i = 0; i < priv->num_tx_queues; i++) {
183 tx_queue = priv->tx_queue[i];
184 /* Initialize some variables in our dev structure */
185 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
186 tx_queue->dirty_tx = tx_queue->tx_bd_base;
187 tx_queue->cur_tx = tx_queue->tx_bd_base;
188 tx_queue->skb_curtx = 0;
189 tx_queue->skb_dirtytx = 0;
191 /* Initialize Transmit Descriptor Ring */
192 txbdp = tx_queue->tx_bd_base;
193 for (j = 0; j < tx_queue->tx_ring_size; j++) {
199 /* Set the last descriptor in the ring to indicate wrap */
201 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
205 rfbptr = ®s->rfbptr0;
206 for (i = 0; i < priv->num_rx_queues; i++) {
207 rx_queue = priv->rx_queue[i];
209 rx_queue->next_to_clean = 0;
210 rx_queue->next_to_use = 0;
212 /* make sure next_to_clean != next_to_use after this
213 * by leaving at least 1 unused descriptor
215 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
217 rx_queue->rfbptr = rfbptr;
222 static int gfar_alloc_skb_resources(struct net_device *ndev)
227 struct gfar_private *priv = netdev_priv(ndev);
228 struct device *dev = priv->dev;
229 struct gfar_priv_tx_q *tx_queue = NULL;
230 struct gfar_priv_rx_q *rx_queue = NULL;
232 priv->total_tx_ring_size = 0;
233 for (i = 0; i < priv->num_tx_queues; i++)
234 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
236 priv->total_rx_ring_size = 0;
237 for (i = 0; i < priv->num_rx_queues; i++)
238 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
240 /* Allocate memory for the buffer descriptors */
241 vaddr = dma_alloc_coherent(dev,
242 (priv->total_tx_ring_size *
243 sizeof(struct txbd8)) +
244 (priv->total_rx_ring_size *
245 sizeof(struct rxbd8)),
250 for (i = 0; i < priv->num_tx_queues; i++) {
251 tx_queue = priv->tx_queue[i];
252 tx_queue->tx_bd_base = vaddr;
253 tx_queue->tx_bd_dma_base = addr;
254 tx_queue->dev = ndev;
255 /* enet DMA only understands physical addresses */
256 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
257 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
260 /* Start the rx descriptor ring where the tx ring leaves off */
261 for (i = 0; i < priv->num_rx_queues; i++) {
262 rx_queue = priv->rx_queue[i];
263 rx_queue->rx_bd_base = vaddr;
264 rx_queue->rx_bd_dma_base = addr;
265 rx_queue->dev = ndev;
266 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
267 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
270 /* Setup the skbuff rings */
271 for (i = 0; i < priv->num_tx_queues; i++) {
272 tx_queue = priv->tx_queue[i];
273 tx_queue->tx_skbuff =
274 kmalloc_array(tx_queue->tx_ring_size,
275 sizeof(*tx_queue->tx_skbuff),
277 if (!tx_queue->tx_skbuff)
280 for (k = 0; k < tx_queue->tx_ring_size; k++)
281 tx_queue->tx_skbuff[k] = NULL;
284 for (i = 0; i < priv->num_rx_queues; i++) {
285 rx_queue = priv->rx_queue[i];
286 rx_queue->rx_skbuff =
287 kmalloc_array(rx_queue->rx_ring_size,
288 sizeof(*rx_queue->rx_skbuff),
290 if (!rx_queue->rx_skbuff)
293 for (j = 0; j < rx_queue->rx_ring_size; j++)
294 rx_queue->rx_skbuff[j] = NULL;
302 free_skb_resources(priv);
306 static void gfar_init_tx_rx_base(struct gfar_private *priv)
308 struct gfar __iomem *regs = priv->gfargrp[0].regs;
312 baddr = ®s->tbase0;
313 for (i = 0; i < priv->num_tx_queues; i++) {
314 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
318 baddr = ®s->rbase0;
319 for (i = 0; i < priv->num_rx_queues; i++) {
320 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
325 static void gfar_init_rqprm(struct gfar_private *priv)
327 struct gfar __iomem *regs = priv->gfargrp[0].regs;
331 baddr = ®s->rqprm0;
332 for (i = 0; i < priv->num_rx_queues; i++) {
333 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
334 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
339 static void gfar_rx_buff_size_config(struct gfar_private *priv)
341 int frame_size = priv->ndev->mtu + ETH_HLEN + ETH_FCS_LEN;
343 /* set this when rx hw offload (TOE) functions are being used */
344 priv->uses_rxfcb = 0;
346 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
347 priv->uses_rxfcb = 1;
349 if (priv->hwts_rx_en)
350 priv->uses_rxfcb = 1;
352 if (priv->uses_rxfcb)
353 frame_size += GMAC_FCB_LEN;
355 frame_size += priv->padding;
357 frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
358 INCREMENTAL_BUFFER_SIZE;
360 priv->rx_buffer_size = frame_size;
363 static void gfar_mac_rx_config(struct gfar_private *priv)
365 struct gfar __iomem *regs = priv->gfargrp[0].regs;
368 if (priv->rx_filer_enable) {
369 rctrl |= RCTRL_FILREN;
370 /* Program the RIR0 reg with the required distribution */
371 if (priv->poll_mode == GFAR_SQ_POLLING)
372 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
373 else /* GFAR_MQ_POLLING */
374 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
377 /* Restore PROMISC mode */
378 if (priv->ndev->flags & IFF_PROMISC)
381 if (priv->ndev->features & NETIF_F_RXCSUM)
382 rctrl |= RCTRL_CHECKSUMMING;
384 if (priv->extended_hash)
385 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
388 rctrl &= ~RCTRL_PAL_MASK;
389 rctrl |= RCTRL_PADDING(priv->padding);
392 /* Enable HW time stamping if requested from user space */
393 if (priv->hwts_rx_en)
394 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
396 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
397 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
399 /* Clear the LFC bit */
400 gfar_write(®s->rctrl, rctrl);
401 /* Init flow control threshold values */
402 gfar_init_rqprm(priv);
403 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL);
406 /* Init rctrl based on our settings */
407 gfar_write(®s->rctrl, rctrl);
410 static void gfar_mac_tx_config(struct gfar_private *priv)
412 struct gfar __iomem *regs = priv->gfargrp[0].regs;
415 if (priv->ndev->features & NETIF_F_IP_CSUM)
416 tctrl |= TCTRL_INIT_CSUM;
418 if (priv->prio_sched_en)
419 tctrl |= TCTRL_TXSCHED_PRIO;
421 tctrl |= TCTRL_TXSCHED_WRRS;
422 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
423 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
426 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
427 tctrl |= TCTRL_VLINS;
429 gfar_write(®s->tctrl, tctrl);
432 static void gfar_configure_coalescing(struct gfar_private *priv,
433 unsigned long tx_mask, unsigned long rx_mask)
435 struct gfar __iomem *regs = priv->gfargrp[0].regs;
438 if (priv->mode == MQ_MG_MODE) {
441 baddr = ®s->txic0;
442 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
443 gfar_write(baddr + i, 0);
444 if (likely(priv->tx_queue[i]->txcoalescing))
445 gfar_write(baddr + i, priv->tx_queue[i]->txic);
448 baddr = ®s->rxic0;
449 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
450 gfar_write(baddr + i, 0);
451 if (likely(priv->rx_queue[i]->rxcoalescing))
452 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
455 /* Backward compatible case -- even if we enable
456 * multiple queues, there's only single reg to program
458 gfar_write(®s->txic, 0);
459 if (likely(priv->tx_queue[0]->txcoalescing))
460 gfar_write(®s->txic, priv->tx_queue[0]->txic);
462 gfar_write(®s->rxic, 0);
463 if (unlikely(priv->rx_queue[0]->rxcoalescing))
464 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
468 void gfar_configure_coalescing_all(struct gfar_private *priv)
470 gfar_configure_coalescing(priv, 0xFF, 0xFF);
473 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
475 struct gfar_private *priv = netdev_priv(dev);
476 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
477 unsigned long tx_packets = 0, tx_bytes = 0;
480 for (i = 0; i < priv->num_rx_queues; i++) {
481 rx_packets += priv->rx_queue[i]->stats.rx_packets;
482 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
483 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
486 dev->stats.rx_packets = rx_packets;
487 dev->stats.rx_bytes = rx_bytes;
488 dev->stats.rx_dropped = rx_dropped;
490 for (i = 0; i < priv->num_tx_queues; i++) {
491 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
492 tx_packets += priv->tx_queue[i]->stats.tx_packets;
495 dev->stats.tx_bytes = tx_bytes;
496 dev->stats.tx_packets = tx_packets;
501 static int gfar_set_mac_addr(struct net_device *dev, void *p)
503 eth_mac_addr(dev, p);
505 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
510 static const struct net_device_ops gfar_netdev_ops = {
511 .ndo_open = gfar_enet_open,
512 .ndo_start_xmit = gfar_start_xmit,
513 .ndo_stop = gfar_close,
514 .ndo_change_mtu = gfar_change_mtu,
515 .ndo_set_features = gfar_set_features,
516 .ndo_set_rx_mode = gfar_set_multi,
517 .ndo_tx_timeout = gfar_timeout,
518 .ndo_do_ioctl = gfar_ioctl,
519 .ndo_get_stats = gfar_get_stats,
520 .ndo_set_mac_address = gfar_set_mac_addr,
521 .ndo_validate_addr = eth_validate_addr,
522 #ifdef CONFIG_NET_POLL_CONTROLLER
523 .ndo_poll_controller = gfar_netpoll,
527 static void gfar_ints_disable(struct gfar_private *priv)
530 for (i = 0; i < priv->num_grps; i++) {
531 struct gfar __iomem *regs = priv->gfargrp[i].regs;
533 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
535 /* Initialize IMASK */
536 gfar_write(®s->imask, IMASK_INIT_CLEAR);
540 static void gfar_ints_enable(struct gfar_private *priv)
543 for (i = 0; i < priv->num_grps; i++) {
544 struct gfar __iomem *regs = priv->gfargrp[i].regs;
545 /* Unmask the interrupts we look for */
546 gfar_write(®s->imask, IMASK_DEFAULT);
550 static void lock_tx_qs(struct gfar_private *priv)
554 for (i = 0; i < priv->num_tx_queues; i++)
555 spin_lock(&priv->tx_queue[i]->txlock);
558 static void unlock_tx_qs(struct gfar_private *priv)
562 for (i = 0; i < priv->num_tx_queues; i++)
563 spin_unlock(&priv->tx_queue[i]->txlock);
566 static int gfar_alloc_tx_queues(struct gfar_private *priv)
570 for (i = 0; i < priv->num_tx_queues; i++) {
571 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
573 if (!priv->tx_queue[i])
576 priv->tx_queue[i]->tx_skbuff = NULL;
577 priv->tx_queue[i]->qindex = i;
578 priv->tx_queue[i]->dev = priv->ndev;
579 spin_lock_init(&(priv->tx_queue[i]->txlock));
584 static int gfar_alloc_rx_queues(struct gfar_private *priv)
588 for (i = 0; i < priv->num_rx_queues; i++) {
589 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
591 if (!priv->rx_queue[i])
594 priv->rx_queue[i]->rx_skbuff = NULL;
595 priv->rx_queue[i]->qindex = i;
596 priv->rx_queue[i]->dev = priv->ndev;
601 static void gfar_free_tx_queues(struct gfar_private *priv)
605 for (i = 0; i < priv->num_tx_queues; i++)
606 kfree(priv->tx_queue[i]);
609 static void gfar_free_rx_queues(struct gfar_private *priv)
613 for (i = 0; i < priv->num_rx_queues; i++)
614 kfree(priv->rx_queue[i]);
617 static void unmap_group_regs(struct gfar_private *priv)
621 for (i = 0; i < MAXGROUPS; i++)
622 if (priv->gfargrp[i].regs)
623 iounmap(priv->gfargrp[i].regs);
626 static void free_gfar_dev(struct gfar_private *priv)
630 for (i = 0; i < priv->num_grps; i++)
631 for (j = 0; j < GFAR_NUM_IRQS; j++) {
632 kfree(priv->gfargrp[i].irqinfo[j]);
633 priv->gfargrp[i].irqinfo[j] = NULL;
636 free_netdev(priv->ndev);
639 static void disable_napi(struct gfar_private *priv)
643 for (i = 0; i < priv->num_grps; i++) {
644 napi_disable(&priv->gfargrp[i].napi_rx);
645 napi_disable(&priv->gfargrp[i].napi_tx);
649 static void enable_napi(struct gfar_private *priv)
653 for (i = 0; i < priv->num_grps; i++) {
654 napi_enable(&priv->gfargrp[i].napi_rx);
655 napi_enable(&priv->gfargrp[i].napi_tx);
659 static int gfar_parse_group(struct device_node *np,
660 struct gfar_private *priv, const char *model)
662 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
665 for (i = 0; i < GFAR_NUM_IRQS; i++) {
666 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
668 if (!grp->irqinfo[i])
672 grp->regs = of_iomap(np, 0);
676 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
678 /* If we aren't the FEC we have multiple interrupts */
679 if (model && strcasecmp(model, "FEC")) {
680 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
681 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
682 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
683 gfar_irq(grp, RX)->irq == NO_IRQ ||
684 gfar_irq(grp, ER)->irq == NO_IRQ)
689 spin_lock_init(&grp->grplock);
690 if (priv->mode == MQ_MG_MODE) {
691 u32 rxq_mask, txq_mask;
694 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
695 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
697 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
699 grp->rx_bit_map = rxq_mask ?
700 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
703 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
705 grp->tx_bit_map = txq_mask ?
706 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
709 if (priv->poll_mode == GFAR_SQ_POLLING) {
710 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
711 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
712 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
715 grp->rx_bit_map = 0xFF;
716 grp->tx_bit_map = 0xFF;
719 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
720 * right to left, so we need to revert the 8 bits to get the q index
722 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
723 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
725 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
726 * also assign queues to groups
728 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
730 grp->rx_queue = priv->rx_queue[i];
731 grp->num_rx_queues++;
732 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
733 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
734 priv->rx_queue[i]->grp = grp;
737 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
739 grp->tx_queue = priv->tx_queue[i];
740 grp->num_tx_queues++;
741 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
742 priv->tqueue |= (TQUEUE_EN0 >> i);
743 priv->tx_queue[i]->grp = grp;
751 static int gfar_of_group_count(struct device_node *np)
753 struct device_node *child;
756 for_each_available_child_of_node(np, child)
757 if (!of_node_cmp(child->name, "queue-group"))
763 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
767 const void *mac_addr;
769 struct net_device *dev = NULL;
770 struct gfar_private *priv = NULL;
771 struct device_node *np = ofdev->dev.of_node;
772 struct device_node *child = NULL;
773 struct property *stash;
776 unsigned int num_tx_qs, num_rx_qs;
777 unsigned short mode, poll_mode;
782 if (of_device_is_compatible(np, "fsl,etsec2")) {
784 poll_mode = GFAR_SQ_POLLING;
787 poll_mode = GFAR_SQ_POLLING;
790 if (mode == SQ_SG_MODE) {
793 } else { /* MQ_MG_MODE */
794 /* get the actual number of supported groups */
795 unsigned int num_grps = gfar_of_group_count(np);
797 if (num_grps == 0 || num_grps > MAXGROUPS) {
798 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
800 pr_err("Cannot do alloc_etherdev, aborting\n");
804 if (poll_mode == GFAR_SQ_POLLING) {
805 num_tx_qs = num_grps; /* one txq per int group */
806 num_rx_qs = num_grps; /* one rxq per int group */
807 } else { /* GFAR_MQ_POLLING */
808 u32 tx_queues, rx_queues;
811 /* parse the num of HW tx and rx queues */
812 ret = of_property_read_u32(np, "fsl,num_tx_queues",
814 num_tx_qs = ret ? 1 : tx_queues;
816 ret = of_property_read_u32(np, "fsl,num_rx_queues",
818 num_rx_qs = ret ? 1 : rx_queues;
822 if (num_tx_qs > MAX_TX_QS) {
823 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
824 num_tx_qs, MAX_TX_QS);
825 pr_err("Cannot do alloc_etherdev, aborting\n");
829 if (num_rx_qs > MAX_RX_QS) {
830 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
831 num_rx_qs, MAX_RX_QS);
832 pr_err("Cannot do alloc_etherdev, aborting\n");
836 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
841 priv = netdev_priv(dev);
845 priv->poll_mode = poll_mode;
847 priv->num_tx_queues = num_tx_qs;
848 netif_set_real_num_rx_queues(dev, num_rx_qs);
849 priv->num_rx_queues = num_rx_qs;
851 err = gfar_alloc_tx_queues(priv);
853 goto tx_alloc_failed;
855 err = gfar_alloc_rx_queues(priv);
857 goto rx_alloc_failed;
859 err = of_property_read_string(np, "model", &model);
861 pr_err("Device model property missing, aborting\n");
862 goto rx_alloc_failed;
865 /* Init Rx queue filer rule set linked list */
866 INIT_LIST_HEAD(&priv->rx_list.list);
867 priv->rx_list.count = 0;
868 mutex_init(&priv->rx_queue_access);
870 for (i = 0; i < MAXGROUPS; i++)
871 priv->gfargrp[i].regs = NULL;
873 /* Parse and initialize group specific information */
874 if (priv->mode == MQ_MG_MODE) {
875 for_each_available_child_of_node(np, child) {
876 if (of_node_cmp(child->name, "queue-group"))
879 err = gfar_parse_group(child, priv, model);
883 } else { /* SQ_SG_MODE */
884 err = gfar_parse_group(np, priv, model);
889 stash = of_find_property(np, "bd-stash", NULL);
892 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
893 priv->bd_stash_en = 1;
896 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
899 priv->rx_stash_size = stash_len;
901 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
904 priv->rx_stash_index = stash_idx;
906 if (stash_len || stash_idx)
907 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
909 mac_addr = of_get_mac_address(np);
912 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
914 if (model && !strcasecmp(model, "TSEC"))
915 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
916 FSL_GIANFAR_DEV_HAS_COALESCE |
917 FSL_GIANFAR_DEV_HAS_RMON |
918 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
920 if (model && !strcasecmp(model, "eTSEC"))
921 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
922 FSL_GIANFAR_DEV_HAS_COALESCE |
923 FSL_GIANFAR_DEV_HAS_RMON |
924 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
925 FSL_GIANFAR_DEV_HAS_CSUM |
926 FSL_GIANFAR_DEV_HAS_VLAN |
927 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
928 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
929 FSL_GIANFAR_DEV_HAS_TIMER;
931 err = of_property_read_string(np, "phy-connection-type", &ctype);
933 /* We only care about rgmii-id. The rest are autodetected */
934 if (err == 0 && !strcmp(ctype, "rgmii-id"))
935 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
937 priv->interface = PHY_INTERFACE_MODE_MII;
939 if (of_find_property(np, "fsl,magic-packet", NULL))
940 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
942 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
944 /* In the case of a fixed PHY, the DT node associated
945 * to the PHY is the Ethernet MAC DT node.
947 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
948 err = of_phy_register_fixed_link(np);
952 priv->phy_node = of_node_get(np);
955 /* Find the TBI PHY. If it's not there, we don't support SGMII */
956 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
961 unmap_group_regs(priv);
963 gfar_free_rx_queues(priv);
965 gfar_free_tx_queues(priv);
970 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
972 struct hwtstamp_config config;
973 struct gfar_private *priv = netdev_priv(netdev);
975 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
978 /* reserved for future extensions */
982 switch (config.tx_type) {
983 case HWTSTAMP_TX_OFF:
984 priv->hwts_tx_en = 0;
987 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
989 priv->hwts_tx_en = 1;
995 switch (config.rx_filter) {
996 case HWTSTAMP_FILTER_NONE:
997 if (priv->hwts_rx_en) {
998 priv->hwts_rx_en = 0;
1003 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
1005 if (!priv->hwts_rx_en) {
1006 priv->hwts_rx_en = 1;
1009 config.rx_filter = HWTSTAMP_FILTER_ALL;
1013 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1017 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
1019 struct hwtstamp_config config;
1020 struct gfar_private *priv = netdev_priv(netdev);
1023 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1024 config.rx_filter = (priv->hwts_rx_en ?
1025 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
1027 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1031 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1033 struct gfar_private *priv = netdev_priv(dev);
1035 if (!netif_running(dev))
1038 if (cmd == SIOCSHWTSTAMP)
1039 return gfar_hwtstamp_set(dev, rq);
1040 if (cmd == SIOCGHWTSTAMP)
1041 return gfar_hwtstamp_get(dev, rq);
1046 return phy_mii_ioctl(priv->phydev, rq, cmd);
1049 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1052 u32 rqfpr = FPR_FILER_MASK;
1056 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1057 priv->ftp_rqfpr[rqfar] = rqfpr;
1058 priv->ftp_rqfcr[rqfar] = rqfcr;
1059 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1062 rqfcr = RQFCR_CMP_NOMATCH;
1063 priv->ftp_rqfpr[rqfar] = rqfpr;
1064 priv->ftp_rqfcr[rqfar] = rqfcr;
1065 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1068 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1070 priv->ftp_rqfcr[rqfar] = rqfcr;
1071 priv->ftp_rqfpr[rqfar] = rqfpr;
1072 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1075 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1077 priv->ftp_rqfcr[rqfar] = rqfcr;
1078 priv->ftp_rqfpr[rqfar] = rqfpr;
1079 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1084 static void gfar_init_filer_table(struct gfar_private *priv)
1087 u32 rqfar = MAX_FILER_IDX;
1089 u32 rqfpr = FPR_FILER_MASK;
1092 rqfcr = RQFCR_CMP_MATCH;
1093 priv->ftp_rqfcr[rqfar] = rqfcr;
1094 priv->ftp_rqfpr[rqfar] = rqfpr;
1095 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1097 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1098 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1099 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1100 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1101 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1102 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1104 /* cur_filer_idx indicated the first non-masked rule */
1105 priv->cur_filer_idx = rqfar;
1107 /* Rest are masked rules */
1108 rqfcr = RQFCR_CMP_NOMATCH;
1109 for (i = 0; i < rqfar; i++) {
1110 priv->ftp_rqfcr[i] = rqfcr;
1111 priv->ftp_rqfpr[i] = rqfpr;
1112 gfar_write_filer(priv, i, rqfcr, rqfpr);
1117 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1119 unsigned int pvr = mfspr(SPRN_PVR);
1120 unsigned int svr = mfspr(SPRN_SVR);
1121 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1122 unsigned int rev = svr & 0xffff;
1124 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1125 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1126 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1127 priv->errata |= GFAR_ERRATA_74;
1129 /* MPC8313 and MPC837x all rev */
1130 if ((pvr == 0x80850010 && mod == 0x80b0) ||
1131 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1132 priv->errata |= GFAR_ERRATA_76;
1134 /* MPC8313 Rev < 2.0 */
1135 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1136 priv->errata |= GFAR_ERRATA_12;
1139 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1141 unsigned int svr = mfspr(SPRN_SVR);
1143 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1144 priv->errata |= GFAR_ERRATA_12;
1145 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1146 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1147 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1151 static void gfar_detect_errata(struct gfar_private *priv)
1153 struct device *dev = &priv->ofdev->dev;
1155 /* no plans to fix */
1156 priv->errata |= GFAR_ERRATA_A002;
1159 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1160 __gfar_detect_errata_85xx(priv);
1161 else /* non-mpc85xx parts, i.e. e300 core based */
1162 __gfar_detect_errata_83xx(priv);
1166 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1170 void gfar_mac_reset(struct gfar_private *priv)
1172 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1175 /* Reset MAC layer */
1176 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1178 /* We need to delay at least 3 TX clocks */
1181 /* the soft reset bit is not self-resetting, so we need to
1182 * clear it before resuming normal operation
1184 gfar_write(®s->maccfg1, 0);
1188 /* Compute rx_buff_size based on config flags */
1189 gfar_rx_buff_size_config(priv);
1191 /* Initialize the max receive frame/buffer lengths */
1192 gfar_write(®s->maxfrm, priv->rx_buffer_size);
1193 gfar_write(®s->mrblr, priv->rx_buffer_size);
1195 /* Initialize the Minimum Frame Length Register */
1196 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1198 /* Initialize MACCFG2. */
1199 tempval = MACCFG2_INIT_SETTINGS;
1201 /* If the mtu is larger than the max size for standard
1202 * ethernet frames (ie, a jumbo frame), then set maccfg2
1203 * to allow huge frames, and to check the length
1205 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
1206 gfar_has_errata(priv, GFAR_ERRATA_74))
1207 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1209 gfar_write(®s->maccfg2, tempval);
1211 /* Clear mac addr hash registers */
1212 gfar_write(®s->igaddr0, 0);
1213 gfar_write(®s->igaddr1, 0);
1214 gfar_write(®s->igaddr2, 0);
1215 gfar_write(®s->igaddr3, 0);
1216 gfar_write(®s->igaddr4, 0);
1217 gfar_write(®s->igaddr5, 0);
1218 gfar_write(®s->igaddr6, 0);
1219 gfar_write(®s->igaddr7, 0);
1221 gfar_write(®s->gaddr0, 0);
1222 gfar_write(®s->gaddr1, 0);
1223 gfar_write(®s->gaddr2, 0);
1224 gfar_write(®s->gaddr3, 0);
1225 gfar_write(®s->gaddr4, 0);
1226 gfar_write(®s->gaddr5, 0);
1227 gfar_write(®s->gaddr6, 0);
1228 gfar_write(®s->gaddr7, 0);
1230 if (priv->extended_hash)
1231 gfar_clear_exact_match(priv->ndev);
1233 gfar_mac_rx_config(priv);
1235 gfar_mac_tx_config(priv);
1237 gfar_set_mac_address(priv->ndev);
1239 gfar_set_multi(priv->ndev);
1241 /* clear ievent and imask before configuring coalescing */
1242 gfar_ints_disable(priv);
1244 /* Configure the coalescing support */
1245 gfar_configure_coalescing_all(priv);
1248 static void gfar_hw_init(struct gfar_private *priv)
1250 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1253 /* Stop the DMA engine now, in case it was running before
1254 * (The firmware could have used it, and left it running).
1258 gfar_mac_reset(priv);
1260 /* Zero out the rmon mib registers if it has them */
1261 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1262 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1264 /* Mask off the CAM interrupts */
1265 gfar_write(®s->rmon.cam1, 0xffffffff);
1266 gfar_write(®s->rmon.cam2, 0xffffffff);
1269 /* Initialize ECNTRL */
1270 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1272 /* Set the extraction length and index */
1273 attrs = ATTRELI_EL(priv->rx_stash_size) |
1274 ATTRELI_EI(priv->rx_stash_index);
1276 gfar_write(®s->attreli, attrs);
1278 /* Start with defaults, and add stashing
1279 * depending on driver parameters
1281 attrs = ATTR_INIT_SETTINGS;
1283 if (priv->bd_stash_en)
1284 attrs |= ATTR_BDSTASH;
1286 if (priv->rx_stash_size != 0)
1287 attrs |= ATTR_BUFSTASH;
1289 gfar_write(®s->attr, attrs);
1292 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1293 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1294 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1296 /* Program the interrupt steering regs, only for MG devices */
1297 if (priv->num_grps > 1)
1298 gfar_write_isrg(priv);
1301 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1303 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1305 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1306 priv->extended_hash = 1;
1307 priv->hash_width = 9;
1309 priv->hash_regs[0] = ®s->igaddr0;
1310 priv->hash_regs[1] = ®s->igaddr1;
1311 priv->hash_regs[2] = ®s->igaddr2;
1312 priv->hash_regs[3] = ®s->igaddr3;
1313 priv->hash_regs[4] = ®s->igaddr4;
1314 priv->hash_regs[5] = ®s->igaddr5;
1315 priv->hash_regs[6] = ®s->igaddr6;
1316 priv->hash_regs[7] = ®s->igaddr7;
1317 priv->hash_regs[8] = ®s->gaddr0;
1318 priv->hash_regs[9] = ®s->gaddr1;
1319 priv->hash_regs[10] = ®s->gaddr2;
1320 priv->hash_regs[11] = ®s->gaddr3;
1321 priv->hash_regs[12] = ®s->gaddr4;
1322 priv->hash_regs[13] = ®s->gaddr5;
1323 priv->hash_regs[14] = ®s->gaddr6;
1324 priv->hash_regs[15] = ®s->gaddr7;
1327 priv->extended_hash = 0;
1328 priv->hash_width = 8;
1330 priv->hash_regs[0] = ®s->gaddr0;
1331 priv->hash_regs[1] = ®s->gaddr1;
1332 priv->hash_regs[2] = ®s->gaddr2;
1333 priv->hash_regs[3] = ®s->gaddr3;
1334 priv->hash_regs[4] = ®s->gaddr4;
1335 priv->hash_regs[5] = ®s->gaddr5;
1336 priv->hash_regs[6] = ®s->gaddr6;
1337 priv->hash_regs[7] = ®s->gaddr7;
1341 /* Set up the ethernet device structure, private data,
1342 * and anything else we need before we start
1344 static int gfar_probe(struct platform_device *ofdev)
1346 struct net_device *dev = NULL;
1347 struct gfar_private *priv = NULL;
1350 err = gfar_of_init(ofdev, &dev);
1355 priv = netdev_priv(dev);
1357 priv->ofdev = ofdev;
1358 priv->dev = &ofdev->dev;
1359 SET_NETDEV_DEV(dev, &ofdev->dev);
1361 spin_lock_init(&priv->bflock);
1362 INIT_WORK(&priv->reset_task, gfar_reset_task);
1364 platform_set_drvdata(ofdev, priv);
1366 gfar_detect_errata(priv);
1368 /* Set the dev->base_addr to the gfar reg region */
1369 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1371 /* Fill in the dev structure */
1372 dev->watchdog_timeo = TX_TIMEOUT;
1374 dev->netdev_ops = &gfar_netdev_ops;
1375 dev->ethtool_ops = &gfar_ethtool_ops;
1377 /* Register for napi ...We are registering NAPI for each grp */
1378 for (i = 0; i < priv->num_grps; i++) {
1379 if (priv->poll_mode == GFAR_SQ_POLLING) {
1380 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1381 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1382 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1383 gfar_poll_tx_sq, 2);
1385 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1386 gfar_poll_rx, GFAR_DEV_WEIGHT);
1387 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1392 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1393 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1395 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1396 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1399 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1400 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1401 NETIF_F_HW_VLAN_CTAG_RX;
1402 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1405 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1407 gfar_init_addr_hash_table(priv);
1409 /* Insert receive time stamps into padding alignment bytes */
1410 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1413 if (dev->features & NETIF_F_IP_CSUM ||
1414 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1415 dev->needed_headroom = GMAC_FCB_LEN;
1417 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1419 /* Initializing some of the rx/tx queue level parameters */
1420 for (i = 0; i < priv->num_tx_queues; i++) {
1421 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1422 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1423 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1424 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1427 for (i = 0; i < priv->num_rx_queues; i++) {
1428 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1429 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1430 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1433 /* always enable rx filer */
1434 priv->rx_filer_enable = 1;
1435 /* Enable most messages by default */
1436 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1437 /* use pritority h/w tx queue scheduling for single queue devices */
1438 if (priv->num_tx_queues == 1)
1439 priv->prio_sched_en = 1;
1441 set_bit(GFAR_DOWN, &priv->state);
1445 /* Carrier starts down, phylib will bring it up */
1446 netif_carrier_off(dev);
1448 err = register_netdev(dev);
1451 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1455 device_init_wakeup(&dev->dev,
1456 priv->device_flags &
1457 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1459 /* fill out IRQ number and name fields */
1460 for (i = 0; i < priv->num_grps; i++) {
1461 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1462 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1463 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1464 dev->name, "_g", '0' + i, "_tx");
1465 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1466 dev->name, "_g", '0' + i, "_rx");
1467 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1468 dev->name, "_g", '0' + i, "_er");
1470 strcpy(gfar_irq(grp, TX)->name, dev->name);
1473 /* Initialize the filer table */
1474 gfar_init_filer_table(priv);
1476 /* Print out the device info */
1477 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1479 /* Even more device info helps when determining which kernel
1480 * provided which set of benchmarks.
1482 netdev_info(dev, "Running with NAPI enabled\n");
1483 for (i = 0; i < priv->num_rx_queues; i++)
1484 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1485 i, priv->rx_queue[i]->rx_ring_size);
1486 for (i = 0; i < priv->num_tx_queues; i++)
1487 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1488 i, priv->tx_queue[i]->tx_ring_size);
1493 unmap_group_regs(priv);
1494 gfar_free_rx_queues(priv);
1495 gfar_free_tx_queues(priv);
1496 of_node_put(priv->phy_node);
1497 of_node_put(priv->tbi_node);
1498 free_gfar_dev(priv);
1502 static int gfar_remove(struct platform_device *ofdev)
1504 struct gfar_private *priv = platform_get_drvdata(ofdev);
1506 of_node_put(priv->phy_node);
1507 of_node_put(priv->tbi_node);
1509 unregister_netdev(priv->ndev);
1510 unmap_group_regs(priv);
1511 gfar_free_rx_queues(priv);
1512 gfar_free_tx_queues(priv);
1513 free_gfar_dev(priv);
1520 static int gfar_suspend(struct device *dev)
1522 struct gfar_private *priv = dev_get_drvdata(dev);
1523 struct net_device *ndev = priv->ndev;
1524 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1525 unsigned long flags;
1528 int magic_packet = priv->wol_en &&
1529 (priv->device_flags &
1530 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1532 netif_device_detach(ndev);
1534 if (netif_running(ndev)) {
1536 local_irq_save(flags);
1539 gfar_halt_nodisable(priv);
1541 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1542 tempval = gfar_read(®s->maccfg1);
1544 tempval &= ~MACCFG1_TX_EN;
1547 tempval &= ~MACCFG1_RX_EN;
1549 gfar_write(®s->maccfg1, tempval);
1552 local_irq_restore(flags);
1557 /* Enable interrupt on Magic Packet */
1558 gfar_write(®s->imask, IMASK_MAG);
1560 /* Enable Magic Packet mode */
1561 tempval = gfar_read(®s->maccfg2);
1562 tempval |= MACCFG2_MPEN;
1563 gfar_write(®s->maccfg2, tempval);
1565 phy_stop(priv->phydev);
1572 static int gfar_resume(struct device *dev)
1574 struct gfar_private *priv = dev_get_drvdata(dev);
1575 struct net_device *ndev = priv->ndev;
1576 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1577 unsigned long flags;
1579 int magic_packet = priv->wol_en &&
1580 (priv->device_flags &
1581 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1583 if (!netif_running(ndev)) {
1584 netif_device_attach(ndev);
1588 if (!magic_packet && priv->phydev)
1589 phy_start(priv->phydev);
1591 /* Disable Magic Packet mode, in case something
1594 local_irq_save(flags);
1597 tempval = gfar_read(®s->maccfg2);
1598 tempval &= ~MACCFG2_MPEN;
1599 gfar_write(®s->maccfg2, tempval);
1604 local_irq_restore(flags);
1606 netif_device_attach(ndev);
1613 static int gfar_restore(struct device *dev)
1615 struct gfar_private *priv = dev_get_drvdata(dev);
1616 struct net_device *ndev = priv->ndev;
1618 if (!netif_running(ndev)) {
1619 netif_device_attach(ndev);
1624 gfar_init_bds(ndev);
1626 gfar_mac_reset(priv);
1628 gfar_init_tx_rx_base(priv);
1634 priv->oldduplex = -1;
1637 phy_start(priv->phydev);
1639 netif_device_attach(ndev);
1645 static struct dev_pm_ops gfar_pm_ops = {
1646 .suspend = gfar_suspend,
1647 .resume = gfar_resume,
1648 .freeze = gfar_suspend,
1649 .thaw = gfar_resume,
1650 .restore = gfar_restore,
1653 #define GFAR_PM_OPS (&gfar_pm_ops)
1657 #define GFAR_PM_OPS NULL
1661 /* Reads the controller's registers to determine what interface
1662 * connects it to the PHY.
1664 static phy_interface_t gfar_get_interface(struct net_device *dev)
1666 struct gfar_private *priv = netdev_priv(dev);
1667 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1670 ecntrl = gfar_read(®s->ecntrl);
1672 if (ecntrl & ECNTRL_SGMII_MODE)
1673 return PHY_INTERFACE_MODE_SGMII;
1675 if (ecntrl & ECNTRL_TBI_MODE) {
1676 if (ecntrl & ECNTRL_REDUCED_MODE)
1677 return PHY_INTERFACE_MODE_RTBI;
1679 return PHY_INTERFACE_MODE_TBI;
1682 if (ecntrl & ECNTRL_REDUCED_MODE) {
1683 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1684 return PHY_INTERFACE_MODE_RMII;
1687 phy_interface_t interface = priv->interface;
1689 /* This isn't autodetected right now, so it must
1690 * be set by the device tree or platform code.
1692 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1693 return PHY_INTERFACE_MODE_RGMII_ID;
1695 return PHY_INTERFACE_MODE_RGMII;
1699 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1700 return PHY_INTERFACE_MODE_GMII;
1702 return PHY_INTERFACE_MODE_MII;
1706 /* Initializes driver's PHY state, and attaches to the PHY.
1707 * Returns 0 on success.
1709 static int init_phy(struct net_device *dev)
1711 struct gfar_private *priv = netdev_priv(dev);
1712 uint gigabit_support =
1713 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1714 GFAR_SUPPORTED_GBIT : 0;
1715 phy_interface_t interface;
1719 priv->oldduplex = -1;
1721 interface = gfar_get_interface(dev);
1723 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1725 if (!priv->phydev) {
1726 dev_err(&dev->dev, "could not attach to PHY\n");
1730 if (interface == PHY_INTERFACE_MODE_SGMII)
1731 gfar_configure_serdes(dev);
1733 /* Remove any features not supported by the controller */
1734 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1735 priv->phydev->advertising = priv->phydev->supported;
1737 /* Add support for flow control, but don't advertise it by default */
1738 priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1743 /* Initialize TBI PHY interface for communicating with the
1744 * SERDES lynx PHY on the chip. We communicate with this PHY
1745 * through the MDIO bus on each controller, treating it as a
1746 * "normal" PHY at the address found in the TBIPA register. We assume
1747 * that the TBIPA register is valid. Either the MDIO bus code will set
1748 * it to a value that doesn't conflict with other PHYs on the bus, or the
1749 * value doesn't matter, as there are no other PHYs on the bus.
1751 static void gfar_configure_serdes(struct net_device *dev)
1753 struct gfar_private *priv = netdev_priv(dev);
1754 struct phy_device *tbiphy;
1756 if (!priv->tbi_node) {
1757 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1758 "device tree specify a tbi-handle\n");
1762 tbiphy = of_phy_find_device(priv->tbi_node);
1764 dev_err(&dev->dev, "error: Could not get TBI device\n");
1768 /* If the link is already up, we must already be ok, and don't need to
1769 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1770 * everything for us? Resetting it takes the link down and requires
1771 * several seconds for it to come back.
1773 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1776 /* Single clk mode, mii mode off(for serdes communication) */
1777 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1779 phy_write(tbiphy, MII_ADVERTISE,
1780 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1781 ADVERTISE_1000XPSE_ASYM);
1783 phy_write(tbiphy, MII_BMCR,
1784 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1788 static int __gfar_is_rx_idle(struct gfar_private *priv)
1792 /* Normaly TSEC should not hang on GRS commands, so we should
1793 * actually wait for IEVENT_GRSC flag.
1795 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1798 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1799 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1800 * and the Rx can be safely reset.
1802 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1804 if ((res & 0xffff) == (res >> 16))
1810 /* Halt the receive and transmit queues */
1811 static void gfar_halt_nodisable(struct gfar_private *priv)
1813 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1815 unsigned int timeout;
1818 gfar_ints_disable(priv);
1820 if (gfar_is_dma_stopped(priv))
1823 /* Stop the DMA, and wait for it to stop */
1824 tempval = gfar_read(®s->dmactrl);
1825 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1826 gfar_write(®s->dmactrl, tempval);
1830 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1836 stopped = gfar_is_dma_stopped(priv);
1838 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1839 !__gfar_is_rx_idle(priv))
1843 /* Halt the receive and transmit queues */
1844 void gfar_halt(struct gfar_private *priv)
1846 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1849 /* Dissable the Rx/Tx hw queues */
1850 gfar_write(®s->rqueue, 0);
1851 gfar_write(®s->tqueue, 0);
1855 gfar_halt_nodisable(priv);
1857 /* Disable Rx/Tx DMA */
1858 tempval = gfar_read(®s->maccfg1);
1859 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1860 gfar_write(®s->maccfg1, tempval);
1863 void stop_gfar(struct net_device *dev)
1865 struct gfar_private *priv = netdev_priv(dev);
1867 netif_tx_stop_all_queues(dev);
1869 smp_mb__before_atomic();
1870 set_bit(GFAR_DOWN, &priv->state);
1871 smp_mb__after_atomic();
1875 /* disable ints and gracefully shut down Rx/Tx DMA */
1878 phy_stop(priv->phydev);
1880 free_skb_resources(priv);
1883 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1885 struct txbd8 *txbdp;
1886 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1889 txbdp = tx_queue->tx_bd_base;
1891 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1892 if (!tx_queue->tx_skbuff[i])
1895 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1896 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1898 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1901 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1902 be16_to_cpu(txbdp->length),
1906 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1907 tx_queue->tx_skbuff[i] = NULL;
1909 kfree(tx_queue->tx_skbuff);
1910 tx_queue->tx_skbuff = NULL;
1913 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1915 struct rxbd8 *rxbdp;
1916 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1919 rxbdp = rx_queue->rx_bd_base;
1921 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1922 if (rx_queue->rx_skbuff[i]) {
1923 dma_unmap_single(priv->dev, be32_to_cpu(rxbdp->bufPtr),
1924 priv->rx_buffer_size,
1926 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1927 rx_queue->rx_skbuff[i] = NULL;
1933 kfree(rx_queue->rx_skbuff);
1934 rx_queue->rx_skbuff = NULL;
1937 /* If there are any tx skbs or rx skbs still around, free them.
1938 * Then free tx_skbuff and rx_skbuff
1940 static void free_skb_resources(struct gfar_private *priv)
1942 struct gfar_priv_tx_q *tx_queue = NULL;
1943 struct gfar_priv_rx_q *rx_queue = NULL;
1946 /* Go through all the buffer descriptors and free their data buffers */
1947 for (i = 0; i < priv->num_tx_queues; i++) {
1948 struct netdev_queue *txq;
1950 tx_queue = priv->tx_queue[i];
1951 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1952 if (tx_queue->tx_skbuff)
1953 free_skb_tx_queue(tx_queue);
1954 netdev_tx_reset_queue(txq);
1957 for (i = 0; i < priv->num_rx_queues; i++) {
1958 rx_queue = priv->rx_queue[i];
1959 if (rx_queue->rx_skbuff)
1960 free_skb_rx_queue(rx_queue);
1963 dma_free_coherent(priv->dev,
1964 sizeof(struct txbd8) * priv->total_tx_ring_size +
1965 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1966 priv->tx_queue[0]->tx_bd_base,
1967 priv->tx_queue[0]->tx_bd_dma_base);
1970 void gfar_start(struct gfar_private *priv)
1972 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1976 /* Enable Rx/Tx hw queues */
1977 gfar_write(®s->rqueue, priv->rqueue);
1978 gfar_write(®s->tqueue, priv->tqueue);
1980 /* Initialize DMACTRL to have WWR and WOP */
1981 tempval = gfar_read(®s->dmactrl);
1982 tempval |= DMACTRL_INIT_SETTINGS;
1983 gfar_write(®s->dmactrl, tempval);
1985 /* Make sure we aren't stopped */
1986 tempval = gfar_read(®s->dmactrl);
1987 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1988 gfar_write(®s->dmactrl, tempval);
1990 for (i = 0; i < priv->num_grps; i++) {
1991 regs = priv->gfargrp[i].regs;
1992 /* Clear THLT/RHLT, so that the DMA starts polling now */
1993 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1994 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1997 /* Enable Rx/Tx DMA */
1998 tempval = gfar_read(®s->maccfg1);
1999 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2000 gfar_write(®s->maccfg1, tempval);
2002 gfar_ints_enable(priv);
2004 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
2007 static void free_grp_irqs(struct gfar_priv_grp *grp)
2009 free_irq(gfar_irq(grp, TX)->irq, grp);
2010 free_irq(gfar_irq(grp, RX)->irq, grp);
2011 free_irq(gfar_irq(grp, ER)->irq, grp);
2014 static int register_grp_irqs(struct gfar_priv_grp *grp)
2016 struct gfar_private *priv = grp->priv;
2017 struct net_device *dev = priv->ndev;
2020 /* If the device has multiple interrupts, register for
2021 * them. Otherwise, only register for the one
2023 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2024 /* Install our interrupt handlers for Error,
2025 * Transmit, and Receive
2027 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2028 gfar_irq(grp, ER)->name, grp);
2030 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2031 gfar_irq(grp, ER)->irq);
2035 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2036 gfar_irq(grp, TX)->name, grp);
2038 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2039 gfar_irq(grp, TX)->irq);
2042 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2043 gfar_irq(grp, RX)->name, grp);
2045 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2046 gfar_irq(grp, RX)->irq);
2050 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2051 gfar_irq(grp, TX)->name, grp);
2053 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2054 gfar_irq(grp, TX)->irq);
2062 free_irq(gfar_irq(grp, TX)->irq, grp);
2064 free_irq(gfar_irq(grp, ER)->irq, grp);
2070 static void gfar_free_irq(struct gfar_private *priv)
2075 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2076 for (i = 0; i < priv->num_grps; i++)
2077 free_grp_irqs(&priv->gfargrp[i]);
2079 for (i = 0; i < priv->num_grps; i++)
2080 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2085 static int gfar_request_irq(struct gfar_private *priv)
2089 for (i = 0; i < priv->num_grps; i++) {
2090 err = register_grp_irqs(&priv->gfargrp[i]);
2092 for (j = 0; j < i; j++)
2093 free_grp_irqs(&priv->gfargrp[j]);
2101 /* Bring the controller up and running */
2102 int startup_gfar(struct net_device *ndev)
2104 struct gfar_private *priv = netdev_priv(ndev);
2107 gfar_mac_reset(priv);
2109 err = gfar_alloc_skb_resources(ndev);
2113 gfar_init_tx_rx_base(priv);
2115 smp_mb__before_atomic();
2116 clear_bit(GFAR_DOWN, &priv->state);
2117 smp_mb__after_atomic();
2119 /* Start Rx/Tx DMA and enable the interrupts */
2122 phy_start(priv->phydev);
2126 netif_tx_wake_all_queues(ndev);
2131 /* Called when something needs to use the ethernet device
2132 * Returns 0 for success.
2134 static int gfar_enet_open(struct net_device *dev)
2136 struct gfar_private *priv = netdev_priv(dev);
2139 err = init_phy(dev);
2143 err = gfar_request_irq(priv);
2147 err = startup_gfar(dev);
2151 device_set_wakeup_enable(&dev->dev, priv->wol_en);
2156 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2158 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2160 memset(fcb, 0, GMAC_FCB_LEN);
2165 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2168 /* If we're here, it's a IP packet with a TCP or UDP
2169 * payload. We set it to checksum, using a pseudo-header
2172 u8 flags = TXFCB_DEFAULT;
2174 /* Tell the controller what the protocol is
2175 * And provide the already calculated phcs
2177 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2179 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2181 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2183 /* l3os is the distance between the start of the
2184 * frame (skb->data) and the start of the IP hdr.
2185 * l4os is the distance between the start of the
2186 * l3 hdr and the l4 hdr
2188 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2189 fcb->l4os = skb_network_header_len(skb);
2194 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2196 fcb->flags |= TXFCB_VLN;
2197 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2200 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2201 struct txbd8 *base, int ring_size)
2203 struct txbd8 *new_bd = bdp + stride;
2205 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2208 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2211 return skip_txbd(bdp, 1, base, ring_size);
2214 /* eTSEC12: csum generation not supported for some fcb offsets */
2215 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2216 unsigned long fcb_addr)
2218 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2219 (fcb_addr % 0x20) > 0x18);
2222 /* eTSEC76: csum generation for frames larger than 2500 may
2223 * cause excess delays before start of transmission
2225 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2228 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2232 /* This is called by the kernel when a frame is ready for transmission.
2233 * It is pointed to by the dev->hard_start_xmit function pointer
2235 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2237 struct gfar_private *priv = netdev_priv(dev);
2238 struct gfar_priv_tx_q *tx_queue = NULL;
2239 struct netdev_queue *txq;
2240 struct gfar __iomem *regs = NULL;
2241 struct txfcb *fcb = NULL;
2242 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2245 int do_tstamp, do_csum, do_vlan;
2247 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2249 rq = skb->queue_mapping;
2250 tx_queue = priv->tx_queue[rq];
2251 txq = netdev_get_tx_queue(dev, rq);
2252 base = tx_queue->tx_bd_base;
2253 regs = tx_queue->grp->regs;
2255 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2256 do_vlan = skb_vlan_tag_present(skb);
2257 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2260 if (do_csum || do_vlan)
2261 fcb_len = GMAC_FCB_LEN;
2263 /* check if time stamp should be generated */
2264 if (unlikely(do_tstamp))
2265 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2267 /* make space for additional header when fcb is needed */
2268 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2269 struct sk_buff *skb_new;
2271 skb_new = skb_realloc_headroom(skb, fcb_len);
2273 dev->stats.tx_errors++;
2274 dev_kfree_skb_any(skb);
2275 return NETDEV_TX_OK;
2279 skb_set_owner_w(skb_new, skb->sk);
2280 dev_consume_skb_any(skb);
2284 /* total number of fragments in the SKB */
2285 nr_frags = skb_shinfo(skb)->nr_frags;
2287 /* calculate the required number of TxBDs for this skb */
2288 if (unlikely(do_tstamp))
2289 nr_txbds = nr_frags + 2;
2291 nr_txbds = nr_frags + 1;
2293 /* check if there is space to queue this packet */
2294 if (nr_txbds > tx_queue->num_txbdfree) {
2295 /* no space, stop the queue */
2296 netif_tx_stop_queue(txq);
2297 dev->stats.tx_fifo_errors++;
2298 return NETDEV_TX_BUSY;
2301 /* Update transmit stats */
2302 bytes_sent = skb->len;
2303 tx_queue->stats.tx_bytes += bytes_sent;
2304 /* keep Tx bytes on wire for BQL accounting */
2305 GFAR_CB(skb)->bytes_sent = bytes_sent;
2306 tx_queue->stats.tx_packets++;
2308 txbdp = txbdp_start = tx_queue->cur_tx;
2309 lstatus = be32_to_cpu(txbdp->lstatus);
2311 /* Time stamp insertion requires one additional TxBD */
2312 if (unlikely(do_tstamp))
2313 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2314 tx_queue->tx_ring_size);
2316 if (nr_frags == 0) {
2317 if (unlikely(do_tstamp)) {
2318 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2320 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2321 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2323 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2326 /* Place the fragment addresses and lengths into the TxBDs */
2327 for (i = 0; i < nr_frags; i++) {
2328 unsigned int frag_len;
2329 /* Point at the next BD, wrapping as needed */
2330 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2332 frag_len = skb_shinfo(skb)->frags[i].size;
2334 lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
2335 BD_LFLAG(TXBD_READY);
2337 /* Handle the last BD specially */
2338 if (i == nr_frags - 1)
2339 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2341 bufaddr = skb_frag_dma_map(priv->dev,
2342 &skb_shinfo(skb)->frags[i],
2346 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2349 /* set the TxBD length and buffer pointer */
2350 txbdp->bufPtr = cpu_to_be32(bufaddr);
2351 txbdp->lstatus = cpu_to_be32(lstatus);
2354 lstatus = be32_to_cpu(txbdp_start->lstatus);
2357 /* Add TxPAL between FCB and frame if required */
2358 if (unlikely(do_tstamp)) {
2359 skb_push(skb, GMAC_TXPAL_LEN);
2360 memset(skb->data, 0, GMAC_TXPAL_LEN);
2363 /* Add TxFCB if required */
2365 fcb = gfar_add_fcb(skb);
2366 lstatus |= BD_LFLAG(TXBD_TOE);
2369 /* Set up checksumming */
2371 gfar_tx_checksum(skb, fcb, fcb_len);
2373 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2374 unlikely(gfar_csum_errata_76(priv, skb->len))) {
2375 __skb_pull(skb, GMAC_FCB_LEN);
2376 skb_checksum_help(skb);
2377 if (do_vlan || do_tstamp) {
2378 /* put back a new fcb for vlan/tstamp TOE */
2379 fcb = gfar_add_fcb(skb);
2381 /* Tx TOE not used */
2382 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2389 gfar_tx_vlan(skb, fcb);
2391 /* Setup tx hardware time stamping if requested */
2392 if (unlikely(do_tstamp)) {
2393 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2397 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2399 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2402 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2404 /* If time stamping is requested one additional TxBD must be set up. The
2405 * first TxBD points to the FCB and must have a data length of
2406 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2407 * the full frame length.
2409 if (unlikely(do_tstamp)) {
2410 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2412 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2414 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2415 (skb_headlen(skb) - fcb_len);
2417 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2418 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2419 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2421 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2424 netdev_tx_sent_queue(txq, bytes_sent);
2428 txbdp_start->lstatus = cpu_to_be32(lstatus);
2430 gfar_wmb(); /* force lstatus write before tx_skbuff */
2432 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2434 /* Update the current skb pointer to the next entry we will use
2435 * (wrapping if necessary)
2437 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2438 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2440 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2442 /* We can work in parallel with gfar_clean_tx_ring(), except
2443 * when modifying num_txbdfree. Note that we didn't grab the lock
2444 * when we were reading the num_txbdfree and checking for available
2445 * space, that's because outside of this function it can only grow.
2447 spin_lock_bh(&tx_queue->txlock);
2448 /* reduce TxBD free count */
2449 tx_queue->num_txbdfree -= (nr_txbds);
2450 spin_unlock_bh(&tx_queue->txlock);
2452 /* If the next BD still needs to be cleaned up, then the bds
2453 * are full. We need to tell the kernel to stop sending us stuff.
2455 if (!tx_queue->num_txbdfree) {
2456 netif_tx_stop_queue(txq);
2458 dev->stats.tx_fifo_errors++;
2461 /* Tell the DMA to go go go */
2462 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2464 return NETDEV_TX_OK;
2467 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2469 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2470 for (i = 0; i < nr_frags; i++) {
2471 lstatus = be32_to_cpu(txbdp->lstatus);
2472 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2475 lstatus &= ~BD_LFLAG(TXBD_READY);
2476 txbdp->lstatus = cpu_to_be32(lstatus);
2477 bufaddr = be32_to_cpu(txbdp->bufPtr);
2478 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2480 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2483 dev_kfree_skb_any(skb);
2484 return NETDEV_TX_OK;
2487 /* Stops the kernel queue, and halts the controller */
2488 static int gfar_close(struct net_device *dev)
2490 struct gfar_private *priv = netdev_priv(dev);
2492 cancel_work_sync(&priv->reset_task);
2495 /* Disconnect from the PHY */
2496 phy_disconnect(priv->phydev);
2497 priv->phydev = NULL;
2499 gfar_free_irq(priv);
2504 /* Changes the mac address if the controller is not running. */
2505 static int gfar_set_mac_address(struct net_device *dev)
2507 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2512 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2514 struct gfar_private *priv = netdev_priv(dev);
2515 int frame_size = new_mtu + ETH_HLEN;
2517 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2518 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2522 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2525 if (dev->flags & IFF_UP)
2530 if (dev->flags & IFF_UP)
2533 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2538 void reset_gfar(struct net_device *ndev)
2540 struct gfar_private *priv = netdev_priv(ndev);
2542 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2548 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2551 /* gfar_reset_task gets scheduled when a packet has not been
2552 * transmitted after a set amount of time.
2553 * For now, assume that clearing out all the structures, and
2554 * starting over will fix the problem.
2556 static void gfar_reset_task(struct work_struct *work)
2558 struct gfar_private *priv = container_of(work, struct gfar_private,
2560 reset_gfar(priv->ndev);
2563 static void gfar_timeout(struct net_device *dev)
2565 struct gfar_private *priv = netdev_priv(dev);
2567 dev->stats.tx_errors++;
2568 schedule_work(&priv->reset_task);
2571 static void gfar_align_skb(struct sk_buff *skb)
2573 /* We need the data buffer to be aligned properly. We will reserve
2574 * as many bytes as needed to align the data properly
2576 skb_reserve(skb, RXBUF_ALIGNMENT -
2577 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2580 /* Interrupt Handler for Transmit complete */
2581 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2583 struct net_device *dev = tx_queue->dev;
2584 struct netdev_queue *txq;
2585 struct gfar_private *priv = netdev_priv(dev);
2586 struct txbd8 *bdp, *next = NULL;
2587 struct txbd8 *lbdp = NULL;
2588 struct txbd8 *base = tx_queue->tx_bd_base;
2589 struct sk_buff *skb;
2591 int tx_ring_size = tx_queue->tx_ring_size;
2592 int frags = 0, nr_txbds = 0;
2595 int tqi = tx_queue->qindex;
2596 unsigned int bytes_sent = 0;
2600 txq = netdev_get_tx_queue(dev, tqi);
2601 bdp = tx_queue->dirty_tx;
2602 skb_dirtytx = tx_queue->skb_dirtytx;
2604 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2606 frags = skb_shinfo(skb)->nr_frags;
2608 /* When time stamping, one additional TxBD must be freed.
2609 * Also, we need to dma_unmap_single() the TxPAL.
2611 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2612 nr_txbds = frags + 2;
2614 nr_txbds = frags + 1;
2616 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2618 lstatus = be32_to_cpu(lbdp->lstatus);
2620 /* Only clean completed frames */
2621 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2622 (lstatus & BD_LENGTH_MASK))
2625 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2626 next = next_txbd(bdp, base, tx_ring_size);
2627 buflen = be16_to_cpu(next->length) +
2628 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2630 buflen = be16_to_cpu(bdp->length);
2632 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2633 buflen, DMA_TO_DEVICE);
2635 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2636 struct skb_shared_hwtstamps shhwtstamps;
2637 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2639 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2640 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2641 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2642 skb_tstamp_tx(skb, &shhwtstamps);
2643 gfar_clear_txbd_status(bdp);
2647 gfar_clear_txbd_status(bdp);
2648 bdp = next_txbd(bdp, base, tx_ring_size);
2650 for (i = 0; i < frags; i++) {
2651 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2652 be16_to_cpu(bdp->length),
2654 gfar_clear_txbd_status(bdp);
2655 bdp = next_txbd(bdp, base, tx_ring_size);
2658 bytes_sent += GFAR_CB(skb)->bytes_sent;
2660 dev_kfree_skb_any(skb);
2662 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2664 skb_dirtytx = (skb_dirtytx + 1) &
2665 TX_RING_MOD_MASK(tx_ring_size);
2668 spin_lock(&tx_queue->txlock);
2669 tx_queue->num_txbdfree += nr_txbds;
2670 spin_unlock(&tx_queue->txlock);
2673 /* If we freed a buffer, we can restart transmission, if necessary */
2674 if (tx_queue->num_txbdfree &&
2675 netif_tx_queue_stopped(txq) &&
2676 !(test_bit(GFAR_DOWN, &priv->state)))
2677 netif_wake_subqueue(priv->ndev, tqi);
2679 /* Update dirty indicators */
2680 tx_queue->skb_dirtytx = skb_dirtytx;
2681 tx_queue->dirty_tx = bdp;
2683 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2686 static struct sk_buff *gfar_new_skb(struct net_device *ndev,
2687 dma_addr_t *bufaddr)
2689 struct gfar_private *priv = netdev_priv(ndev);
2690 struct sk_buff *skb;
2693 skb = netdev_alloc_skb(ndev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2697 gfar_align_skb(skb);
2699 addr = dma_map_single(priv->dev, skb->data,
2700 priv->rx_buffer_size, DMA_FROM_DEVICE);
2701 if (unlikely(dma_mapping_error(priv->dev, addr))) {
2702 dev_kfree_skb_any(skb);
2710 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2712 struct gfar_private *priv = netdev_priv(rx_queue->dev);
2713 struct gfar_extra_stats *estats = &priv->extra_stats;
2715 netdev_err(rx_queue->dev, "Can't alloc RX buffers\n");
2716 atomic64_inc(&estats->rx_alloc_err);
2719 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2722 struct net_device *ndev = rx_queue->dev;
2723 struct rxbd8 *bdp, *base;
2727 i = rx_queue->next_to_use;
2728 base = rx_queue->rx_bd_base;
2729 bdp = &rx_queue->rx_bd_base[i];
2731 while (alloc_cnt--) {
2732 struct sk_buff *skb = rx_queue->rx_skbuff[i];
2735 skb = gfar_new_skb(ndev, &bufaddr);
2736 if (unlikely(!skb)) {
2737 gfar_rx_alloc_err(rx_queue);
2740 } else { /* restore from sleep state */
2741 bufaddr = be32_to_cpu(bdp->bufPtr);
2744 rx_queue->rx_skbuff[i] = skb;
2746 /* Setup the new RxBD */
2747 gfar_init_rxbdp(rx_queue, bdp, bufaddr);
2749 /* Update to the next pointer */
2750 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2752 if (unlikely(++i == rx_queue->rx_ring_size))
2756 rx_queue->next_to_use = i;
2759 static inline void count_errors(unsigned short status, struct net_device *dev)
2761 struct gfar_private *priv = netdev_priv(dev);
2762 struct net_device_stats *stats = &dev->stats;
2763 struct gfar_extra_stats *estats = &priv->extra_stats;
2765 /* If the packet was truncated, none of the other errors matter */
2766 if (status & RXBD_TRUNCATED) {
2767 stats->rx_length_errors++;
2769 atomic64_inc(&estats->rx_trunc);
2773 /* Count the errors, if there were any */
2774 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2775 stats->rx_length_errors++;
2777 if (status & RXBD_LARGE)
2778 atomic64_inc(&estats->rx_large);
2780 atomic64_inc(&estats->rx_short);
2782 if (status & RXBD_NONOCTET) {
2783 stats->rx_frame_errors++;
2784 atomic64_inc(&estats->rx_nonoctet);
2786 if (status & RXBD_CRCERR) {
2787 atomic64_inc(&estats->rx_crcerr);
2788 stats->rx_crc_errors++;
2790 if (status & RXBD_OVERRUN) {
2791 atomic64_inc(&estats->rx_overrun);
2792 stats->rx_crc_errors++;
2796 irqreturn_t gfar_receive(int irq, void *grp_id)
2798 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2799 unsigned long flags;
2802 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2803 spin_lock_irqsave(&grp->grplock, flags);
2804 imask = gfar_read(&grp->regs->imask);
2805 imask &= IMASK_RX_DISABLED;
2806 gfar_write(&grp->regs->imask, imask);
2807 spin_unlock_irqrestore(&grp->grplock, flags);
2808 __napi_schedule(&grp->napi_rx);
2810 /* Clear IEVENT, so interrupts aren't called again
2811 * because of the packets that have already arrived.
2813 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2819 /* Interrupt Handler for Transmit complete */
2820 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2822 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2823 unsigned long flags;
2826 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2827 spin_lock_irqsave(&grp->grplock, flags);
2828 imask = gfar_read(&grp->regs->imask);
2829 imask &= IMASK_TX_DISABLED;
2830 gfar_write(&grp->regs->imask, imask);
2831 spin_unlock_irqrestore(&grp->grplock, flags);
2832 __napi_schedule(&grp->napi_tx);
2834 /* Clear IEVENT, so interrupts aren't called again
2835 * because of the packets that have already arrived.
2837 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2843 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2845 /* If valid headers were found, and valid sums
2846 * were verified, then we tell the kernel that no
2847 * checksumming is necessary. Otherwise, it is [FIXME]
2849 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2850 (RXFCB_CIP | RXFCB_CTU))
2851 skb->ip_summed = CHECKSUM_UNNECESSARY;
2853 skb_checksum_none_assert(skb);
2856 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2857 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2858 struct napi_struct *napi)
2860 struct gfar_private *priv = netdev_priv(dev);
2861 struct rxfcb *fcb = NULL;
2863 /* fcb is at the beginning if exists */
2864 fcb = (struct rxfcb *)skb->data;
2866 /* Remove the FCB from the skb
2867 * Remove the padded bytes, if there are any
2869 if (priv->uses_rxfcb) {
2870 skb_record_rx_queue(skb, fcb->rq);
2871 skb_pull(skb, GMAC_FCB_LEN);
2874 /* Get receive timestamp from the skb */
2875 if (priv->hwts_rx_en) {
2876 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2877 u64 *ns = (u64 *) skb->data;
2879 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2880 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2884 skb_pull(skb, priv->padding);
2886 if (dev->features & NETIF_F_RXCSUM)
2887 gfar_rx_checksum(skb, fcb);
2889 /* Tell the skb what kind of packet this is */
2890 skb->protocol = eth_type_trans(skb, dev);
2892 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2893 * Even if vlan rx accel is disabled, on some chips
2894 * RXFCB_VLN is pseudo randomly set.
2896 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2897 be16_to_cpu(fcb->flags) & RXFCB_VLN)
2898 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2899 be16_to_cpu(fcb->vlctl));
2901 /* Send the packet up the stack */
2902 napi_gro_receive(napi, skb);
2906 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2907 * until the budget/quota has been reached. Returns the number
2910 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2912 struct net_device *dev = rx_queue->dev;
2913 struct rxbd8 *bdp, *base;
2914 struct sk_buff *skb;
2916 int cleaned_cnt = gfar_rxbd_unused(rx_queue);
2917 struct gfar_private *priv = netdev_priv(dev);
2919 /* Get the first full descriptor */
2920 base = rx_queue->rx_bd_base;
2921 i = rx_queue->next_to_clean;
2923 while (rx_work_limit--) {
2925 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
2926 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2930 bdp = &rx_queue->rx_bd_base[i];
2931 if (be16_to_cpu(bdp->status) & RXBD_EMPTY)
2934 /* order rx buffer descriptor reads */
2937 /* fetch next to clean buffer from the ring */
2938 skb = rx_queue->rx_skbuff[i];
2940 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2941 priv->rx_buffer_size, DMA_FROM_DEVICE);
2943 if (unlikely(!(be16_to_cpu(bdp->status) & RXBD_ERR) &&
2944 be16_to_cpu(bdp->length) > priv->rx_buffer_size))
2945 bdp->status = cpu_to_be16(RXBD_LARGE);
2947 if (unlikely(!(be16_to_cpu(bdp->status) & RXBD_LAST) ||
2948 be16_to_cpu(bdp->status) & RXBD_ERR)) {
2949 count_errors(be16_to_cpu(bdp->status), dev);
2951 /* discard faulty buffer */
2955 /* Increment the number of packets */
2956 rx_queue->stats.rx_packets++;
2960 int pkt_len = be16_to_cpu(bdp->length) -
2962 /* Remove the FCS from the packet length */
2963 skb_put(skb, pkt_len);
2964 rx_queue->stats.rx_bytes += pkt_len;
2965 skb_record_rx_queue(skb, rx_queue->qindex);
2966 gfar_process_frame(dev, skb,
2967 &rx_queue->grp->napi_rx);
2970 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2971 rx_queue->stats.rx_dropped++;
2972 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2977 rx_queue->rx_skbuff[i] = NULL;
2979 if (unlikely(++i == rx_queue->rx_ring_size))
2983 rx_queue->next_to_clean = i;
2986 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2988 /* Update Last Free RxBD pointer for LFC */
2989 if (unlikely(priv->tx_actual_en)) {
2990 bdp = gfar_rxbd_lastfree(rx_queue);
2991 gfar_write(rx_queue->rfbptr, (u32)bdp);
2997 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2999 struct gfar_priv_grp *gfargrp =
3000 container_of(napi, struct gfar_priv_grp, napi_rx);
3001 struct gfar __iomem *regs = gfargrp->regs;
3002 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3005 /* Clear IEVENT, so interrupts aren't called again
3006 * because of the packets that have already arrived
3008 gfar_write(®s->ievent, IEVENT_RX_MASK);
3010 work_done = gfar_clean_rx_ring(rx_queue, budget);
3012 if (work_done < budget) {
3014 napi_complete(napi);
3015 /* Clear the halt bit in RSTAT */
3016 gfar_write(®s->rstat, gfargrp->rstat);
3018 spin_lock_irq(&gfargrp->grplock);
3019 imask = gfar_read(®s->imask);
3020 imask |= IMASK_RX_DEFAULT;
3021 gfar_write(®s->imask, imask);
3022 spin_unlock_irq(&gfargrp->grplock);
3028 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3030 struct gfar_priv_grp *gfargrp =
3031 container_of(napi, struct gfar_priv_grp, napi_tx);
3032 struct gfar __iomem *regs = gfargrp->regs;
3033 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3036 /* Clear IEVENT, so interrupts aren't called again
3037 * because of the packets that have already arrived
3039 gfar_write(®s->ievent, IEVENT_TX_MASK);
3041 /* run Tx cleanup to completion */
3042 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3043 gfar_clean_tx_ring(tx_queue);
3045 napi_complete(napi);
3047 spin_lock_irq(&gfargrp->grplock);
3048 imask = gfar_read(®s->imask);
3049 imask |= IMASK_TX_DEFAULT;
3050 gfar_write(®s->imask, imask);
3051 spin_unlock_irq(&gfargrp->grplock);
3056 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3058 struct gfar_priv_grp *gfargrp =
3059 container_of(napi, struct gfar_priv_grp, napi_rx);
3060 struct gfar_private *priv = gfargrp->priv;
3061 struct gfar __iomem *regs = gfargrp->regs;
3062 struct gfar_priv_rx_q *rx_queue = NULL;
3063 int work_done = 0, work_done_per_q = 0;
3064 int i, budget_per_q = 0;
3065 unsigned long rstat_rxf;
3068 /* Clear IEVENT, so interrupts aren't called again
3069 * because of the packets that have already arrived
3071 gfar_write(®s->ievent, IEVENT_RX_MASK);
3073 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
3075 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3077 budget_per_q = budget/num_act_queues;
3079 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3080 /* skip queue if not active */
3081 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3084 rx_queue = priv->rx_queue[i];
3086 gfar_clean_rx_ring(rx_queue, budget_per_q);
3087 work_done += work_done_per_q;
3089 /* finished processing this queue */
3090 if (work_done_per_q < budget_per_q) {
3091 /* clear active queue hw indication */
3092 gfar_write(®s->rstat,
3093 RSTAT_CLEAR_RXF0 >> i);
3096 if (!num_act_queues)
3101 if (!num_act_queues) {
3103 napi_complete(napi);
3105 /* Clear the halt bit in RSTAT */
3106 gfar_write(®s->rstat, gfargrp->rstat);
3108 spin_lock_irq(&gfargrp->grplock);
3109 imask = gfar_read(®s->imask);
3110 imask |= IMASK_RX_DEFAULT;
3111 gfar_write(®s->imask, imask);
3112 spin_unlock_irq(&gfargrp->grplock);
3118 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3120 struct gfar_priv_grp *gfargrp =
3121 container_of(napi, struct gfar_priv_grp, napi_tx);
3122 struct gfar_private *priv = gfargrp->priv;
3123 struct gfar __iomem *regs = gfargrp->regs;
3124 struct gfar_priv_tx_q *tx_queue = NULL;
3125 int has_tx_work = 0;
3128 /* Clear IEVENT, so interrupts aren't called again
3129 * because of the packets that have already arrived
3131 gfar_write(®s->ievent, IEVENT_TX_MASK);
3133 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3134 tx_queue = priv->tx_queue[i];
3135 /* run Tx cleanup to completion */
3136 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3137 gfar_clean_tx_ring(tx_queue);
3144 napi_complete(napi);
3146 spin_lock_irq(&gfargrp->grplock);
3147 imask = gfar_read(®s->imask);
3148 imask |= IMASK_TX_DEFAULT;
3149 gfar_write(®s->imask, imask);
3150 spin_unlock_irq(&gfargrp->grplock);
3157 #ifdef CONFIG_NET_POLL_CONTROLLER
3158 /* Polling 'interrupt' - used by things like netconsole to send skbs
3159 * without having to re-enable interrupts. It's not called while
3160 * the interrupt routine is executing.
3162 static void gfar_netpoll(struct net_device *dev)
3164 struct gfar_private *priv = netdev_priv(dev);
3167 /* If the device has multiple interrupts, run tx/rx */
3168 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3169 for (i = 0; i < priv->num_grps; i++) {
3170 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3172 disable_irq(gfar_irq(grp, TX)->irq);
3173 disable_irq(gfar_irq(grp, RX)->irq);
3174 disable_irq(gfar_irq(grp, ER)->irq);
3175 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3176 enable_irq(gfar_irq(grp, ER)->irq);
3177 enable_irq(gfar_irq(grp, RX)->irq);
3178 enable_irq(gfar_irq(grp, TX)->irq);
3181 for (i = 0; i < priv->num_grps; i++) {
3182 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3184 disable_irq(gfar_irq(grp, TX)->irq);
3185 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3186 enable_irq(gfar_irq(grp, TX)->irq);
3192 /* The interrupt handler for devices with one interrupt */
3193 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3195 struct gfar_priv_grp *gfargrp = grp_id;
3197 /* Save ievent for future reference */
3198 u32 events = gfar_read(&gfargrp->regs->ievent);
3200 /* Check for reception */
3201 if (events & IEVENT_RX_MASK)
3202 gfar_receive(irq, grp_id);
3204 /* Check for transmit completion */
3205 if (events & IEVENT_TX_MASK)
3206 gfar_transmit(irq, grp_id);
3208 /* Check for errors */
3209 if (events & IEVENT_ERR_MASK)
3210 gfar_error(irq, grp_id);
3215 /* Called every time the controller might need to be made
3216 * aware of new link state. The PHY code conveys this
3217 * information through variables in the phydev structure, and this
3218 * function converts those variables into the appropriate
3219 * register values, and can bring down the device if needed.
3221 static void adjust_link(struct net_device *dev)
3223 struct gfar_private *priv = netdev_priv(dev);
3224 struct phy_device *phydev = priv->phydev;
3226 if (unlikely(phydev->link != priv->oldlink ||
3227 (phydev->link && (phydev->duplex != priv->oldduplex ||
3228 phydev->speed != priv->oldspeed))))
3229 gfar_update_link_state(priv);
3232 /* Update the hash table based on the current list of multicast
3233 * addresses we subscribe to. Also, change the promiscuity of
3234 * the device based on the flags (this function is called
3235 * whenever dev->flags is changed
3237 static void gfar_set_multi(struct net_device *dev)
3239 struct netdev_hw_addr *ha;
3240 struct gfar_private *priv = netdev_priv(dev);
3241 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3244 if (dev->flags & IFF_PROMISC) {
3245 /* Set RCTRL to PROM */
3246 tempval = gfar_read(®s->rctrl);
3247 tempval |= RCTRL_PROM;
3248 gfar_write(®s->rctrl, tempval);
3250 /* Set RCTRL to not PROM */
3251 tempval = gfar_read(®s->rctrl);
3252 tempval &= ~(RCTRL_PROM);
3253 gfar_write(®s->rctrl, tempval);
3256 if (dev->flags & IFF_ALLMULTI) {
3257 /* Set the hash to rx all multicast frames */
3258 gfar_write(®s->igaddr0, 0xffffffff);
3259 gfar_write(®s->igaddr1, 0xffffffff);
3260 gfar_write(®s->igaddr2, 0xffffffff);
3261 gfar_write(®s->igaddr3, 0xffffffff);
3262 gfar_write(®s->igaddr4, 0xffffffff);
3263 gfar_write(®s->igaddr5, 0xffffffff);
3264 gfar_write(®s->igaddr6, 0xffffffff);
3265 gfar_write(®s->igaddr7, 0xffffffff);
3266 gfar_write(®s->gaddr0, 0xffffffff);
3267 gfar_write(®s->gaddr1, 0xffffffff);
3268 gfar_write(®s->gaddr2, 0xffffffff);
3269 gfar_write(®s->gaddr3, 0xffffffff);
3270 gfar_write(®s->gaddr4, 0xffffffff);
3271 gfar_write(®s->gaddr5, 0xffffffff);
3272 gfar_write(®s->gaddr6, 0xffffffff);
3273 gfar_write(®s->gaddr7, 0xffffffff);
3278 /* zero out the hash */
3279 gfar_write(®s->igaddr0, 0x0);
3280 gfar_write(®s->igaddr1, 0x0);
3281 gfar_write(®s->igaddr2, 0x0);
3282 gfar_write(®s->igaddr3, 0x0);
3283 gfar_write(®s->igaddr4, 0x0);
3284 gfar_write(®s->igaddr5, 0x0);
3285 gfar_write(®s->igaddr6, 0x0);
3286 gfar_write(®s->igaddr7, 0x0);
3287 gfar_write(®s->gaddr0, 0x0);
3288 gfar_write(®s->gaddr1, 0x0);
3289 gfar_write(®s->gaddr2, 0x0);
3290 gfar_write(®s->gaddr3, 0x0);
3291 gfar_write(®s->gaddr4, 0x0);
3292 gfar_write(®s->gaddr5, 0x0);
3293 gfar_write(®s->gaddr6, 0x0);
3294 gfar_write(®s->gaddr7, 0x0);
3296 /* If we have extended hash tables, we need to
3297 * clear the exact match registers to prepare for
3300 if (priv->extended_hash) {
3301 em_num = GFAR_EM_NUM + 1;
3302 gfar_clear_exact_match(dev);
3309 if (netdev_mc_empty(dev))
3312 /* Parse the list, and set the appropriate bits */
3313 netdev_for_each_mc_addr(ha, dev) {
3315 gfar_set_mac_for_addr(dev, idx, ha->addr);
3318 gfar_set_hash_for_addr(dev, ha->addr);
3324 /* Clears each of the exact match registers to zero, so they
3325 * don't interfere with normal reception
3327 static void gfar_clear_exact_match(struct net_device *dev)
3330 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3332 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3333 gfar_set_mac_for_addr(dev, idx, zero_arr);
3336 /* Set the appropriate hash bit for the given addr */
3337 /* The algorithm works like so:
3338 * 1) Take the Destination Address (ie the multicast address), and
3339 * do a CRC on it (little endian), and reverse the bits of the
3341 * 2) Use the 8 most significant bits as a hash into a 256-entry
3342 * table. The table is controlled through 8 32-bit registers:
3343 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3344 * gaddr7. This means that the 3 most significant bits in the
3345 * hash index which gaddr register to use, and the 5 other bits
3346 * indicate which bit (assuming an IBM numbering scheme, which
3347 * for PowerPC (tm) is usually the case) in the register holds
3350 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3353 struct gfar_private *priv = netdev_priv(dev);
3354 u32 result = ether_crc(ETH_ALEN, addr);
3355 int width = priv->hash_width;
3356 u8 whichbit = (result >> (32 - width)) & 0x1f;
3357 u8 whichreg = result >> (32 - width + 5);
3358 u32 value = (1 << (31-whichbit));
3360 tempval = gfar_read(priv->hash_regs[whichreg]);
3362 gfar_write(priv->hash_regs[whichreg], tempval);
3366 /* There are multiple MAC Address register pairs on some controllers
3367 * This function sets the numth pair to a given address
3369 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3372 struct gfar_private *priv = netdev_priv(dev);
3373 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3375 u32 __iomem *macptr = ®s->macstnaddr1;
3379 /* For a station address of 0x12345678ABCD in transmission
3380 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3381 * MACnADDR2 is set to 0x34120000.
3383 tempval = (addr[5] << 24) | (addr[4] << 16) |
3384 (addr[3] << 8) | addr[2];
3386 gfar_write(macptr, tempval);
3388 tempval = (addr[1] << 24) | (addr[0] << 16);
3390 gfar_write(macptr+1, tempval);
3393 /* GFAR error interrupt handler */
3394 static irqreturn_t gfar_error(int irq, void *grp_id)
3396 struct gfar_priv_grp *gfargrp = grp_id;
3397 struct gfar __iomem *regs = gfargrp->regs;
3398 struct gfar_private *priv= gfargrp->priv;
3399 struct net_device *dev = priv->ndev;
3401 /* Save ievent for future reference */
3402 u32 events = gfar_read(®s->ievent);
3405 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3407 /* Magic Packet is not an error. */
3408 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3409 (events & IEVENT_MAG))
3410 events &= ~IEVENT_MAG;
3413 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3415 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3416 events, gfar_read(®s->imask));
3418 /* Update the error counters */
3419 if (events & IEVENT_TXE) {
3420 dev->stats.tx_errors++;
3422 if (events & IEVENT_LC)
3423 dev->stats.tx_window_errors++;
3424 if (events & IEVENT_CRL)
3425 dev->stats.tx_aborted_errors++;
3426 if (events & IEVENT_XFUN) {
3427 netif_dbg(priv, tx_err, dev,
3428 "TX FIFO underrun, packet dropped\n");
3429 dev->stats.tx_dropped++;
3430 atomic64_inc(&priv->extra_stats.tx_underrun);
3432 schedule_work(&priv->reset_task);
3434 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3436 if (events & IEVENT_BSY) {
3437 dev->stats.rx_errors++;
3438 atomic64_inc(&priv->extra_stats.rx_bsy);
3440 gfar_receive(irq, grp_id);
3442 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3443 gfar_read(®s->rstat));
3445 if (events & IEVENT_BABR) {
3446 dev->stats.rx_errors++;
3447 atomic64_inc(&priv->extra_stats.rx_babr);
3449 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3451 if (events & IEVENT_EBERR) {
3452 atomic64_inc(&priv->extra_stats.eberr);
3453 netif_dbg(priv, rx_err, dev, "bus error\n");
3455 if (events & IEVENT_RXC)
3456 netif_dbg(priv, rx_status, dev, "control frame\n");
3458 if (events & IEVENT_BABT) {
3459 atomic64_inc(&priv->extra_stats.tx_babt);
3460 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3465 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3467 struct phy_device *phydev = priv->phydev;
3470 if (!phydev->duplex)
3473 if (!priv->pause_aneg_en) {
3474 if (priv->tx_pause_en)
3475 val |= MACCFG1_TX_FLOW;
3476 if (priv->rx_pause_en)
3477 val |= MACCFG1_RX_FLOW;
3479 u16 lcl_adv, rmt_adv;
3481 /* get link partner capabilities */
3484 rmt_adv = LPA_PAUSE_CAP;
3485 if (phydev->asym_pause)
3486 rmt_adv |= LPA_PAUSE_ASYM;
3489 if (phydev->advertising & ADVERTISED_Pause)
3490 lcl_adv |= ADVERTISE_PAUSE_CAP;
3491 if (phydev->advertising & ADVERTISED_Asym_Pause)
3492 lcl_adv |= ADVERTISE_PAUSE_ASYM;
3494 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3495 if (flowctrl & FLOW_CTRL_TX)
3496 val |= MACCFG1_TX_FLOW;
3497 if (flowctrl & FLOW_CTRL_RX)
3498 val |= MACCFG1_RX_FLOW;
3504 static noinline void gfar_update_link_state(struct gfar_private *priv)
3506 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3507 struct phy_device *phydev = priv->phydev;
3508 struct gfar_priv_rx_q *rx_queue = NULL;
3512 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3516 u32 tempval1 = gfar_read(®s->maccfg1);
3517 u32 tempval = gfar_read(®s->maccfg2);
3518 u32 ecntrl = gfar_read(®s->ecntrl);
3519 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3521 if (phydev->duplex != priv->oldduplex) {
3522 if (!(phydev->duplex))
3523 tempval &= ~(MACCFG2_FULL_DUPLEX);
3525 tempval |= MACCFG2_FULL_DUPLEX;
3527 priv->oldduplex = phydev->duplex;
3530 if (phydev->speed != priv->oldspeed) {
3531 switch (phydev->speed) {
3534 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3536 ecntrl &= ~(ECNTRL_R100);
3541 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3543 /* Reduced mode distinguishes
3544 * between 10 and 100
3546 if (phydev->speed == SPEED_100)
3547 ecntrl |= ECNTRL_R100;
3549 ecntrl &= ~(ECNTRL_R100);
3552 netif_warn(priv, link, priv->ndev,
3553 "Ack! Speed (%d) is not 10/100/1000!\n",
3558 priv->oldspeed = phydev->speed;
3561 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3562 tempval1 |= gfar_get_flowctrl_cfg(priv);
3564 /* Turn last free buffer recording on */
3565 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3566 for (i = 0; i < priv->num_rx_queues; i++) {
3567 rx_queue = priv->rx_queue[i];
3568 bdp = gfar_rxbd_lastfree(rx_queue);
3569 gfar_write(rx_queue->rfbptr, (u32)bdp);
3572 priv->tx_actual_en = 1;
3575 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3576 priv->tx_actual_en = 0;
3578 gfar_write(®s->maccfg1, tempval1);
3579 gfar_write(®s->maccfg2, tempval);
3580 gfar_write(®s->ecntrl, ecntrl);
3585 } else if (priv->oldlink) {
3588 priv->oldduplex = -1;
3591 if (netif_msg_link(priv))
3592 phy_print_status(phydev);
3595 static const struct of_device_id gfar_match[] =
3599 .compatible = "gianfar",
3602 .compatible = "fsl,etsec2",
3606 MODULE_DEVICE_TABLE(of, gfar_match);
3608 /* Structure for a device driver */
3609 static struct platform_driver gfar_driver = {
3611 .name = "fsl-gianfar",
3613 .of_match_table = gfar_match,
3615 .probe = gfar_probe,
3616 .remove = gfar_remove,
3619 module_platform_driver(gfar_driver);