1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
81 #include <linux/of_mdio.h>
82 #include <linux/of_platform.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
87 #include <linux/net_tstamp.h>
92 #include <asm/uaccess.h>
93 #include <linux/module.h>
94 #include <linux/dma-mapping.h>
95 #include <linux/crc32.h>
96 #include <linux/mii.h>
97 #include <linux/phy.h>
98 #include <linux/phy_fixed.h>
100 #include <linux/of_net.h>
104 #define TX_TIMEOUT (1*HZ)
106 const char gfar_driver_version[] = "1.3";
108 static int gfar_enet_open(struct net_device *dev);
109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
110 static void gfar_reset_task(struct work_struct *work);
111 static void gfar_timeout(struct net_device *dev);
112 static int gfar_close(struct net_device *dev);
113 struct sk_buff *gfar_new_skb(struct net_device *dev);
114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
115 struct sk_buff *skb);
116 static int gfar_set_mac_address(struct net_device *dev);
117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
118 static irqreturn_t gfar_error(int irq, void *dev_id);
119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
121 static void adjust_link(struct net_device *dev);
122 static void init_registers(struct net_device *dev);
123 static int init_phy(struct net_device *dev);
124 static int gfar_probe(struct platform_device *ofdev);
125 static int gfar_remove(struct platform_device *ofdev);
126 static void free_skb_resources(struct gfar_private *priv);
127 static void gfar_set_multi(struct net_device *dev);
128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
129 static void gfar_configure_serdes(struct net_device *dev);
130 static int gfar_poll(struct napi_struct *napi, int budget);
131 #ifdef CONFIG_NET_POLL_CONTROLLER
132 static void gfar_netpoll(struct net_device *dev);
134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
136 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 int amount_pull, struct napi_struct *napi);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
157 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
158 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
159 lstatus |= BD_LFLAG(RXBD_WRAP);
163 bdp->lstatus = lstatus;
166 static int gfar_init_bds(struct net_device *ndev)
168 struct gfar_private *priv = netdev_priv(ndev);
169 struct gfar_priv_tx_q *tx_queue = NULL;
170 struct gfar_priv_rx_q *rx_queue = NULL;
175 for (i = 0; i < priv->num_tx_queues; i++) {
176 tx_queue = priv->tx_queue[i];
177 /* Initialize some variables in our dev structure */
178 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
179 tx_queue->dirty_tx = tx_queue->tx_bd_base;
180 tx_queue->cur_tx = tx_queue->tx_bd_base;
181 tx_queue->skb_curtx = 0;
182 tx_queue->skb_dirtytx = 0;
184 /* Initialize Transmit Descriptor Ring */
185 txbdp = tx_queue->tx_bd_base;
186 for (j = 0; j < tx_queue->tx_ring_size; j++) {
192 /* Set the last descriptor in the ring to indicate wrap */
194 txbdp->status |= TXBD_WRAP;
197 for (i = 0; i < priv->num_rx_queues; i++) {
198 rx_queue = priv->rx_queue[i];
199 rx_queue->cur_rx = rx_queue->rx_bd_base;
200 rx_queue->skb_currx = 0;
201 rxbdp = rx_queue->rx_bd_base;
203 for (j = 0; j < rx_queue->rx_ring_size; j++) {
204 struct sk_buff *skb = rx_queue->rx_skbuff[j];
207 gfar_init_rxbdp(rx_queue, rxbdp,
210 skb = gfar_new_skb(ndev);
212 netdev_err(ndev, "Can't allocate RX buffers\n");
215 rx_queue->rx_skbuff[j] = skb;
217 gfar_new_rxbdp(rx_queue, rxbdp, skb);
228 static int gfar_alloc_skb_resources(struct net_device *ndev)
233 struct gfar_private *priv = netdev_priv(ndev);
234 struct device *dev = &priv->ofdev->dev;
235 struct gfar_priv_tx_q *tx_queue = NULL;
236 struct gfar_priv_rx_q *rx_queue = NULL;
238 priv->total_tx_ring_size = 0;
239 for (i = 0; i < priv->num_tx_queues; i++)
240 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
242 priv->total_rx_ring_size = 0;
243 for (i = 0; i < priv->num_rx_queues; i++)
244 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
246 /* Allocate memory for the buffer descriptors */
247 vaddr = dma_alloc_coherent(dev,
248 sizeof(struct txbd8) * priv->total_tx_ring_size +
249 sizeof(struct rxbd8) * priv->total_rx_ring_size,
252 netif_err(priv, ifup, ndev,
253 "Could not allocate buffer descriptors!\n");
257 for (i = 0; i < priv->num_tx_queues; i++) {
258 tx_queue = priv->tx_queue[i];
259 tx_queue->tx_bd_base = vaddr;
260 tx_queue->tx_bd_dma_base = addr;
261 tx_queue->dev = ndev;
262 /* enet DMA only understands physical addresses */
263 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
264 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
267 /* Start the rx descriptor ring where the tx ring leaves off */
268 for (i = 0; i < priv->num_rx_queues; i++) {
269 rx_queue = priv->rx_queue[i];
270 rx_queue->rx_bd_base = vaddr;
271 rx_queue->rx_bd_dma_base = addr;
272 rx_queue->dev = ndev;
273 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
274 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
277 /* Setup the skbuff rings */
278 for (i = 0; i < priv->num_tx_queues; i++) {
279 tx_queue = priv->tx_queue[i];
280 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
281 tx_queue->tx_ring_size,
283 if (!tx_queue->tx_skbuff) {
284 netif_err(priv, ifup, ndev,
285 "Could not allocate tx_skbuff\n");
289 for (k = 0; k < tx_queue->tx_ring_size; k++)
290 tx_queue->tx_skbuff[k] = NULL;
293 for (i = 0; i < priv->num_rx_queues; i++) {
294 rx_queue = priv->rx_queue[i];
295 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
296 rx_queue->rx_ring_size,
299 if (!rx_queue->rx_skbuff) {
300 netif_err(priv, ifup, ndev,
301 "Could not allocate rx_skbuff\n");
305 for (j = 0; j < rx_queue->rx_ring_size; j++)
306 rx_queue->rx_skbuff[j] = NULL;
309 if (gfar_init_bds(ndev))
315 free_skb_resources(priv);
319 static void gfar_init_tx_rx_base(struct gfar_private *priv)
321 struct gfar __iomem *regs = priv->gfargrp[0].regs;
325 baddr = ®s->tbase0;
326 for (i = 0; i < priv->num_tx_queues; i++) {
327 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
331 baddr = ®s->rbase0;
332 for (i = 0; i < priv->num_rx_queues; i++) {
333 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
338 static void gfar_init_mac(struct net_device *ndev)
340 struct gfar_private *priv = netdev_priv(ndev);
341 struct gfar __iomem *regs = priv->gfargrp[0].regs;
346 /* write the tx/rx base registers */
347 gfar_init_tx_rx_base(priv);
349 /* Configure the coalescing support */
350 gfar_configure_coalescing(priv, 0xFF, 0xFF);
352 if (priv->rx_filer_enable) {
353 rctrl |= RCTRL_FILREN;
354 /* Program the RIR0 reg with the required distribution */
355 gfar_write(®s->rir0, DEFAULT_RIR0);
358 if (ndev->features & NETIF_F_RXCSUM)
359 rctrl |= RCTRL_CHECKSUMMING;
361 if (priv->extended_hash) {
362 rctrl |= RCTRL_EXTHASH;
364 gfar_clear_exact_match(ndev);
369 rctrl &= ~RCTRL_PAL_MASK;
370 rctrl |= RCTRL_PADDING(priv->padding);
373 /* Insert receive time stamps into padding alignment bytes */
374 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
375 rctrl &= ~RCTRL_PAL_MASK;
376 rctrl |= RCTRL_PADDING(8);
380 /* Enable HW time stamping if requested from user space */
381 if (priv->hwts_rx_en)
382 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
384 if (ndev->features & NETIF_F_HW_VLAN_RX)
385 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
387 /* Init rctrl based on our settings */
388 gfar_write(®s->rctrl, rctrl);
390 if (ndev->features & NETIF_F_IP_CSUM)
391 tctrl |= TCTRL_INIT_CSUM;
393 if (priv->prio_sched_en)
394 tctrl |= TCTRL_TXSCHED_PRIO;
396 tctrl |= TCTRL_TXSCHED_WRRS;
397 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
398 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
401 gfar_write(®s->tctrl, tctrl);
403 /* Set the extraction length and index */
404 attrs = ATTRELI_EL(priv->rx_stash_size) |
405 ATTRELI_EI(priv->rx_stash_index);
407 gfar_write(®s->attreli, attrs);
409 /* Start with defaults, and add stashing or locking
410 * depending on the approprate variables
412 attrs = ATTR_INIT_SETTINGS;
414 if (priv->bd_stash_en)
415 attrs |= ATTR_BDSTASH;
417 if (priv->rx_stash_size != 0)
418 attrs |= ATTR_BUFSTASH;
420 gfar_write(®s->attr, attrs);
422 gfar_write(®s->fifo_tx_thr, priv->fifo_threshold);
423 gfar_write(®s->fifo_tx_starve, priv->fifo_starve);
424 gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off);
427 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
429 struct gfar_private *priv = netdev_priv(dev);
430 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
431 unsigned long tx_packets = 0, tx_bytes = 0;
434 for (i = 0; i < priv->num_rx_queues; i++) {
435 rx_packets += priv->rx_queue[i]->stats.rx_packets;
436 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
437 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
440 dev->stats.rx_packets = rx_packets;
441 dev->stats.rx_bytes = rx_bytes;
442 dev->stats.rx_dropped = rx_dropped;
444 for (i = 0; i < priv->num_tx_queues; i++) {
445 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
446 tx_packets += priv->tx_queue[i]->stats.tx_packets;
449 dev->stats.tx_bytes = tx_bytes;
450 dev->stats.tx_packets = tx_packets;
455 static const struct net_device_ops gfar_netdev_ops = {
456 .ndo_open = gfar_enet_open,
457 .ndo_start_xmit = gfar_start_xmit,
458 .ndo_stop = gfar_close,
459 .ndo_change_mtu = gfar_change_mtu,
460 .ndo_set_features = gfar_set_features,
461 .ndo_set_rx_mode = gfar_set_multi,
462 .ndo_tx_timeout = gfar_timeout,
463 .ndo_do_ioctl = gfar_ioctl,
464 .ndo_get_stats = gfar_get_stats,
465 .ndo_set_mac_address = eth_mac_addr,
466 .ndo_validate_addr = eth_validate_addr,
467 #ifdef CONFIG_NET_POLL_CONTROLLER
468 .ndo_poll_controller = gfar_netpoll,
472 void lock_rx_qs(struct gfar_private *priv)
476 for (i = 0; i < priv->num_rx_queues; i++)
477 spin_lock(&priv->rx_queue[i]->rxlock);
480 void lock_tx_qs(struct gfar_private *priv)
484 for (i = 0; i < priv->num_tx_queues; i++)
485 spin_lock(&priv->tx_queue[i]->txlock);
488 void unlock_rx_qs(struct gfar_private *priv)
492 for (i = 0; i < priv->num_rx_queues; i++)
493 spin_unlock(&priv->rx_queue[i]->rxlock);
496 void unlock_tx_qs(struct gfar_private *priv)
500 for (i = 0; i < priv->num_tx_queues; i++)
501 spin_unlock(&priv->tx_queue[i]->txlock);
504 static bool gfar_is_vlan_on(struct gfar_private *priv)
506 return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
507 (priv->ndev->features & NETIF_F_HW_VLAN_TX);
510 /* Returns 1 if incoming frames use an FCB */
511 static inline int gfar_uses_fcb(struct gfar_private *priv)
513 return gfar_is_vlan_on(priv) ||
514 (priv->ndev->features & NETIF_F_RXCSUM) ||
515 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
518 static void free_tx_pointers(struct gfar_private *priv)
522 for (i = 0; i < priv->num_tx_queues; i++)
523 kfree(priv->tx_queue[i]);
526 static void free_rx_pointers(struct gfar_private *priv)
530 for (i = 0; i < priv->num_rx_queues; i++)
531 kfree(priv->rx_queue[i]);
534 static void unmap_group_regs(struct gfar_private *priv)
538 for (i = 0; i < MAXGROUPS; i++)
539 if (priv->gfargrp[i].regs)
540 iounmap(priv->gfargrp[i].regs);
543 static void disable_napi(struct gfar_private *priv)
547 for (i = 0; i < priv->num_grps; i++)
548 napi_disable(&priv->gfargrp[i].napi);
551 static void enable_napi(struct gfar_private *priv)
555 for (i = 0; i < priv->num_grps; i++)
556 napi_enable(&priv->gfargrp[i].napi);
559 static int gfar_parse_group(struct device_node *np,
560 struct gfar_private *priv, const char *model)
564 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
565 if (!priv->gfargrp[priv->num_grps].regs)
568 priv->gfargrp[priv->num_grps].interruptTransmit =
569 irq_of_parse_and_map(np, 0);
571 /* If we aren't the FEC we have multiple interrupts */
572 if (model && strcasecmp(model, "FEC")) {
573 priv->gfargrp[priv->num_grps].interruptReceive =
574 irq_of_parse_and_map(np, 1);
575 priv->gfargrp[priv->num_grps].interruptError =
576 irq_of_parse_and_map(np,2);
577 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
578 priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ ||
579 priv->gfargrp[priv->num_grps].interruptError == NO_IRQ)
583 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
584 priv->gfargrp[priv->num_grps].priv = priv;
585 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
586 if (priv->mode == MQ_MG_MODE) {
587 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
588 priv->gfargrp[priv->num_grps].rx_bit_map = queue_mask ?
589 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
590 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
591 priv->gfargrp[priv->num_grps].tx_bit_map = queue_mask ?
592 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
594 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
595 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
602 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
606 const void *mac_addr;
608 struct net_device *dev = NULL;
609 struct gfar_private *priv = NULL;
610 struct device_node *np = ofdev->dev.of_node;
611 struct device_node *child = NULL;
613 const u32 *stash_len;
614 const u32 *stash_idx;
615 unsigned int num_tx_qs, num_rx_qs;
616 u32 *tx_queues, *rx_queues;
618 if (!np || !of_device_is_available(np))
621 /* parse the num of tx and rx queues */
622 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
623 num_tx_qs = tx_queues ? *tx_queues : 1;
625 if (num_tx_qs > MAX_TX_QS) {
626 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
627 num_tx_qs, MAX_TX_QS);
628 pr_err("Cannot do alloc_etherdev, aborting\n");
632 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
633 num_rx_qs = rx_queues ? *rx_queues : 1;
635 if (num_rx_qs > MAX_RX_QS) {
636 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
637 num_rx_qs, MAX_RX_QS);
638 pr_err("Cannot do alloc_etherdev, aborting\n");
642 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
647 priv = netdev_priv(dev);
648 priv->node = ofdev->dev.of_node;
651 priv->num_tx_queues = num_tx_qs;
652 netif_set_real_num_rx_queues(dev, num_rx_qs);
653 priv->num_rx_queues = num_rx_qs;
654 priv->num_grps = 0x0;
656 /* Init Rx queue filer rule set linked list */
657 INIT_LIST_HEAD(&priv->rx_list.list);
658 priv->rx_list.count = 0;
659 mutex_init(&priv->rx_queue_access);
661 model = of_get_property(np, "model", NULL);
663 for (i = 0; i < MAXGROUPS; i++)
664 priv->gfargrp[i].regs = NULL;
666 /* Parse and initialize group specific information */
667 if (of_device_is_compatible(np, "fsl,etsec2")) {
668 priv->mode = MQ_MG_MODE;
669 for_each_child_of_node(np, child) {
670 err = gfar_parse_group(child, priv, model);
675 priv->mode = SQ_SG_MODE;
676 err = gfar_parse_group(np, priv, model);
681 for (i = 0; i < priv->num_tx_queues; i++)
682 priv->tx_queue[i] = NULL;
683 for (i = 0; i < priv->num_rx_queues; i++)
684 priv->rx_queue[i] = NULL;
686 for (i = 0; i < priv->num_tx_queues; i++) {
687 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
689 if (!priv->tx_queue[i]) {
691 goto tx_alloc_failed;
693 priv->tx_queue[i]->tx_skbuff = NULL;
694 priv->tx_queue[i]->qindex = i;
695 priv->tx_queue[i]->dev = dev;
696 spin_lock_init(&(priv->tx_queue[i]->txlock));
699 for (i = 0; i < priv->num_rx_queues; i++) {
700 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
702 if (!priv->rx_queue[i]) {
704 goto rx_alloc_failed;
706 priv->rx_queue[i]->rx_skbuff = NULL;
707 priv->rx_queue[i]->qindex = i;
708 priv->rx_queue[i]->dev = dev;
709 spin_lock_init(&(priv->rx_queue[i]->rxlock));
713 stash = of_get_property(np, "bd-stash", NULL);
716 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
717 priv->bd_stash_en = 1;
720 stash_len = of_get_property(np, "rx-stash-len", NULL);
723 priv->rx_stash_size = *stash_len;
725 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
728 priv->rx_stash_index = *stash_idx;
730 if (stash_len || stash_idx)
731 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
733 mac_addr = of_get_mac_address(np);
736 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
738 if (model && !strcasecmp(model, "TSEC"))
739 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
740 FSL_GIANFAR_DEV_HAS_COALESCE |
741 FSL_GIANFAR_DEV_HAS_RMON |
742 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
744 if (model && !strcasecmp(model, "eTSEC"))
745 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
746 FSL_GIANFAR_DEV_HAS_COALESCE |
747 FSL_GIANFAR_DEV_HAS_RMON |
748 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
749 FSL_GIANFAR_DEV_HAS_PADDING |
750 FSL_GIANFAR_DEV_HAS_CSUM |
751 FSL_GIANFAR_DEV_HAS_VLAN |
752 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
753 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
754 FSL_GIANFAR_DEV_HAS_TIMER;
756 ctype = of_get_property(np, "phy-connection-type", NULL);
758 /* We only care about rgmii-id. The rest are autodetected */
759 if (ctype && !strcmp(ctype, "rgmii-id"))
760 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
762 priv->interface = PHY_INTERFACE_MODE_MII;
764 if (of_get_property(np, "fsl,magic-packet", NULL))
765 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
767 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
769 /* Find the TBI PHY. If it's not there, we don't support SGMII */
770 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
775 free_rx_pointers(priv);
777 free_tx_pointers(priv);
779 unmap_group_regs(priv);
784 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
785 struct ifreq *ifr, int cmd)
787 struct hwtstamp_config config;
788 struct gfar_private *priv = netdev_priv(netdev);
790 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
793 /* reserved for future extensions */
797 switch (config.tx_type) {
798 case HWTSTAMP_TX_OFF:
799 priv->hwts_tx_en = 0;
802 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
804 priv->hwts_tx_en = 1;
810 switch (config.rx_filter) {
811 case HWTSTAMP_FILTER_NONE:
812 if (priv->hwts_rx_en) {
814 priv->hwts_rx_en = 0;
815 startup_gfar(netdev);
819 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
821 if (!priv->hwts_rx_en) {
823 priv->hwts_rx_en = 1;
824 startup_gfar(netdev);
826 config.rx_filter = HWTSTAMP_FILTER_ALL;
830 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
834 /* Ioctl MII Interface */
835 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
837 struct gfar_private *priv = netdev_priv(dev);
839 if (!netif_running(dev))
842 if (cmd == SIOCSHWTSTAMP)
843 return gfar_hwtstamp_ioctl(dev, rq, cmd);
848 return phy_mii_ioctl(priv->phydev, rq, cmd);
851 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
853 unsigned int new_bit_map = 0x0;
854 int mask = 0x1 << (max_qs - 1), i;
856 for (i = 0; i < max_qs; i++) {
858 new_bit_map = new_bit_map + (1 << i);
864 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
867 u32 rqfpr = FPR_FILER_MASK;
871 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
872 priv->ftp_rqfpr[rqfar] = rqfpr;
873 priv->ftp_rqfcr[rqfar] = rqfcr;
874 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
877 rqfcr = RQFCR_CMP_NOMATCH;
878 priv->ftp_rqfpr[rqfar] = rqfpr;
879 priv->ftp_rqfcr[rqfar] = rqfcr;
880 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
883 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
885 priv->ftp_rqfcr[rqfar] = rqfcr;
886 priv->ftp_rqfpr[rqfar] = rqfpr;
887 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
890 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
892 priv->ftp_rqfcr[rqfar] = rqfcr;
893 priv->ftp_rqfpr[rqfar] = rqfpr;
894 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
899 static void gfar_init_filer_table(struct gfar_private *priv)
902 u32 rqfar = MAX_FILER_IDX;
904 u32 rqfpr = FPR_FILER_MASK;
907 rqfcr = RQFCR_CMP_MATCH;
908 priv->ftp_rqfcr[rqfar] = rqfcr;
909 priv->ftp_rqfpr[rqfar] = rqfpr;
910 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
912 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
913 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
914 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
915 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
916 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
917 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
919 /* cur_filer_idx indicated the first non-masked rule */
920 priv->cur_filer_idx = rqfar;
922 /* Rest are masked rules */
923 rqfcr = RQFCR_CMP_NOMATCH;
924 for (i = 0; i < rqfar; i++) {
925 priv->ftp_rqfcr[i] = rqfcr;
926 priv->ftp_rqfpr[i] = rqfpr;
927 gfar_write_filer(priv, i, rqfcr, rqfpr);
931 static void gfar_detect_errata(struct gfar_private *priv)
933 struct device *dev = &priv->ofdev->dev;
934 unsigned int pvr = mfspr(SPRN_PVR);
935 unsigned int svr = mfspr(SPRN_SVR);
936 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
937 unsigned int rev = svr & 0xffff;
939 /* MPC8313 Rev 2.0 and higher; All MPC837x */
940 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
941 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
942 priv->errata |= GFAR_ERRATA_74;
944 /* MPC8313 and MPC837x all rev */
945 if ((pvr == 0x80850010 && mod == 0x80b0) ||
946 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
947 priv->errata |= GFAR_ERRATA_76;
949 /* MPC8313 and MPC837x all rev */
950 if ((pvr == 0x80850010 && mod == 0x80b0) ||
951 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
952 priv->errata |= GFAR_ERRATA_A002;
954 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
955 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
956 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
957 priv->errata |= GFAR_ERRATA_12;
960 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
964 /* Set up the ethernet device structure, private data,
965 * and anything else we need before we start
967 static int gfar_probe(struct platform_device *ofdev)
970 struct net_device *dev = NULL;
971 struct gfar_private *priv = NULL;
972 struct gfar __iomem *regs = NULL;
973 int err = 0, i, grp_idx = 0;
974 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
978 err = gfar_of_init(ofdev, &dev);
983 priv = netdev_priv(dev);
986 priv->node = ofdev->dev.of_node;
987 SET_NETDEV_DEV(dev, &ofdev->dev);
989 spin_lock_init(&priv->bflock);
990 INIT_WORK(&priv->reset_task, gfar_reset_task);
992 dev_set_drvdata(&ofdev->dev, priv);
993 regs = priv->gfargrp[0].regs;
995 gfar_detect_errata(priv);
997 /* Stop the DMA engine now, in case it was running before
998 * (The firmware could have used it, and left it running).
1002 /* Reset MAC layer */
1003 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1005 /* We need to delay at least 3 TX clocks */
1008 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1009 gfar_write(®s->maccfg1, tempval);
1011 /* Initialize MACCFG2. */
1012 tempval = MACCFG2_INIT_SETTINGS;
1013 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1014 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1015 gfar_write(®s->maccfg2, tempval);
1017 /* Initialize ECNTRL */
1018 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1020 /* Set the dev->base_addr to the gfar reg region */
1021 dev->base_addr = (unsigned long) regs;
1023 SET_NETDEV_DEV(dev, &ofdev->dev);
1025 /* Fill in the dev structure */
1026 dev->watchdog_timeo = TX_TIMEOUT;
1028 dev->netdev_ops = &gfar_netdev_ops;
1029 dev->ethtool_ops = &gfar_ethtool_ops;
1031 /* Register for napi ...We are registering NAPI for each grp */
1032 for (i = 0; i < priv->num_grps; i++)
1033 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1036 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1037 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1039 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1040 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1043 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1044 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1045 dev->features |= NETIF_F_HW_VLAN_RX;
1048 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1049 priv->extended_hash = 1;
1050 priv->hash_width = 9;
1052 priv->hash_regs[0] = ®s->igaddr0;
1053 priv->hash_regs[1] = ®s->igaddr1;
1054 priv->hash_regs[2] = ®s->igaddr2;
1055 priv->hash_regs[3] = ®s->igaddr3;
1056 priv->hash_regs[4] = ®s->igaddr4;
1057 priv->hash_regs[5] = ®s->igaddr5;
1058 priv->hash_regs[6] = ®s->igaddr6;
1059 priv->hash_regs[7] = ®s->igaddr7;
1060 priv->hash_regs[8] = ®s->gaddr0;
1061 priv->hash_regs[9] = ®s->gaddr1;
1062 priv->hash_regs[10] = ®s->gaddr2;
1063 priv->hash_regs[11] = ®s->gaddr3;
1064 priv->hash_regs[12] = ®s->gaddr4;
1065 priv->hash_regs[13] = ®s->gaddr5;
1066 priv->hash_regs[14] = ®s->gaddr6;
1067 priv->hash_regs[15] = ®s->gaddr7;
1070 priv->extended_hash = 0;
1071 priv->hash_width = 8;
1073 priv->hash_regs[0] = ®s->gaddr0;
1074 priv->hash_regs[1] = ®s->gaddr1;
1075 priv->hash_regs[2] = ®s->gaddr2;
1076 priv->hash_regs[3] = ®s->gaddr3;
1077 priv->hash_regs[4] = ®s->gaddr4;
1078 priv->hash_regs[5] = ®s->gaddr5;
1079 priv->hash_regs[6] = ®s->gaddr6;
1080 priv->hash_regs[7] = ®s->gaddr7;
1083 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1084 priv->padding = DEFAULT_PADDING;
1088 if (dev->features & NETIF_F_IP_CSUM ||
1089 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1090 dev->needed_headroom = GMAC_FCB_LEN;
1092 /* Program the isrg regs only if number of grps > 1 */
1093 if (priv->num_grps > 1) {
1094 baddr = ®s->isrg0;
1095 for (i = 0; i < priv->num_grps; i++) {
1096 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1097 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1098 gfar_write(baddr, isrg);
1104 /* Need to reverse the bit maps as bit_map's MSB is q0
1105 * but, for_each_set_bit parses from right to left, which
1106 * basically reverses the queue numbers
1108 for (i = 0; i< priv->num_grps; i++) {
1109 priv->gfargrp[i].tx_bit_map =
1110 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1111 priv->gfargrp[i].rx_bit_map =
1112 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1115 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1116 * also assign queues to groups
1118 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1119 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1121 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1122 priv->num_rx_queues) {
1123 priv->gfargrp[grp_idx].num_rx_queues++;
1124 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1125 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1126 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1128 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1130 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1131 priv->num_tx_queues) {
1132 priv->gfargrp[grp_idx].num_tx_queues++;
1133 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1134 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1135 tqueue = tqueue | (TQUEUE_EN0 >> i);
1137 priv->gfargrp[grp_idx].rstat = rstat;
1138 priv->gfargrp[grp_idx].tstat = tstat;
1142 gfar_write(®s->rqueue, rqueue);
1143 gfar_write(®s->tqueue, tqueue);
1145 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1147 /* Initializing some of the rx/tx queue level parameters */
1148 for (i = 0; i < priv->num_tx_queues; i++) {
1149 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1150 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1151 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1152 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1155 for (i = 0; i < priv->num_rx_queues; i++) {
1156 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1157 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1158 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1161 /* always enable rx filer */
1162 priv->rx_filer_enable = 1;
1163 /* Enable most messages by default */
1164 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1165 /* use pritority h/w tx queue scheduling for single queue devices */
1166 if (priv->num_tx_queues == 1)
1167 priv->prio_sched_en = 1;
1169 /* Carrier starts down, phylib will bring it up */
1170 netif_carrier_off(dev);
1172 err = register_netdev(dev);
1175 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1179 device_init_wakeup(&dev->dev,
1180 priv->device_flags &
1181 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1183 /* fill out IRQ number and name fields */
1184 for (i = 0; i < priv->num_grps; i++) {
1185 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1186 sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s",
1187 dev->name, "_g", '0' + i, "_tx");
1188 sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s",
1189 dev->name, "_g", '0' + i, "_rx");
1190 sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s",
1191 dev->name, "_g", '0' + i, "_er");
1193 strcpy(priv->gfargrp[i].int_name_tx, dev->name);
1196 /* Initialize the filer table */
1197 gfar_init_filer_table(priv);
1199 /* Create all the sysfs files */
1200 gfar_init_sysfs(dev);
1202 /* Print out the device info */
1203 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1205 /* Even more device info helps when determining which kernel
1206 * provided which set of benchmarks.
1208 netdev_info(dev, "Running with NAPI enabled\n");
1209 for (i = 0; i < priv->num_rx_queues; i++)
1210 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1211 i, priv->rx_queue[i]->rx_ring_size);
1212 for (i = 0; i < priv->num_tx_queues; i++)
1213 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1214 i, priv->tx_queue[i]->tx_ring_size);
1219 unmap_group_regs(priv);
1220 free_tx_pointers(priv);
1221 free_rx_pointers(priv);
1223 of_node_put(priv->phy_node);
1225 of_node_put(priv->tbi_node);
1230 static int gfar_remove(struct platform_device *ofdev)
1232 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1235 of_node_put(priv->phy_node);
1237 of_node_put(priv->tbi_node);
1239 dev_set_drvdata(&ofdev->dev, NULL);
1241 unregister_netdev(priv->ndev);
1242 unmap_group_regs(priv);
1243 free_netdev(priv->ndev);
1250 static int gfar_suspend(struct device *dev)
1252 struct gfar_private *priv = dev_get_drvdata(dev);
1253 struct net_device *ndev = priv->ndev;
1254 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1255 unsigned long flags;
1258 int magic_packet = priv->wol_en &&
1259 (priv->device_flags &
1260 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1262 netif_device_detach(ndev);
1264 if (netif_running(ndev)) {
1266 local_irq_save(flags);
1270 gfar_halt_nodisable(ndev);
1272 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1273 tempval = gfar_read(®s->maccfg1);
1275 tempval &= ~MACCFG1_TX_EN;
1278 tempval &= ~MACCFG1_RX_EN;
1280 gfar_write(®s->maccfg1, tempval);
1284 local_irq_restore(flags);
1289 /* Enable interrupt on Magic Packet */
1290 gfar_write(®s->imask, IMASK_MAG);
1292 /* Enable Magic Packet mode */
1293 tempval = gfar_read(®s->maccfg2);
1294 tempval |= MACCFG2_MPEN;
1295 gfar_write(®s->maccfg2, tempval);
1297 phy_stop(priv->phydev);
1304 static int gfar_resume(struct device *dev)
1306 struct gfar_private *priv = dev_get_drvdata(dev);
1307 struct net_device *ndev = priv->ndev;
1308 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1309 unsigned long flags;
1311 int magic_packet = priv->wol_en &&
1312 (priv->device_flags &
1313 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1315 if (!netif_running(ndev)) {
1316 netif_device_attach(ndev);
1320 if (!magic_packet && priv->phydev)
1321 phy_start(priv->phydev);
1323 /* Disable Magic Packet mode, in case something
1326 local_irq_save(flags);
1330 tempval = gfar_read(®s->maccfg2);
1331 tempval &= ~MACCFG2_MPEN;
1332 gfar_write(®s->maccfg2, tempval);
1338 local_irq_restore(flags);
1340 netif_device_attach(ndev);
1347 static int gfar_restore(struct device *dev)
1349 struct gfar_private *priv = dev_get_drvdata(dev);
1350 struct net_device *ndev = priv->ndev;
1352 if (!netif_running(ndev)) {
1353 netif_device_attach(ndev);
1358 if (gfar_init_bds(ndev)) {
1359 free_skb_resources(priv);
1363 init_registers(ndev);
1364 gfar_set_mac_address(ndev);
1365 gfar_init_mac(ndev);
1370 priv->oldduplex = -1;
1373 phy_start(priv->phydev);
1375 netif_device_attach(ndev);
1381 static struct dev_pm_ops gfar_pm_ops = {
1382 .suspend = gfar_suspend,
1383 .resume = gfar_resume,
1384 .freeze = gfar_suspend,
1385 .thaw = gfar_resume,
1386 .restore = gfar_restore,
1389 #define GFAR_PM_OPS (&gfar_pm_ops)
1393 #define GFAR_PM_OPS NULL
1397 /* Reads the controller's registers to determine what interface
1398 * connects it to the PHY.
1400 static phy_interface_t gfar_get_interface(struct net_device *dev)
1402 struct gfar_private *priv = netdev_priv(dev);
1403 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1406 ecntrl = gfar_read(®s->ecntrl);
1408 if (ecntrl & ECNTRL_SGMII_MODE)
1409 return PHY_INTERFACE_MODE_SGMII;
1411 if (ecntrl & ECNTRL_TBI_MODE) {
1412 if (ecntrl & ECNTRL_REDUCED_MODE)
1413 return PHY_INTERFACE_MODE_RTBI;
1415 return PHY_INTERFACE_MODE_TBI;
1418 if (ecntrl & ECNTRL_REDUCED_MODE) {
1419 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1420 return PHY_INTERFACE_MODE_RMII;
1423 phy_interface_t interface = priv->interface;
1425 /* This isn't autodetected right now, so it must
1426 * be set by the device tree or platform code.
1428 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1429 return PHY_INTERFACE_MODE_RGMII_ID;
1431 return PHY_INTERFACE_MODE_RGMII;
1435 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1436 return PHY_INTERFACE_MODE_GMII;
1438 return PHY_INTERFACE_MODE_MII;
1442 /* Initializes driver's PHY state, and attaches to the PHY.
1443 * Returns 0 on success.
1445 static int init_phy(struct net_device *dev)
1447 struct gfar_private *priv = netdev_priv(dev);
1448 uint gigabit_support =
1449 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1450 SUPPORTED_1000baseT_Full : 0;
1451 phy_interface_t interface;
1455 priv->oldduplex = -1;
1457 interface = gfar_get_interface(dev);
1459 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1462 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1464 if (!priv->phydev) {
1465 dev_err(&dev->dev, "could not attach to PHY\n");
1469 if (interface == PHY_INTERFACE_MODE_SGMII)
1470 gfar_configure_serdes(dev);
1472 /* Remove any features not supported by the controller */
1473 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1474 priv->phydev->advertising = priv->phydev->supported;
1479 /* Initialize TBI PHY interface for communicating with the
1480 * SERDES lynx PHY on the chip. We communicate with this PHY
1481 * through the MDIO bus on each controller, treating it as a
1482 * "normal" PHY at the address found in the TBIPA register. We assume
1483 * that the TBIPA register is valid. Either the MDIO bus code will set
1484 * it to a value that doesn't conflict with other PHYs on the bus, or the
1485 * value doesn't matter, as there are no other PHYs on the bus.
1487 static void gfar_configure_serdes(struct net_device *dev)
1489 struct gfar_private *priv = netdev_priv(dev);
1490 struct phy_device *tbiphy;
1492 if (!priv->tbi_node) {
1493 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1494 "device tree specify a tbi-handle\n");
1498 tbiphy = of_phy_find_device(priv->tbi_node);
1500 dev_err(&dev->dev, "error: Could not get TBI device\n");
1504 /* If the link is already up, we must already be ok, and don't need to
1505 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1506 * everything for us? Resetting it takes the link down and requires
1507 * several seconds for it to come back.
1509 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1512 /* Single clk mode, mii mode off(for serdes communication) */
1513 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1515 phy_write(tbiphy, MII_ADVERTISE,
1516 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1517 ADVERTISE_1000XPSE_ASYM);
1519 phy_write(tbiphy, MII_BMCR,
1520 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1524 static void init_registers(struct net_device *dev)
1526 struct gfar_private *priv = netdev_priv(dev);
1527 struct gfar __iomem *regs = NULL;
1530 for (i = 0; i < priv->num_grps; i++) {
1531 regs = priv->gfargrp[i].regs;
1533 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1535 /* Initialize IMASK */
1536 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1539 regs = priv->gfargrp[0].regs;
1540 /* Init hash registers to zero */
1541 gfar_write(®s->igaddr0, 0);
1542 gfar_write(®s->igaddr1, 0);
1543 gfar_write(®s->igaddr2, 0);
1544 gfar_write(®s->igaddr3, 0);
1545 gfar_write(®s->igaddr4, 0);
1546 gfar_write(®s->igaddr5, 0);
1547 gfar_write(®s->igaddr6, 0);
1548 gfar_write(®s->igaddr7, 0);
1550 gfar_write(®s->gaddr0, 0);
1551 gfar_write(®s->gaddr1, 0);
1552 gfar_write(®s->gaddr2, 0);
1553 gfar_write(®s->gaddr3, 0);
1554 gfar_write(®s->gaddr4, 0);
1555 gfar_write(®s->gaddr5, 0);
1556 gfar_write(®s->gaddr6, 0);
1557 gfar_write(®s->gaddr7, 0);
1559 /* Zero out the rmon mib registers if it has them */
1560 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1561 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1563 /* Mask off the CAM interrupts */
1564 gfar_write(®s->rmon.cam1, 0xffffffff);
1565 gfar_write(®s->rmon.cam2, 0xffffffff);
1568 /* Initialize the max receive buffer length */
1569 gfar_write(®s->mrblr, priv->rx_buffer_size);
1571 /* Initialize the Minimum Frame Length Register */
1572 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1575 static int __gfar_is_rx_idle(struct gfar_private *priv)
1579 /* Normaly TSEC should not hang on GRS commands, so we should
1580 * actually wait for IEVENT_GRSC flag.
1582 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1585 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1586 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1587 * and the Rx can be safely reset.
1589 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1591 if ((res & 0xffff) == (res >> 16))
1597 /* Halt the receive and transmit queues */
1598 static void gfar_halt_nodisable(struct net_device *dev)
1600 struct gfar_private *priv = netdev_priv(dev);
1601 struct gfar __iomem *regs = NULL;
1605 for (i = 0; i < priv->num_grps; i++) {
1606 regs = priv->gfargrp[i].regs;
1607 /* Mask all interrupts */
1608 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1610 /* Clear all interrupts */
1611 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1614 regs = priv->gfargrp[0].regs;
1615 /* Stop the DMA, and wait for it to stop */
1616 tempval = gfar_read(®s->dmactrl);
1617 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1618 (DMACTRL_GRS | DMACTRL_GTS)) {
1621 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1622 gfar_write(®s->dmactrl, tempval);
1625 ret = spin_event_timeout(((gfar_read(®s->ievent) &
1626 (IEVENT_GRSC | IEVENT_GTSC)) ==
1627 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1628 if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC))
1629 ret = __gfar_is_rx_idle(priv);
1634 /* Halt the receive and transmit queues */
1635 void gfar_halt(struct net_device *dev)
1637 struct gfar_private *priv = netdev_priv(dev);
1638 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1641 gfar_halt_nodisable(dev);
1643 /* Disable Rx and Tx */
1644 tempval = gfar_read(®s->maccfg1);
1645 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1646 gfar_write(®s->maccfg1, tempval);
1649 static void free_grp_irqs(struct gfar_priv_grp *grp)
1651 free_irq(grp->interruptError, grp);
1652 free_irq(grp->interruptTransmit, grp);
1653 free_irq(grp->interruptReceive, grp);
1656 void stop_gfar(struct net_device *dev)
1658 struct gfar_private *priv = netdev_priv(dev);
1659 unsigned long flags;
1662 phy_stop(priv->phydev);
1666 local_irq_save(flags);
1674 local_irq_restore(flags);
1677 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1678 for (i = 0; i < priv->num_grps; i++)
1679 free_grp_irqs(&priv->gfargrp[i]);
1681 for (i = 0; i < priv->num_grps; i++)
1682 free_irq(priv->gfargrp[i].interruptTransmit,
1686 free_skb_resources(priv);
1689 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1691 struct txbd8 *txbdp;
1692 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1695 txbdp = tx_queue->tx_bd_base;
1697 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1698 if (!tx_queue->tx_skbuff[i])
1701 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1702 txbdp->length, DMA_TO_DEVICE);
1704 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1707 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1708 txbdp->length, DMA_TO_DEVICE);
1711 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1712 tx_queue->tx_skbuff[i] = NULL;
1714 kfree(tx_queue->tx_skbuff);
1715 tx_queue->tx_skbuff = NULL;
1718 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1720 struct rxbd8 *rxbdp;
1721 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1724 rxbdp = rx_queue->rx_bd_base;
1726 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1727 if (rx_queue->rx_skbuff[i]) {
1728 dma_unmap_single(&priv->ofdev->dev,
1729 rxbdp->bufPtr, priv->rx_buffer_size,
1731 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1732 rx_queue->rx_skbuff[i] = NULL;
1738 kfree(rx_queue->rx_skbuff);
1739 rx_queue->rx_skbuff = NULL;
1742 /* If there are any tx skbs or rx skbs still around, free them.
1743 * Then free tx_skbuff and rx_skbuff
1745 static void free_skb_resources(struct gfar_private *priv)
1747 struct gfar_priv_tx_q *tx_queue = NULL;
1748 struct gfar_priv_rx_q *rx_queue = NULL;
1751 /* Go through all the buffer descriptors and free their data buffers */
1752 for (i = 0; i < priv->num_tx_queues; i++) {
1753 struct netdev_queue *txq;
1755 tx_queue = priv->tx_queue[i];
1756 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1757 if (tx_queue->tx_skbuff)
1758 free_skb_tx_queue(tx_queue);
1759 netdev_tx_reset_queue(txq);
1762 for (i = 0; i < priv->num_rx_queues; i++) {
1763 rx_queue = priv->rx_queue[i];
1764 if (rx_queue->rx_skbuff)
1765 free_skb_rx_queue(rx_queue);
1768 dma_free_coherent(&priv->ofdev->dev,
1769 sizeof(struct txbd8) * priv->total_tx_ring_size +
1770 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1771 priv->tx_queue[0]->tx_bd_base,
1772 priv->tx_queue[0]->tx_bd_dma_base);
1775 void gfar_start(struct net_device *dev)
1777 struct gfar_private *priv = netdev_priv(dev);
1778 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1782 /* Enable Rx and Tx in MACCFG1 */
1783 tempval = gfar_read(®s->maccfg1);
1784 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1785 gfar_write(®s->maccfg1, tempval);
1787 /* Initialize DMACTRL to have WWR and WOP */
1788 tempval = gfar_read(®s->dmactrl);
1789 tempval |= DMACTRL_INIT_SETTINGS;
1790 gfar_write(®s->dmactrl, tempval);
1792 /* Make sure we aren't stopped */
1793 tempval = gfar_read(®s->dmactrl);
1794 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1795 gfar_write(®s->dmactrl, tempval);
1797 for (i = 0; i < priv->num_grps; i++) {
1798 regs = priv->gfargrp[i].regs;
1799 /* Clear THLT/RHLT, so that the DMA starts polling now */
1800 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1801 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1802 /* Unmask the interrupts we look for */
1803 gfar_write(®s->imask, IMASK_DEFAULT);
1806 dev->trans_start = jiffies; /* prevent tx timeout */
1809 void gfar_configure_coalescing(struct gfar_private *priv,
1810 unsigned long tx_mask, unsigned long rx_mask)
1812 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1816 /* Backward compatible case ---- even if we enable
1817 * multiple queues, there's only single reg to program
1819 gfar_write(®s->txic, 0);
1820 if (likely(priv->tx_queue[0]->txcoalescing))
1821 gfar_write(®s->txic, priv->tx_queue[0]->txic);
1823 gfar_write(®s->rxic, 0);
1824 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1825 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
1827 if (priv->mode == MQ_MG_MODE) {
1828 baddr = ®s->txic0;
1829 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1830 gfar_write(baddr + i, 0);
1831 if (likely(priv->tx_queue[i]->txcoalescing))
1832 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1835 baddr = ®s->rxic0;
1836 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1837 gfar_write(baddr + i, 0);
1838 if (likely(priv->rx_queue[i]->rxcoalescing))
1839 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1844 static int register_grp_irqs(struct gfar_priv_grp *grp)
1846 struct gfar_private *priv = grp->priv;
1847 struct net_device *dev = priv->ndev;
1850 /* If the device has multiple interrupts, register for
1851 * them. Otherwise, only register for the one
1853 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1854 /* Install our interrupt handlers for Error,
1855 * Transmit, and Receive
1857 if ((err = request_irq(grp->interruptError, gfar_error,
1858 0, grp->int_name_er, grp)) < 0) {
1859 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1860 grp->interruptError);
1865 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1866 0, grp->int_name_tx, grp)) < 0) {
1867 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1868 grp->interruptTransmit);
1872 if ((err = request_irq(grp->interruptReceive, gfar_receive,
1873 0, grp->int_name_rx, grp)) < 0) {
1874 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1875 grp->interruptReceive);
1879 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt,
1880 0, grp->int_name_tx, grp)) < 0) {
1881 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1882 grp->interruptTransmit);
1890 free_irq(grp->interruptTransmit, grp);
1892 free_irq(grp->interruptError, grp);
1898 /* Bring the controller up and running */
1899 int startup_gfar(struct net_device *ndev)
1901 struct gfar_private *priv = netdev_priv(ndev);
1902 struct gfar __iomem *regs = NULL;
1905 for (i = 0; i < priv->num_grps; i++) {
1906 regs= priv->gfargrp[i].regs;
1907 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1910 regs= priv->gfargrp[0].regs;
1911 err = gfar_alloc_skb_resources(ndev);
1915 gfar_init_mac(ndev);
1917 for (i = 0; i < priv->num_grps; i++) {
1918 err = register_grp_irqs(&priv->gfargrp[i]);
1920 for (j = 0; j < i; j++)
1921 free_grp_irqs(&priv->gfargrp[j]);
1926 /* Start the controller */
1929 phy_start(priv->phydev);
1931 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1936 free_skb_resources(priv);
1940 /* Called when something needs to use the ethernet device
1941 * Returns 0 for success.
1943 static int gfar_enet_open(struct net_device *dev)
1945 struct gfar_private *priv = netdev_priv(dev);
1950 /* Initialize a bunch of registers */
1951 init_registers(dev);
1953 gfar_set_mac_address(dev);
1955 err = init_phy(dev);
1962 err = startup_gfar(dev);
1968 netif_tx_start_all_queues(dev);
1970 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1975 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1977 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1979 memset(fcb, 0, GMAC_FCB_LEN);
1984 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1987 /* If we're here, it's a IP packet with a TCP or UDP
1988 * payload. We set it to checksum, using a pseudo-header
1991 u8 flags = TXFCB_DEFAULT;
1993 /* Tell the controller what the protocol is
1994 * And provide the already calculated phcs
1996 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1998 fcb->phcs = udp_hdr(skb)->check;
2000 fcb->phcs = tcp_hdr(skb)->check;
2002 /* l3os is the distance between the start of the
2003 * frame (skb->data) and the start of the IP hdr.
2004 * l4os is the distance between the start of the
2005 * l3 hdr and the l4 hdr
2007 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2008 fcb->l4os = skb_network_header_len(skb);
2013 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2015 fcb->flags |= TXFCB_VLN;
2016 fcb->vlctl = vlan_tx_tag_get(skb);
2019 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2020 struct txbd8 *base, int ring_size)
2022 struct txbd8 *new_bd = bdp + stride;
2024 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2027 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2030 return skip_txbd(bdp, 1, base, ring_size);
2033 /* This is called by the kernel when a frame is ready for transmission.
2034 * It is pointed to by the dev->hard_start_xmit function pointer
2036 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2038 struct gfar_private *priv = netdev_priv(dev);
2039 struct gfar_priv_tx_q *tx_queue = NULL;
2040 struct netdev_queue *txq;
2041 struct gfar __iomem *regs = NULL;
2042 struct txfcb *fcb = NULL;
2043 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2045 int i, rq = 0, do_tstamp = 0;
2047 unsigned long flags;
2048 unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2050 /* TOE=1 frames larger than 2500 bytes may see excess delays
2051 * before start of transmission.
2053 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2054 skb->ip_summed == CHECKSUM_PARTIAL &&
2058 ret = skb_checksum_help(skb);
2063 rq = skb->queue_mapping;
2064 tx_queue = priv->tx_queue[rq];
2065 txq = netdev_get_tx_queue(dev, rq);
2066 base = tx_queue->tx_bd_base;
2067 regs = tx_queue->grp->regs;
2069 /* check if time stamp should be generated */
2070 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2071 priv->hwts_tx_en)) {
2073 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2076 /* make space for additional header when fcb is needed */
2077 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2078 vlan_tx_tag_present(skb) ||
2079 unlikely(do_tstamp)) &&
2080 (skb_headroom(skb) < fcb_length)) {
2081 struct sk_buff *skb_new;
2083 skb_new = skb_realloc_headroom(skb, fcb_length);
2085 dev->stats.tx_errors++;
2087 return NETDEV_TX_OK;
2091 skb_set_owner_w(skb_new, skb->sk);
2096 /* total number of fragments in the SKB */
2097 nr_frags = skb_shinfo(skb)->nr_frags;
2099 /* calculate the required number of TxBDs for this skb */
2100 if (unlikely(do_tstamp))
2101 nr_txbds = nr_frags + 2;
2103 nr_txbds = nr_frags + 1;
2105 /* check if there is space to queue this packet */
2106 if (nr_txbds > tx_queue->num_txbdfree) {
2107 /* no space, stop the queue */
2108 netif_tx_stop_queue(txq);
2109 dev->stats.tx_fifo_errors++;
2110 return NETDEV_TX_BUSY;
2113 /* Update transmit stats */
2114 tx_queue->stats.tx_bytes += skb->len;
2115 tx_queue->stats.tx_packets++;
2117 txbdp = txbdp_start = tx_queue->cur_tx;
2118 lstatus = txbdp->lstatus;
2120 /* Time stamp insertion requires one additional TxBD */
2121 if (unlikely(do_tstamp))
2122 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2123 tx_queue->tx_ring_size);
2125 if (nr_frags == 0) {
2126 if (unlikely(do_tstamp))
2127 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2130 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2132 /* Place the fragment addresses and lengths into the TxBDs */
2133 for (i = 0; i < nr_frags; i++) {
2134 /* Point at the next BD, wrapping as needed */
2135 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2137 length = skb_shinfo(skb)->frags[i].size;
2139 lstatus = txbdp->lstatus | length |
2140 BD_LFLAG(TXBD_READY);
2142 /* Handle the last BD specially */
2143 if (i == nr_frags - 1)
2144 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2146 bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2147 &skb_shinfo(skb)->frags[i],
2152 /* set the TxBD length and buffer pointer */
2153 txbdp->bufPtr = bufaddr;
2154 txbdp->lstatus = lstatus;
2157 lstatus = txbdp_start->lstatus;
2160 /* Add TxPAL between FCB and frame if required */
2161 if (unlikely(do_tstamp)) {
2162 skb_push(skb, GMAC_TXPAL_LEN);
2163 memset(skb->data, 0, GMAC_TXPAL_LEN);
2166 /* Set up checksumming */
2167 if (CHECKSUM_PARTIAL == skb->ip_summed) {
2168 fcb = gfar_add_fcb(skb);
2169 /* as specified by errata */
2170 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2171 ((unsigned long)fcb % 0x20) > 0x18)) {
2172 __skb_pull(skb, GMAC_FCB_LEN);
2173 skb_checksum_help(skb);
2175 lstatus |= BD_LFLAG(TXBD_TOE);
2176 gfar_tx_checksum(skb, fcb, fcb_length);
2180 if (vlan_tx_tag_present(skb)) {
2181 if (unlikely(NULL == fcb)) {
2182 fcb = gfar_add_fcb(skb);
2183 lstatus |= BD_LFLAG(TXBD_TOE);
2186 gfar_tx_vlan(skb, fcb);
2189 /* Setup tx hardware time stamping if requested */
2190 if (unlikely(do_tstamp)) {
2191 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2193 fcb = gfar_add_fcb(skb);
2195 lstatus |= BD_LFLAG(TXBD_TOE);
2198 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2199 skb_headlen(skb), DMA_TO_DEVICE);
2201 /* If time stamping is requested one additional TxBD must be set up. The
2202 * first TxBD points to the FCB and must have a data length of
2203 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2204 * the full frame length.
2206 if (unlikely(do_tstamp)) {
2207 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2208 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2209 (skb_headlen(skb) - fcb_length);
2210 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2212 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2215 netdev_tx_sent_queue(txq, skb->len);
2217 /* We can work in parallel with gfar_clean_tx_ring(), except
2218 * when modifying num_txbdfree. Note that we didn't grab the lock
2219 * when we were reading the num_txbdfree and checking for available
2220 * space, that's because outside of this function it can only grow,
2221 * and once we've got needed space, it cannot suddenly disappear.
2223 * The lock also protects us from gfar_error(), which can modify
2224 * regs->tstat and thus retrigger the transfers, which is why we
2225 * also must grab the lock before setting ready bit for the first
2226 * to be transmitted BD.
2228 spin_lock_irqsave(&tx_queue->txlock, flags);
2230 /* The powerpc-specific eieio() is used, as wmb() has too strong
2231 * semantics (it requires synchronization between cacheable and
2232 * uncacheable mappings, which eieio doesn't provide and which we
2233 * don't need), thus requiring a more expensive sync instruction. At
2234 * some point, the set of architecture-independent barrier functions
2235 * should be expanded to include weaker barriers.
2239 txbdp_start->lstatus = lstatus;
2241 eieio(); /* force lstatus write before tx_skbuff */
2243 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2245 /* Update the current skb pointer to the next entry we will use
2246 * (wrapping if necessary)
2248 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2249 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2251 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2253 /* reduce TxBD free count */
2254 tx_queue->num_txbdfree -= (nr_txbds);
2256 /* If the next BD still needs to be cleaned up, then the bds
2257 * are full. We need to tell the kernel to stop sending us stuff.
2259 if (!tx_queue->num_txbdfree) {
2260 netif_tx_stop_queue(txq);
2262 dev->stats.tx_fifo_errors++;
2265 /* Tell the DMA to go go go */
2266 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2269 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2271 return NETDEV_TX_OK;
2274 /* Stops the kernel queue, and halts the controller */
2275 static int gfar_close(struct net_device *dev)
2277 struct gfar_private *priv = netdev_priv(dev);
2281 cancel_work_sync(&priv->reset_task);
2284 /* Disconnect from the PHY */
2285 phy_disconnect(priv->phydev);
2286 priv->phydev = NULL;
2288 netif_tx_stop_all_queues(dev);
2293 /* Changes the mac address if the controller is not running. */
2294 static int gfar_set_mac_address(struct net_device *dev)
2296 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2301 /* Check if rx parser should be activated */
2302 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2304 struct gfar __iomem *regs;
2307 regs = priv->gfargrp[0].regs;
2309 tempval = gfar_read(®s->rctrl);
2310 /* If parse is no longer required, then disable parser */
2311 if (tempval & RCTRL_REQ_PARSER)
2312 tempval |= RCTRL_PRSDEP_INIT;
2314 tempval &= ~RCTRL_PRSDEP_INIT;
2315 gfar_write(®s->rctrl, tempval);
2318 /* Enables and disables VLAN insertion/extraction */
2319 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2321 struct gfar_private *priv = netdev_priv(dev);
2322 struct gfar __iomem *regs = NULL;
2323 unsigned long flags;
2326 regs = priv->gfargrp[0].regs;
2327 local_irq_save(flags);
2330 if (features & NETIF_F_HW_VLAN_TX) {
2331 /* Enable VLAN tag insertion */
2332 tempval = gfar_read(®s->tctrl);
2333 tempval |= TCTRL_VLINS;
2334 gfar_write(®s->tctrl, tempval);
2336 /* Disable VLAN tag insertion */
2337 tempval = gfar_read(®s->tctrl);
2338 tempval &= ~TCTRL_VLINS;
2339 gfar_write(®s->tctrl, tempval);
2342 if (features & NETIF_F_HW_VLAN_RX) {
2343 /* Enable VLAN tag extraction */
2344 tempval = gfar_read(®s->rctrl);
2345 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2346 gfar_write(®s->rctrl, tempval);
2348 /* Disable VLAN tag extraction */
2349 tempval = gfar_read(®s->rctrl);
2350 tempval &= ~RCTRL_VLEX;
2351 gfar_write(®s->rctrl, tempval);
2353 gfar_check_rx_parser_mode(priv);
2356 gfar_change_mtu(dev, dev->mtu);
2359 local_irq_restore(flags);
2362 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2364 int tempsize, tempval;
2365 struct gfar_private *priv = netdev_priv(dev);
2366 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2367 int oldsize = priv->rx_buffer_size;
2368 int frame_size = new_mtu + ETH_HLEN;
2370 if (gfar_is_vlan_on(priv))
2371 frame_size += VLAN_HLEN;
2373 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2374 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2378 if (gfar_uses_fcb(priv))
2379 frame_size += GMAC_FCB_LEN;
2381 frame_size += priv->padding;
2383 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2384 INCREMENTAL_BUFFER_SIZE;
2386 /* Only stop and start the controller if it isn't already
2387 * stopped, and we changed something
2389 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2392 priv->rx_buffer_size = tempsize;
2396 gfar_write(®s->mrblr, priv->rx_buffer_size);
2397 gfar_write(®s->maxfrm, priv->rx_buffer_size);
2399 /* If the mtu is larger than the max size for standard
2400 * ethernet frames (ie, a jumbo frame), then set maccfg2
2401 * to allow huge frames, and to check the length
2403 tempval = gfar_read(®s->maccfg2);
2405 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2406 gfar_has_errata(priv, GFAR_ERRATA_74))
2407 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2409 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2411 gfar_write(®s->maccfg2, tempval);
2413 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2419 /* gfar_reset_task gets scheduled when a packet has not been
2420 * transmitted after a set amount of time.
2421 * For now, assume that clearing out all the structures, and
2422 * starting over will fix the problem.
2424 static void gfar_reset_task(struct work_struct *work)
2426 struct gfar_private *priv = container_of(work, struct gfar_private,
2428 struct net_device *dev = priv->ndev;
2430 if (dev->flags & IFF_UP) {
2431 netif_tx_stop_all_queues(dev);
2434 netif_tx_start_all_queues(dev);
2437 netif_tx_schedule_all(dev);
2440 static void gfar_timeout(struct net_device *dev)
2442 struct gfar_private *priv = netdev_priv(dev);
2444 dev->stats.tx_errors++;
2445 schedule_work(&priv->reset_task);
2448 static void gfar_align_skb(struct sk_buff *skb)
2450 /* We need the data buffer to be aligned properly. We will reserve
2451 * as many bytes as needed to align the data properly
2453 skb_reserve(skb, RXBUF_ALIGNMENT -
2454 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2457 /* Interrupt Handler for Transmit complete */
2458 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2460 struct net_device *dev = tx_queue->dev;
2461 struct netdev_queue *txq;
2462 struct gfar_private *priv = netdev_priv(dev);
2463 struct gfar_priv_rx_q *rx_queue = NULL;
2464 struct txbd8 *bdp, *next = NULL;
2465 struct txbd8 *lbdp = NULL;
2466 struct txbd8 *base = tx_queue->tx_bd_base;
2467 struct sk_buff *skb;
2469 int tx_ring_size = tx_queue->tx_ring_size;
2470 int frags = 0, nr_txbds = 0;
2473 int tqi = tx_queue->qindex;
2474 unsigned int bytes_sent = 0;
2478 rx_queue = priv->rx_queue[tqi];
2479 txq = netdev_get_tx_queue(dev, tqi);
2480 bdp = tx_queue->dirty_tx;
2481 skb_dirtytx = tx_queue->skb_dirtytx;
2483 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2484 unsigned long flags;
2486 frags = skb_shinfo(skb)->nr_frags;
2488 /* When time stamping, one additional TxBD must be freed.
2489 * Also, we need to dma_unmap_single() the TxPAL.
2491 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2492 nr_txbds = frags + 2;
2494 nr_txbds = frags + 1;
2496 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2498 lstatus = lbdp->lstatus;
2500 /* Only clean completed frames */
2501 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2502 (lstatus & BD_LENGTH_MASK))
2505 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2506 next = next_txbd(bdp, base, tx_ring_size);
2507 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2509 buflen = bdp->length;
2511 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2512 buflen, DMA_TO_DEVICE);
2514 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2515 struct skb_shared_hwtstamps shhwtstamps;
2516 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2518 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2519 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2520 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2521 skb_tstamp_tx(skb, &shhwtstamps);
2522 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2526 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2527 bdp = next_txbd(bdp, base, tx_ring_size);
2529 for (i = 0; i < frags; i++) {
2530 dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr,
2531 bdp->length, DMA_TO_DEVICE);
2532 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2533 bdp = next_txbd(bdp, base, tx_ring_size);
2536 bytes_sent += skb->len;
2538 dev_kfree_skb_any(skb);
2540 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2542 skb_dirtytx = (skb_dirtytx + 1) &
2543 TX_RING_MOD_MASK(tx_ring_size);
2546 spin_lock_irqsave(&tx_queue->txlock, flags);
2547 tx_queue->num_txbdfree += nr_txbds;
2548 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2551 /* If we freed a buffer, we can restart transmission, if necessary */
2552 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2553 netif_wake_subqueue(dev, tqi);
2555 /* Update dirty indicators */
2556 tx_queue->skb_dirtytx = skb_dirtytx;
2557 tx_queue->dirty_tx = bdp;
2559 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2564 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2566 unsigned long flags;
2568 spin_lock_irqsave(&gfargrp->grplock, flags);
2569 if (napi_schedule_prep(&gfargrp->napi)) {
2570 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2571 __napi_schedule(&gfargrp->napi);
2573 /* Clear IEVENT, so interrupts aren't called again
2574 * because of the packets that have already arrived.
2576 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2578 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2582 /* Interrupt Handler for Transmit complete */
2583 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2585 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2589 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2590 struct sk_buff *skb)
2592 struct net_device *dev = rx_queue->dev;
2593 struct gfar_private *priv = netdev_priv(dev);
2596 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2597 priv->rx_buffer_size, DMA_FROM_DEVICE);
2598 gfar_init_rxbdp(rx_queue, bdp, buf);
2601 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2603 struct gfar_private *priv = netdev_priv(dev);
2604 struct sk_buff *skb;
2606 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2610 gfar_align_skb(skb);
2615 struct sk_buff *gfar_new_skb(struct net_device *dev)
2617 return gfar_alloc_skb(dev);
2620 static inline void count_errors(unsigned short status, struct net_device *dev)
2622 struct gfar_private *priv = netdev_priv(dev);
2623 struct net_device_stats *stats = &dev->stats;
2624 struct gfar_extra_stats *estats = &priv->extra_stats;
2626 /* If the packet was truncated, none of the other errors matter */
2627 if (status & RXBD_TRUNCATED) {
2628 stats->rx_length_errors++;
2634 /* Count the errors, if there were any */
2635 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2636 stats->rx_length_errors++;
2638 if (status & RXBD_LARGE)
2643 if (status & RXBD_NONOCTET) {
2644 stats->rx_frame_errors++;
2645 estats->rx_nonoctet++;
2647 if (status & RXBD_CRCERR) {
2648 estats->rx_crcerr++;
2649 stats->rx_crc_errors++;
2651 if (status & RXBD_OVERRUN) {
2652 estats->rx_overrun++;
2653 stats->rx_crc_errors++;
2657 irqreturn_t gfar_receive(int irq, void *grp_id)
2659 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2663 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2665 /* If valid headers were found, and valid sums
2666 * were verified, then we tell the kernel that no
2667 * checksumming is necessary. Otherwise, it is [FIXME]
2669 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2670 skb->ip_summed = CHECKSUM_UNNECESSARY;
2672 skb_checksum_none_assert(skb);
2676 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2677 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2678 int amount_pull, struct napi_struct *napi)
2680 struct gfar_private *priv = netdev_priv(dev);
2681 struct rxfcb *fcb = NULL;
2685 /* fcb is at the beginning if exists */
2686 fcb = (struct rxfcb *)skb->data;
2688 /* Remove the FCB from the skb
2689 * Remove the padded bytes, if there are any
2692 skb_record_rx_queue(skb, fcb->rq);
2693 skb_pull(skb, amount_pull);
2696 /* Get receive timestamp from the skb */
2697 if (priv->hwts_rx_en) {
2698 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2699 u64 *ns = (u64 *) skb->data;
2701 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2702 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2706 skb_pull(skb, priv->padding);
2708 if (dev->features & NETIF_F_RXCSUM)
2709 gfar_rx_checksum(skb, fcb);
2711 /* Tell the skb what kind of packet this is */
2712 skb->protocol = eth_type_trans(skb, dev);
2714 /* There's need to check for NETIF_F_HW_VLAN_RX here.
2715 * Even if vlan rx accel is disabled, on some chips
2716 * RXFCB_VLN is pseudo randomly set.
2718 if (dev->features & NETIF_F_HW_VLAN_RX &&
2719 fcb->flags & RXFCB_VLN)
2720 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2722 /* Send the packet up the stack */
2723 ret = napi_gro_receive(napi, skb);
2725 if (GRO_DROP == ret)
2726 priv->extra_stats.kernel_dropped++;
2731 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2732 * until the budget/quota has been reached. Returns the number
2735 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2737 struct net_device *dev = rx_queue->dev;
2738 struct rxbd8 *bdp, *base;
2739 struct sk_buff *skb;
2743 struct gfar_private *priv = netdev_priv(dev);
2745 /* Get the first full descriptor */
2746 bdp = rx_queue->cur_rx;
2747 base = rx_queue->rx_bd_base;
2749 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2751 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2752 struct sk_buff *newskb;
2756 /* Add another skb for the future */
2757 newskb = gfar_new_skb(dev);
2759 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2761 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2762 priv->rx_buffer_size, DMA_FROM_DEVICE);
2764 if (unlikely(!(bdp->status & RXBD_ERR) &&
2765 bdp->length > priv->rx_buffer_size))
2766 bdp->status = RXBD_LARGE;
2768 /* We drop the frame if we failed to allocate a new buffer */
2769 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2770 bdp->status & RXBD_ERR)) {
2771 count_errors(bdp->status, dev);
2773 if (unlikely(!newskb))
2778 /* Increment the number of packets */
2779 rx_queue->stats.rx_packets++;
2783 pkt_len = bdp->length - ETH_FCS_LEN;
2784 /* Remove the FCS from the packet length */
2785 skb_put(skb, pkt_len);
2786 rx_queue->stats.rx_bytes += pkt_len;
2787 skb_record_rx_queue(skb, rx_queue->qindex);
2788 gfar_process_frame(dev, skb, amount_pull,
2789 &rx_queue->grp->napi);
2792 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2793 rx_queue->stats.rx_dropped++;
2794 priv->extra_stats.rx_skbmissing++;
2799 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2801 /* Setup the new bdp */
2802 gfar_new_rxbdp(rx_queue, bdp, newskb);
2804 /* Update to the next pointer */
2805 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2807 /* update to point at the next skb */
2808 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2809 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2812 /* Update the current rxbd pointer to be the next one */
2813 rx_queue->cur_rx = bdp;
2818 static int gfar_poll(struct napi_struct *napi, int budget)
2820 struct gfar_priv_grp *gfargrp =
2821 container_of(napi, struct gfar_priv_grp, napi);
2822 struct gfar_private *priv = gfargrp->priv;
2823 struct gfar __iomem *regs = gfargrp->regs;
2824 struct gfar_priv_tx_q *tx_queue = NULL;
2825 struct gfar_priv_rx_q *rx_queue = NULL;
2826 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2827 int tx_cleaned = 0, i, left_over_budget = budget;
2828 unsigned long serviced_queues = 0;
2831 num_queues = gfargrp->num_rx_queues;
2832 budget_per_queue = budget/num_queues;
2834 /* Clear IEVENT, so interrupts aren't called again
2835 * because of the packets that have already arrived
2837 gfar_write(®s->ievent, IEVENT_RTX_MASK);
2839 while (num_queues && left_over_budget) {
2840 budget_per_queue = left_over_budget/num_queues;
2841 left_over_budget = 0;
2843 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2844 if (test_bit(i, &serviced_queues))
2846 rx_queue = priv->rx_queue[i];
2847 tx_queue = priv->tx_queue[rx_queue->qindex];
2849 tx_cleaned += gfar_clean_tx_ring(tx_queue);
2850 rx_cleaned_per_queue =
2851 gfar_clean_rx_ring(rx_queue, budget_per_queue);
2852 rx_cleaned += rx_cleaned_per_queue;
2853 if (rx_cleaned_per_queue < budget_per_queue) {
2854 left_over_budget = left_over_budget +
2856 rx_cleaned_per_queue);
2857 set_bit(i, &serviced_queues);
2866 if (rx_cleaned < budget) {
2867 napi_complete(napi);
2869 /* Clear the halt bit in RSTAT */
2870 gfar_write(®s->rstat, gfargrp->rstat);
2872 gfar_write(®s->imask, IMASK_DEFAULT);
2874 /* If we are coalescing interrupts, update the timer
2875 * Otherwise, clear it
2877 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2878 gfargrp->tx_bit_map);
2884 #ifdef CONFIG_NET_POLL_CONTROLLER
2885 /* Polling 'interrupt' - used by things like netconsole to send skbs
2886 * without having to re-enable interrupts. It's not called while
2887 * the interrupt routine is executing.
2889 static void gfar_netpoll(struct net_device *dev)
2891 struct gfar_private *priv = netdev_priv(dev);
2894 /* If the device has multiple interrupts, run tx/rx */
2895 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2896 for (i = 0; i < priv->num_grps; i++) {
2897 disable_irq(priv->gfargrp[i].interruptTransmit);
2898 disable_irq(priv->gfargrp[i].interruptReceive);
2899 disable_irq(priv->gfargrp[i].interruptError);
2900 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2902 enable_irq(priv->gfargrp[i].interruptError);
2903 enable_irq(priv->gfargrp[i].interruptReceive);
2904 enable_irq(priv->gfargrp[i].interruptTransmit);
2907 for (i = 0; i < priv->num_grps; i++) {
2908 disable_irq(priv->gfargrp[i].interruptTransmit);
2909 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2911 enable_irq(priv->gfargrp[i].interruptTransmit);
2917 /* The interrupt handler for devices with one interrupt */
2918 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2920 struct gfar_priv_grp *gfargrp = grp_id;
2922 /* Save ievent for future reference */
2923 u32 events = gfar_read(&gfargrp->regs->ievent);
2925 /* Check for reception */
2926 if (events & IEVENT_RX_MASK)
2927 gfar_receive(irq, grp_id);
2929 /* Check for transmit completion */
2930 if (events & IEVENT_TX_MASK)
2931 gfar_transmit(irq, grp_id);
2933 /* Check for errors */
2934 if (events & IEVENT_ERR_MASK)
2935 gfar_error(irq, grp_id);
2940 /* Called every time the controller might need to be made
2941 * aware of new link state. The PHY code conveys this
2942 * information through variables in the phydev structure, and this
2943 * function converts those variables into the appropriate
2944 * register values, and can bring down the device if needed.
2946 static void adjust_link(struct net_device *dev)
2948 struct gfar_private *priv = netdev_priv(dev);
2949 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2950 unsigned long flags;
2951 struct phy_device *phydev = priv->phydev;
2954 local_irq_save(flags);
2958 u32 tempval = gfar_read(®s->maccfg2);
2959 u32 ecntrl = gfar_read(®s->ecntrl);
2961 /* Now we make sure that we can be in full duplex mode.
2962 * If not, we operate in half-duplex mode.
2964 if (phydev->duplex != priv->oldduplex) {
2966 if (!(phydev->duplex))
2967 tempval &= ~(MACCFG2_FULL_DUPLEX);
2969 tempval |= MACCFG2_FULL_DUPLEX;
2971 priv->oldduplex = phydev->duplex;
2974 if (phydev->speed != priv->oldspeed) {
2976 switch (phydev->speed) {
2979 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2981 ecntrl &= ~(ECNTRL_R100);
2986 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2988 /* Reduced mode distinguishes
2989 * between 10 and 100
2991 if (phydev->speed == SPEED_100)
2992 ecntrl |= ECNTRL_R100;
2994 ecntrl &= ~(ECNTRL_R100);
2997 netif_warn(priv, link, dev,
2998 "Ack! Speed (%d) is not 10/100/1000!\n",
3003 priv->oldspeed = phydev->speed;
3006 gfar_write(®s->maccfg2, tempval);
3007 gfar_write(®s->ecntrl, ecntrl);
3009 if (!priv->oldlink) {
3013 } else if (priv->oldlink) {
3017 priv->oldduplex = -1;
3020 if (new_state && netif_msg_link(priv))
3021 phy_print_status(phydev);
3023 local_irq_restore(flags);
3026 /* Update the hash table based on the current list of multicast
3027 * addresses we subscribe to. Also, change the promiscuity of
3028 * the device based on the flags (this function is called
3029 * whenever dev->flags is changed
3031 static void gfar_set_multi(struct net_device *dev)
3033 struct netdev_hw_addr *ha;
3034 struct gfar_private *priv = netdev_priv(dev);
3035 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3038 if (dev->flags & IFF_PROMISC) {
3039 /* Set RCTRL to PROM */
3040 tempval = gfar_read(®s->rctrl);
3041 tempval |= RCTRL_PROM;
3042 gfar_write(®s->rctrl, tempval);
3044 /* Set RCTRL to not PROM */
3045 tempval = gfar_read(®s->rctrl);
3046 tempval &= ~(RCTRL_PROM);
3047 gfar_write(®s->rctrl, tempval);
3050 if (dev->flags & IFF_ALLMULTI) {
3051 /* Set the hash to rx all multicast frames */
3052 gfar_write(®s->igaddr0, 0xffffffff);
3053 gfar_write(®s->igaddr1, 0xffffffff);
3054 gfar_write(®s->igaddr2, 0xffffffff);
3055 gfar_write(®s->igaddr3, 0xffffffff);
3056 gfar_write(®s->igaddr4, 0xffffffff);
3057 gfar_write(®s->igaddr5, 0xffffffff);
3058 gfar_write(®s->igaddr6, 0xffffffff);
3059 gfar_write(®s->igaddr7, 0xffffffff);
3060 gfar_write(®s->gaddr0, 0xffffffff);
3061 gfar_write(®s->gaddr1, 0xffffffff);
3062 gfar_write(®s->gaddr2, 0xffffffff);
3063 gfar_write(®s->gaddr3, 0xffffffff);
3064 gfar_write(®s->gaddr4, 0xffffffff);
3065 gfar_write(®s->gaddr5, 0xffffffff);
3066 gfar_write(®s->gaddr6, 0xffffffff);
3067 gfar_write(®s->gaddr7, 0xffffffff);
3072 /* zero out the hash */
3073 gfar_write(®s->igaddr0, 0x0);
3074 gfar_write(®s->igaddr1, 0x0);
3075 gfar_write(®s->igaddr2, 0x0);
3076 gfar_write(®s->igaddr3, 0x0);
3077 gfar_write(®s->igaddr4, 0x0);
3078 gfar_write(®s->igaddr5, 0x0);
3079 gfar_write(®s->igaddr6, 0x0);
3080 gfar_write(®s->igaddr7, 0x0);
3081 gfar_write(®s->gaddr0, 0x0);
3082 gfar_write(®s->gaddr1, 0x0);
3083 gfar_write(®s->gaddr2, 0x0);
3084 gfar_write(®s->gaddr3, 0x0);
3085 gfar_write(®s->gaddr4, 0x0);
3086 gfar_write(®s->gaddr5, 0x0);
3087 gfar_write(®s->gaddr6, 0x0);
3088 gfar_write(®s->gaddr7, 0x0);
3090 /* If we have extended hash tables, we need to
3091 * clear the exact match registers to prepare for
3094 if (priv->extended_hash) {
3095 em_num = GFAR_EM_NUM + 1;
3096 gfar_clear_exact_match(dev);
3103 if (netdev_mc_empty(dev))
3106 /* Parse the list, and set the appropriate bits */
3107 netdev_for_each_mc_addr(ha, dev) {
3109 gfar_set_mac_for_addr(dev, idx, ha->addr);
3112 gfar_set_hash_for_addr(dev, ha->addr);
3118 /* Clears each of the exact match registers to zero, so they
3119 * don't interfere with normal reception
3121 static void gfar_clear_exact_match(struct net_device *dev)
3124 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3126 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3127 gfar_set_mac_for_addr(dev, idx, zero_arr);
3130 /* Set the appropriate hash bit for the given addr */
3131 /* The algorithm works like so:
3132 * 1) Take the Destination Address (ie the multicast address), and
3133 * do a CRC on it (little endian), and reverse the bits of the
3135 * 2) Use the 8 most significant bits as a hash into a 256-entry
3136 * table. The table is controlled through 8 32-bit registers:
3137 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3138 * gaddr7. This means that the 3 most significant bits in the
3139 * hash index which gaddr register to use, and the 5 other bits
3140 * indicate which bit (assuming an IBM numbering scheme, which
3141 * for PowerPC (tm) is usually the case) in the register holds
3144 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3147 struct gfar_private *priv = netdev_priv(dev);
3148 u32 result = ether_crc(ETH_ALEN, addr);
3149 int width = priv->hash_width;
3150 u8 whichbit = (result >> (32 - width)) & 0x1f;
3151 u8 whichreg = result >> (32 - width + 5);
3152 u32 value = (1 << (31-whichbit));
3154 tempval = gfar_read(priv->hash_regs[whichreg]);
3156 gfar_write(priv->hash_regs[whichreg], tempval);
3160 /* There are multiple MAC Address register pairs on some controllers
3161 * This function sets the numth pair to a given address
3163 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3166 struct gfar_private *priv = netdev_priv(dev);
3167 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3169 char tmpbuf[ETH_ALEN];
3171 u32 __iomem *macptr = ®s->macstnaddr1;
3175 /* Now copy it into the mac registers backwards, cuz
3176 * little endian is silly
3178 for (idx = 0; idx < ETH_ALEN; idx++)
3179 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3181 gfar_write(macptr, *((u32 *) (tmpbuf)));
3183 tempval = *((u32 *) (tmpbuf + 4));
3185 gfar_write(macptr+1, tempval);
3188 /* GFAR error interrupt handler */
3189 static irqreturn_t gfar_error(int irq, void *grp_id)
3191 struct gfar_priv_grp *gfargrp = grp_id;
3192 struct gfar __iomem *regs = gfargrp->regs;
3193 struct gfar_private *priv= gfargrp->priv;
3194 struct net_device *dev = priv->ndev;
3196 /* Save ievent for future reference */
3197 u32 events = gfar_read(®s->ievent);
3200 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3202 /* Magic Packet is not an error. */
3203 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3204 (events & IEVENT_MAG))
3205 events &= ~IEVENT_MAG;
3208 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3210 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3211 events, gfar_read(®s->imask));
3213 /* Update the error counters */
3214 if (events & IEVENT_TXE) {
3215 dev->stats.tx_errors++;
3217 if (events & IEVENT_LC)
3218 dev->stats.tx_window_errors++;
3219 if (events & IEVENT_CRL)
3220 dev->stats.tx_aborted_errors++;
3221 if (events & IEVENT_XFUN) {
3222 unsigned long flags;
3224 netif_dbg(priv, tx_err, dev,
3225 "TX FIFO underrun, packet dropped\n");
3226 dev->stats.tx_dropped++;
3227 priv->extra_stats.tx_underrun++;
3229 local_irq_save(flags);
3232 /* Reactivate the Tx Queues */
3233 gfar_write(®s->tstat, gfargrp->tstat);
3236 local_irq_restore(flags);
3238 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3240 if (events & IEVENT_BSY) {
3241 dev->stats.rx_errors++;
3242 priv->extra_stats.rx_bsy++;
3244 gfar_receive(irq, grp_id);
3246 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3247 gfar_read(®s->rstat));
3249 if (events & IEVENT_BABR) {
3250 dev->stats.rx_errors++;
3251 priv->extra_stats.rx_babr++;
3253 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3255 if (events & IEVENT_EBERR) {
3256 priv->extra_stats.eberr++;
3257 netif_dbg(priv, rx_err, dev, "bus error\n");
3259 if (events & IEVENT_RXC)
3260 netif_dbg(priv, rx_status, dev, "control frame\n");
3262 if (events & IEVENT_BABT) {
3263 priv->extra_stats.tx_babt++;
3264 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3269 static struct of_device_id gfar_match[] =
3273 .compatible = "gianfar",
3276 .compatible = "fsl,etsec2",
3280 MODULE_DEVICE_TABLE(of, gfar_match);
3282 /* Structure for a device driver */
3283 static struct platform_driver gfar_driver = {
3285 .name = "fsl-gianfar",
3286 .owner = THIS_MODULE,
3288 .of_match_table = gfar_match,
3290 .probe = gfar_probe,
3291 .remove = gfar_remove,
3294 module_platform_driver(gfar_driver);