2 * PTP 1588 clock using the eTSEC
4 * Copyright (C) 2010 OMICRON electronics GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23 #include <linux/device.h>
24 #include <linux/hrtimer.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
30 #include <linux/of_platform.h>
31 #include <linux/timex.h>
34 #include <linux/ptp_clock_kernel.h>
39 * gianfar ptp registers
40 * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
42 struct gianfar_ptp_registers {
43 u32 tmr_ctrl; /* Timer control register */
44 u32 tmr_tevent; /* Timestamp event register */
45 u32 tmr_temask; /* Timer event mask register */
46 u32 tmr_pevent; /* Timestamp event register */
47 u32 tmr_pemask; /* Timer event mask register */
48 u32 tmr_stat; /* Timestamp status register */
49 u32 tmr_cnt_h; /* Timer counter high register */
50 u32 tmr_cnt_l; /* Timer counter low register */
51 u32 tmr_add; /* Timer drift compensation addend register */
52 u32 tmr_acc; /* Timer accumulator register */
53 u32 tmr_prsc; /* Timer prescale */
55 u32 tmroff_h; /* Timer offset high */
56 u32 tmroff_l; /* Timer offset low */
58 u32 tmr_alarm1_h; /* Timer alarm 1 high register */
59 u32 tmr_alarm1_l; /* Timer alarm 1 high register */
60 u32 tmr_alarm2_h; /* Timer alarm 2 high register */
61 u32 tmr_alarm2_l; /* Timer alarm 2 high register */
63 u32 tmr_fiper1; /* Timer fixed period interval */
64 u32 tmr_fiper2; /* Timer fixed period interval */
65 u32 tmr_fiper3; /* Timer fixed period interval */
67 u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
68 u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
69 u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
70 u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
73 /* Bit definitions for the TMR_CTRL register */
74 #define ALM1P (1<<31) /* Alarm1 output polarity */
75 #define ALM2P (1<<30) /* Alarm2 output polarity */
76 #define FS (1<<28) /* FIPER start indication */
77 #define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
78 #define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
79 #define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
80 #define TCLK_PERIOD_MASK (0x3ff)
81 #define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
82 #define FRD (1<<14) /* FIPER Realignment Disable */
83 #define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
84 #define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
85 #define ETEP2 (1<<9) /* External trigger 2 edge polarity */
86 #define ETEP1 (1<<8) /* External trigger 1 edge polarity */
87 #define COPH (1<<7) /* Generated clock output phase. */
88 #define CIPH (1<<6) /* External oscillator input clock phase */
89 #define TMSR (1<<5) /* Timer soft reset. */
90 #define BYP (1<<3) /* Bypass drift compensated clock */
91 #define TE (1<<2) /* 1588 timer enable. */
92 #define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
93 #define CKSEL_MASK (0x3)
95 /* Bit definitions for the TMR_TEVENT register */
96 #define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
97 #define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
98 #define ALM2 (1<<17) /* Current time = alarm time register 2 */
99 #define ALM1 (1<<16) /* Current time = alarm time register 1 */
100 #define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
101 #define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
102 #define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
104 /* Bit definitions for the TMR_TEMASK register */
105 #define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
106 #define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
107 #define ALM2EN (1<<17) /* Timer ALM2 event enable */
108 #define ALM1EN (1<<16) /* Timer ALM1 event enable */
109 #define PP1EN (1<<7) /* Periodic pulse event 1 enable */
110 #define PP2EN (1<<6) /* Periodic pulse event 2 enable */
112 /* Bit definitions for the TMR_PEVENT register */
113 #define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
114 #define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
115 #define RXP (1<<0) /* PTP frame has been received */
117 /* Bit definitions for the TMR_PEMASK register */
118 #define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
119 #define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
120 #define RXPEN (1<<0) /* Receive PTP packet event enable */
122 /* Bit definitions for the TMR_STAT register */
123 #define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
124 #define STAT_VEC_MASK (0x3f)
126 /* Bit definitions for the TMR_PRSC register */
127 #define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
128 #define PRSC_OCK_MASK (0xffff)
131 #define DRIVER "gianfar_ptp"
132 #define DEFAULT_CKSEL 1
134 #define REG_SIZE sizeof(struct gianfar_ptp_registers)
137 struct gianfar_ptp_registers *regs;
138 spinlock_t lock; /* protects regs */
139 struct ptp_clock *clock;
140 struct ptp_clock_info caps;
141 struct resource *rsrc;
143 u64 alarm_interval; /* for periodic alarm */
145 u32 tclk_period; /* nanoseconds */
154 * Register access functions
157 /* Caller must hold etsects->lock. */
158 static u64 tmr_cnt_read(struct etsects *etsects)
163 lo = gfar_read(&etsects->regs->tmr_cnt_l);
164 hi = gfar_read(&etsects->regs->tmr_cnt_h);
165 ns = ((u64) hi) << 32;
170 /* Caller must hold etsects->lock. */
171 static void tmr_cnt_write(struct etsects *etsects, u64 ns)
174 u32 lo = ns & 0xffffffff;
176 gfar_write(&etsects->regs->tmr_cnt_l, lo);
177 gfar_write(&etsects->regs->tmr_cnt_h, hi);
180 /* Caller must hold etsects->lock. */
181 static void set_alarm(struct etsects *etsects)
186 ns = tmr_cnt_read(etsects) + 1500000000ULL;
187 ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
188 ns -= etsects->tclk_period;
190 lo = ns & 0xffffffff;
191 gfar_write(&etsects->regs->tmr_alarm1_l, lo);
192 gfar_write(&etsects->regs->tmr_alarm1_h, hi);
195 /* Caller must hold etsects->lock. */
196 static void set_fipers(struct etsects *etsects)
199 gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
200 gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
204 * Interrupt service routine
207 static irqreturn_t isr(int irq, void *priv)
209 struct etsects *etsects = priv;
210 struct ptp_clock_event event;
212 u32 ack = 0, lo, hi, mask, val;
214 val = gfar_read(&etsects->regs->tmr_tevent);
218 hi = gfar_read(&etsects->regs->tmr_etts1_h);
219 lo = gfar_read(&etsects->regs->tmr_etts1_l);
220 event.type = PTP_CLOCK_EXTTS;
222 event.timestamp = ((u64) hi) << 32;
223 event.timestamp |= lo;
224 ptp_clock_event(etsects->clock, &event);
229 hi = gfar_read(&etsects->regs->tmr_etts2_h);
230 lo = gfar_read(&etsects->regs->tmr_etts2_l);
231 event.type = PTP_CLOCK_EXTTS;
233 event.timestamp = ((u64) hi) << 32;
234 event.timestamp |= lo;
235 ptp_clock_event(etsects->clock, &event);
240 if (etsects->alarm_value) {
241 event.type = PTP_CLOCK_ALARM;
243 event.timestamp = etsects->alarm_value;
244 ptp_clock_event(etsects->clock, &event);
246 if (etsects->alarm_interval) {
247 ns = etsects->alarm_value + etsects->alarm_interval;
249 lo = ns & 0xffffffff;
250 spin_lock(&etsects->lock);
251 gfar_write(&etsects->regs->tmr_alarm2_l, lo);
252 gfar_write(&etsects->regs->tmr_alarm2_h, hi);
253 spin_unlock(&etsects->lock);
254 etsects->alarm_value = ns;
256 gfar_write(&etsects->regs->tmr_tevent, ALM2);
257 spin_lock(&etsects->lock);
258 mask = gfar_read(&etsects->regs->tmr_temask);
260 gfar_write(&etsects->regs->tmr_temask, mask);
261 spin_unlock(&etsects->lock);
262 etsects->alarm_value = 0;
263 etsects->alarm_interval = 0;
269 event.type = PTP_CLOCK_PPS;
270 ptp_clock_event(etsects->clock, &event);
274 gfar_write(&etsects->regs->tmr_tevent, ack);
281 * PTP clock operations
284 static int ptp_gianfar_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
289 struct etsects *etsects = container_of(ptp, struct etsects, caps);
295 tmr_add = etsects->tmr_add;
298 diff = div_u64(adj, 1000000000ULL);
300 tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
302 gfar_write(&etsects->regs->tmr_add, tmr_add);
307 static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
311 struct etsects *etsects = container_of(ptp, struct etsects, caps);
313 spin_lock_irqsave(&etsects->lock, flags);
315 now = tmr_cnt_read(etsects);
317 tmr_cnt_write(etsects, now);
319 spin_unlock_irqrestore(&etsects->lock, flags);
326 static int ptp_gianfar_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
331 struct etsects *etsects = container_of(ptp, struct etsects, caps);
333 spin_lock_irqsave(&etsects->lock, flags);
335 ns = tmr_cnt_read(etsects);
337 spin_unlock_irqrestore(&etsects->lock, flags);
339 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
340 ts->tv_nsec = remainder;
344 static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
345 const struct timespec *ts)
349 struct etsects *etsects = container_of(ptp, struct etsects, caps);
351 ns = ts->tv_sec * 1000000000ULL;
354 spin_lock_irqsave(&etsects->lock, flags);
356 tmr_cnt_write(etsects, ns);
359 spin_unlock_irqrestore(&etsects->lock, flags);
364 static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
365 struct ptp_clock_request *rq, int on)
367 struct etsects *etsects = container_of(ptp, struct etsects, caps);
372 case PTP_CLK_REQ_EXTTS:
373 switch (rq->extts.index) {
383 spin_lock_irqsave(&etsects->lock, flags);
384 mask = gfar_read(&etsects->regs->tmr_temask);
389 gfar_write(&etsects->regs->tmr_temask, mask);
390 spin_unlock_irqrestore(&etsects->lock, flags);
393 case PTP_CLK_REQ_PPS:
394 spin_lock_irqsave(&etsects->lock, flags);
395 mask = gfar_read(&etsects->regs->tmr_temask);
400 gfar_write(&etsects->regs->tmr_temask, mask);
401 spin_unlock_irqrestore(&etsects->lock, flags);
411 static struct ptp_clock_info ptp_gianfar_caps = {
412 .owner = THIS_MODULE,
413 .name = "gianfar clock",
416 .n_ext_ts = N_EXT_TS,
419 .adjfreq = ptp_gianfar_adjfreq,
420 .adjtime = ptp_gianfar_adjtime,
421 .gettime = ptp_gianfar_gettime,
422 .settime = ptp_gianfar_settime,
423 .enable = ptp_gianfar_enable,
428 static int get_of_u32(struct device_node *node, char *str, u32 *val)
431 const u32 *prop = of_get_property(node, str, &plen);
433 if (!prop || plen != sizeof(*prop))
439 static int gianfar_ptp_probe(struct platform_device *dev)
441 struct device_node *node = dev->dev.of_node;
442 struct etsects *etsects;
448 etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
454 etsects->caps = ptp_gianfar_caps;
455 etsects->cksel = DEFAULT_CKSEL;
457 if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) ||
458 get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) ||
459 get_of_u32(node, "fsl,tmr-add", &etsects->tmr_add) ||
460 get_of_u32(node, "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
461 get_of_u32(node, "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
462 get_of_u32(node, "fsl,max-adj", &etsects->caps.max_adj)) {
463 pr_err("device tree node missing required elements\n");
467 etsects->irq = platform_get_irq(dev, 0);
469 if (etsects->irq == NO_IRQ) {
470 pr_err("irq not in device tree\n");
473 if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
474 pr_err("request_irq failed\n");
478 etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
479 if (!etsects->rsrc) {
480 pr_err("no resource\n");
483 if (request_resource(&iomem_resource, etsects->rsrc)) {
484 pr_err("resource busy\n");
488 spin_lock_init(&etsects->lock);
490 etsects->regs = ioremap(etsects->rsrc->start,
491 resource_size(etsects->rsrc));
492 if (!etsects->regs) {
493 pr_err("ioremap ptp registers failed\n");
496 getnstimeofday(&now);
497 ptp_gianfar_settime(&etsects->caps, &now);
500 (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
501 (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
503 spin_lock_irqsave(&etsects->lock, flags);
505 gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl);
506 gfar_write(&etsects->regs->tmr_add, etsects->tmr_add);
507 gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
508 gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
509 gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
511 gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|FS|RTPE|TE|FRD);
513 spin_unlock_irqrestore(&etsects->lock, flags);
515 etsects->clock = ptp_clock_register(&etsects->caps, &dev->dev);
516 if (IS_ERR(etsects->clock)) {
517 err = PTR_ERR(etsects->clock);
520 gfar_phc_index = ptp_clock_index(etsects->clock);
522 dev_set_drvdata(&dev->dev, etsects);
528 release_resource(etsects->rsrc);
530 free_irq(etsects->irq, etsects);
537 static int gianfar_ptp_remove(struct platform_device *dev)
539 struct etsects *etsects = dev_get_drvdata(&dev->dev);
541 gfar_write(&etsects->regs->tmr_temask, 0);
542 gfar_write(&etsects->regs->tmr_ctrl, 0);
545 ptp_clock_unregister(etsects->clock);
546 iounmap(etsects->regs);
547 release_resource(etsects->rsrc);
548 free_irq(etsects->irq, etsects);
554 static struct of_device_id match_table[] = {
555 { .compatible = "fsl,etsec-ptp" },
559 static struct platform_driver gianfar_ptp_driver = {
561 .name = "gianfar_ptp",
562 .of_match_table = match_table,
563 .owner = THIS_MODULE,
565 .probe = gianfar_ptp_probe,
566 .remove = gianfar_ptp_remove,
569 module_platform_driver(gianfar_ptp_driver);
571 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
572 MODULE_DESCRIPTION("PTP clock using the eTSEC");
573 MODULE_LICENSE("GPL");