1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 /* Linux PRO/1000 Ethernet Driver main header file */
34 #include <linux/bitops.h>
35 #include <linux/types.h>
36 #include <linux/timer.h>
37 #include <linux/workqueue.h>
39 #include <linux/netdevice.h>
40 #include <linux/pci.h>
41 #include <linux/pci-aspm.h>
42 #include <linux/crc32.h>
43 #include <linux/if_vlan.h>
44 #include <linux/clocksource.h>
45 #include <linux/net_tstamp.h>
46 #include <linux/ptp_clock_kernel.h>
47 #include <linux/ptp_classify.h>
48 #include <linux/mii.h>
49 #include <linux/mdio.h>
54 #define e_dbg(format, arg...) \
55 netdev_dbg(hw->adapter->netdev, format, ## arg)
56 #define e_err(format, arg...) \
57 netdev_err(adapter->netdev, format, ## arg)
58 #define e_info(format, arg...) \
59 netdev_info(adapter->netdev, format, ## arg)
60 #define e_warn(format, arg...) \
61 netdev_warn(adapter->netdev, format, ## arg)
62 #define e_notice(format, arg...) \
63 netdev_notice(adapter->netdev, format, ## arg)
65 /* Interrupt modes, as used by the IntMode parameter */
66 #define E1000E_INT_MODE_LEGACY 0
67 #define E1000E_INT_MODE_MSI 1
68 #define E1000E_INT_MODE_MSIX 2
70 /* Tx/Rx descriptor defines */
71 #define E1000_DEFAULT_TXD 256
72 #define E1000_MAX_TXD 4096
73 #define E1000_MIN_TXD 64
75 #define E1000_DEFAULT_RXD 256
76 #define E1000_MAX_RXD 4096
77 #define E1000_MIN_RXD 64
79 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
80 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
82 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
84 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
85 /* How many Rx Buffers do we bundle into one write to the hardware ? */
86 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
88 #define AUTO_ALL_MODES 0
89 #define E1000_EEPROM_APME 0x0400
91 #define E1000_MNG_VLAN_NONE (-1)
93 #define DEFAULT_JUMBO 9234
95 /* Time to wait before putting the device into D3 if there's no link (in ms). */
96 #define LINK_TIMEOUT 100
98 /* Count for polling __E1000_RESET condition every 10-20msec.
99 * Experimentation has shown the reset can take approximately 210msec.
101 #define E1000_CHECK_RESET_COUNT 25
103 #define DEFAULT_RDTR 0
104 #define DEFAULT_RADV 8
105 #define BURST_RDTR 0x20
106 #define BURST_RADV 0x20
108 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
109 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
110 * WTHRESH=4, so a setting of 5 gives the most efficient bus
111 * utilization but to avoid possible Tx stalls, set it to 1
113 #define E1000_TXDCTL_DMA_BURST_ENABLE \
114 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
115 E1000_TXDCTL_COUNT_DESC | \
116 (1 << 16) | /* wthresh must be +1 more than desired */\
117 (1 << 8) | /* hthresh */ \
120 #define E1000_RXDCTL_DMA_BURST_ENABLE \
121 (0x01000000 | /* set descriptor granularity */ \
122 (4 << 16) | /* set writeback threshold */ \
123 (4 << 8) | /* set prefetch threshold */ \
124 0x20) /* set hthresh */
126 #define E1000_TIDV_FPD (1 << 31)
127 #define E1000_RDTR_FPD (1 << 31)
144 struct e1000_ps_page {
146 u64 dma; /* must be u64 - written to hw */
149 /* wrappers around a pointer to a socket buffer,
150 * so a DMA handle can be stored along with the buffer
152 struct e1000_buffer {
158 unsigned long time_stamp;
162 unsigned int bytecount;
167 /* arrays of page information for packet split */
168 struct e1000_ps_page *ps_pages;
175 struct e1000_adapter *adapter; /* back pointer to adapter */
176 void *desc; /* pointer to ring memory */
177 dma_addr_t dma; /* phys address of ring */
178 unsigned int size; /* length of ring in bytes */
179 unsigned int count; /* number of desc. in ring */
187 /* array of buffer information structs */
188 struct e1000_buffer *buffer_info;
190 char name[IFNAMSIZ + 5];
193 void __iomem *itr_register;
196 struct sk_buff *rx_skb_top;
199 /* PHY register snapshot values */
200 struct e1000_phy_regs {
201 u16 bmcr; /* basic mode control register */
202 u16 bmsr; /* basic mode status register */
203 u16 advertise; /* auto-negotiation advertisement */
204 u16 lpa; /* link partner ability register */
205 u16 expansion; /* auto-negotiation expansion reg */
206 u16 ctrl1000; /* 1000BASE-T control register */
207 u16 stat1000; /* 1000BASE-T status register */
208 u16 estatus; /* extended status register */
211 /* board specific private data structure */
212 struct e1000_adapter {
213 struct timer_list watchdog_timer;
214 struct timer_list phy_info_timer;
215 struct timer_list blink_timer;
217 struct work_struct reset_task;
218 struct work_struct watchdog_task;
220 const struct e1000_info *ei;
222 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
230 /* track device up/down/testing state */
233 /* Interrupt Throttle Rate */
239 /* Tx - one ring per active queue */
240 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
243 struct napi_struct napi;
245 unsigned int uncorr_errors; /* uncorrectable ECC errors */
246 unsigned int corr_errors; /* correctable ECC errors */
247 unsigned int restart_queue;
251 bool tx_hang_recheck;
252 u8 tx_timeout_factor;
255 u32 tx_abs_int_delay;
257 unsigned int total_tx_bytes;
258 unsigned int total_tx_packets;
259 unsigned int total_rx_bytes;
260 unsigned int total_rx_packets;
267 u32 tx_timeout_count;
274 bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
275 int work_to_do) ____cacheline_aligned_in_smp;
276 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
278 struct e1000_ring *rx_ring;
281 u32 rx_abs_int_delay;
289 u32 alloc_rx_buff_failed;
291 u32 rx_hwtstamp_cleared;
293 unsigned int rx_ps_pages;
298 /* OS defined structs */
299 struct net_device *netdev;
300 struct pci_dev *pdev;
302 /* structs defined in e1000_hw.h */
305 spinlock_t stats64_lock; /* protects statistics counters */
306 struct e1000_hw_stats stats;
307 struct e1000_phy_info phy_info;
308 struct e1000_phy_stats phy_stats;
310 /* Snapshot of PHY registers */
311 struct e1000_phy_regs phy_regs;
313 struct e1000_ring test_tx_ring;
314 struct e1000_ring test_rx_ring;
318 unsigned int num_vectors;
319 struct msix_entry *msix_entries;
326 u32 max_hw_frame_size;
332 struct work_struct downshift_task;
333 struct work_struct update_phy_task;
334 struct work_struct print_hang_task;
342 struct hwtstamp_config hwtstamp_config;
343 struct delayed_work systim_overflow_work;
344 struct sk_buff *tx_hwtstamp_skb;
345 struct work_struct tx_hwtstamp_work;
346 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
347 struct cyclecounter cc;
348 struct timecounter tc;
349 struct ptp_clock *ptp_clock;
350 struct ptp_clock_info ptp_clock_info;
356 enum e1000_mac_type mac;
360 u32 max_hw_frame_size;
361 s32 (*get_variants)(struct e1000_adapter *);
362 const struct e1000_mac_operations *mac_ops;
363 const struct e1000_phy_operations *phy_ops;
364 const struct e1000_nvm_operations *nvm_ops;
367 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
369 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
370 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
371 * its resolution) is based on the contents of the TIMINCA register - it
372 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
373 * For the best accuracy, the incperiod should be as small as possible. The
374 * incvalue is scaled by a factor as large as possible (while still fitting
375 * in bits 23:0) so that relatively small clock corrections can be made.
377 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
378 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
379 * bits to count nanoseconds leaving the rest for fractional nonseconds.
381 #define INCVALUE_96MHz 125
382 #define INCVALUE_SHIFT_96MHz 17
383 #define INCPERIOD_SHIFT_96MHz 2
384 #define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz)
386 #define INCVALUE_25MHz 40
387 #define INCVALUE_SHIFT_25MHz 18
388 #define INCPERIOD_25MHz 1
390 /* Another drawback of scaling the incvalue by a large factor is the
391 * 64-bit SYSTIM register overflows more quickly. This is dealt with
392 * by simply reading the clock before it overflows.
394 * Clock ns bits Overflows after
395 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
396 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
397 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
399 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
401 /* hardware capability, feature, and workaround flags */
402 #define FLAG_HAS_AMT (1 << 0)
403 #define FLAG_HAS_FLASH (1 << 1)
404 #define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
405 #define FLAG_HAS_WOL (1 << 3)
407 #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
408 #define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
409 #define FLAG_HAS_JUMBO_FRAMES (1 << 7)
410 #define FLAG_READ_ONLY_NVM (1 << 8)
411 #define FLAG_IS_ICH (1 << 9)
412 #define FLAG_HAS_MSIX (1 << 10)
413 #define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
414 #define FLAG_IS_QUAD_PORT_A (1 << 12)
415 #define FLAG_IS_QUAD_PORT (1 << 13)
416 #define FLAG_HAS_HW_TIMESTAMP (1 << 14)
417 #define FLAG_APME_IN_WUC (1 << 15)
418 #define FLAG_APME_IN_CTRL3 (1 << 16)
419 #define FLAG_APME_CHECK_PORT_B (1 << 17)
420 #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
421 #define FLAG_NO_WAKE_UCAST (1 << 19)
422 #define FLAG_MNG_PT_ENABLED (1 << 20)
423 #define FLAG_RESET_OVERWRITES_LAA (1 << 21)
424 #define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
425 #define FLAG_TARC_SET_BIT_ZERO (1 << 23)
426 #define FLAG_RX_NEEDS_RESTART (1 << 24)
427 #define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
428 #define FLAG_SMART_POWER_DOWN (1 << 26)
429 #define FLAG_MSI_ENABLED (1 << 27)
430 /* reserved (1 << 28) */
431 #define FLAG_TSO_FORCE (1 << 29)
432 #define FLAG_RESTART_NOW (1 << 30)
433 #define FLAG_MSI_TEST_FAILED (1 << 31)
435 #define FLAG2_CRC_STRIPPING (1 << 0)
436 #define FLAG2_HAS_PHY_WAKEUP (1 << 1)
437 #define FLAG2_IS_DISCARDING (1 << 2)
438 #define FLAG2_DISABLE_ASPM_L1 (1 << 3)
439 #define FLAG2_HAS_PHY_STATS (1 << 4)
440 #define FLAG2_HAS_EEE (1 << 5)
441 #define FLAG2_DMA_BURST (1 << 6)
442 #define FLAG2_DISABLE_ASPM_L0S (1 << 7)
443 #define FLAG2_DISABLE_AIM (1 << 8)
444 #define FLAG2_CHECK_PHY_HANG (1 << 9)
445 #define FLAG2_NO_DISABLE_RX (1 << 10)
446 #define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
447 #define FLAG2_DFLT_CRC_STRIPPING (1 << 12)
448 #define FLAG2_CHECK_RX_HWTSTAMP (1 << 13)
450 #define E1000_RX_DESC_PS(R, i) \
451 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
452 #define E1000_RX_DESC_EXT(R, i) \
453 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
454 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
455 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
456 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
461 __E1000_ACCESS_SHARED_RESOURCE,
469 latency_invalid = 255
472 extern char e1000e_driver_name[];
473 extern const char e1000e_driver_version[];
475 void e1000e_check_options(struct e1000_adapter *adapter);
476 void e1000e_set_ethtool_ops(struct net_device *netdev);
478 int e1000e_up(struct e1000_adapter *adapter);
479 void e1000e_down(struct e1000_adapter *adapter);
480 void e1000e_reinit_locked(struct e1000_adapter *adapter);
481 void e1000e_reset(struct e1000_adapter *adapter);
482 void e1000e_power_up_phy(struct e1000_adapter *adapter);
483 int e1000e_setup_rx_resources(struct e1000_ring *ring);
484 int e1000e_setup_tx_resources(struct e1000_ring *ring);
485 void e1000e_free_rx_resources(struct e1000_ring *ring);
486 void e1000e_free_tx_resources(struct e1000_ring *ring);
487 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
488 struct rtnl_link_stats64 *stats);
489 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
490 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
491 void e1000e_get_hw_control(struct e1000_adapter *adapter);
492 void e1000e_release_hw_control(struct e1000_adapter *adapter);
493 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
495 extern unsigned int copybreak;
497 extern const struct e1000_info e1000_82571_info;
498 extern const struct e1000_info e1000_82572_info;
499 extern const struct e1000_info e1000_82573_info;
500 extern const struct e1000_info e1000_82574_info;
501 extern const struct e1000_info e1000_82583_info;
502 extern const struct e1000_info e1000_ich8_info;
503 extern const struct e1000_info e1000_ich9_info;
504 extern const struct e1000_info e1000_ich10_info;
505 extern const struct e1000_info e1000_pch_info;
506 extern const struct e1000_info e1000_pch2_info;
507 extern const struct e1000_info e1000_pch_lpt_info;
508 extern const struct e1000_info e1000_es2_info;
510 void e1000e_ptp_init(struct e1000_adapter *adapter);
511 void e1000e_ptp_remove(struct e1000_adapter *adapter);
513 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
515 return hw->phy.ops.reset(hw);
518 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
520 return hw->phy.ops.read_reg(hw, offset, data);
523 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
525 return hw->phy.ops.read_reg_locked(hw, offset, data);
528 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
530 return hw->phy.ops.write_reg(hw, offset, data);
533 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
535 return hw->phy.ops.write_reg_locked(hw, offset, data);
538 void e1000e_reload_nvm_generic(struct e1000_hw *hw);
540 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
542 if (hw->mac.ops.read_mac_addr)
543 return hw->mac.ops.read_mac_addr(hw);
545 return e1000_read_mac_addr_generic(hw);
548 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
550 return hw->nvm.ops.validate(hw);
553 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
555 return hw->nvm.ops.update(hw);
558 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
561 return hw->nvm.ops.read(hw, offset, words, data);
564 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
567 return hw->nvm.ops.write(hw, offset, words, data);
570 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
572 return hw->phy.ops.get_info(hw);
575 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
577 return readl(hw->hw_addr + reg);
580 #define er32(reg) __er32(hw, E1000_##reg)
583 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
584 * @hw: pointer to the HW structure
586 * When updating the MAC CSR registers, the Manageability Engine (ME) could
587 * be accessing the registers at the same time. Normally, this is handled in
588 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
589 * accesses later than it should which could result in the register to have
590 * an incorrect value. Workaround this by checking the FWSM register which
591 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
592 * and try again a number of times.
594 static inline s32 __ew32_prepare(struct e1000_hw *hw)
596 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
598 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
604 static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
606 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
609 writel(val, hw->hw_addr + reg);
612 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
614 #define e1e_flush() er32(STATUS)
616 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
617 (__ew32((a), (reg + ((offset) << 2)), (value)))
619 #define E1000_READ_REG_ARRAY(a, reg, offset) \
620 (readl((a)->hw_addr + reg + ((offset) << 2)))
622 #endif /* _E1000_H_ */