drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* 82562G 10/100 Network Connection
  30  * 82562G-2 10/100 Network Connection
  31  * 82562GT 10/100 Network Connection
  32  * 82562GT-2 10/100 Network Connection
  33  * 82562V 10/100 Network Connection
  34  * 82562V-2 10/100 Network Connection
  35  * 82566DC-2 Gigabit Network Connection
  36  * 82566DC Gigabit Network Connection
  37  * 82566DM-2 Gigabit Network Connection
  38  * 82566DM Gigabit Network Connection
  39  * 82566MC Gigabit Network Connection
  40  * 82566MM Gigabit Network Connection
  41  * 82567LM Gigabit Network Connection
  42  * 82567LF Gigabit Network Connection
  43  * 82567V Gigabit Network Connection
  44  * 82567LM-2 Gigabit Network Connection
  45  * 82567LF-2 Gigabit Network Connection
  46  * 82567V-2 Gigabit Network Connection
  47  * 82567LF-3 Gigabit Network Connection
  48  * 82567LM-3 Gigabit Network Connection
  49  * 82567LM-4 Gigabit Network Connection
  50  * 82577LM Gigabit Network Connection
  51  * 82577LC Gigabit Network Connection
  52  * 82578DM Gigabit Network Connection
  53  * 82578DC Gigabit Network Connection
  54  * 82579LM Gigabit Network Connection
  55  * 82579V Gigabit Network Connection
  56  */
  57
  58 #include "e1000.h"
  59
  60 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  61 /* Offset 04h HSFSTS */
  62 union ich8_hws_flash_status {
  63         struct ich8_hsfsts {
  64                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  65                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  66                 u16 dael:1;     /* bit 2 Direct Access error Log */
  67                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  68                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  69                 u16 reserved1:2;        /* bit 13:6 Reserved */
  70                 u16 reserved2:6;        /* bit 13:6 Reserved */
  71                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  72                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  73         } hsf_status;
  74         u16 regval;
  75 };
  76
  77 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  78 /* Offset 06h FLCTL */
  79 union ich8_hws_flash_ctrl {
  80         struct ich8_hsflctl {
  81                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  82                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  83                 u16 reserved:5; /* 7:3 Reserved  */
  84                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  85                 u16 flockdn:6;  /* 15:10 Reserved */
  86         } hsf_ctrl;
  87         u16 regval;
  88 };
  89
  90 /* ICH Flash Region Access Permissions */
  91 union ich8_hws_flash_regacc {
  92         struct ich8_flracc {
  93                 u32 grra:8;     /* 0:7 GbE region Read Access */
  94                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  95                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  96                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  97         } hsf_flregacc;
  98         u16 regval;
  99 };
 100
 101 /* ICH Flash Protected Region */
 102 union ich8_flash_protected_range {
 103         struct ich8_pr {
 104                 u32 base:13;    /* 0:12 Protected Range Base */
 105                 u32 reserved1:2;        /* 13:14 Reserved */
 106                 u32 rpe:1;      /* 15 Read Protection Enable */
 107                 u32 limit:13;   /* 16:28 Protected Range Limit */
 108                 u32 reserved2:2;        /* 29:30 Reserved */
 109                 u32 wpe:1;      /* 31 Write Protection Enable */
 110         } range;
 111         u32 regval;
 112 };
 113
 114 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 115 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 116 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 117 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 118                                                 u32 offset, u8 byte);
 119 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 120                                          u8 *data);
 121 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 122                                          u16 *data);
 123 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 124                                          u8 size, u16 *data);
 125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 126 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 127 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 128 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 129 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 130 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 131 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 132 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 133 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 134 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 135 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 136 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 137 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 138 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 139 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 140 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 141 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 142 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 143 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 144 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 145 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 146
 147 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 148 {
 149         return readw(hw->flash_address + reg);
 150 }
 151
 152 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 153 {
 154         return readl(hw->flash_address + reg);
 155 }
 156
 157 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 158 {
 159         writew(val, hw->flash_address + reg);
 160 }
 161
 162 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 163 {
 164         writel(val, hw->flash_address + reg);
 165 }
 166
 167 #define er16flash(reg)          __er16flash(hw, (reg))
 168 #define er32flash(reg)          __er32flash(hw, (reg))
 169 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 170 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 171
 172 /**
 173  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 174  *  @hw: pointer to the HW structure
 175  *
 176  *  Test access to the PHY registers by reading the PHY ID registers.  If
 177  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 178  *  otherwise assume the read PHY ID is correct if it is valid.
 179  *
 180  *  Assumes the sw/fw/hw semaphore is already acquired.
 181  **/
 182 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 183 {
 184         u16 phy_reg = 0;
 185         u32 phy_id = 0;
 186         s32 ret_val;
 187         u16 retry_count;
 188         u32 mac_reg = 0;
 189
 190         for (retry_count = 0; retry_count < 2; retry_count++) {
 191                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 192                 if (ret_val || (phy_reg == 0xFFFF))
 193                         continue;
 194                 phy_id = (u32)(phy_reg << 16);
 195
 196                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 197                 if (ret_val || (phy_reg == 0xFFFF)) {
 198                         phy_id = 0;
 199                         continue;
 200                 }
 201                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 202                 break;
 203         }
 204
 205         if (hw->phy.id) {
 206                 if (hw->phy.id == phy_id)
 207                         goto out;
 208         } else if (phy_id) {
 209                 hw->phy.id = phy_id;
 210                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 211                 goto out;
 212         }
 213
 214         /* In case the PHY needs to be in mdio slow mode,
 215          * set slow mode and try to get the PHY id again.
 216          */
 217         hw->phy.ops.release(hw);
 218         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 219         if (!ret_val)
 220                 ret_val = e1000e_get_phy_id(hw);
 221         hw->phy.ops.acquire(hw);
 222
 223         if (ret_val)
 224                 return false;
 225 out:
 226         if (hw->mac.type == e1000_pch_lpt) {
 227                 /* Unforce SMBus mode in PHY */
 228                 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 229                 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 230                 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 231
 232                 /* Unforce SMBus mode in MAC */
 233                 mac_reg = er32(CTRL_EXT);
 234                 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 235                 ew32(CTRL_EXT, mac_reg);
 236         }
 237
 238         return true;
 239 }
 240
 241 /**
 242  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 243  *  @hw: pointer to the HW structure
 244  *
 245  *  Workarounds/flow necessary for PHY initialization during driver load
 246  *  and resume paths.
 247  **/
 248 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 249 {
 250         u32 mac_reg, fwsm = er32(FWSM);
 251         s32 ret_val;
 252
 253         /* Gate automatic PHY configuration by hardware on managed and
 254          * non-managed 82579 and newer adapters.
 255          */
 256         e1000_gate_hw_phy_config_ich8lan(hw, true);
 257
 258         ret_val = hw->phy.ops.acquire(hw);
 259         if (ret_val) {
 260                 e_dbg("Failed to initialize PHY flow\n");
 261                 goto out;
 262         }
 263
 264         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 265          * inaccessible and resetting the PHY is not blocked, toggle the
 266          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 267          */
 268         switch (hw->mac.type) {
 269         case e1000_pch_lpt:
 270                 if (e1000_phy_is_accessible_pchlan(hw))
 271                         break;
 272
 273                 /* Before toggling LANPHYPC, see if PHY is accessible by
 274                  * forcing MAC to SMBus mode first.
 275                  */
 276                 mac_reg = er32(CTRL_EXT);
 277                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 278                 ew32(CTRL_EXT, mac_reg);
 279
 280                 /* Wait 50 milliseconds for MAC to finish any retries
 281                  * that it might be trying to perform from previous
 282                  * attempts to acknowledge any phy read requests.
 283                  */
 284                 msleep(50);
 285
 286                 /* fall-through */
 287         case e1000_pch2lan:
 288                 if (e1000_phy_is_accessible_pchlan(hw))
 289                         break;
 290
 291                 /* fall-through */
 292         case e1000_pchlan:
 293                 if ((hw->mac.type == e1000_pchlan) &&
 294                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 295                         break;
 296
 297                 if (hw->phy.ops.check_reset_block(hw)) {
 298                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 299                         ret_val = -E1000_ERR_PHY;
 300                         break;
 301                 }
 302
 303                 e_dbg("Toggling LANPHYPC\n");
 304
 305                 /* Set Phy Config Counter to 50msec */
 306                 mac_reg = er32(FEXTNVM3);
 307                 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 308                 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 309                 ew32(FEXTNVM3, mac_reg);
 310
 311                 /* Toggle LANPHYPC Value bit */
 312                 mac_reg = er32(CTRL);
 313                 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 314                 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 315                 ew32(CTRL, mac_reg);
 316                 e1e_flush();
 317                 usleep_range(10, 20);
 318                 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 319                 ew32(CTRL, mac_reg);
 320                 e1e_flush();
 321                 if (hw->mac.type < e1000_pch_lpt) {
 322                         msleep(50);
 323                 } else {
 324                         u16 count = 20;
 325                         do {
 326                                 usleep_range(5000, 10000);
 327                         } while (!(er32(CTRL_EXT) &
 328                                    E1000_CTRL_EXT_LPCD) && count--);
 329                         usleep_range(30000, 60000);
 330                         if (e1000_phy_is_accessible_pchlan(hw))
 331                                 break;
 332
 333                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 334                          * so ensure that the MAC is also out of SMBus mode
 335                          */
 336                         mac_reg = er32(CTRL_EXT);
 337                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 338                         ew32(CTRL_EXT, mac_reg);
 339
 340                         if (e1000_phy_is_accessible_pchlan(hw))
 341                                 break;
 342
 343                         ret_val = -E1000_ERR_PHY;
 344                 }
 345                 break;
 346         default:
 347                 break;
 348         }
 349
 350         hw->phy.ops.release(hw);
 351         if (!ret_val) {
 352                 /* Reset the PHY before any access to it.  Doing so, ensures
 353                  * that the PHY is in a known good state before we read/write
 354                  * PHY registers.  The generic reset is sufficient here,
 355                  * because we haven't determined the PHY type yet.
 356                  */
 357                 ret_val = e1000e_phy_hw_reset_generic(hw);
 358         }
 359
 360 out:
 361         /* Ungate automatic PHY configuration on non-managed 82579 */
 362         if ((hw->mac.type == e1000_pch2lan) &&
 363             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 364                 usleep_range(10000, 20000);
 365                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 366         }
 367
 368         return ret_val;
 369 }
 370
 371 /**
 372  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 373  *  @hw: pointer to the HW structure
 374  *
 375  *  Initialize family-specific PHY parameters and function pointers.
 376  **/
 377 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 378 {
 379         struct e1000_phy_info *phy = &hw->phy;
 380         s32 ret_val;
 381
 382         phy->addr = 1;
 383         phy->reset_delay_us = 100;
 384
 385         phy->ops.set_page = e1000_set_page_igp;
 386         phy->ops.read_reg = e1000_read_phy_reg_hv;
 387         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 388         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 389         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 390         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 391         phy->ops.write_reg = e1000_write_phy_reg_hv;
 392         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 393         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 394         phy->ops.power_up = e1000_power_up_phy_copper;
 395         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 396         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 397
 398         phy->id = e1000_phy_unknown;
 399
 400         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 401         if (ret_val)
 402                 return ret_val;
 403
 404         if (phy->id == e1000_phy_unknown)
 405                 switch (hw->mac.type) {
 406                 default:
 407                         ret_val = e1000e_get_phy_id(hw);
 408                         if (ret_val)
 409                                 return ret_val;
 410                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 411                                 break;
 412                         /* fall-through */
 413                 case e1000_pch2lan:
 414                 case e1000_pch_lpt:
 415                         /* In case the PHY needs to be in mdio slow mode,
 416                          * set slow mode and try to get the PHY id again.
 417                          */
 418                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 419                         if (ret_val)
 420                                 return ret_val;
 421                         ret_val = e1000e_get_phy_id(hw);
 422                         if (ret_val)
 423                                 return ret_val;
 424                         break;
 425                 }
 426         phy->type = e1000e_get_phy_type_from_id(phy->id);
 427
 428         switch (phy->type) {
 429         case e1000_phy_82577:
 430         case e1000_phy_82579:
 431         case e1000_phy_i217:
 432                 phy->ops.check_polarity = e1000_check_polarity_82577;
 433                 phy->ops.force_speed_duplex =
 434                     e1000_phy_force_speed_duplex_82577;
 435                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 436                 phy->ops.get_info = e1000_get_phy_info_82577;
 437                 phy->ops.commit = e1000e_phy_sw_reset;
 438                 break;
 439         case e1000_phy_82578:
 440                 phy->ops.check_polarity = e1000_check_polarity_m88;
 441                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 442                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 443                 phy->ops.get_info = e1000e_get_phy_info_m88;
 444                 break;
 445         default:
 446                 ret_val = -E1000_ERR_PHY;
 447                 break;
 448         }
 449
 450         return ret_val;
 451 }
 452
 453 /**
 454  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 455  *  @hw: pointer to the HW structure
 456  *
 457  *  Initialize family-specific PHY parameters and function pointers.
 458  **/
 459 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 460 {
 461         struct e1000_phy_info *phy = &hw->phy;
 462         s32 ret_val;
 463         u16 i = 0;
 464
 465         phy->addr = 1;
 466         phy->reset_delay_us = 100;
 467
 468         phy->ops.power_up = e1000_power_up_phy_copper;
 469         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 470
 471         /* We may need to do this twice - once for IGP and if that fails,
 472          * we'll set BM func pointers and try again
 473          */
 474         ret_val = e1000e_determine_phy_address(hw);
 475         if (ret_val) {
 476                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 477                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 478                 ret_val = e1000e_determine_phy_address(hw);
 479                 if (ret_val) {
 480                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 481                         return ret_val;
 482                 }
 483         }
 484
 485         phy->id = 0;
 486         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 487                (i++ < 100)) {
 488                 usleep_range(1000, 2000);
 489                 ret_val = e1000e_get_phy_id(hw);
 490                 if (ret_val)
 491                         return ret_val;
 492         }
 493
 494         /* Verify phy id */
 495         switch (phy->id) {
 496         case IGP03E1000_E_PHY_ID:
 497                 phy->type = e1000_phy_igp_3;
 498                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 499                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 500                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 501                 phy->ops.get_info = e1000e_get_phy_info_igp;
 502                 phy->ops.check_polarity = e1000_check_polarity_igp;
 503                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 504                 break;
 505         case IFE_E_PHY_ID:
 506         case IFE_PLUS_E_PHY_ID:
 507         case IFE_C_E_PHY_ID:
 508                 phy->type = e1000_phy_ife;
 509                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 510                 phy->ops.get_info = e1000_get_phy_info_ife;
 511                 phy->ops.check_polarity = e1000_check_polarity_ife;
 512                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 513                 break;
 514         case BME1000_E_PHY_ID:
 515                 phy->type = e1000_phy_bm;
 516                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 517                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 518                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 519                 phy->ops.commit = e1000e_phy_sw_reset;
 520                 phy->ops.get_info = e1000e_get_phy_info_m88;
 521                 phy->ops.check_polarity = e1000_check_polarity_m88;
 522                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 523                 break;
 524         default:
 525                 return -E1000_ERR_PHY;
 526                 break;
 527         }
 528
 529         return 0;
 530 }
 531
 532 /**
 533  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 534  *  @hw: pointer to the HW structure
 535  *
 536  *  Initialize family-specific NVM parameters and function
 537  *  pointers.
 538  **/
 539 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 540 {
 541         struct e1000_nvm_info *nvm = &hw->nvm;
 542         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 543         u32 gfpreg, sector_base_addr, sector_end_addr;
 544         u16 i;
 545
 546         /* Can't read flash registers if the register set isn't mapped. */
 547         if (!hw->flash_address) {
 548                 e_dbg("ERROR: Flash registers not mapped\n");
 549                 return -E1000_ERR_CONFIG;
 550         }
 551
 552         nvm->type = e1000_nvm_flash_sw;
 553
 554         gfpreg = er32flash(ICH_FLASH_GFPREG);
 555
 556         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 557          * Add 1 to sector_end_addr since this sector is included in
 558          * the overall size.
 559          */
 560         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 561         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 562
 563         /* flash_base_addr is byte-aligned */
 564         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 565
 566         /* find total size of the NVM, then cut in half since the total
 567          * size represents two separate NVM banks.
 568          */
 569         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 570                                 << FLASH_SECTOR_ADDR_SHIFT);
 571         nvm->flash_bank_size /= 2;
 572         /* Adjust to word count */
 573         nvm->flash_bank_size /= sizeof(u16);
 574
 575         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 576
 577         /* Clear shadow ram */
 578         for (i = 0; i < nvm->word_size; i++) {
 579                 dev_spec->shadow_ram[i].modified = false;
 580                 dev_spec->shadow_ram[i].value = 0xFFFF;
 581         }
 582
 583         return 0;
 584 }
 585
 586 /**
 587  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 588  *  @hw: pointer to the HW structure
 589  *
 590  *  Initialize family-specific MAC parameters and function
 591  *  pointers.
 592  **/
 593 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 594 {
 595         struct e1000_mac_info *mac = &hw->mac;
 596
 597         /* Set media type function pointer */
 598         hw->phy.media_type = e1000_media_type_copper;
 599
 600         /* Set mta register count */
 601         mac->mta_reg_count = 32;
 602         /* Set rar entry count */
 603         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 604         if (mac->type == e1000_ich8lan)
 605                 mac->rar_entry_count--;
 606         /* FWSM register */
 607         mac->has_fwsm = true;
 608         /* ARC subsystem not supported */
 609         mac->arc_subsystem_valid = false;
 610         /* Adaptive IFS supported */
 611         mac->adaptive_ifs = true;
 612
 613         /* LED and other operations */
 614         switch (mac->type) {
 615         case e1000_ich8lan:
 616         case e1000_ich9lan:
 617         case e1000_ich10lan:
 618                 /* check management mode */
 619                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 620                 /* ID LED init */
 621                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 622                 /* blink LED */
 623                 mac->ops.blink_led = e1000e_blink_led_generic;
 624                 /* setup LED */
 625                 mac->ops.setup_led = e1000e_setup_led_generic;
 626                 /* cleanup LED */
 627                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 628                 /* turn on/off LED */
 629                 mac->ops.led_on = e1000_led_on_ich8lan;
 630                 mac->ops.led_off = e1000_led_off_ich8lan;
 631                 break;
 632         case e1000_pch2lan:
 633                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 634                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 635                 /* fall-through */
 636         case e1000_pch_lpt:
 637         case e1000_pchlan:
 638                 /* check management mode */
 639                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 640                 /* ID LED init */
 641                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 642                 /* setup LED */
 643                 mac->ops.setup_led = e1000_setup_led_pchlan;
 644                 /* cleanup LED */
 645                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 646                 /* turn on/off LED */
 647                 mac->ops.led_on = e1000_led_on_pchlan;
 648                 mac->ops.led_off = e1000_led_off_pchlan;
 649                 break;
 650         default:
 651                 break;
 652         }
 653
 654         if (mac->type == e1000_pch_lpt) {
 655                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 656                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 657                 mac->ops.setup_physical_interface =
 658                     e1000_setup_copper_link_pch_lpt;
 659         }
 660
 661         /* Enable PCS Lock-loss workaround for ICH8 */
 662         if (mac->type == e1000_ich8lan)
 663                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 664
 665         return 0;
 666 }
 667
 668 /**
 669  *  __e1000_access_emi_reg_locked - Read/write EMI register
 670  *  @hw: pointer to the HW structure
 671  *  @addr: EMI address to program
 672  *  @data: pointer to value to read/write from/to the EMI address
 673  *  @read: boolean flag to indicate read or write
 674  *
 675  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 676  **/
 677 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 678                                          u16 *data, bool read)
 679 {
 680         s32 ret_val;
 681
 682         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 683         if (ret_val)
 684                 return ret_val;
 685
 686         if (read)
 687                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 688         else
 689                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 690
 691         return ret_val;
 692 }
 693
 694 /**
 695  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 696  *  @hw: pointer to the HW structure
 697  *  @addr: EMI address to program
 698  *  @data: value to be read from the EMI address
 699  *
 700  *  Assumes the SW/FW/HW Semaphore is already acquired.
 701  **/
 702 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 703 {
 704         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 705 }
 706
 707 /**
 708  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 709  *  @hw: pointer to the HW structure
 710  *  @addr: EMI address to program
 711  *  @data: value to be written to the EMI address
 712  *
 713  *  Assumes the SW/FW/HW Semaphore is already acquired.
 714  **/
 715 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 716 {
 717         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 718 }
 719
 720 /**
 721  *  e1000_set_eee_pchlan - Enable/disable EEE support
 722  *  @hw: pointer to the HW structure
 723  *
 724  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 725  *  the link and the EEE capabilities of the link partner.  The LPI Control
 726  *  register bits will remain set only if/when link is up.
 727  **/
 728 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 729 {
 730         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 731         s32 ret_val;
 732         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 733
 734         switch (hw->phy.type) {
 735         case e1000_phy_82579:
 736                 lpa = I82579_EEE_LP_ABILITY;
 737                 pcs_status = I82579_EEE_PCS_STATUS;
 738                 adv_addr = I82579_EEE_ADVERTISEMENT;
 739                 break;
 740         case e1000_phy_i217:
 741                 lpa = I217_EEE_LP_ABILITY;
 742                 pcs_status = I217_EEE_PCS_STATUS;
 743                 adv_addr = I217_EEE_ADVERTISEMENT;
 744                 break;
 745         default:
 746                 return 0;
 747         }
 748
 749         ret_val = hw->phy.ops.acquire(hw);
 750         if (ret_val)
 751                 return ret_val;
 752
 753         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 754         if (ret_val)
 755                 goto release;
 756
 757         /* Clear bits that enable EEE in various speeds */
 758         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 759
 760         /* Enable EEE if not disabled by user */
 761         if (!dev_spec->eee_disable) {
 762                 /* Save off link partner's EEE ability */
 763                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 764                                                     &dev_spec->eee_lp_ability);
 765                 if (ret_val)
 766                         goto release;
 767
 768                 /* Read EEE advertisement */
 769                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 770                 if (ret_val)
 771                         goto release;
 772
 773                 /* Enable EEE only for speeds in which the link partner is
 774                  * EEE capable and for which we advertise EEE.
 775                  */
 776                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 777                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 778
 779                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 780                         e1e_rphy_locked(hw, MII_LPA, &data);
 781                         if (data & LPA_100FULL)
 782                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 783                         else
 784                                 /* EEE is not supported in 100Half, so ignore
 785                                  * partner's EEE in 100 ability if full-duplex
 786                                  * is not advertised.
 787                                  */
 788                                 dev_spec->eee_lp_ability &=
 789                                     ~I82579_EEE_100_SUPPORTED;
 790                 }
 791         }
 792
 793         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 794         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 795         if (ret_val)
 796                 goto release;
 797
 798         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 799 release:
 800         hw->phy.ops.release(hw);
 801
 802         return ret_val;
 803 }
 804
 805 /**
 806  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 807  *  @hw:   pointer to the HW structure
 808  *  @link: link up bool flag
 809  *
 810  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 811  *  preventing further DMA write requests.  Workaround the issue by disabling
 812  *  the de-assertion of the clock request when in 1Gpbs mode.
 813  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 814  *  speeds in order to avoid Tx hangs.
 815  **/
 816 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 817 {
 818         u32 fextnvm6 = er32(FEXTNVM6);
 819         u32 status = er32(STATUS);
 820         s32 ret_val = 0;
 821         u16 reg;
 822
 823         if (link && (status & E1000_STATUS_SPEED_1000)) {
 824                 ret_val = hw->phy.ops.acquire(hw);
 825                 if (ret_val)
 826                         return ret_val;
 827
 828                 ret_val =
 829                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 830                                                 &reg);
 831                 if (ret_val)
 832                         goto release;
 833
 834                 ret_val =
 835                     e1000e_write_kmrn_reg_locked(hw,
 836                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 837                                                  reg &
 838                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 839                 if (ret_val)
 840                         goto release;
 841
 842                 usleep_range(10, 20);
 843
 844                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 845
 846                 ret_val =
 847                     e1000e_write_kmrn_reg_locked(hw,
 848                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 849                                                  reg);
 850 release:
 851                 hw->phy.ops.release(hw);
 852         } else {
 853                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 854                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 855
 856                 if (!link || ((status & E1000_STATUS_SPEED_100) &&
 857                               (status & E1000_STATUS_FD)))
 858                         goto update_fextnvm6;
 859
 860                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 861                 if (ret_val)
 862                         return ret_val;
 863
 864                 /* Clear link status transmit timeout */
 865                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 866
 867                 if (status & E1000_STATUS_SPEED_100) {
 868                         /* Set inband Tx timeout to 5x10us for 100Half */
 869                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 870
 871                         /* Do not extend the K1 entry latency for 100Half */
 872                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 873                 } else {
 874                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 875                         reg |= 50 <<
 876                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 877
 878                         /* Extend the K1 entry latency for 10 Mbps */
 879                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 880                 }
 881
 882                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 883                 if (ret_val)
 884                         return ret_val;
 885
 886 update_fextnvm6:
 887                 ew32(FEXTNVM6, fextnvm6);
 888         }
 889
 890         return ret_val;
 891 }
 892
 893 /**
 894  *  e1000_platform_pm_pch_lpt - Set platform power management values
 895  *  @hw: pointer to the HW structure
 896  *  @link: bool indicating link status
 897  *
 898  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 899  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
 900  *  when link is up (which must not exceed the maximum latency supported
 901  *  by the platform), otherwise specify there is no LTR requirement.
 902  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
 903  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
 904  *  Capability register set, on this device LTR is set by writing the
 905  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
 906  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
 907  *  message to the PMC.
 908  **/
 909 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
 910 {
 911         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
 912             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
 913         u16 lat_enc = 0;        /* latency encoded */
 914
 915         if (link) {
 916                 u16 speed, duplex, scale = 0;
 917                 u16 max_snoop, max_nosnoop;
 918                 u16 max_ltr_enc;        /* max LTR latency encoded */
 919                 s64 lat_ns;     /* latency (ns) */
 920                 s64 value;
 921                 u32 rxa;
 922
 923                 if (!hw->adapter->max_frame_size) {
 924                         e_dbg("max_frame_size not set.\n");
 925                         return -E1000_ERR_CONFIG;
 926                 }
 927
 928                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
 929                 if (!speed) {
 930                         e_dbg("Speed not set.\n");
 931                         return -E1000_ERR_CONFIG;
 932                 }
 933
 934                 /* Rx Packet Buffer Allocation size (KB) */
 935                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
 936
 937                 /* Determine the maximum latency tolerated by the device.
 938                  *
 939                  * Per the PCIe spec, the tolerated latencies are encoded as
 940                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
 941                  * a 10-bit value (0-1023) to provide a range from 1 ns to
 942                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
 943                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
 944                  */
 945                 lat_ns = ((s64)rxa * 1024 -
 946                           (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;
 947                 if (lat_ns < 0)
 948                         lat_ns = 0;
 949                 else
 950                         do_div(lat_ns, speed);
 951
 952                 value = lat_ns;
 953                 while (value > PCI_LTR_VALUE_MASK) {
 954                         scale++;
 955                         value = DIV_ROUND_UP(value, (1 << 5));
 956                 }
 957                 if (scale > E1000_LTRV_SCALE_MAX) {
 958                         e_dbg("Invalid LTR latency scale %d\n", scale);
 959                         return -E1000_ERR_CONFIG;
 960                 }
 961                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
 962
 963                 /* Determine the maximum latency tolerated by the platform */
 964                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
 965                                      &max_snoop);
 966                 pci_read_config_word(hw->adapter->pdev,
 967                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
 968                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
 969
 970                 if (lat_enc > max_ltr_enc)
 971                         lat_enc = max_ltr_enc;
 972         }
 973
 974         /* Set Snoop and No-Snoop latencies the same */
 975         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
 976         ew32(LTRV, reg);
 977
 978         return 0;
 979 }
 980
 981 /**
 982  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 983  *  @hw: pointer to the HW structure
 984  *
 985  *  Checks to see of the link status of the hardware has changed.  If a
 986  *  change in link status has been detected, then we read the PHY registers
 987  *  to get the current speed/duplex if link exists.
 988  **/
 989 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 990 {
 991         struct e1000_mac_info *mac = &hw->mac;
 992         s32 ret_val;
 993         bool link;
 994         u16 phy_reg;
 995
 996         /* We only want to go out to the PHY registers to see if Auto-Neg
 997          * has completed and/or if our link status has changed.  The
 998          * get_link_status flag is set upon receiving a Link Status
 999          * Change or Rx Sequence Error interrupt.
1000          */
1001         if (!mac->get_link_status)
1002                 return 0;
1003
1004         /* First we want to see if the MII Status Register reports
1005          * link.  If so, then we want to get the current speed/duplex
1006          * of the PHY.
1007          */
1008         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1009         if (ret_val)
1010                 return ret_val;
1011
1012         if (hw->mac.type == e1000_pchlan) {
1013                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1014                 if (ret_val)
1015                         return ret_val;
1016         }
1017
1018         /* When connected at 10Mbps half-duplex, 82579 parts are excessively
1019          * aggressive resulting in many collisions. To avoid this, increase
1020          * the IPG and reduce Rx latency in the PHY.
1021          */
1022         if ((hw->mac.type == e1000_pch2lan) && link) {
1023                 u32 reg;
1024                 reg = er32(STATUS);
1025                 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1026                         reg = er32(TIPG);
1027                         reg &= ~E1000_TIPG_IPGT_MASK;
1028                         reg |= 0xFF;
1029                         ew32(TIPG, reg);
1030
1031                         /* Reduce Rx latency in analog PHY */
1032                         ret_val = hw->phy.ops.acquire(hw);
1033                         if (ret_val)
1034                                 return ret_val;
1035
1036                         ret_val =
1037                             e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
1038
1039                         hw->phy.ops.release(hw);
1040
1041                         if (ret_val)
1042                                 return ret_val;
1043                 }
1044         }
1045
1046         /* Work-around I218 hang issue */
1047         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1048             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1049             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1050             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1051                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1052                 if (ret_val)
1053                         return ret_val;
1054         }
1055
1056         if (hw->mac.type == e1000_pch_lpt) {
1057                 /* Set platform power management values for
1058                  * Latency Tolerance Reporting (LTR)
1059                  */
1060                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1061                 if (ret_val)
1062                         return ret_val;
1063         }
1064
1065         /* Clear link partner's EEE ability */
1066         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1067
1068         if (!link)
1069                 return 0;       /* No link detected */
1070
1071         mac->get_link_status = false;
1072
1073         switch (hw->mac.type) {
1074         case e1000_pch2lan:
1075                 ret_val = e1000_k1_workaround_lv(hw);
1076                 if (ret_val)
1077                         return ret_val;
1078                 /* fall-thru */
1079         case e1000_pchlan:
1080                 if (hw->phy.type == e1000_phy_82578) {
1081                         ret_val = e1000_link_stall_workaround_hv(hw);
1082                         if (ret_val)
1083                                 return ret_val;
1084                 }
1085
1086                 /* Workaround for PCHx parts in half-duplex:
1087                  * Set the number of preambles removed from the packet
1088                  * when it is passed from the PHY to the MAC to prevent
1089                  * the MAC from misinterpreting the packet type.
1090                  */
1091                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1092                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1093
1094                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1095                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1096
1097                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1098                 break;
1099         default:
1100                 break;
1101         }
1102
1103         /* Check if there was DownShift, must be checked
1104          * immediately after link-up
1105          */
1106         e1000e_check_downshift(hw);
1107
1108         /* Enable/Disable EEE after link up */
1109         ret_val = e1000_set_eee_pchlan(hw);
1110         if (ret_val)
1111                 return ret_val;
1112
1113         /* If we are forcing speed/duplex, then we simply return since
1114          * we have already determined whether we have link or not.
1115          */
1116         if (!mac->autoneg)
1117                 return -E1000_ERR_CONFIG;
1118
1119         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1120          * of MAC speed/duplex configuration.  So we only need to
1121          * configure Collision Distance in the MAC.
1122          */
1123         mac->ops.config_collision_dist(hw);
1124
1125         /* Configure Flow Control now that Auto-Neg has completed.
1126          * First, we need to restore the desired flow control
1127          * settings because we may have had to re-autoneg with a
1128          * different link partner.
1129          */
1130         ret_val = e1000e_config_fc_after_link_up(hw);
1131         if (ret_val)
1132                 e_dbg("Error configuring flow control\n");
1133
1134         return ret_val;
1135 }
1136
1137 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1138 {
1139         struct e1000_hw *hw = &adapter->hw;
1140         s32 rc;
1141
1142         rc = e1000_init_mac_params_ich8lan(hw);
1143         if (rc)
1144                 return rc;
1145
1146         rc = e1000_init_nvm_params_ich8lan(hw);
1147         if (rc)
1148                 return rc;
1149
1150         switch (hw->mac.type) {
1151         case e1000_ich8lan:
1152         case e1000_ich9lan:
1153         case e1000_ich10lan:
1154                 rc = e1000_init_phy_params_ich8lan(hw);
1155                 break;
1156         case e1000_pchlan:
1157         case e1000_pch2lan:
1158         case e1000_pch_lpt:
1159                 rc = e1000_init_phy_params_pchlan(hw);
1160                 break;
1161         default:
1162                 break;
1163         }
1164         if (rc)
1165                 return rc;
1166
1167         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1168          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1169          */
1170         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1171             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1172              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1173                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1174                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
1175
1176                 hw->mac.ops.blink_led = NULL;
1177         }
1178
1179         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1180             (adapter->hw.phy.type != e1000_phy_ife))
1181                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1182
1183         /* Enable workaround for 82579 w/ ME enabled */
1184         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1185             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1186                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1187
1188         return 0;
1189 }
1190
1191 static DEFINE_MUTEX(nvm_mutex);
1192
1193 /**
1194  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1195  *  @hw: pointer to the HW structure
1196  *
1197  *  Acquires the mutex for performing NVM operations.
1198  **/
1199 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1200 {
1201         mutex_lock(&nvm_mutex);
1202
1203         return 0;
1204 }
1205
1206 /**
1207  *  e1000_release_nvm_ich8lan - Release NVM mutex
1208  *  @hw: pointer to the HW structure
1209  *
1210  *  Releases the mutex used while performing NVM operations.
1211  **/
1212 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1213 {
1214         mutex_unlock(&nvm_mutex);
1215 }
1216
1217 /**
1218  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1219  *  @hw: pointer to the HW structure
1220  *
1221  *  Acquires the software control flag for performing PHY and select
1222  *  MAC CSR accesses.
1223  **/
1224 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1225 {
1226         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1227         s32 ret_val = 0;
1228
1229         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1230                              &hw->adapter->state)) {
1231                 e_dbg("contention for Phy access\n");
1232                 return -E1000_ERR_PHY;
1233         }
1234
1235         while (timeout) {
1236                 extcnf_ctrl = er32(EXTCNF_CTRL);
1237                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1238                         break;
1239
1240                 mdelay(1);
1241                 timeout--;
1242         }
1243
1244         if (!timeout) {
1245                 e_dbg("SW has already locked the resource.\n");
1246                 ret_val = -E1000_ERR_CONFIG;
1247                 goto out;
1248         }
1249
1250         timeout = SW_FLAG_TIMEOUT;
1251
1252         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1253         ew32(EXTCNF_CTRL, extcnf_ctrl);
1254
1255         while (timeout) {
1256                 extcnf_ctrl = er32(EXTCNF_CTRL);
1257                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1258                         break;
1259
1260                 mdelay(1);
1261                 timeout--;
1262         }
1263
1264         if (!timeout) {
1265                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1266                       er32(FWSM), extcnf_ctrl);
1267                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1268                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1269                 ret_val = -E1000_ERR_CONFIG;
1270                 goto out;
1271         }
1272
1273 out:
1274         if (ret_val)
1275                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1276
1277         return ret_val;
1278 }
1279
1280 /**
1281  *  e1000_release_swflag_ich8lan - Release software control flag
1282  *  @hw: pointer to the HW structure
1283  *
1284  *  Releases the software control flag for performing PHY and select
1285  *  MAC CSR accesses.
1286  **/
1287 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1288 {
1289         u32 extcnf_ctrl;
1290
1291         extcnf_ctrl = er32(EXTCNF_CTRL);
1292
1293         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1294                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1295                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1296         } else {
1297                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1298         }
1299
1300         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1301 }
1302
1303 /**
1304  *  e1000_check_mng_mode_ich8lan - Checks management mode
1305  *  @hw: pointer to the HW structure
1306  *
1307  *  This checks if the adapter has any manageability enabled.
1308  *  This is a function pointer entry point only called by read/write
1309  *  routines for the PHY and NVM parts.
1310  **/
1311 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1312 {
1313         u32 fwsm;
1314
1315         fwsm = er32(FWSM);
1316         return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
1317                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1318                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
1319 }
1320
1321 /**
1322  *  e1000_check_mng_mode_pchlan - Checks management mode
1323  *  @hw: pointer to the HW structure
1324  *
1325  *  This checks if the adapter has iAMT enabled.
1326  *  This is a function pointer entry point only called by read/write
1327  *  routines for the PHY and NVM parts.
1328  **/
1329 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1330 {
1331         u32 fwsm;
1332
1333         fwsm = er32(FWSM);
1334         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1335             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1336 }
1337
1338 /**
1339  *  e1000_rar_set_pch2lan - Set receive address register
1340  *  @hw: pointer to the HW structure
1341  *  @addr: pointer to the receive address
1342  *  @index: receive address array register
1343  *
1344  *  Sets the receive address array register at index to the address passed
1345  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1346  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1347  *  Use SHRA[0-3] in place of those reserved for ME.
1348  **/
1349 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1350 {
1351         u32 rar_low, rar_high;
1352
1353         /* HW expects these in little endian so we reverse the byte order
1354          * from network order (big endian) to little endian
1355          */
1356         rar_low = ((u32)addr[0] |
1357                    ((u32)addr[1] << 8) |
1358                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1359
1360         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1361
1362         /* If MAC address zero, no need to set the AV bit */
1363         if (rar_low || rar_high)
1364                 rar_high |= E1000_RAH_AV;
1365
1366         if (index == 0) {
1367                 ew32(RAL(index), rar_low);
1368                 e1e_flush();
1369                 ew32(RAH(index), rar_high);
1370                 e1e_flush();
1371                 return;
1372         }
1373
1374         if (index < hw->mac.rar_entry_count) {
1375                 s32 ret_val;
1376
1377                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1378                 if (ret_val)
1379                         goto out;
1380
1381                 ew32(SHRAL(index - 1), rar_low);
1382                 e1e_flush();
1383                 ew32(SHRAH(index - 1), rar_high);
1384                 e1e_flush();
1385
1386                 e1000_release_swflag_ich8lan(hw);
1387
1388                 /* verify the register updates */
1389                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1390                     (er32(SHRAH(index - 1)) == rar_high))
1391                         return;
1392
1393                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1394                       (index - 1), er32(FWSM));
1395         }
1396
1397 out:
1398         e_dbg("Failed to write receive address at index %d\n", index);
1399 }
1400
1401 /**
1402  *  e1000_rar_set_pch_lpt - Set receive address registers
1403  *  @hw: pointer to the HW structure
1404  *  @addr: pointer to the receive address
1405  *  @index: receive address array register
1406  *
1407  *  Sets the receive address register array at index to the address passed
1408  *  in by addr. For LPT, RAR[0] is the base address register that is to
1409  *  contain the MAC address. SHRA[0-10] are the shared receive address
1410  *  registers that are shared between the Host and manageability engine (ME).
1411  **/
1412 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1413 {
1414         u32 rar_low, rar_high;
1415         u32 wlock_mac;
1416
1417         /* HW expects these in little endian so we reverse the byte order
1418          * from network order (big endian) to little endian
1419          */
1420         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1421                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1422
1423         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1424
1425         /* If MAC address zero, no need to set the AV bit */
1426         if (rar_low || rar_high)
1427                 rar_high |= E1000_RAH_AV;
1428
1429         if (index == 0) {
1430                 ew32(RAL(index), rar_low);
1431                 e1e_flush();
1432                 ew32(RAH(index), rar_high);
1433                 e1e_flush();
1434                 return;
1435         }
1436
1437         /* The manageability engine (ME) can lock certain SHRAR registers that
1438          * it is using - those registers are unavailable for use.
1439          */
1440         if (index < hw->mac.rar_entry_count) {
1441                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1442                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1443
1444                 /* Check if all SHRAR registers are locked */
1445                 if (wlock_mac == 1)
1446                         goto out;
1447
1448                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1449                         s32 ret_val;
1450
1451                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1452
1453                         if (ret_val)
1454                                 goto out;
1455
1456                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1457                         e1e_flush();
1458                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1459                         e1e_flush();
1460
1461                         e1000_release_swflag_ich8lan(hw);
1462
1463                         /* verify the register updates */
1464                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1465                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1466                                 return;
1467                 }
1468         }
1469
1470 out:
1471         e_dbg("Failed to write receive address at index %d\n", index);
1472 }
1473
1474 /**
1475  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1476  *  @hw: pointer to the HW structure
1477  *
1478  *  Checks if firmware is blocking the reset of the PHY.
1479  *  This is a function pointer entry point only called by
1480  *  reset routines.
1481  **/
1482 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1483 {
1484         u32 fwsm;
1485
1486         fwsm = er32(FWSM);
1487
1488         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
1489 }
1490
1491 /**
1492  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1493  *  @hw: pointer to the HW structure
1494  *
1495  *  Assumes semaphore already acquired.
1496  *
1497  **/
1498 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1499 {
1500         u16 phy_data;
1501         u32 strap = er32(STRAP);
1502         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1503             E1000_STRAP_SMT_FREQ_SHIFT;
1504         s32 ret_val;
1505
1506         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1507
1508         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1509         if (ret_val)
1510                 return ret_val;
1511
1512         phy_data &= ~HV_SMB_ADDR_MASK;
1513         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1514         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1515
1516         if (hw->phy.type == e1000_phy_i217) {
1517                 /* Restore SMBus frequency */
1518                 if (freq--) {
1519                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1520                         phy_data |= (freq & (1 << 0)) <<
1521                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
1522                         phy_data |= (freq & (1 << 1)) <<
1523                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1524                 } else {
1525                         e_dbg("Unsupported SMB frequency in PHY\n");
1526                 }
1527         }
1528
1529         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1530 }
1531
1532 /**
1533  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1534  *  @hw:   pointer to the HW structure
1535  *
1536  *  SW should configure the LCD from the NVM extended configuration region
1537  *  as a workaround for certain parts.
1538  **/
1539 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1540 {
1541         struct e1000_phy_info *phy = &hw->phy;
1542         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1543         s32 ret_val = 0;
1544         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1545
1546         /* Initialize the PHY from the NVM on ICH platforms.  This
1547          * is needed due to an issue where the NVM configuration is
1548          * not properly autoloaded after power transitions.
1549          * Therefore, after each PHY reset, we will load the
1550          * configuration data out of the NVM manually.
1551          */
1552         switch (hw->mac.type) {
1553         case e1000_ich8lan:
1554                 if (phy->type != e1000_phy_igp_3)
1555                         return ret_val;
1556
1557                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1558                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1559                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1560                         break;
1561                 }
1562                 /* Fall-thru */
1563         case e1000_pchlan:
1564         case e1000_pch2lan:
1565         case e1000_pch_lpt:
1566                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1567                 break;
1568         default:
1569                 return ret_val;
1570         }
1571
1572         ret_val = hw->phy.ops.acquire(hw);
1573         if (ret_val)
1574                 return ret_val;
1575
1576         data = er32(FEXTNVM);
1577         if (!(data & sw_cfg_mask))
1578                 goto release;
1579
1580         /* Make sure HW does not configure LCD from PHY
1581          * extended configuration before SW configuration
1582          */
1583         data = er32(EXTCNF_CTRL);
1584         if ((hw->mac.type < e1000_pch2lan) &&
1585             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1586                 goto release;
1587
1588         cnf_size = er32(EXTCNF_SIZE);
1589         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1590         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1591         if (!cnf_size)
1592                 goto release;
1593
1594         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1595         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1596
1597         if (((hw->mac.type == e1000_pchlan) &&
1598              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1599             (hw->mac.type > e1000_pchlan)) {
1600                 /* HW configures the SMBus address and LEDs when the
1601                  * OEM and LCD Write Enable bits are set in the NVM.
1602                  * When both NVM bits are cleared, SW will configure
1603                  * them instead.
1604                  */
1605                 ret_val = e1000_write_smbus_addr(hw);
1606                 if (ret_val)
1607                         goto release;
1608
1609                 data = er32(LEDCTL);
1610                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1611                                                         (u16)data);
1612                 if (ret_val)
1613                         goto release;
1614         }
1615
1616         /* Configure LCD from extended configuration region. */
1617
1618         /* cnf_base_addr is in DWORD */
1619         word_addr = (u16)(cnf_base_addr << 1);
1620
1621         for (i = 0; i < cnf_size; i++) {
1622                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
1623                 if (ret_val)
1624                         goto release;
1625
1626                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1627                                          1, &reg_addr);
1628                 if (ret_val)
1629                         goto release;
1630
1631                 /* Save off the PHY page for future writes. */
1632                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1633                         phy_page = reg_data;
1634                         continue;
1635                 }
1636
1637                 reg_addr &= PHY_REG_MASK;
1638                 reg_addr |= phy_page;
1639
1640                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
1641                 if (ret_val)
1642                         goto release;
1643         }
1644
1645 release:
1646         hw->phy.ops.release(hw);
1647         return ret_val;
1648 }
1649
1650 /**
1651  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1652  *  @hw:   pointer to the HW structure
1653  *  @link: link up bool flag
1654  *
1655  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1656  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1657  *  If link is down, the function will restore the default K1 setting located
1658  *  in the NVM.
1659  **/
1660 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1661 {
1662         s32 ret_val = 0;
1663         u16 status_reg = 0;
1664         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1665
1666         if (hw->mac.type != e1000_pchlan)
1667                 return 0;
1668
1669         /* Wrap the whole flow with the sw flag */
1670         ret_val = hw->phy.ops.acquire(hw);
1671         if (ret_val)
1672                 return ret_val;
1673
1674         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1675         if (link) {
1676                 if (hw->phy.type == e1000_phy_82578) {
1677                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1678                                                   &status_reg);
1679                         if (ret_val)
1680                                 goto release;
1681
1682                         status_reg &= (BM_CS_STATUS_LINK_UP |
1683                                        BM_CS_STATUS_RESOLVED |
1684                                        BM_CS_STATUS_SPEED_MASK);
1685
1686                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1687                                            BM_CS_STATUS_RESOLVED |
1688                                            BM_CS_STATUS_SPEED_1000))
1689                                 k1_enable = false;
1690                 }
1691
1692                 if (hw->phy.type == e1000_phy_82577) {
1693                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1694                         if (ret_val)
1695                                 goto release;
1696
1697                         status_reg &= (HV_M_STATUS_LINK_UP |
1698                                        HV_M_STATUS_AUTONEG_COMPLETE |
1699                                        HV_M_STATUS_SPEED_MASK);
1700
1701                         if (status_reg == (HV_M_STATUS_LINK_UP |
1702                                            HV_M_STATUS_AUTONEG_COMPLETE |
1703                                            HV_M_STATUS_SPEED_1000))
1704                                 k1_enable = false;
1705                 }
1706
1707                 /* Link stall fix for link up */
1708                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1709                 if (ret_val)
1710                         goto release;
1711
1712         } else {
1713                 /* Link stall fix for link down */
1714                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1715                 if (ret_val)
1716                         goto release;
1717         }
1718
1719         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1720
1721 release:
1722         hw->phy.ops.release(hw);
1723
1724         return ret_val;
1725 }
1726
1727 /**
1728  *  e1000_configure_k1_ich8lan - Configure K1 power state
1729  *  @hw: pointer to the HW structure
1730  *  @enable: K1 state to configure
1731  *
1732  *  Configure the K1 power state based on the provided parameter.
1733  *  Assumes semaphore already acquired.
1734  *
1735  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1736  **/
1737 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1738 {
1739         s32 ret_val;
1740         u32 ctrl_reg = 0;
1741         u32 ctrl_ext = 0;
1742         u32 reg = 0;
1743         u16 kmrn_reg = 0;
1744
1745         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1746                                               &kmrn_reg);
1747         if (ret_val)
1748                 return ret_val;
1749
1750         if (k1_enable)
1751                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1752         else
1753                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1754
1755         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1756                                                kmrn_reg);
1757         if (ret_val)
1758                 return ret_val;
1759
1760         usleep_range(20, 40);
1761         ctrl_ext = er32(CTRL_EXT);
1762         ctrl_reg = er32(CTRL);
1763
1764         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1765         reg |= E1000_CTRL_FRCSPD;
1766         ew32(CTRL, reg);
1767
1768         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1769         e1e_flush();
1770         usleep_range(20, 40);
1771         ew32(CTRL, ctrl_reg);
1772         ew32(CTRL_EXT, ctrl_ext);
1773         e1e_flush();
1774         usleep_range(20, 40);
1775
1776         return 0;
1777 }
1778
1779 /**
1780  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1781  *  @hw:       pointer to the HW structure
1782  *  @d0_state: boolean if entering d0 or d3 device state
1783  *
1784  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1785  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1786  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1787  **/
1788 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1789 {
1790         s32 ret_val = 0;
1791         u32 mac_reg;
1792         u16 oem_reg;
1793
1794         if (hw->mac.type < e1000_pchlan)
1795                 return ret_val;
1796
1797         ret_val = hw->phy.ops.acquire(hw);
1798         if (ret_val)
1799                 return ret_val;
1800
1801         if (hw->mac.type == e1000_pchlan) {
1802                 mac_reg = er32(EXTCNF_CTRL);
1803                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1804                         goto release;
1805         }
1806
1807         mac_reg = er32(FEXTNVM);
1808         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1809                 goto release;
1810
1811         mac_reg = er32(PHY_CTRL);
1812
1813         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
1814         if (ret_val)
1815                 goto release;
1816
1817         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1818
1819         if (d0_state) {
1820                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1821                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1822
1823                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1824                         oem_reg |= HV_OEM_BITS_LPLU;
1825         } else {
1826                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1827                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1828                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1829
1830                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1831                                E1000_PHY_CTRL_NOND0A_LPLU))
1832                         oem_reg |= HV_OEM_BITS_LPLU;
1833         }
1834
1835         /* Set Restart auto-neg to activate the bits */
1836         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1837             !hw->phy.ops.check_reset_block(hw))
1838                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1839
1840         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
1841
1842 release:
1843         hw->phy.ops.release(hw);
1844
1845         return ret_val;
1846 }
1847
1848 /**
1849  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1850  *  @hw:   pointer to the HW structure
1851  **/
1852 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1853 {
1854         s32 ret_val;
1855         u16 data;
1856
1857         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1858         if (ret_val)
1859                 return ret_val;
1860
1861         data |= HV_KMRN_MDIO_SLOW;
1862
1863         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1864
1865         return ret_val;
1866 }
1867
1868 /**
1869  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1870  *  done after every PHY reset.
1871  **/
1872 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1873 {
1874         s32 ret_val = 0;
1875         u16 phy_data;
1876
1877         if (hw->mac.type != e1000_pchlan)
1878                 return 0;
1879
1880         /* Set MDIO slow mode before any other MDIO access */
1881         if (hw->phy.type == e1000_phy_82577) {
1882                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1883                 if (ret_val)
1884                         return ret_val;
1885         }
1886
1887         if (((hw->phy.type == e1000_phy_82577) &&
1888              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1889             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1890                 /* Disable generation of early preamble */
1891                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1892                 if (ret_val)
1893                         return ret_val;
1894
1895                 /* Preamble tuning for SSC */
1896                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1897                 if (ret_val)
1898                         return ret_val;
1899         }
1900
1901         if (hw->phy.type == e1000_phy_82578) {
1902                 /* Return registers to default by doing a soft reset then
1903                  * writing 0x3140 to the control register.
1904                  */
1905                 if (hw->phy.revision < 2) {
1906                         e1000e_phy_sw_reset(hw);
1907                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
1908                 }
1909         }
1910
1911         /* Select page 0 */
1912         ret_val = hw->phy.ops.acquire(hw);
1913         if (ret_val)
1914                 return ret_val;
1915
1916         hw->phy.addr = 1;
1917         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1918         hw->phy.ops.release(hw);
1919         if (ret_val)
1920                 return ret_val;
1921
1922         /* Configure the K1 Si workaround during phy reset assuming there is
1923          * link so that it disables K1 if link is in 1Gbps.
1924          */
1925         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1926         if (ret_val)
1927                 return ret_val;
1928
1929         /* Workaround for link disconnects on a busy hub in half duplex */
1930         ret_val = hw->phy.ops.acquire(hw);
1931         if (ret_val)
1932                 return ret_val;
1933         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1934         if (ret_val)
1935                 goto release;
1936         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
1937         if (ret_val)
1938                 goto release;
1939
1940         /* set MSE higher to enable link to stay up when noise is high */
1941         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
1942 release:
1943         hw->phy.ops.release(hw);
1944
1945         return ret_val;
1946 }
1947
1948 /**
1949  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1950  *  @hw:   pointer to the HW structure
1951  **/
1952 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1953 {
1954         u32 mac_reg;
1955         u16 i, phy_reg = 0;
1956         s32 ret_val;
1957
1958         ret_val = hw->phy.ops.acquire(hw);
1959         if (ret_val)
1960                 return;
1961         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1962         if (ret_val)
1963                 goto release;
1964
1965         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1966         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1967                 mac_reg = er32(RAL(i));
1968                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1969                                            (u16)(mac_reg & 0xFFFF));
1970                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1971                                            (u16)((mac_reg >> 16) & 0xFFFF));
1972
1973                 mac_reg = er32(RAH(i));
1974                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1975                                            (u16)(mac_reg & 0xFFFF));
1976                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1977                                            (u16)((mac_reg & E1000_RAH_AV)
1978                                                  >> 16));
1979         }
1980
1981         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1982
1983 release:
1984         hw->phy.ops.release(hw);
1985 }
1986
1987 /**
1988  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1989  *  with 82579 PHY
1990  *  @hw: pointer to the HW structure
1991  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1992  **/
1993 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1994 {
1995         s32 ret_val = 0;
1996         u16 phy_reg, data;
1997         u32 mac_reg;
1998         u16 i;
1999
2000         if (hw->mac.type < e1000_pch2lan)
2001                 return 0;
2002
2003         /* disable Rx path while enabling/disabling workaround */
2004         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2005         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
2006         if (ret_val)
2007                 return ret_val;
2008
2009         if (enable) {
2010                 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
2011                  * SHRAL/H) and initial CRC values to the MAC
2012                  */
2013                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
2014                         u8 mac_addr[ETH_ALEN] = { 0 };
2015                         u32 addr_high, addr_low;
2016
2017                         addr_high = er32(RAH(i));
2018                         if (!(addr_high & E1000_RAH_AV))
2019                                 continue;
2020                         addr_low = er32(RAL(i));
2021                         mac_addr[0] = (addr_low & 0xFF);
2022                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2023                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2024                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2025                         mac_addr[4] = (addr_high & 0xFF);
2026                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2027
2028                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2029                 }
2030
2031                 /* Write Rx addresses to the PHY */
2032                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2033
2034                 /* Enable jumbo frame workaround in the MAC */
2035                 mac_reg = er32(FFLT_DBG);
2036                 mac_reg &= ~(1 << 14);
2037                 mac_reg |= (7 << 15);
2038                 ew32(FFLT_DBG, mac_reg);
2039
2040                 mac_reg = er32(RCTL);
2041                 mac_reg |= E1000_RCTL_SECRC;
2042                 ew32(RCTL, mac_reg);
2043
2044                 ret_val = e1000e_read_kmrn_reg(hw,
2045                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2046                                                &data);
2047                 if (ret_val)
2048                         return ret_val;
2049                 ret_val = e1000e_write_kmrn_reg(hw,
2050                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2051                                                 data | (1 << 0));
2052                 if (ret_val)
2053                         return ret_val;
2054                 ret_val = e1000e_read_kmrn_reg(hw,
2055                                                E1000_KMRNCTRLSTA_HD_CTRL,
2056                                                &data);
2057                 if (ret_val)
2058                         return ret_val;
2059                 data &= ~(0xF << 8);
2060                 data |= (0xB << 8);
2061                 ret_val = e1000e_write_kmrn_reg(hw,
2062                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2063                                                 data);
2064                 if (ret_val)
2065                         return ret_val;
2066
2067                 /* Enable jumbo frame workaround in the PHY */
2068                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2069                 data &= ~(0x7F << 5);
2070                 data |= (0x37 << 5);
2071                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2072                 if (ret_val)
2073                         return ret_val;
2074                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2075                 data &= ~(1 << 13);
2076                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2077                 if (ret_val)
2078                         return ret_val;
2079                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2080                 data &= ~(0x3FF << 2);
2081                 data |= (0x1A << 2);
2082                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2083                 if (ret_val)
2084                         return ret_val;
2085                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2086                 if (ret_val)
2087                         return ret_val;
2088                 e1e_rphy(hw, HV_PM_CTRL, &data);
2089                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2090                 if (ret_val)
2091                         return ret_val;
2092         } else {
2093                 /* Write MAC register values back to h/w defaults */
2094                 mac_reg = er32(FFLT_DBG);
2095                 mac_reg &= ~(0xF << 14);
2096                 ew32(FFLT_DBG, mac_reg);
2097
2098                 mac_reg = er32(RCTL);
2099                 mac_reg &= ~E1000_RCTL_SECRC;
2100                 ew32(RCTL, mac_reg);
2101
2102                 ret_val = e1000e_read_kmrn_reg(hw,
2103                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2104                                                &data);
2105                 if (ret_val)
2106                         return ret_val;
2107                 ret_val = e1000e_write_kmrn_reg(hw,
2108                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2109                                                 data & ~(1 << 0));
2110                 if (ret_val)
2111                         return ret_val;
2112                 ret_val = e1000e_read_kmrn_reg(hw,
2113                                                E1000_KMRNCTRLSTA_HD_CTRL,
2114                                                &data);
2115                 if (ret_val)
2116                         return ret_val;
2117                 data &= ~(0xF << 8);
2118                 data |= (0xB << 8);
2119                 ret_val = e1000e_write_kmrn_reg(hw,
2120                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2121                                                 data);
2122                 if (ret_val)
2123                         return ret_val;
2124
2125                 /* Write PHY register values back to h/w defaults */
2126                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2127                 data &= ~(0x7F << 5);
2128                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2129                 if (ret_val)
2130                         return ret_val;
2131                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2132                 data |= (1 << 13);
2133                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2134                 if (ret_val)
2135                         return ret_val;
2136                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2137                 data &= ~(0x3FF << 2);
2138                 data |= (0x8 << 2);
2139                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2140                 if (ret_val)
2141                         return ret_val;
2142                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2143                 if (ret_val)
2144                         return ret_val;
2145                 e1e_rphy(hw, HV_PM_CTRL, &data);
2146                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2147                 if (ret_val)
2148                         return ret_val;
2149         }
2150
2151         /* re-enable Rx path after enabling/disabling workaround */
2152         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2153 }
2154
2155 /**
2156  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2157  *  done after every PHY reset.
2158  **/
2159 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2160 {
2161         s32 ret_val = 0;
2162
2163         if (hw->mac.type != e1000_pch2lan)
2164                 return 0;
2165
2166         /* Set MDIO slow mode before any other MDIO access */
2167         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2168         if (ret_val)
2169                 return ret_val;
2170
2171         ret_val = hw->phy.ops.acquire(hw);
2172         if (ret_val)
2173                 return ret_val;
2174         /* set MSE higher to enable link to stay up when noise is high */
2175         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2176         if (ret_val)
2177                 goto release;
2178         /* drop link after 5 times MSE threshold was reached */
2179         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2180 release:
2181         hw->phy.ops.release(hw);
2182
2183         return ret_val;
2184 }
2185
2186 /**
2187  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2188  *  @hw:   pointer to the HW structure
2189  *
2190  *  Workaround to set the K1 beacon duration for 82579 parts
2191  **/
2192 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2193 {
2194         s32 ret_val = 0;
2195         u16 status_reg = 0;
2196         u32 mac_reg;
2197         u16 phy_reg;
2198
2199         if (hw->mac.type != e1000_pch2lan)
2200                 return 0;
2201
2202         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2203         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2204         if (ret_val)
2205                 return ret_val;
2206
2207         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2208             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2209                 mac_reg = er32(FEXTNVM4);
2210                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2211
2212                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
2213                 if (ret_val)
2214                         return ret_val;
2215
2216                 if (status_reg & HV_M_STATUS_SPEED_1000) {
2217                         u16 pm_phy_reg;
2218
2219                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2220                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2221                         /* LV 1G Packet drop issue wa  */
2222                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2223                         if (ret_val)
2224                                 return ret_val;
2225                         pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2226                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2227                         if (ret_val)
2228                                 return ret_val;
2229                 } else {
2230                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2231                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2232                 }
2233                 ew32(FEXTNVM4, mac_reg);
2234                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
2235         }
2236
2237         return ret_val;
2238 }
2239
2240 /**
2241  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2242  *  @hw:   pointer to the HW structure
2243  *  @gate: boolean set to true to gate, false to ungate
2244  *
2245  *  Gate/ungate the automatic PHY configuration via hardware; perform
2246  *  the configuration via software instead.
2247  **/
2248 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2249 {
2250         u32 extcnf_ctrl;
2251
2252         if (hw->mac.type < e1000_pch2lan)
2253                 return;
2254
2255         extcnf_ctrl = er32(EXTCNF_CTRL);
2256
2257         if (gate)
2258                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2259         else
2260                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2261
2262         ew32(EXTCNF_CTRL, extcnf_ctrl);
2263 }
2264
2265 /**
2266  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2267  *  @hw: pointer to the HW structure
2268  *
2269  *  Check the appropriate indication the MAC has finished configuring the
2270  *  PHY after a software reset.
2271  **/
2272 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2273 {
2274         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2275
2276         /* Wait for basic configuration completes before proceeding */
2277         do {
2278                 data = er32(STATUS);
2279                 data &= E1000_STATUS_LAN_INIT_DONE;
2280                 usleep_range(100, 200);
2281         } while ((!data) && --loop);
2282
2283         /* If basic configuration is incomplete before the above loop
2284          * count reaches 0, loading the configuration from NVM will
2285          * leave the PHY in a bad state possibly resulting in no link.
2286          */
2287         if (loop == 0)
2288                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2289
2290         /* Clear the Init Done bit for the next init event */
2291         data = er32(STATUS);
2292         data &= ~E1000_STATUS_LAN_INIT_DONE;
2293         ew32(STATUS, data);
2294 }
2295
2296 /**
2297  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2298  *  @hw: pointer to the HW structure
2299  **/
2300 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2301 {
2302         s32 ret_val = 0;
2303         u16 reg;
2304
2305         if (hw->phy.ops.check_reset_block(hw))
2306                 return 0;
2307
2308         /* Allow time for h/w to get to quiescent state after reset */
2309         usleep_range(10000, 20000);
2310
2311         /* Perform any necessary post-reset workarounds */
2312         switch (hw->mac.type) {
2313         case e1000_pchlan:
2314                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2315                 if (ret_val)
2316                         return ret_val;
2317                 break;
2318         case e1000_pch2lan:
2319                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2320                 if (ret_val)
2321                         return ret_val;
2322                 break;
2323         default:
2324                 break;
2325         }
2326
2327         /* Clear the host wakeup bit after lcd reset */
2328         if (hw->mac.type >= e1000_pchlan) {
2329                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2330                 reg &= ~BM_WUC_HOST_WU_BIT;
2331                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2332         }
2333
2334         /* Configure the LCD with the extended configuration region in NVM */
2335         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2336         if (ret_val)
2337                 return ret_val;
2338
2339         /* Configure the LCD with the OEM bits in NVM */
2340         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2341
2342         if (hw->mac.type == e1000_pch2lan) {
2343                 /* Ungate automatic PHY configuration on non-managed 82579 */
2344                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2345                         usleep_range(10000, 20000);
2346                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2347                 }
2348
2349                 /* Set EEE LPI Update Timer to 200usec */
2350                 ret_val = hw->phy.ops.acquire(hw);
2351                 if (ret_val)
2352                         return ret_val;
2353                 ret_val = e1000_write_emi_reg_locked(hw,
2354                                                      I82579_LPI_UPDATE_TIMER,
2355                                                      0x1387);
2356                 hw->phy.ops.release(hw);
2357         }
2358
2359         return ret_val;
2360 }
2361
2362 /**
2363  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2364  *  @hw: pointer to the HW structure
2365  *
2366  *  Resets the PHY
2367  *  This is a function pointer entry point called by drivers
2368  *  or other shared routines.
2369  **/
2370 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2371 {
2372         s32 ret_val = 0;
2373
2374         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2375         if ((hw->mac.type == e1000_pch2lan) &&
2376             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2377                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2378
2379         ret_val = e1000e_phy_hw_reset_generic(hw);
2380         if (ret_val)
2381                 return ret_val;
2382
2383         return e1000_post_phy_reset_ich8lan(hw);
2384 }
2385
2386 /**
2387  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2388  *  @hw: pointer to the HW structure
2389  *  @active: true to enable LPLU, false to disable
2390  *
2391  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2392  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2393  *  the phy speed. This function will manually set the LPLU bit and restart
2394  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2395  *  since it configures the same bit.
2396  **/
2397 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2398 {
2399         s32 ret_val;
2400         u16 oem_reg;
2401
2402         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2403         if (ret_val)
2404                 return ret_val;
2405
2406         if (active)
2407                 oem_reg |= HV_OEM_BITS_LPLU;
2408         else
2409                 oem_reg &= ~HV_OEM_BITS_LPLU;
2410
2411         if (!hw->phy.ops.check_reset_block(hw))
2412                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2413
2414         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2415 }
2416
2417 /**
2418  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2419  *  @hw: pointer to the HW structure
2420  *  @active: true to enable LPLU, false to disable
2421  *
2422  *  Sets the LPLU D0 state according to the active flag.  When
2423  *  activating LPLU this function also disables smart speed
2424  *  and vice versa.  LPLU will not be activated unless the
2425  *  device autonegotiation advertisement meets standards of
2426  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2427  *  This is a function pointer entry point only called by
2428  *  PHY setup routines.
2429  **/
2430 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2431 {
2432         struct e1000_phy_info *phy = &hw->phy;
2433         u32 phy_ctrl;
2434         s32 ret_val = 0;
2435         u16 data;
2436
2437         if (phy->type == e1000_phy_ife)
2438                 return 0;
2439
2440         phy_ctrl = er32(PHY_CTRL);
2441
2442         if (active) {
2443                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2444                 ew32(PHY_CTRL, phy_ctrl);
2445
2446                 if (phy->type != e1000_phy_igp_3)
2447                         return 0;
2448
2449                 /* Call gig speed drop workaround on LPLU before accessing
2450                  * any PHY registers
2451                  */
2452                 if (hw->mac.type == e1000_ich8lan)
2453                         e1000e_gig_downshift_workaround_ich8lan(hw);
2454
2455                 /* When LPLU is enabled, we should disable SmartSpeed */
2456                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2457                 if (ret_val)
2458                         return ret_val;
2459                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2460                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2461                 if (ret_val)
2462                         return ret_val;
2463         } else {
2464                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2465                 ew32(PHY_CTRL, phy_ctrl);
2466
2467                 if (phy->type != e1000_phy_igp_3)
2468                         return 0;
2469
2470                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2471                  * during Dx states where the power conservation is most
2472                  * important.  During driver activity we should enable
2473                  * SmartSpeed, so performance is maintained.
2474                  */
2475                 if (phy->smart_speed == e1000_smart_speed_on) {
2476                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2477                                            &data);
2478                         if (ret_val)
2479                                 return ret_val;
2480
2481                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2482                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2483                                            data);
2484                         if (ret_val)
2485                                 return ret_val;
2486                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2487                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2488                                            &data);
2489                         if (ret_val)
2490                                 return ret_val;
2491
2492                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2493                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2494                                            data);
2495                         if (ret_val)
2496                                 return ret_val;
2497                 }
2498         }
2499
2500         return 0;
2501 }
2502
2503 /**
2504  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2505  *  @hw: pointer to the HW structure
2506  *  @active: true to enable LPLU, false to disable
2507  *
2508  *  Sets the LPLU D3 state according to the active flag.  When
2509  *  activating LPLU this function also disables smart speed
2510  *  and vice versa.  LPLU will not be activated unless the
2511  *  device autonegotiation advertisement meets standards of
2512  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2513  *  This is a function pointer entry point only called by
2514  *  PHY setup routines.
2515  **/
2516 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2517 {
2518         struct e1000_phy_info *phy = &hw->phy;
2519         u32 phy_ctrl;
2520         s32 ret_val = 0;
2521         u16 data;
2522
2523         phy_ctrl = er32(PHY_CTRL);
2524
2525         if (!active) {
2526                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2527                 ew32(PHY_CTRL, phy_ctrl);
2528
2529                 if (phy->type != e1000_phy_igp_3)
2530                         return 0;
2531
2532                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2533                  * during Dx states where the power conservation is most
2534                  * important.  During driver activity we should enable
2535                  * SmartSpeed, so performance is maintained.
2536                  */
2537                 if (phy->smart_speed == e1000_smart_speed_on) {
2538                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2539                                            &data);
2540                         if (ret_val)
2541                                 return ret_val;
2542
2543                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2544                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2545                                            data);
2546                         if (ret_val)
2547                                 return ret_val;
2548                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2549                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2550                                            &data);
2551                         if (ret_val)
2552                                 return ret_val;
2553
2554                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2555                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2556                                            data);
2557                         if (ret_val)
2558                                 return ret_val;
2559                 }
2560         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2561                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2562                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2563                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2564                 ew32(PHY_CTRL, phy_ctrl);
2565
2566                 if (phy->type != e1000_phy_igp_3)
2567                         return 0;
2568
2569                 /* Call gig speed drop workaround on LPLU before accessing
2570                  * any PHY registers
2571                  */
2572                 if (hw->mac.type == e1000_ich8lan)
2573                         e1000e_gig_downshift_workaround_ich8lan(hw);
2574
2575                 /* When LPLU is enabled, we should disable SmartSpeed */
2576                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2577                 if (ret_val)
2578                         return ret_val;
2579
2580                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2581                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2582         }
2583
2584         return ret_val;
2585 }
2586
2587 /**
2588  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2589  *  @hw: pointer to the HW structure
2590  *  @bank:  pointer to the variable that returns the active bank
2591  *
2592  *  Reads signature byte from the NVM using the flash access registers.
2593  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2594  **/
2595 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2596 {
2597         u32 eecd;
2598         struct e1000_nvm_info *nvm = &hw->nvm;
2599         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2600         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2601         u8 sig_byte = 0;
2602         s32 ret_val;
2603
2604         switch (hw->mac.type) {
2605         case e1000_ich8lan:
2606         case e1000_ich9lan:
2607                 eecd = er32(EECD);
2608                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2609                     E1000_EECD_SEC1VAL_VALID_MASK) {
2610                         if (eecd & E1000_EECD_SEC1VAL)
2611                                 *bank = 1;
2612                         else
2613                                 *bank = 0;
2614
2615                         return 0;
2616                 }
2617                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2618                 /* fall-thru */
2619         default:
2620                 /* set bank to 0 in case flash read fails */
2621                 *bank = 0;
2622
2623                 /* Check bank 0 */
2624                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2625                                                         &sig_byte);
2626                 if (ret_val)
2627                         return ret_val;
2628                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2629                     E1000_ICH_NVM_SIG_VALUE) {
2630                         *bank = 0;
2631                         return 0;
2632                 }
2633
2634                 /* Check bank 1 */
2635                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2636                                                         bank1_offset,
2637                                                         &sig_byte);
2638                 if (ret_val)
2639                         return ret_val;
2640                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2641                     E1000_ICH_NVM_SIG_VALUE) {
2642                         *bank = 1;
2643                         return 0;
2644                 }
2645
2646                 e_dbg("ERROR: No valid NVM bank present\n");
2647                 return -E1000_ERR_NVM;
2648         }
2649 }
2650
2651 /**
2652  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2653  *  @hw: pointer to the HW structure
2654  *  @offset: The offset (in bytes) of the word(s) to read.
2655  *  @words: Size of data to read in words
2656  *  @data: Pointer to the word(s) to read at offset.
2657  *
2658  *  Reads a word(s) from the NVM using the flash access registers.
2659  **/
2660 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2661                                   u16 *data)
2662 {
2663         struct e1000_nvm_info *nvm = &hw->nvm;
2664         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2665         u32 act_offset;
2666         s32 ret_val = 0;
2667         u32 bank = 0;
2668         u16 i, word;
2669
2670         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2671             (words == 0)) {
2672                 e_dbg("nvm parameter(s) out of bounds\n");
2673                 ret_val = -E1000_ERR_NVM;
2674                 goto out;
2675         }
2676
2677         nvm->ops.acquire(hw);
2678
2679         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2680         if (ret_val) {
2681                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2682                 bank = 0;
2683         }
2684
2685         act_offset = (bank) ? nvm->flash_bank_size : 0;
2686         act_offset += offset;
2687
2688         ret_val = 0;
2689         for (i = 0; i < words; i++) {
2690                 if (dev_spec->shadow_ram[offset + i].modified) {
2691                         data[i] = dev_spec->shadow_ram[offset + i].value;
2692                 } else {
2693                         ret_val = e1000_read_flash_word_ich8lan(hw,
2694                                                                 act_offset + i,
2695                                                                 &word);
2696                         if (ret_val)
2697                                 break;
2698                         data[i] = word;
2699                 }
2700         }
2701
2702         nvm->ops.release(hw);
2703
2704 out:
2705         if (ret_val)
2706                 e_dbg("NVM read error: %d\n", ret_val);
2707
2708         return ret_val;
2709 }
2710
2711 /**
2712  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2713  *  @hw: pointer to the HW structure
2714  *
2715  *  This function does initial flash setup so that a new read/write/erase cycle
2716  *  can be started.
2717  **/
2718 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2719 {
2720         union ich8_hws_flash_status hsfsts;
2721         s32 ret_val = -E1000_ERR_NVM;
2722
2723         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2724
2725         /* Check if the flash descriptor is valid */
2726         if (!hsfsts.hsf_status.fldesvalid) {
2727                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
2728                 return -E1000_ERR_NVM;
2729         }
2730
2731         /* Clear FCERR and DAEL in hw status by writing 1 */
2732         hsfsts.hsf_status.flcerr = 1;
2733         hsfsts.hsf_status.dael = 1;
2734
2735         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2736
2737         /* Either we should have a hardware SPI cycle in progress
2738          * bit to check against, in order to start a new cycle or
2739          * FDONE bit should be changed in the hardware so that it
2740          * is 1 after hardware reset, which can then be used as an
2741          * indication whether a cycle is in progress or has been
2742          * completed.
2743          */
2744
2745         if (!hsfsts.hsf_status.flcinprog) {
2746                 /* There is no cycle running at present,
2747                  * so we can start a cycle.
2748                  * Begin by setting Flash Cycle Done.
2749                  */
2750                 hsfsts.hsf_status.flcdone = 1;
2751                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2752                 ret_val = 0;
2753         } else {
2754                 s32 i;
2755
2756                 /* Otherwise poll for sometime so the current
2757                  * cycle has a chance to end before giving up.
2758                  */
2759                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2760                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2761                         if (!hsfsts.hsf_status.flcinprog) {
2762                                 ret_val = 0;
2763                                 break;
2764                         }
2765                         udelay(1);
2766                 }
2767                 if (!ret_val) {
2768                         /* Successful in waiting for previous cycle to timeout,
2769                          * now set the Flash Cycle Done.
2770                          */
2771                         hsfsts.hsf_status.flcdone = 1;
2772                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2773                 } else {
2774                         e_dbg("Flash controller busy, cannot get access\n");
2775                 }
2776         }
2777
2778         return ret_val;
2779 }
2780
2781 /**
2782  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2783  *  @hw: pointer to the HW structure
2784  *  @timeout: maximum time to wait for completion
2785  *
2786  *  This function starts a flash cycle and waits for its completion.
2787  **/
2788 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2789 {
2790         union ich8_hws_flash_ctrl hsflctl;
2791         union ich8_hws_flash_status hsfsts;
2792         u32 i = 0;
2793
2794         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2795         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2796         hsflctl.hsf_ctrl.flcgo = 1;
2797         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2798
2799         /* wait till FDONE bit is set to 1 */
2800         do {
2801                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2802                 if (hsfsts.hsf_status.flcdone)
2803                         break;
2804                 udelay(1);
2805         } while (i++ < timeout);
2806
2807         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
2808                 return 0;
2809
2810         return -E1000_ERR_NVM;
2811 }
2812
2813 /**
2814  *  e1000_read_flash_word_ich8lan - Read word from flash
2815  *  @hw: pointer to the HW structure
2816  *  @offset: offset to data location
2817  *  @data: pointer to the location for storing the data
2818  *
2819  *  Reads the flash word at offset into data.  Offset is converted
2820  *  to bytes before read.
2821  **/
2822 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2823                                          u16 *data)
2824 {
2825         /* Must convert offset into bytes. */
2826         offset <<= 1;
2827
2828         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2829 }
2830
2831 /**
2832  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2833  *  @hw: pointer to the HW structure
2834  *  @offset: The offset of the byte to read.
2835  *  @data: Pointer to a byte to store the value read.
2836  *
2837  *  Reads a single byte from the NVM using the flash access registers.
2838  **/
2839 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2840                                          u8 *data)
2841 {
2842         s32 ret_val;
2843         u16 word = 0;
2844
2845         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2846         if (ret_val)
2847                 return ret_val;
2848
2849         *data = (u8)word;
2850
2851         return 0;
2852 }
2853
2854 /**
2855  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2856  *  @hw: pointer to the HW structure
2857  *  @offset: The offset (in bytes) of the byte or word to read.
2858  *  @size: Size of data to read, 1=byte 2=word
2859  *  @data: Pointer to the word to store the value read.
2860  *
2861  *  Reads a byte or word from the NVM using the flash access registers.
2862  **/
2863 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2864                                          u8 size, u16 *data)
2865 {
2866         union ich8_hws_flash_status hsfsts;
2867         union ich8_hws_flash_ctrl hsflctl;
2868         u32 flash_linear_addr;
2869         u32 flash_data = 0;
2870         s32 ret_val = -E1000_ERR_NVM;
2871         u8 count = 0;
2872
2873         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2874                 return -E1000_ERR_NVM;
2875
2876         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2877                              hw->nvm.flash_base_addr);
2878
2879         do {
2880                 udelay(1);
2881                 /* Steps */
2882                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2883                 if (ret_val)
2884                         break;
2885
2886                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2887                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2888                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2889                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2890                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2891
2892                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2893
2894                 ret_val =
2895                     e1000_flash_cycle_ich8lan(hw,
2896                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
2897
2898                 /* Check if FCERR is set to 1, if set to 1, clear it
2899                  * and try the whole sequence a few more times, else
2900                  * read in (shift in) the Flash Data0, the order is
2901                  * least significant byte first msb to lsb
2902                  */
2903                 if (!ret_val) {
2904                         flash_data = er32flash(ICH_FLASH_FDATA0);
2905                         if (size == 1)
2906                                 *data = (u8)(flash_data & 0x000000FF);
2907                         else if (size == 2)
2908                                 *data = (u16)(flash_data & 0x0000FFFF);
2909                         break;
2910                 } else {
2911                         /* If we've gotten here, then things are probably
2912                          * completely hosed, but if the error condition is
2913                          * detected, it won't hurt to give it another try...
2914                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2915                          */
2916                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2917                         if (hsfsts.hsf_status.flcerr) {
2918                                 /* Repeat for some time before giving up. */
2919                                 continue;
2920                         } else if (!hsfsts.hsf_status.flcdone) {
2921                                 e_dbg("Timeout error - flash cycle did not complete.\n");
2922                                 break;
2923                         }
2924                 }
2925         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2926
2927         return ret_val;
2928 }
2929
2930 /**
2931  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2932  *  @hw: pointer to the HW structure
2933  *  @offset: The offset (in bytes) of the word(s) to write.
2934  *  @words: Size of data to write in words
2935  *  @data: Pointer to the word(s) to write at offset.
2936  *
2937  *  Writes a byte or word to the NVM using the flash access registers.
2938  **/
2939 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2940                                    u16 *data)
2941 {
2942         struct e1000_nvm_info *nvm = &hw->nvm;
2943         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2944         u16 i;
2945
2946         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2947             (words == 0)) {
2948                 e_dbg("nvm parameter(s) out of bounds\n");
2949                 return -E1000_ERR_NVM;
2950         }
2951
2952         nvm->ops.acquire(hw);
2953
2954         for (i = 0; i < words; i++) {
2955                 dev_spec->shadow_ram[offset + i].modified = true;
2956                 dev_spec->shadow_ram[offset + i].value = data[i];
2957         }
2958
2959         nvm->ops.release(hw);
2960
2961         return 0;
2962 }
2963
2964 /**
2965  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2966  *  @hw: pointer to the HW structure
2967  *
2968  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2969  *  which writes the checksum to the shadow ram.  The changes in the shadow
2970  *  ram are then committed to the EEPROM by processing each bank at a time
2971  *  checking for the modified bit and writing only the pending changes.
2972  *  After a successful commit, the shadow ram is cleared and is ready for
2973  *  future writes.
2974  **/
2975 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2976 {
2977         struct e1000_nvm_info *nvm = &hw->nvm;
2978         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2979         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2980         s32 ret_val;
2981         u16 data;
2982
2983         ret_val = e1000e_update_nvm_checksum_generic(hw);
2984         if (ret_val)
2985                 goto out;
2986
2987         if (nvm->type != e1000_nvm_flash_sw)
2988                 goto out;
2989
2990         nvm->ops.acquire(hw);
2991
2992         /* We're writing to the opposite bank so if we're on bank 1,
2993          * write to bank 0 etc.  We also need to erase the segment that
2994          * is going to be written
2995          */
2996         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2997         if (ret_val) {
2998                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2999                 bank = 0;
3000         }
3001
3002         if (bank == 0) {
3003                 new_bank_offset = nvm->flash_bank_size;
3004                 old_bank_offset = 0;
3005                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3006                 if (ret_val)
3007                         goto release;
3008         } else {
3009                 old_bank_offset = nvm->flash_bank_size;
3010                 new_bank_offset = 0;
3011                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3012                 if (ret_val)
3013                         goto release;
3014         }
3015
3016         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3017                 /* Determine whether to write the value stored
3018                  * in the other NVM bank or a modified value stored
3019                  * in the shadow RAM
3020                  */
3021                 if (dev_spec->shadow_ram[i].modified) {
3022                         data = dev_spec->shadow_ram[i].value;
3023                 } else {
3024                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3025                                                                 old_bank_offset,
3026                                                                 &data);
3027                         if (ret_val)
3028                                 break;
3029                 }
3030
3031                 /* If the word is 0x13, then make sure the signature bits
3032                  * (15:14) are 11b until the commit has completed.
3033                  * This will allow us to write 10b which indicates the
3034                  * signature is valid.  We want to do this after the write
3035                  * has completed so that we don't mark the segment valid
3036                  * while the write is still in progress
3037                  */
3038                 if (i == E1000_ICH_NVM_SIG_WORD)
3039                         data |= E1000_ICH_NVM_SIG_MASK;
3040
3041                 /* Convert offset to bytes. */
3042                 act_offset = (i + new_bank_offset) << 1;
3043
3044                 usleep_range(100, 200);
3045                 /* Write the bytes to the new bank. */
3046                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3047                                                                act_offset,
3048                                                                (u8)data);
3049                 if (ret_val)
3050                         break;
3051
3052                 usleep_range(100, 200);
3053                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3054                                                                act_offset + 1,
3055                                                                (u8)(data >> 8));
3056                 if (ret_val)
3057                         break;
3058         }
3059
3060         /* Don't bother writing the segment valid bits if sector
3061          * programming failed.
3062          */
3063         if (ret_val) {
3064                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3065                 e_dbg("Flash commit failed.\n");
3066                 goto release;
3067         }
3068
3069         /* Finally validate the new segment by setting bit 15:14
3070          * to 10b in word 0x13 , this can be done without an
3071          * erase as well since these bits are 11 to start with
3072          * and we need to change bit 14 to 0b
3073          */
3074         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3075         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3076         if (ret_val)
3077                 goto release;
3078
3079         data &= 0xBFFF;
3080         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3081                                                        act_offset * 2 + 1,
3082                                                        (u8)(data >> 8));
3083         if (ret_val)
3084                 goto release;
3085
3086         /* And invalidate the previously valid segment by setting
3087          * its signature word (0x13) high_byte to 0b. This can be
3088          * done without an erase because flash erase sets all bits
3089          * to 1's. We can write 1's to 0's without an erase
3090          */
3091         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3092         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3093         if (ret_val)
3094                 goto release;
3095
3096         /* Great!  Everything worked, we can now clear the cached entries. */
3097         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3098                 dev_spec->shadow_ram[i].modified = false;
3099                 dev_spec->shadow_ram[i].value = 0xFFFF;
3100         }
3101
3102 release:
3103         nvm->ops.release(hw);
3104
3105         /* Reload the EEPROM, or else modifications will not appear
3106          * until after the next adapter reset.
3107          */
3108         if (!ret_val) {
3109                 nvm->ops.reload(hw);
3110                 usleep_range(10000, 20000);
3111         }
3112
3113 out:
3114         if (ret_val)
3115                 e_dbg("NVM update error: %d\n", ret_val);
3116
3117         return ret_val;
3118 }
3119
3120 /**
3121  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3122  *  @hw: pointer to the HW structure
3123  *
3124  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3125  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3126  *  calculated, in which case we need to calculate the checksum and set bit 6.
3127  **/
3128 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3129 {
3130         s32 ret_val;
3131         u16 data;
3132         u16 word;
3133         u16 valid_csum_mask;
3134
3135         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3136          * the checksum needs to be fixed.  This bit is an indication that
3137          * the NVM was prepared by OEM software and did not calculate
3138          * the checksum...a likely scenario.
3139          */
3140         switch (hw->mac.type) {
3141         case e1000_pch_lpt:
3142                 word = NVM_COMPAT;
3143                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3144                 break;
3145         default:
3146                 word = NVM_FUTURE_INIT_WORD1;
3147                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3148                 break;
3149         }
3150
3151         ret_val = e1000_read_nvm(hw, word, 1, &data);
3152         if (ret_val)
3153                 return ret_val;
3154
3155         if (!(data & valid_csum_mask)) {
3156                 data |= valid_csum_mask;
3157                 ret_val = e1000_write_nvm(hw, word, 1, &data);
3158                 if (ret_val)
3159                         return ret_val;
3160                 ret_val = e1000e_update_nvm_checksum(hw);
3161                 if (ret_val)
3162                         return ret_val;
3163         }
3164
3165         return e1000e_validate_nvm_checksum_generic(hw);
3166 }
3167
3168 /**
3169  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3170  *  @hw: pointer to the HW structure
3171  *
3172  *  To prevent malicious write/erase of the NVM, set it to be read-only
3173  *  so that the hardware ignores all write/erase cycles of the NVM via
3174  *  the flash control registers.  The shadow-ram copy of the NVM will
3175  *  still be updated, however any updates to this copy will not stick
3176  *  across driver reloads.
3177  **/
3178 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3179 {
3180         struct e1000_nvm_info *nvm = &hw->nvm;
3181         union ich8_flash_protected_range pr0;
3182         union ich8_hws_flash_status hsfsts;
3183         u32 gfpreg;
3184
3185         nvm->ops.acquire(hw);
3186
3187         gfpreg = er32flash(ICH_FLASH_GFPREG);
3188
3189         /* Write-protect GbE Sector of NVM */
3190         pr0.regval = er32flash(ICH_FLASH_PR0);
3191         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3192         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3193         pr0.range.wpe = true;
3194         ew32flash(ICH_FLASH_PR0, pr0.regval);
3195
3196         /* Lock down a subset of GbE Flash Control Registers, e.g.
3197          * PR0 to prevent the write-protection from being lifted.
3198          * Once FLOCKDN is set, the registers protected by it cannot
3199          * be written until FLOCKDN is cleared by a hardware reset.
3200          */
3201         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3202         hsfsts.hsf_status.flockdn = true;
3203         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3204
3205         nvm->ops.release(hw);
3206 }
3207
3208 /**
3209  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3210  *  @hw: pointer to the HW structure
3211  *  @offset: The offset (in bytes) of the byte/word to read.
3212  *  @size: Size of data to read, 1=byte 2=word
3213  *  @data: The byte(s) to write to the NVM.
3214  *
3215  *  Writes one/two bytes to the NVM using the flash access registers.
3216  **/
3217 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3218                                           u8 size, u16 data)
3219 {
3220         union ich8_hws_flash_status hsfsts;
3221         union ich8_hws_flash_ctrl hsflctl;
3222         u32 flash_linear_addr;
3223         u32 flash_data = 0;
3224         s32 ret_val;
3225         u8 count = 0;
3226
3227         if (size < 1 || size > 2 || data > size * 0xff ||
3228             offset > ICH_FLASH_LINEAR_ADDR_MASK)
3229                 return -E1000_ERR_NVM;
3230
3231         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3232                              hw->nvm.flash_base_addr);
3233
3234         do {
3235                 udelay(1);
3236                 /* Steps */
3237                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3238                 if (ret_val)
3239                         break;
3240
3241                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3242                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3243                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3244                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3245                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3246
3247                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3248
3249                 if (size == 1)
3250                         flash_data = (u32)data & 0x00FF;
3251                 else
3252                         flash_data = (u32)data;
3253
3254                 ew32flash(ICH_FLASH_FDATA0, flash_data);
3255
3256                 /* check if FCERR is set to 1 , if set to 1, clear it
3257                  * and try the whole sequence a few more times else done
3258                  */
3259                 ret_val =
3260                     e1000_flash_cycle_ich8lan(hw,
3261                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3262                 if (!ret_val)
3263                         break;
3264
3265                 /* If we're here, then things are most likely
3266                  * completely hosed, but if the error condition
3267                  * is detected, it won't hurt to give it another
3268                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3269                  */
3270                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3271                 if (hsfsts.hsf_status.flcerr)
3272                         /* Repeat for some time before giving up. */
3273                         continue;
3274                 if (!hsfsts.hsf_status.flcdone) {
3275                         e_dbg("Timeout error - flash cycle did not complete.\n");
3276                         break;
3277                 }
3278         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3279
3280         return ret_val;
3281 }
3282
3283 /**
3284  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3285  *  @hw: pointer to the HW structure
3286  *  @offset: The index of the byte to read.
3287  *  @data: The byte to write to the NVM.
3288  *
3289  *  Writes a single byte to the NVM using the flash access registers.
3290  **/
3291 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3292                                           u8 data)
3293 {
3294         u16 word = (u16)data;
3295
3296         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3297 }
3298
3299 /**
3300  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3301  *  @hw: pointer to the HW structure
3302  *  @offset: The offset of the byte to write.
3303  *  @byte: The byte to write to the NVM.
3304  *
3305  *  Writes a single byte to the NVM using the flash access registers.
3306  *  Goes through a retry algorithm before giving up.
3307  **/
3308 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3309                                                 u32 offset, u8 byte)
3310 {
3311         s32 ret_val;
3312         u16 program_retries;
3313
3314         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3315         if (!ret_val)
3316                 return ret_val;
3317
3318         for (program_retries = 0; program_retries < 100; program_retries++) {
3319                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3320                 usleep_range(100, 200);
3321                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3322                 if (!ret_val)
3323                         break;
3324         }
3325         if (program_retries == 100)
3326                 return -E1000_ERR_NVM;
3327
3328         return 0;
3329 }
3330
3331 /**
3332  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3333  *  @hw: pointer to the HW structure
3334  *  @bank: 0 for first bank, 1 for second bank, etc.
3335  *
3336  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3337  *  bank N is 4096 * N + flash_reg_addr.
3338  **/
3339 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3340 {
3341         struct e1000_nvm_info *nvm = &hw->nvm;
3342         union ich8_hws_flash_status hsfsts;
3343         union ich8_hws_flash_ctrl hsflctl;
3344         u32 flash_linear_addr;
3345         /* bank size is in 16bit words - adjust to bytes */
3346         u32 flash_bank_size = nvm->flash_bank_size * 2;
3347         s32 ret_val;
3348         s32 count = 0;
3349         s32 j, iteration, sector_size;
3350
3351         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3352
3353         /* Determine HW Sector size: Read BERASE bits of hw flash status
3354          * register
3355          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3356          *     consecutive sectors.  The start index for the nth Hw sector
3357          *     can be calculated as = bank * 4096 + n * 256
3358          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3359          *     The start index for the nth Hw sector can be calculated
3360          *     as = bank * 4096
3361          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3362          *     (ich9 only, otherwise error condition)
3363          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3364          */
3365         switch (hsfsts.hsf_status.berasesz) {
3366         case 0:
3367                 /* Hw sector size 256 */
3368                 sector_size = ICH_FLASH_SEG_SIZE_256;
3369                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3370                 break;
3371         case 1:
3372                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3373                 iteration = 1;
3374                 break;
3375         case 2:
3376                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3377                 iteration = 1;
3378                 break;
3379         case 3:
3380                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3381                 iteration = 1;
3382                 break;
3383         default:
3384                 return -E1000_ERR_NVM;
3385         }
3386
3387         /* Start with the base address, then add the sector offset. */
3388         flash_linear_addr = hw->nvm.flash_base_addr;
3389         flash_linear_addr += (bank) ? flash_bank_size : 0;
3390
3391         for (j = 0; j < iteration; j++) {
3392                 do {
3393                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3394
3395                         /* Steps */
3396                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3397                         if (ret_val)
3398                                 return ret_val;
3399
3400                         /* Write a value 11 (block Erase) in Flash
3401                          * Cycle field in hw flash control
3402                          */
3403                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3404                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3405                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3406
3407                         /* Write the last 24 bits of an index within the
3408                          * block into Flash Linear address field in Flash
3409                          * Address.
3410                          */
3411                         flash_linear_addr += (j * sector_size);
3412                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3413
3414                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3415                         if (!ret_val)
3416                                 break;
3417
3418                         /* Check if FCERR is set to 1.  If 1,
3419                          * clear it and try the whole sequence
3420                          * a few more times else Done
3421                          */
3422                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3423                         if (hsfsts.hsf_status.flcerr)
3424                                 /* repeat for some time before giving up */
3425                                 continue;
3426                         else if (!hsfsts.hsf_status.flcdone)
3427                                 return ret_val;
3428                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3429         }
3430
3431         return 0;
3432 }
3433
3434 /**
3435  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3436  *  @hw: pointer to the HW structure
3437  *  @data: Pointer to the LED settings
3438  *
3439  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3440  *  settings is all 0's or F's, set the LED default to a valid LED default
3441  *  setting.
3442  **/
3443 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3444 {
3445         s32 ret_val;
3446
3447         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3448         if (ret_val) {
3449                 e_dbg("NVM Read Error\n");
3450                 return ret_val;
3451         }
3452
3453         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3454                 *data = ID_LED_DEFAULT_ICH8LAN;
3455
3456         return 0;
3457 }
3458
3459 /**
3460  *  e1000_id_led_init_pchlan - store LED configurations
3461  *  @hw: pointer to the HW structure
3462  *
3463  *  PCH does not control LEDs via the LEDCTL register, rather it uses
3464  *  the PHY LED configuration register.
3465  *
3466  *  PCH also does not have an "always on" or "always off" mode which
3467  *  complicates the ID feature.  Instead of using the "on" mode to indicate
3468  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3469  *  use "link_up" mode.  The LEDs will still ID on request if there is no
3470  *  link based on logic in e1000_led_[on|off]_pchlan().
3471  **/
3472 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3473 {
3474         struct e1000_mac_info *mac = &hw->mac;
3475         s32 ret_val;
3476         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3477         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3478         u16 data, i, temp, shift;
3479
3480         /* Get default ID LED modes */
3481         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3482         if (ret_val)
3483                 return ret_val;
3484
3485         mac->ledctl_default = er32(LEDCTL);
3486         mac->ledctl_mode1 = mac->ledctl_default;
3487         mac->ledctl_mode2 = mac->ledctl_default;
3488
3489         for (i = 0; i < 4; i++) {
3490                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3491                 shift = (i * 5);
3492                 switch (temp) {
3493                 case ID_LED_ON1_DEF2:
3494                 case ID_LED_ON1_ON2:
3495                 case ID_LED_ON1_OFF2:
3496                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3497                         mac->ledctl_mode1 |= (ledctl_on << shift);
3498                         break;
3499                 case ID_LED_OFF1_DEF2:
3500                 case ID_LED_OFF1_ON2:
3501                 case ID_LED_OFF1_OFF2:
3502                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3503                         mac->ledctl_mode1 |= (ledctl_off << shift);
3504                         break;
3505                 default:
3506                         /* Do nothing */
3507                         break;
3508                 }
3509                 switch (temp) {
3510                 case ID_LED_DEF1_ON2:
3511                 case ID_LED_ON1_ON2:
3512                 case ID_LED_OFF1_ON2:
3513                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3514                         mac->ledctl_mode2 |= (ledctl_on << shift);
3515                         break;
3516                 case ID_LED_DEF1_OFF2:
3517                 case ID_LED_ON1_OFF2:
3518                 case ID_LED_OFF1_OFF2:
3519                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3520                         mac->ledctl_mode2 |= (ledctl_off << shift);
3521                         break;
3522                 default:
3523                         /* Do nothing */
3524                         break;
3525                 }
3526         }
3527
3528         return 0;
3529 }
3530
3531 /**
3532  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3533  *  @hw: pointer to the HW structure
3534  *
3535  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3536  *  register, so the the bus width is hard coded.
3537  **/
3538 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3539 {
3540         struct e1000_bus_info *bus = &hw->bus;
3541         s32 ret_val;
3542
3543         ret_val = e1000e_get_bus_info_pcie(hw);
3544
3545         /* ICH devices are "PCI Express"-ish.  They have
3546          * a configuration space, but do not contain
3547          * PCI Express Capability registers, so bus width
3548          * must be hardcoded.
3549          */
3550         if (bus->width == e1000_bus_width_unknown)
3551                 bus->width = e1000_bus_width_pcie_x1;
3552
3553         return ret_val;
3554 }
3555
3556 /**
3557  *  e1000_reset_hw_ich8lan - Reset the hardware
3558  *  @hw: pointer to the HW structure
3559  *
3560  *  Does a full reset of the hardware which includes a reset of the PHY and
3561  *  MAC.
3562  **/
3563 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3564 {
3565         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3566         u16 kum_cfg;
3567         u32 ctrl, reg;
3568         s32 ret_val;
3569
3570         /* Prevent the PCI-E bus from sticking if there is no TLP connection
3571          * on the last TLP read/write transaction when MAC is reset.
3572          */
3573         ret_val = e1000e_disable_pcie_master(hw);
3574         if (ret_val)
3575                 e_dbg("PCI-E Master disable polling has failed.\n");
3576
3577         e_dbg("Masking off all interrupts\n");
3578         ew32(IMC, 0xffffffff);
3579
3580         /* Disable the Transmit and Receive units.  Then delay to allow
3581          * any pending transactions to complete before we hit the MAC
3582          * with the global reset.
3583          */
3584         ew32(RCTL, 0);
3585         ew32(TCTL, E1000_TCTL_PSP);
3586         e1e_flush();
3587
3588         usleep_range(10000, 20000);
3589
3590         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3591         if (hw->mac.type == e1000_ich8lan) {
3592                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3593                 ew32(PBA, E1000_PBA_8K);
3594                 /* Set Packet Buffer Size to 16k. */
3595                 ew32(PBS, E1000_PBS_16K);
3596         }
3597
3598         if (hw->mac.type == e1000_pchlan) {
3599                 /* Save the NVM K1 bit setting */
3600                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3601                 if (ret_val)
3602                         return ret_val;
3603
3604                 if (kum_cfg & E1000_NVM_K1_ENABLE)
3605                         dev_spec->nvm_k1_enabled = true;
3606                 else
3607                         dev_spec->nvm_k1_enabled = false;
3608         }
3609
3610         ctrl = er32(CTRL);
3611
3612         if (!hw->phy.ops.check_reset_block(hw)) {
3613                 /* Full-chip reset requires MAC and PHY reset at the same
3614                  * time to make sure the interface between MAC and the
3615                  * external PHY is reset.
3616                  */
3617                 ctrl |= E1000_CTRL_PHY_RST;
3618
3619                 /* Gate automatic PHY configuration by hardware on
3620                  * non-managed 82579
3621                  */
3622                 if ((hw->mac.type == e1000_pch2lan) &&
3623                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3624                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3625         }
3626         ret_val = e1000_acquire_swflag_ich8lan(hw);
3627         e_dbg("Issuing a global reset to ich8lan\n");
3628         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3629         /* cannot issue a flush here because it hangs the hardware */
3630         msleep(20);
3631
3632         /* Set Phy Config Counter to 50msec */
3633         if (hw->mac.type == e1000_pch2lan) {
3634                 reg = er32(FEXTNVM3);
3635                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3636                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3637                 ew32(FEXTNVM3, reg);
3638         }
3639
3640         if (!ret_val)
3641                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3642
3643         if (ctrl & E1000_CTRL_PHY_RST) {
3644                 ret_val = hw->phy.ops.get_cfg_done(hw);
3645                 if (ret_val)
3646                         return ret_val;
3647
3648                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3649                 if (ret_val)
3650                         return ret_val;
3651         }
3652
3653         /* For PCH, this write will make sure that any noise
3654          * will be detected as a CRC error and be dropped rather than show up
3655          * as a bad packet to the DMA engine.
3656          */
3657         if (hw->mac.type == e1000_pchlan)
3658                 ew32(CRC_OFFSET, 0x65656565);
3659
3660         ew32(IMC, 0xffffffff);
3661         er32(ICR);
3662
3663         reg = er32(KABGTXD);
3664         reg |= E1000_KABGTXD_BGSQLBIAS;
3665         ew32(KABGTXD, reg);
3666
3667         return 0;
3668 }
3669
3670 /**
3671  *  e1000_init_hw_ich8lan - Initialize the hardware
3672  *  @hw: pointer to the HW structure
3673  *
3674  *  Prepares the hardware for transmit and receive by doing the following:
3675  *   - initialize hardware bits
3676  *   - initialize LED identification
3677  *   - setup receive address registers
3678  *   - setup flow control
3679  *   - setup transmit descriptors
3680  *   - clear statistics
3681  **/
3682 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3683 {
3684         struct e1000_mac_info *mac = &hw->mac;
3685         u32 ctrl_ext, txdctl, snoop;
3686         s32 ret_val;
3687         u16 i;
3688
3689         e1000_initialize_hw_bits_ich8lan(hw);
3690
3691         /* Initialize identification LED */
3692         ret_val = mac->ops.id_led_init(hw);
3693         /* An error is not fatal and we should not stop init due to this */
3694         if (ret_val)
3695                 e_dbg("Error initializing identification LED\n");
3696
3697         /* Setup the receive address. */
3698         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3699
3700         /* Zero out the Multicast HASH table */
3701         e_dbg("Zeroing the MTA\n");
3702         for (i = 0; i < mac->mta_reg_count; i++)
3703                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3704
3705         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3706          * the ME.  Disable wakeup by clearing the host wakeup bit.
3707          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3708          */
3709         if (hw->phy.type == e1000_phy_82578) {
3710                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3711                 i &= ~BM_WUC_HOST_WU_BIT;
3712                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3713                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3714                 if (ret_val)
3715                         return ret_val;
3716         }
3717
3718         /* Setup link and flow control */
3719         ret_val = mac->ops.setup_link(hw);
3720
3721         /* Set the transmit descriptor write-back policy for both queues */
3722         txdctl = er32(TXDCTL(0));
3723         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3724                   E1000_TXDCTL_FULL_TX_DESC_WB);
3725         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3726                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
3727         ew32(TXDCTL(0), txdctl);
3728         txdctl = er32(TXDCTL(1));
3729         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3730                   E1000_TXDCTL_FULL_TX_DESC_WB);
3731         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3732                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
3733         ew32(TXDCTL(1), txdctl);
3734
3735         /* ICH8 has opposite polarity of no_snoop bits.
3736          * By default, we should use snoop behavior.
3737          */
3738         if (mac->type == e1000_ich8lan)
3739                 snoop = PCIE_ICH8_SNOOP_ALL;
3740         else
3741                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
3742         e1000e_set_pcie_no_snoop(hw, snoop);
3743
3744         ctrl_ext = er32(CTRL_EXT);
3745         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3746         ew32(CTRL_EXT, ctrl_ext);
3747
3748         /* Clear all of the statistics registers (clear on read).  It is
3749          * important that we do this after we have tried to establish link
3750          * because the symbol error count will increment wildly if there
3751          * is no link.
3752          */
3753         e1000_clear_hw_cntrs_ich8lan(hw);
3754
3755         return ret_val;
3756 }
3757
3758 /**
3759  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3760  *  @hw: pointer to the HW structure
3761  *
3762  *  Sets/Clears required hardware bits necessary for correctly setting up the
3763  *  hardware for transmit and receive.
3764  **/
3765 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3766 {
3767         u32 reg;
3768
3769         /* Extended Device Control */
3770         reg = er32(CTRL_EXT);
3771         reg |= (1 << 22);
3772         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3773         if (hw->mac.type >= e1000_pchlan)
3774                 reg |= E1000_CTRL_EXT_PHYPDEN;
3775         ew32(CTRL_EXT, reg);
3776
3777         /* Transmit Descriptor Control 0 */
3778         reg = er32(TXDCTL(0));
3779         reg |= (1 << 22);
3780         ew32(TXDCTL(0), reg);
3781
3782         /* Transmit Descriptor Control 1 */
3783         reg = er32(TXDCTL(1));
3784         reg |= (1 << 22);
3785         ew32(TXDCTL(1), reg);
3786
3787         /* Transmit Arbitration Control 0 */
3788         reg = er32(TARC(0));
3789         if (hw->mac.type == e1000_ich8lan)
3790                 reg |= (1 << 28) | (1 << 29);
3791         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3792         ew32(TARC(0), reg);
3793
3794         /* Transmit Arbitration Control 1 */
3795         reg = er32(TARC(1));
3796         if (er32(TCTL) & E1000_TCTL_MULR)
3797                 reg &= ~(1 << 28);
3798         else
3799                 reg |= (1 << 28);
3800         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3801         ew32(TARC(1), reg);
3802
3803         /* Device Status */
3804         if (hw->mac.type == e1000_ich8lan) {
3805                 reg = er32(STATUS);
3806                 reg &= ~(1 << 31);
3807                 ew32(STATUS, reg);
3808         }
3809
3810         /* work-around descriptor data corruption issue during nfs v2 udp
3811          * traffic, just disable the nfs filtering capability
3812          */
3813         reg = er32(RFCTL);
3814         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3815
3816         /* Disable IPv6 extension header parsing because some malformed
3817          * IPv6 headers can hang the Rx.
3818          */
3819         if (hw->mac.type == e1000_ich8lan)
3820                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
3821         ew32(RFCTL, reg);
3822
3823         /* Enable ECC on Lynxpoint */
3824         if (hw->mac.type == e1000_pch_lpt) {
3825                 reg = er32(PBECCSTS);
3826                 reg |= E1000_PBECCSTS_ECC_ENABLE;
3827                 ew32(PBECCSTS, reg);
3828
3829                 reg = er32(CTRL);
3830                 reg |= E1000_CTRL_MEHE;
3831                 ew32(CTRL, reg);
3832         }
3833 }
3834
3835 /**
3836  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3837  *  @hw: pointer to the HW structure
3838  *
3839  *  Determines which flow control settings to use, then configures flow
3840  *  control.  Calls the appropriate media-specific link configuration
3841  *  function.  Assuming the adapter has a valid link partner, a valid link
3842  *  should be established.  Assumes the hardware has previously been reset
3843  *  and the transmitter and receiver are not enabled.
3844  **/
3845 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3846 {
3847         s32 ret_val;
3848
3849         if (hw->phy.ops.check_reset_block(hw))
3850                 return 0;
3851
3852         /* ICH parts do not have a word in the NVM to determine
3853          * the default flow control setting, so we explicitly
3854          * set it to full.
3855          */
3856         if (hw->fc.requested_mode == e1000_fc_default) {
3857                 /* Workaround h/w hang when Tx flow control enabled */
3858                 if (hw->mac.type == e1000_pchlan)
3859                         hw->fc.requested_mode = e1000_fc_rx_pause;
3860                 else
3861                         hw->fc.requested_mode = e1000_fc_full;
3862         }
3863
3864         /* Save off the requested flow control mode for use later.  Depending
3865          * on the link partner's capabilities, we may or may not use this mode.
3866          */
3867         hw->fc.current_mode = hw->fc.requested_mode;
3868
3869         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
3870
3871         /* Continue to configure the copper link. */
3872         ret_val = hw->mac.ops.setup_physical_interface(hw);
3873         if (ret_val)
3874                 return ret_val;
3875
3876         ew32(FCTTV, hw->fc.pause_time);
3877         if ((hw->phy.type == e1000_phy_82578) ||
3878             (hw->phy.type == e1000_phy_82579) ||
3879             (hw->phy.type == e1000_phy_i217) ||
3880             (hw->phy.type == e1000_phy_82577)) {
3881                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3882
3883                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3884                                    hw->fc.pause_time);
3885                 if (ret_val)
3886                         return ret_val;
3887         }
3888
3889         return e1000e_set_fc_watermarks(hw);
3890 }
3891
3892 /**
3893  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3894  *  @hw: pointer to the HW structure
3895  *
3896  *  Configures the kumeran interface to the PHY to wait the appropriate time
3897  *  when polling the PHY, then call the generic setup_copper_link to finish
3898  *  configuring the copper link.
3899  **/
3900 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3901 {
3902         u32 ctrl;
3903         s32 ret_val;
3904         u16 reg_data;
3905
3906         ctrl = er32(CTRL);
3907         ctrl |= E1000_CTRL_SLU;
3908         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3909         ew32(CTRL, ctrl);
3910
3911         /* Set the mac to wait the maximum time between each iteration
3912          * and increase the max iterations when polling the phy;
3913          * this fixes erroneous timeouts at 10Mbps.
3914          */
3915         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3916         if (ret_val)
3917                 return ret_val;
3918         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3919                                        &reg_data);
3920         if (ret_val)
3921                 return ret_val;
3922         reg_data |= 0x3F;
3923         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3924                                         reg_data);
3925         if (ret_val)
3926                 return ret_val;
3927
3928         switch (hw->phy.type) {
3929         case e1000_phy_igp_3:
3930                 ret_val = e1000e_copper_link_setup_igp(hw);
3931                 if (ret_val)
3932                         return ret_val;
3933                 break;
3934         case e1000_phy_bm:
3935         case e1000_phy_82578:
3936                 ret_val = e1000e_copper_link_setup_m88(hw);
3937                 if (ret_val)
3938                         return ret_val;
3939                 break;
3940         case e1000_phy_82577:
3941         case e1000_phy_82579:
3942                 ret_val = e1000_copper_link_setup_82577(hw);
3943                 if (ret_val)
3944                         return ret_val;
3945                 break;
3946         case e1000_phy_ife:
3947                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3948                 if (ret_val)
3949                         return ret_val;
3950
3951                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3952
3953                 switch (hw->phy.mdix) {
3954                 case 1:
3955                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3956                         break;
3957                 case 2:
3958                         reg_data |= IFE_PMC_FORCE_MDIX;
3959                         break;
3960                 case 0:
3961                 default:
3962                         reg_data |= IFE_PMC_AUTO_MDIX;
3963                         break;
3964                 }
3965                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3966                 if (ret_val)
3967                         return ret_val;
3968                 break;
3969         default:
3970                 break;
3971         }
3972
3973         return e1000e_setup_copper_link(hw);
3974 }
3975
3976 /**
3977  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
3978  *  @hw: pointer to the HW structure
3979  *
3980  *  Calls the PHY specific link setup function and then calls the
3981  *  generic setup_copper_link to finish configuring the link for
3982  *  Lynxpoint PCH devices
3983  **/
3984 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
3985 {
3986         u32 ctrl;
3987         s32 ret_val;
3988
3989         ctrl = er32(CTRL);
3990         ctrl |= E1000_CTRL_SLU;
3991         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3992         ew32(CTRL, ctrl);
3993
3994         ret_val = e1000_copper_link_setup_82577(hw);
3995         if (ret_val)
3996                 return ret_val;
3997
3998         return e1000e_setup_copper_link(hw);
3999 }
4000
4001 /**
4002  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4003  *  @hw: pointer to the HW structure
4004  *  @speed: pointer to store current link speed
4005  *  @duplex: pointer to store the current link duplex
4006  *
4007  *  Calls the generic get_speed_and_duplex to retrieve the current link
4008  *  information and then calls the Kumeran lock loss workaround for links at
4009  *  gigabit speeds.
4010  **/
4011 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4012                                           u16 *duplex)
4013 {
4014         s32 ret_val;
4015
4016         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
4017         if (ret_val)
4018                 return ret_val;
4019
4020         if ((hw->mac.type == e1000_ich8lan) &&
4021             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
4022                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4023         }
4024
4025         return ret_val;
4026 }
4027
4028 /**
4029  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4030  *  @hw: pointer to the HW structure
4031  *
4032  *  Work-around for 82566 Kumeran PCS lock loss:
4033  *  On link status change (i.e. PCI reset, speed change) and link is up and
4034  *  speed is gigabit-
4035  *    0) if workaround is optionally disabled do nothing
4036  *    1) wait 1ms for Kumeran link to come up
4037  *    2) check Kumeran Diagnostic register PCS lock loss bit
4038  *    3) if not set the link is locked (all is good), otherwise...
4039  *    4) reset the PHY
4040  *    5) repeat up to 10 times
4041  *  Note: this is only called for IGP3 copper when speed is 1gb.
4042  **/
4043 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4044 {
4045         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4046         u32 phy_ctrl;
4047         s32 ret_val;
4048         u16 i, data;
4049         bool link;
4050
4051         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4052                 return 0;
4053
4054         /* Make sure link is up before proceeding.  If not just return.
4055          * Attempting this while link is negotiating fouled up link
4056          * stability
4057          */
4058         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
4059         if (!link)
4060                 return 0;
4061
4062         for (i = 0; i < 10; i++) {
4063                 /* read once to clear */
4064                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4065                 if (ret_val)
4066                         return ret_val;
4067                 /* and again to get new status */
4068                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4069                 if (ret_val)
4070                         return ret_val;
4071
4072                 /* check for PCS lock */
4073                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4074                         return 0;
4075
4076                 /* Issue PHY reset */
4077                 e1000_phy_hw_reset(hw);
4078                 mdelay(5);
4079         }
4080         /* Disable GigE link negotiation */
4081         phy_ctrl = er32(PHY_CTRL);
4082         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4083                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4084         ew32(PHY_CTRL, phy_ctrl);
4085
4086         /* Call gig speed drop workaround on Gig disable before accessing
4087          * any PHY registers
4088          */
4089         e1000e_gig_downshift_workaround_ich8lan(hw);
4090
4091         /* unable to acquire PCS lock */
4092         return -E1000_ERR_PHY;
4093 }
4094
4095 /**
4096  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4097  *  @hw: pointer to the HW structure
4098  *  @state: boolean value used to set the current Kumeran workaround state
4099  *
4100  *  If ICH8, set the current Kumeran workaround state (enabled - true
4101  *  /disabled - false).
4102  **/
4103 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4104                                                   bool state)
4105 {
4106         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4107
4108         if (hw->mac.type != e1000_ich8lan) {
4109                 e_dbg("Workaround applies to ICH8 only.\n");
4110                 return;
4111         }
4112
4113         dev_spec->kmrn_lock_loss_workaround_enabled = state;
4114 }
4115
4116 /**
4117  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4118  *  @hw: pointer to the HW structure
4119  *
4120  *  Workaround for 82566 power-down on D3 entry:
4121  *    1) disable gigabit link
4122  *    2) write VR power-down enable
4123  *    3) read it back
4124  *  Continue if successful, else issue LCD reset and repeat
4125  **/
4126 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4127 {
4128         u32 reg;
4129         u16 data;
4130         u8 retry = 0;
4131
4132         if (hw->phy.type != e1000_phy_igp_3)
4133                 return;
4134
4135         /* Try the workaround twice (if needed) */
4136         do {
4137                 /* Disable link */
4138                 reg = er32(PHY_CTRL);
4139                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4140                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4141                 ew32(PHY_CTRL, reg);
4142
4143                 /* Call gig speed drop workaround on Gig disable before
4144                  * accessing any PHY registers
4145                  */
4146                 if (hw->mac.type == e1000_ich8lan)
4147                         e1000e_gig_downshift_workaround_ich8lan(hw);
4148
4149                 /* Write VR power-down enable */
4150                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4151                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4152                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4153
4154                 /* Read it back and test */
4155                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4156                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4157                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4158                         break;
4159
4160                 /* Issue PHY reset and repeat at most one more time */
4161                 reg = er32(CTRL);
4162                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4163                 retry++;
4164         } while (retry);
4165 }
4166
4167 /**
4168  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4169  *  @hw: pointer to the HW structure
4170  *
4171  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4172  *  LPLU, Gig disable, MDIC PHY reset):
4173  *    1) Set Kumeran Near-end loopback
4174  *    2) Clear Kumeran Near-end loopback
4175  *  Should only be called for ICH8[m] devices with any 1G Phy.
4176  **/
4177 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4178 {
4179         s32 ret_val;
4180         u16 reg_data;
4181
4182         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
4183                 return;
4184
4185         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4186                                        &reg_data);
4187         if (ret_val)
4188                 return;
4189         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4190         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4191                                         reg_data);
4192         if (ret_val)
4193                 return;
4194         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4195         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
4196 }
4197
4198 /**
4199  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4200  *  @hw: pointer to the HW structure
4201  *
4202  *  During S0 to Sx transition, it is possible the link remains at gig
4203  *  instead of negotiating to a lower speed.  Before going to Sx, set
4204  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4205  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4206  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4207  *  needs to be written.
4208  *  Parts that support (and are linked to a partner which support) EEE in
4209  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4210  *  than 10Mbps w/o EEE.
4211  **/
4212 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4213 {
4214         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4215         u32 phy_ctrl;
4216         s32 ret_val;
4217
4218         phy_ctrl = er32(PHY_CTRL);
4219         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4220
4221         if (hw->phy.type == e1000_phy_i217) {
4222                 u16 phy_reg, device_id = hw->adapter->pdev->device;
4223
4224                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4225                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4226                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4227                     (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4228                         u32 fextnvm6 = er32(FEXTNVM6);
4229
4230                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4231                 }
4232
4233                 ret_val = hw->phy.ops.acquire(hw);
4234                 if (ret_val)
4235                         goto out;
4236
4237                 if (!dev_spec->eee_disable) {
4238                         u16 eee_advert;
4239
4240                         ret_val =
4241                             e1000_read_emi_reg_locked(hw,
4242                                                       I217_EEE_ADVERTISEMENT,
4243                                                       &eee_advert);
4244                         if (ret_val)
4245                                 goto release;
4246
4247                         /* Disable LPLU if both link partners support 100BaseT
4248                          * EEE and 100Full is advertised on both ends of the
4249                          * link.
4250                          */
4251                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4252                             (dev_spec->eee_lp_ability &
4253                              I82579_EEE_100_SUPPORTED) &&
4254                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4255                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4256                                               E1000_PHY_CTRL_NOND0A_LPLU);
4257                 }
4258
4259                 /* For i217 Intel Rapid Start Technology support,
4260                  * when the system is going into Sx and no manageability engine
4261                  * is present, the driver must configure proxy to reset only on
4262                  * power good.  LPI (Low Power Idle) state must also reset only
4263                  * on power good, as well as the MTA (Multicast table array).
4264                  * The SMBus release must also be disabled on LCD reset.
4265                  */
4266                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4267                         /* Enable proxy to reset only on power good. */
4268                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4269                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4270                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4271
4272                         /* Set bit enable LPI (EEE) to reset only on
4273                          * power good.
4274                          */
4275                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4276                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4277                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4278
4279                         /* Disable the SMB release on LCD reset. */
4280                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4281                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4282                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4283                 }
4284
4285                 /* Enable MTA to reset for Intel Rapid Start Technology
4286                  * Support
4287                  */
4288                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4289                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4290                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4291
4292 release:
4293                 hw->phy.ops.release(hw);
4294         }
4295 out:
4296         ew32(PHY_CTRL, phy_ctrl);
4297
4298         if (hw->mac.type == e1000_ich8lan)
4299                 e1000e_gig_downshift_workaround_ich8lan(hw);
4300
4301         if (hw->mac.type >= e1000_pchlan) {
4302                 e1000_oem_bits_config_ich8lan(hw, false);
4303
4304                 /* Reset PHY to activate OEM bits on 82577/8 */
4305                 if (hw->mac.type == e1000_pchlan)
4306                         e1000e_phy_hw_reset_generic(hw);
4307
4308                 ret_val = hw->phy.ops.acquire(hw);
4309                 if (ret_val)
4310                         return;
4311                 e1000_write_smbus_addr(hw);
4312                 hw->phy.ops.release(hw);
4313         }
4314 }
4315
4316 /**
4317  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4318  *  @hw: pointer to the HW structure
4319  *
4320  *  During Sx to S0 transitions on non-managed devices or managed devices
4321  *  on which PHY resets are not blocked, if the PHY registers cannot be
4322  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4323  *  the PHY.
4324  *  On i217, setup Intel Rapid Start Technology.
4325  **/
4326 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4327 {
4328         s32 ret_val;
4329
4330         if (hw->mac.type < e1000_pch2lan)
4331                 return;
4332
4333         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4334         if (ret_val) {
4335                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4336                 return;
4337         }
4338
4339         /* For i217 Intel Rapid Start Technology support when the system
4340          * is transitioning from Sx and no manageability engine is present
4341          * configure SMBus to restore on reset, disable proxy, and enable
4342          * the reset on MTA (Multicast table array).
4343          */
4344         if (hw->phy.type == e1000_phy_i217) {
4345                 u16 phy_reg;
4346
4347                 ret_val = hw->phy.ops.acquire(hw);
4348                 if (ret_val) {
4349                         e_dbg("Failed to setup iRST\n");
4350                         return;
4351                 }
4352
4353                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4354                         /* Restore clear on SMB if no manageability engine
4355                          * is present
4356                          */
4357                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4358                         if (ret_val)
4359                                 goto release;
4360                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4361                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4362
4363                         /* Disable Proxy */
4364                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4365                 }
4366                 /* Enable reset on MTA */
4367                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4368                 if (ret_val)
4369                         goto release;
4370                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4371                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4372 release:
4373                 if (ret_val)
4374                         e_dbg("Error %d in resume workarounds\n", ret_val);
4375                 hw->phy.ops.release(hw);
4376         }
4377 }
4378
4379 /**
4380  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4381  *  @hw: pointer to the HW structure
4382  *
4383  *  Return the LED back to the default configuration.
4384  **/
4385 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4386 {
4387         if (hw->phy.type == e1000_phy_ife)
4388                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4389
4390         ew32(LEDCTL, hw->mac.ledctl_default);
4391         return 0;
4392 }
4393
4394 /**
4395  *  e1000_led_on_ich8lan - Turn LEDs on
4396  *  @hw: pointer to the HW structure
4397  *
4398  *  Turn on the LEDs.
4399  **/
4400 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4401 {
4402         if (hw->phy.type == e1000_phy_ife)
4403                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4404                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4405
4406         ew32(LEDCTL, hw->mac.ledctl_mode2);
4407         return 0;
4408 }
4409
4410 /**
4411  *  e1000_led_off_ich8lan - Turn LEDs off
4412  *  @hw: pointer to the HW structure
4413  *
4414  *  Turn off the LEDs.
4415  **/
4416 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4417 {
4418         if (hw->phy.type == e1000_phy_ife)
4419                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4420                                 (IFE_PSCL_PROBE_MODE |
4421                                  IFE_PSCL_PROBE_LEDS_OFF));
4422
4423         ew32(LEDCTL, hw->mac.ledctl_mode1);
4424         return 0;
4425 }
4426
4427 /**
4428  *  e1000_setup_led_pchlan - Configures SW controllable LED
4429  *  @hw: pointer to the HW structure
4430  *
4431  *  This prepares the SW controllable LED for use.
4432  **/
4433 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4434 {
4435         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4436 }
4437
4438 /**
4439  *  e1000_cleanup_led_pchlan - Restore the default LED operation
4440  *  @hw: pointer to the HW structure
4441  *
4442  *  Return the LED back to the default configuration.
4443  **/
4444 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4445 {
4446         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4447 }
4448
4449 /**
4450  *  e1000_led_on_pchlan - Turn LEDs on
4451  *  @hw: pointer to the HW structure
4452  *
4453  *  Turn on the LEDs.
4454  **/
4455 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4456 {
4457         u16 data = (u16)hw->mac.ledctl_mode2;
4458         u32 i, led;
4459
4460         /* If no link, then turn LED on by setting the invert bit
4461          * for each LED that's mode is "link_up" in ledctl_mode2.
4462          */
4463         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4464                 for (i = 0; i < 3; i++) {
4465                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4466                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4467                             E1000_LEDCTL_MODE_LINK_UP)
4468                                 continue;
4469                         if (led & E1000_PHY_LED0_IVRT)
4470                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4471                         else
4472                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4473                 }
4474         }
4475
4476         return e1e_wphy(hw, HV_LED_CONFIG, data);
4477 }
4478
4479 /**
4480  *  e1000_led_off_pchlan - Turn LEDs off
4481  *  @hw: pointer to the HW structure
4482  *
4483  *  Turn off the LEDs.
4484  **/
4485 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4486 {
4487         u16 data = (u16)hw->mac.ledctl_mode1;
4488         u32 i, led;
4489
4490         /* If no link, then turn LED off by clearing the invert bit
4491          * for each LED that's mode is "link_up" in ledctl_mode1.
4492          */
4493         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4494                 for (i = 0; i < 3; i++) {
4495                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4496                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4497                             E1000_LEDCTL_MODE_LINK_UP)
4498                                 continue;
4499                         if (led & E1000_PHY_LED0_IVRT)
4500                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4501                         else
4502                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4503                 }
4504         }
4505
4506         return e1e_wphy(hw, HV_LED_CONFIG, data);
4507 }
4508
4509 /**
4510  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4511  *  @hw: pointer to the HW structure
4512  *
4513  *  Read appropriate register for the config done bit for completion status
4514  *  and configure the PHY through s/w for EEPROM-less parts.
4515  *
4516  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
4517  *  config done bit, so only an error is logged and continues.  If we were
4518  *  to return with error, EEPROM-less silicon would not be able to be reset
4519  *  or change link.
4520  **/
4521 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4522 {
4523         s32 ret_val = 0;
4524         u32 bank = 0;
4525         u32 status;
4526
4527         e1000e_get_cfg_done_generic(hw);
4528
4529         /* Wait for indication from h/w that it has completed basic config */
4530         if (hw->mac.type >= e1000_ich10lan) {
4531                 e1000_lan_init_done_ich8lan(hw);
4532         } else {
4533                 ret_val = e1000e_get_auto_rd_done(hw);
4534                 if (ret_val) {
4535                         /* When auto config read does not complete, do not
4536                          * return with an error. This can happen in situations
4537                          * where there is no eeprom and prevents getting link.
4538                          */
4539                         e_dbg("Auto Read Done did not complete\n");
4540                         ret_val = 0;
4541                 }
4542         }
4543
4544         /* Clear PHY Reset Asserted bit */
4545         status = er32(STATUS);
4546         if (status & E1000_STATUS_PHYRA)
4547                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4548         else
4549                 e_dbg("PHY Reset Asserted not set - needs delay\n");
4550
4551         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4552         if (hw->mac.type <= e1000_ich9lan) {
4553                 if (!(er32(EECD) & E1000_EECD_PRES) &&
4554                     (hw->phy.type == e1000_phy_igp_3)) {
4555                         e1000e_phy_init_script_igp3(hw);
4556                 }
4557         } else {
4558                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4559                         /* Maybe we should do a basic PHY config */
4560                         e_dbg("EEPROM not present\n");
4561                         ret_val = -E1000_ERR_CONFIG;
4562                 }
4563         }
4564
4565         return ret_val;
4566 }
4567
4568 /**
4569  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4570  * @hw: pointer to the HW structure
4571  *
4572  * In the case of a PHY power down to save power, or to turn off link during a
4573  * driver unload, or wake on lan is not enabled, remove the link.
4574  **/
4575 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4576 {
4577         /* If the management interface is not enabled, then power down */
4578         if (!(hw->mac.ops.check_mng_mode(hw) ||
4579               hw->phy.ops.check_reset_block(hw)))
4580                 e1000_power_down_phy_copper(hw);
4581 }
4582
4583 /**
4584  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4585  *  @hw: pointer to the HW structure
4586  *
4587  *  Clears hardware counters specific to the silicon family and calls
4588  *  clear_hw_cntrs_generic to clear all general purpose counters.
4589  **/
4590 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4591 {
4592         u16 phy_data;
4593         s32 ret_val;
4594
4595         e1000e_clear_hw_cntrs_base(hw);
4596
4597         er32(ALGNERRC);
4598         er32(RXERRC);
4599         er32(TNCRS);
4600         er32(CEXTERR);
4601         er32(TSCTC);
4602         er32(TSCTFC);
4603
4604         er32(MGTPRC);
4605         er32(MGTPDC);
4606         er32(MGTPTC);
4607
4608         er32(IAC);
4609         er32(ICRXOC);
4610
4611         /* Clear PHY statistics registers */
4612         if ((hw->phy.type == e1000_phy_82578) ||
4613             (hw->phy.type == e1000_phy_82579) ||
4614             (hw->phy.type == e1000_phy_i217) ||
4615             (hw->phy.type == e1000_phy_82577)) {
4616                 ret_val = hw->phy.ops.acquire(hw);
4617                 if (ret_val)
4618                         return;
4619                 ret_val = hw->phy.ops.set_page(hw,
4620                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4621                 if (ret_val)
4622                         goto release;
4623                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4624                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4625                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4626                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4627                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4628                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4629                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4630                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4631                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4632                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4633                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4634                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4635                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4636                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4637 release:
4638                 hw->phy.ops.release(hw);
4639         }
4640 }
4641
4642 static const struct e1000_mac_operations ich8_mac_ops = {
4643         /* check_mng_mode dependent on mac type */
4644         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4645         /* cleanup_led dependent on mac type */
4646         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4647         .get_bus_info           = e1000_get_bus_info_ich8lan,
4648         .set_lan_id             = e1000_set_lan_id_single_port,
4649         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4650         /* led_on dependent on mac type */
4651         /* led_off dependent on mac type */
4652         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4653         .reset_hw               = e1000_reset_hw_ich8lan,
4654         .init_hw                = e1000_init_hw_ich8lan,
4655         .setup_link             = e1000_setup_link_ich8lan,
4656         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
4657         /* id_led_init dependent on mac type */
4658         .config_collision_dist  = e1000e_config_collision_dist_generic,
4659         .rar_set                = e1000e_rar_set_generic,
4660 };
4661
4662 static const struct e1000_phy_operations ich8_phy_ops = {
4663         .acquire                = e1000_acquire_swflag_ich8lan,
4664         .check_reset_block      = e1000_check_reset_block_ich8lan,
4665         .commit                 = NULL,
4666         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4667         .get_cable_length       = e1000e_get_cable_length_igp_2,
4668         .read_reg               = e1000e_read_phy_reg_igp,
4669         .release                = e1000_release_swflag_ich8lan,
4670         .reset                  = e1000_phy_hw_reset_ich8lan,
4671         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4672         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4673         .write_reg              = e1000e_write_phy_reg_igp,
4674 };
4675
4676 static const struct e1000_nvm_operations ich8_nvm_ops = {
4677         .acquire                = e1000_acquire_nvm_ich8lan,
4678         .read                   = e1000_read_nvm_ich8lan,
4679         .release                = e1000_release_nvm_ich8lan,
4680         .reload                 = e1000e_reload_nvm_generic,
4681         .update                 = e1000_update_nvm_checksum_ich8lan,
4682         .valid_led_default      = e1000_valid_led_default_ich8lan,
4683         .validate               = e1000_validate_nvm_checksum_ich8lan,
4684         .write                  = e1000_write_nvm_ich8lan,
4685 };
4686
4687 const struct e1000_info e1000_ich8_info = {
4688         .mac                    = e1000_ich8lan,
4689         .flags                  = FLAG_HAS_WOL
4690                                   | FLAG_IS_ICH
4691                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4692                                   | FLAG_HAS_AMT
4693                                   | FLAG_HAS_FLASH
4694                                   | FLAG_APME_IN_WUC,
4695         .pba                    = 8,
4696         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4697         .get_variants           = e1000_get_variants_ich8lan,
4698         .mac_ops                = &ich8_mac_ops,
4699         .phy_ops                = &ich8_phy_ops,
4700         .nvm_ops                = &ich8_nvm_ops,
4701 };
4702
4703 const struct e1000_info e1000_ich9_info = {
4704         .mac                    = e1000_ich9lan,
4705         .flags                  = FLAG_HAS_JUMBO_FRAMES
4706                                   | FLAG_IS_ICH
4707                                   | FLAG_HAS_WOL
4708                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4709                                   | FLAG_HAS_AMT
4710                                   | FLAG_HAS_FLASH
4711                                   | FLAG_APME_IN_WUC,
4712         .pba                    = 18,
4713         .max_hw_frame_size      = DEFAULT_JUMBO,
4714         .get_variants           = e1000_get_variants_ich8lan,
4715         .mac_ops                = &ich8_mac_ops,
4716         .phy_ops                = &ich8_phy_ops,
4717         .nvm_ops                = &ich8_nvm_ops,
4718 };
4719
4720 const struct e1000_info e1000_ich10_info = {
4721         .mac                    = e1000_ich10lan,
4722         .flags                  = FLAG_HAS_JUMBO_FRAMES
4723                                   | FLAG_IS_ICH
4724                                   | FLAG_HAS_WOL
4725                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4726                                   | FLAG_HAS_AMT
4727                                   | FLAG_HAS_FLASH
4728                                   | FLAG_APME_IN_WUC,
4729         .pba                    = 18,
4730         .max_hw_frame_size      = DEFAULT_JUMBO,
4731         .get_variants           = e1000_get_variants_ich8lan,
4732         .mac_ops                = &ich8_mac_ops,
4733         .phy_ops                = &ich8_phy_ops,
4734         .nvm_ops                = &ich8_nvm_ops,
4735 };
4736
4737 const struct e1000_info e1000_pch_info = {
4738         .mac                    = e1000_pchlan,
4739         .flags                  = FLAG_IS_ICH
4740                                   | FLAG_HAS_WOL
4741                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4742                                   | FLAG_HAS_AMT
4743                                   | FLAG_HAS_FLASH
4744                                   | FLAG_HAS_JUMBO_FRAMES
4745                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4746                                   | FLAG_APME_IN_WUC,
4747         .flags2                 = FLAG2_HAS_PHY_STATS,
4748         .pba                    = 26,
4749         .max_hw_frame_size      = 4096,
4750         .get_variants           = e1000_get_variants_ich8lan,
4751         .mac_ops                = &ich8_mac_ops,
4752         .phy_ops                = &ich8_phy_ops,
4753         .nvm_ops                = &ich8_nvm_ops,
4754 };
4755
4756 const struct e1000_info e1000_pch2_info = {
4757         .mac                    = e1000_pch2lan,
4758         .flags                  = FLAG_IS_ICH
4759                                   | FLAG_HAS_WOL
4760                                   | FLAG_HAS_HW_TIMESTAMP
4761                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4762                                   | FLAG_HAS_AMT
4763                                   | FLAG_HAS_FLASH
4764                                   | FLAG_HAS_JUMBO_FRAMES
4765                                   | FLAG_APME_IN_WUC,
4766         .flags2                 = FLAG2_HAS_PHY_STATS
4767                                   | FLAG2_HAS_EEE,
4768         .pba                    = 26,
4769         .max_hw_frame_size      = 9018,
4770         .get_variants           = e1000_get_variants_ich8lan,
4771         .mac_ops                = &ich8_mac_ops,
4772         .phy_ops                = &ich8_phy_ops,
4773         .nvm_ops                = &ich8_nvm_ops,
4774 };
4775
4776 const struct e1000_info e1000_pch_lpt_info = {
4777         .mac                    = e1000_pch_lpt,
4778         .flags                  = FLAG_IS_ICH
4779                                   | FLAG_HAS_WOL
4780                                   | FLAG_HAS_HW_TIMESTAMP
4781                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4782                                   | FLAG_HAS_AMT
4783                                   | FLAG_HAS_FLASH
4784                                   | FLAG_HAS_JUMBO_FRAMES
4785                                   | FLAG_APME_IN_WUC,
4786         .flags2                 = FLAG2_HAS_PHY_STATS
4787                                   | FLAG2_HAS_EEE,
4788         .pba                    = 26,
4789         .max_hw_frame_size      = 9018,
4790         .get_variants           = e1000_get_variants_ich8lan,
4791         .mac_ops                = &ich8_mac_ops,
4792         .phy_ops                = &ich8_phy_ops,
4793         .nvm_ops                = &ich8_nvm_ops,
4794 };