drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /* Intel PRO/1000 Linux driver
   2  * Copyright(c) 1999 - 2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * The full GNU General Public License is included in this distribution in
  14  * the file called "COPYING".
  15  *
  16  * Contact Information:
  17  * Linux NICS <linux.nics@intel.com>
  18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20  */
  21
  22 /* 82562G 10/100 Network Connection
  23  * 82562G-2 10/100 Network Connection
  24  * 82562GT 10/100 Network Connection
  25  * 82562GT-2 10/100 Network Connection
  26  * 82562V 10/100 Network Connection
  27  * 82562V-2 10/100 Network Connection
  28  * 82566DC-2 Gigabit Network Connection
  29  * 82566DC Gigabit Network Connection
  30  * 82566DM-2 Gigabit Network Connection
  31  * 82566DM Gigabit Network Connection
  32  * 82566MC Gigabit Network Connection
  33  * 82566MM Gigabit Network Connection
  34  * 82567LM Gigabit Network Connection
  35  * 82567LF Gigabit Network Connection
  36  * 82567V Gigabit Network Connection
  37  * 82567LM-2 Gigabit Network Connection
  38  * 82567LF-2 Gigabit Network Connection
  39  * 82567V-2 Gigabit Network Connection
  40  * 82567LF-3 Gigabit Network Connection
  41  * 82567LM-3 Gigabit Network Connection
  42  * 82567LM-4 Gigabit Network Connection
  43  * 82577LM Gigabit Network Connection
  44  * 82577LC Gigabit Network Connection
  45  * 82578DM Gigabit Network Connection
  46  * 82578DC Gigabit Network Connection
  47  * 82579LM Gigabit Network Connection
  48  * 82579V Gigabit Network Connection
  49  * Ethernet Connection I217-LM
  50  * Ethernet Connection I217-V
  51  * Ethernet Connection I218-V
  52  * Ethernet Connection I218-LM
  53  * Ethernet Connection (2) I218-LM
  54  * Ethernet Connection (2) I218-V
  55  * Ethernet Connection (3) I218-LM
  56  * Ethernet Connection (3) I218-V
  57  */
  58
  59 #include "e1000.h"
  60
  61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  62 /* Offset 04h HSFSTS */
  63 union ich8_hws_flash_status {
  64         struct ich8_hsfsts {
  65                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  66                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  67                 u16 dael:1;     /* bit 2 Direct Access error Log */
  68                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  69                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  70                 u16 reserved1:2;        /* bit 13:6 Reserved */
  71                 u16 reserved2:6;        /* bit 13:6 Reserved */
  72                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  73                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  74         } hsf_status;
  75         u16 regval;
  76 };
  77
  78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  79 /* Offset 06h FLCTL */
  80 union ich8_hws_flash_ctrl {
  81         struct ich8_hsflctl {
  82                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  83                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  84                 u16 reserved:5; /* 7:3 Reserved  */
  85                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  86                 u16 flockdn:6;  /* 15:10 Reserved */
  87         } hsf_ctrl;
  88         u16 regval;
  89 };
  90
  91 /* ICH Flash Region Access Permissions */
  92 union ich8_hws_flash_regacc {
  93         struct ich8_flracc {
  94                 u32 grra:8;     /* 0:7 GbE region Read Access */
  95                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  96                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  97                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  98         } hsf_flregacc;
  99         u16 regval;
 100 };
 101
 102 /* ICH Flash Protected Region */
 103 union ich8_flash_protected_range {
 104         struct ich8_pr {
 105                 u32 base:13;    /* 0:12 Protected Range Base */
 106                 u32 reserved1:2;        /* 13:14 Reserved */
 107                 u32 rpe:1;      /* 15 Read Protection Enable */
 108                 u32 limit:13;   /* 16:28 Protected Range Limit */
 109                 u32 reserved2:2;        /* 29:30 Reserved */
 110                 u32 wpe:1;      /* 31 Write Protection Enable */
 111         } range;
 112         u32 regval;
 113 };
 114
 115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 119                                                 u32 offset, u8 byte);
 120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 121                                          u8 *data);
 122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 123                                          u16 *data);
 124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 125                                          u8 size, u16 *data);
 126 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 127 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 128 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 129 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 130 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 131 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 132 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 133 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 134 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 135 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 136 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 137 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 138 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 139 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 140 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 141 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 142 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 143 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 144 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 145 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 146 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
 147 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 148 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
 149
 150 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 151 {
 152         return readw(hw->flash_address + reg);
 153 }
 154
 155 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 156 {
 157         return readl(hw->flash_address + reg);
 158 }
 159
 160 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 161 {
 162         writew(val, hw->flash_address + reg);
 163 }
 164
 165 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 166 {
 167         writel(val, hw->flash_address + reg);
 168 }
 169
 170 #define er16flash(reg)          __er16flash(hw, (reg))
 171 #define er32flash(reg)          __er32flash(hw, (reg))
 172 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 173 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 174
 175 /**
 176  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 177  *  @hw: pointer to the HW structure
 178  *
 179  *  Test access to the PHY registers by reading the PHY ID registers.  If
 180  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 181  *  otherwise assume the read PHY ID is correct if it is valid.
 182  *
 183  *  Assumes the sw/fw/hw semaphore is already acquired.
 184  **/
 185 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 186 {
 187         u16 phy_reg = 0;
 188         u32 phy_id = 0;
 189         s32 ret_val = 0;
 190         u16 retry_count;
 191         u32 mac_reg = 0;
 192
 193         for (retry_count = 0; retry_count < 2; retry_count++) {
 194                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 195                 if (ret_val || (phy_reg == 0xFFFF))
 196                         continue;
 197                 phy_id = (u32)(phy_reg << 16);
 198
 199                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 200                 if (ret_val || (phy_reg == 0xFFFF)) {
 201                         phy_id = 0;
 202                         continue;
 203                 }
 204                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 205                 break;
 206         }
 207
 208         if (hw->phy.id) {
 209                 if (hw->phy.id == phy_id)
 210                         goto out;
 211         } else if (phy_id) {
 212                 hw->phy.id = phy_id;
 213                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 214                 goto out;
 215         }
 216
 217         /* In case the PHY needs to be in mdio slow mode,
 218          * set slow mode and try to get the PHY id again.
 219          */
 220         if (hw->mac.type < e1000_pch_lpt) {
 221                 hw->phy.ops.release(hw);
 222                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 223                 if (!ret_val)
 224                         ret_val = e1000e_get_phy_id(hw);
 225                 hw->phy.ops.acquire(hw);
 226         }
 227
 228         if (ret_val)
 229                 return false;
 230 out:
 231         if (hw->mac.type == e1000_pch_lpt) {
 232                 /* Unforce SMBus mode in PHY */
 233                 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 234                 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 235                 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 236
 237                 /* Unforce SMBus mode in MAC */
 238                 mac_reg = er32(CTRL_EXT);
 239                 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 240                 ew32(CTRL_EXT, mac_reg);
 241         }
 242
 243         return true;
 244 }
 245
 246 /**
 247  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 248  *  @hw: pointer to the HW structure
 249  *
 250  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 251  *  used to reset the PHY to a quiescent state when necessary.
 252  **/
 253 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 254 {
 255         u32 mac_reg;
 256
 257         /* Set Phy Config Counter to 50msec */
 258         mac_reg = er32(FEXTNVM3);
 259         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 260         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 261         ew32(FEXTNVM3, mac_reg);
 262
 263         /* Toggle LANPHYPC Value bit */
 264         mac_reg = er32(CTRL);
 265         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 266         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 267         ew32(CTRL, mac_reg);
 268         e1e_flush();
 269         usleep_range(10, 20);
 270         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 271         ew32(CTRL, mac_reg);
 272         e1e_flush();
 273
 274         if (hw->mac.type < e1000_pch_lpt) {
 275                 msleep(50);
 276         } else {
 277                 u16 count = 20;
 278
 279                 do {
 280                         usleep_range(5000, 10000);
 281                 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
 282
 283                 msleep(30);
 284         }
 285 }
 286
 287 /**
 288  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 289  *  @hw: pointer to the HW structure
 290  *
 291  *  Workarounds/flow necessary for PHY initialization during driver load
 292  *  and resume paths.
 293  **/
 294 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 295 {
 296         struct e1000_adapter *adapter = hw->adapter;
 297         u32 mac_reg, fwsm = er32(FWSM);
 298         s32 ret_val;
 299
 300         /* Gate automatic PHY configuration by hardware on managed and
 301          * non-managed 82579 and newer adapters.
 302          */
 303         e1000_gate_hw_phy_config_ich8lan(hw, true);
 304
 305         /* It is not possible to be certain of the current state of ULP
 306          * so forcibly disable it.
 307          */
 308         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 309         e1000_disable_ulp_lpt_lp(hw, true);
 310
 311         ret_val = hw->phy.ops.acquire(hw);
 312         if (ret_val) {
 313                 e_dbg("Failed to initialize PHY flow\n");
 314                 goto out;
 315         }
 316
 317         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 318          * inaccessible and resetting the PHY is not blocked, toggle the
 319          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 320          */
 321         switch (hw->mac.type) {
 322         case e1000_pch_lpt:
 323                 if (e1000_phy_is_accessible_pchlan(hw))
 324                         break;
 325
 326                 /* Before toggling LANPHYPC, see if PHY is accessible by
 327                  * forcing MAC to SMBus mode first.
 328                  */
 329                 mac_reg = er32(CTRL_EXT);
 330                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 331                 ew32(CTRL_EXT, mac_reg);
 332
 333                 /* Wait 50 milliseconds for MAC to finish any retries
 334                  * that it might be trying to perform from previous
 335                  * attempts to acknowledge any phy read requests.
 336                  */
 337                 msleep(50);
 338
 339                 /* fall-through */
 340         case e1000_pch2lan:
 341                 if (e1000_phy_is_accessible_pchlan(hw))
 342                         break;
 343
 344                 /* fall-through */
 345         case e1000_pchlan:
 346                 if ((hw->mac.type == e1000_pchlan) &&
 347                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 348                         break;
 349
 350                 if (hw->phy.ops.check_reset_block(hw)) {
 351                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 352                         ret_val = -E1000_ERR_PHY;
 353                         break;
 354                 }
 355
 356                 /* Toggle LANPHYPC Value bit */
 357                 e1000_toggle_lanphypc_pch_lpt(hw);
 358                 if (hw->mac.type >= e1000_pch_lpt) {
 359                         if (e1000_phy_is_accessible_pchlan(hw))
 360                                 break;
 361
 362                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 363                          * so ensure that the MAC is also out of SMBus mode
 364                          */
 365                         mac_reg = er32(CTRL_EXT);
 366                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 367                         ew32(CTRL_EXT, mac_reg);
 368
 369                         if (e1000_phy_is_accessible_pchlan(hw))
 370                                 break;
 371
 372                         ret_val = -E1000_ERR_PHY;
 373                 }
 374                 break;
 375         default:
 376                 break;
 377         }
 378
 379         hw->phy.ops.release(hw);
 380         if (!ret_val) {
 381
 382                 /* Check to see if able to reset PHY.  Print error if not */
 383                 if (hw->phy.ops.check_reset_block(hw)) {
 384                         e_err("Reset blocked by ME\n");
 385                         goto out;
 386                 }
 387
 388                 /* Reset the PHY before any access to it.  Doing so, ensures
 389                  * that the PHY is in a known good state before we read/write
 390                  * PHY registers.  The generic reset is sufficient here,
 391                  * because we haven't determined the PHY type yet.
 392                  */
 393                 ret_val = e1000e_phy_hw_reset_generic(hw);
 394                 if (ret_val)
 395                         goto out;
 396
 397                 /* On a successful reset, possibly need to wait for the PHY
 398                  * to quiesce to an accessible state before returning control
 399                  * to the calling function.  If the PHY does not quiesce, then
 400                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 401                  *  the PHY is in.
 402                  */
 403                 ret_val = hw->phy.ops.check_reset_block(hw);
 404                 if (ret_val)
 405                         e_err("ME blocked access to PHY after reset\n");
 406         }
 407
 408 out:
 409         /* Ungate automatic PHY configuration on non-managed 82579 */
 410         if ((hw->mac.type == e1000_pch2lan) &&
 411             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 412                 usleep_range(10000, 20000);
 413                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 414         }
 415
 416         return ret_val;
 417 }
 418
 419 /**
 420  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 421  *  @hw: pointer to the HW structure
 422  *
 423  *  Initialize family-specific PHY parameters and function pointers.
 424  **/
 425 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 426 {
 427         struct e1000_phy_info *phy = &hw->phy;
 428         s32 ret_val;
 429
 430         phy->addr = 1;
 431         phy->reset_delay_us = 100;
 432
 433         phy->ops.set_page = e1000_set_page_igp;
 434         phy->ops.read_reg = e1000_read_phy_reg_hv;
 435         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 436         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 437         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 438         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 439         phy->ops.write_reg = e1000_write_phy_reg_hv;
 440         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 441         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 442         phy->ops.power_up = e1000_power_up_phy_copper;
 443         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 444         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 445
 446         phy->id = e1000_phy_unknown;
 447
 448         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 449         if (ret_val)
 450                 return ret_val;
 451
 452         if (phy->id == e1000_phy_unknown)
 453                 switch (hw->mac.type) {
 454                 default:
 455                         ret_val = e1000e_get_phy_id(hw);
 456                         if (ret_val)
 457                                 return ret_val;
 458                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 459                                 break;
 460                         /* fall-through */
 461                 case e1000_pch2lan:
 462                 case e1000_pch_lpt:
 463                         /* In case the PHY needs to be in mdio slow mode,
 464                          * set slow mode and try to get the PHY id again.
 465                          */
 466                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 467                         if (ret_val)
 468                                 return ret_val;
 469                         ret_val = e1000e_get_phy_id(hw);
 470                         if (ret_val)
 471                                 return ret_val;
 472                         break;
 473                 }
 474         phy->type = e1000e_get_phy_type_from_id(phy->id);
 475
 476         switch (phy->type) {
 477         case e1000_phy_82577:
 478         case e1000_phy_82579:
 479         case e1000_phy_i217:
 480                 phy->ops.check_polarity = e1000_check_polarity_82577;
 481                 phy->ops.force_speed_duplex =
 482                     e1000_phy_force_speed_duplex_82577;
 483                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 484                 phy->ops.get_info = e1000_get_phy_info_82577;
 485                 phy->ops.commit = e1000e_phy_sw_reset;
 486                 break;
 487         case e1000_phy_82578:
 488                 phy->ops.check_polarity = e1000_check_polarity_m88;
 489                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 490                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 491                 phy->ops.get_info = e1000e_get_phy_info_m88;
 492                 break;
 493         default:
 494                 ret_val = -E1000_ERR_PHY;
 495                 break;
 496         }
 497
 498         return ret_val;
 499 }
 500
 501 /**
 502  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 503  *  @hw: pointer to the HW structure
 504  *
 505  *  Initialize family-specific PHY parameters and function pointers.
 506  **/
 507 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 508 {
 509         struct e1000_phy_info *phy = &hw->phy;
 510         s32 ret_val;
 511         u16 i = 0;
 512
 513         phy->addr = 1;
 514         phy->reset_delay_us = 100;
 515
 516         phy->ops.power_up = e1000_power_up_phy_copper;
 517         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 518
 519         /* We may need to do this twice - once for IGP and if that fails,
 520          * we'll set BM func pointers and try again
 521          */
 522         ret_val = e1000e_determine_phy_address(hw);
 523         if (ret_val) {
 524                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 525                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 526                 ret_val = e1000e_determine_phy_address(hw);
 527                 if (ret_val) {
 528                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 529                         return ret_val;
 530                 }
 531         }
 532
 533         phy->id = 0;
 534         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 535                (i++ < 100)) {
 536                 usleep_range(1000, 2000);
 537                 ret_val = e1000e_get_phy_id(hw);
 538                 if (ret_val)
 539                         return ret_val;
 540         }
 541
 542         /* Verify phy id */
 543         switch (phy->id) {
 544         case IGP03E1000_E_PHY_ID:
 545                 phy->type = e1000_phy_igp_3;
 546                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 547                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 548                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 549                 phy->ops.get_info = e1000e_get_phy_info_igp;
 550                 phy->ops.check_polarity = e1000_check_polarity_igp;
 551                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 552                 break;
 553         case IFE_E_PHY_ID:
 554         case IFE_PLUS_E_PHY_ID:
 555         case IFE_C_E_PHY_ID:
 556                 phy->type = e1000_phy_ife;
 557                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 558                 phy->ops.get_info = e1000_get_phy_info_ife;
 559                 phy->ops.check_polarity = e1000_check_polarity_ife;
 560                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 561                 break;
 562         case BME1000_E_PHY_ID:
 563                 phy->type = e1000_phy_bm;
 564                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 565                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 566                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 567                 phy->ops.commit = e1000e_phy_sw_reset;
 568                 phy->ops.get_info = e1000e_get_phy_info_m88;
 569                 phy->ops.check_polarity = e1000_check_polarity_m88;
 570                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 571                 break;
 572         default:
 573                 return -E1000_ERR_PHY;
 574                 break;
 575         }
 576
 577         return 0;
 578 }
 579
 580 /**
 581  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 582  *  @hw: pointer to the HW structure
 583  *
 584  *  Initialize family-specific NVM parameters and function
 585  *  pointers.
 586  **/
 587 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 588 {
 589         struct e1000_nvm_info *nvm = &hw->nvm;
 590         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 591         u32 gfpreg, sector_base_addr, sector_end_addr;
 592         u16 i;
 593
 594         /* Can't read flash registers if the register set isn't mapped. */
 595         if (!hw->flash_address) {
 596                 e_dbg("ERROR: Flash registers not mapped\n");
 597                 return -E1000_ERR_CONFIG;
 598         }
 599
 600         nvm->type = e1000_nvm_flash_sw;
 601
 602         gfpreg = er32flash(ICH_FLASH_GFPREG);
 603
 604         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 605          * Add 1 to sector_end_addr since this sector is included in
 606          * the overall size.
 607          */
 608         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 609         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 610
 611         /* flash_base_addr is byte-aligned */
 612         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 613
 614         /* find total size of the NVM, then cut in half since the total
 615          * size represents two separate NVM banks.
 616          */
 617         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 618                                 << FLASH_SECTOR_ADDR_SHIFT);
 619         nvm->flash_bank_size /= 2;
 620         /* Adjust to word count */
 621         nvm->flash_bank_size /= sizeof(u16);
 622
 623         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 624
 625         /* Clear shadow ram */
 626         for (i = 0; i < nvm->word_size; i++) {
 627                 dev_spec->shadow_ram[i].modified = false;
 628                 dev_spec->shadow_ram[i].value = 0xFFFF;
 629         }
 630
 631         return 0;
 632 }
 633
 634 /**
 635  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 636  *  @hw: pointer to the HW structure
 637  *
 638  *  Initialize family-specific MAC parameters and function
 639  *  pointers.
 640  **/
 641 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 642 {
 643         struct e1000_mac_info *mac = &hw->mac;
 644
 645         /* Set media type function pointer */
 646         hw->phy.media_type = e1000_media_type_copper;
 647
 648         /* Set mta register count */
 649         mac->mta_reg_count = 32;
 650         /* Set rar entry count */
 651         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 652         if (mac->type == e1000_ich8lan)
 653                 mac->rar_entry_count--;
 654         /* FWSM register */
 655         mac->has_fwsm = true;
 656         /* ARC subsystem not supported */
 657         mac->arc_subsystem_valid = false;
 658         /* Adaptive IFS supported */
 659         mac->adaptive_ifs = true;
 660
 661         /* LED and other operations */
 662         switch (mac->type) {
 663         case e1000_ich8lan:
 664         case e1000_ich9lan:
 665         case e1000_ich10lan:
 666                 /* check management mode */
 667                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 668                 /* ID LED init */
 669                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 670                 /* blink LED */
 671                 mac->ops.blink_led = e1000e_blink_led_generic;
 672                 /* setup LED */
 673                 mac->ops.setup_led = e1000e_setup_led_generic;
 674                 /* cleanup LED */
 675                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 676                 /* turn on/off LED */
 677                 mac->ops.led_on = e1000_led_on_ich8lan;
 678                 mac->ops.led_off = e1000_led_off_ich8lan;
 679                 break;
 680         case e1000_pch2lan:
 681                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 682                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 683                 /* fall-through */
 684         case e1000_pch_lpt:
 685         case e1000_pchlan:
 686                 /* check management mode */
 687                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 688                 /* ID LED init */
 689                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 690                 /* setup LED */
 691                 mac->ops.setup_led = e1000_setup_led_pchlan;
 692                 /* cleanup LED */
 693                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 694                 /* turn on/off LED */
 695                 mac->ops.led_on = e1000_led_on_pchlan;
 696                 mac->ops.led_off = e1000_led_off_pchlan;
 697                 break;
 698         default:
 699                 break;
 700         }
 701
 702         if (mac->type == e1000_pch_lpt) {
 703                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 704                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 705                 mac->ops.setup_physical_interface =
 706                     e1000_setup_copper_link_pch_lpt;
 707         }
 708
 709         /* Enable PCS Lock-loss workaround for ICH8 */
 710         if (mac->type == e1000_ich8lan)
 711                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 712
 713         return 0;
 714 }
 715
 716 /**
 717  *  __e1000_access_emi_reg_locked - Read/write EMI register
 718  *  @hw: pointer to the HW structure
 719  *  @addr: EMI address to program
 720  *  @data: pointer to value to read/write from/to the EMI address
 721  *  @read: boolean flag to indicate read or write
 722  *
 723  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 724  **/
 725 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 726                                          u16 *data, bool read)
 727 {
 728         s32 ret_val;
 729
 730         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 731         if (ret_val)
 732                 return ret_val;
 733
 734         if (read)
 735                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 736         else
 737                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 738
 739         return ret_val;
 740 }
 741
 742 /**
 743  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 744  *  @hw: pointer to the HW structure
 745  *  @addr: EMI address to program
 746  *  @data: value to be read from the EMI address
 747  *
 748  *  Assumes the SW/FW/HW Semaphore is already acquired.
 749  **/
 750 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 751 {
 752         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 753 }
 754
 755 /**
 756  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 757  *  @hw: pointer to the HW structure
 758  *  @addr: EMI address to program
 759  *  @data: value to be written to the EMI address
 760  *
 761  *  Assumes the SW/FW/HW Semaphore is already acquired.
 762  **/
 763 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 764 {
 765         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 766 }
 767
 768 /**
 769  *  e1000_set_eee_pchlan - Enable/disable EEE support
 770  *  @hw: pointer to the HW structure
 771  *
 772  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 773  *  the link and the EEE capabilities of the link partner.  The LPI Control
 774  *  register bits will remain set only if/when link is up.
 775  *
 776  *  EEE LPI must not be asserted earlier than one second after link is up.
 777  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 778  *  can be link issues with some switches.  Other devices can have EEE LPI
 779  *  enabled immediately upon link up since they have a timer in hardware which
 780  *  prevents LPI from being asserted too early.
 781  **/
 782 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 783 {
 784         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 785         s32 ret_val;
 786         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 787
 788         switch (hw->phy.type) {
 789         case e1000_phy_82579:
 790                 lpa = I82579_EEE_LP_ABILITY;
 791                 pcs_status = I82579_EEE_PCS_STATUS;
 792                 adv_addr = I82579_EEE_ADVERTISEMENT;
 793                 break;
 794         case e1000_phy_i217:
 795                 lpa = I217_EEE_LP_ABILITY;
 796                 pcs_status = I217_EEE_PCS_STATUS;
 797                 adv_addr = I217_EEE_ADVERTISEMENT;
 798                 break;
 799         default:
 800                 return 0;
 801         }
 802
 803         ret_val = hw->phy.ops.acquire(hw);
 804         if (ret_val)
 805                 return ret_val;
 806
 807         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 808         if (ret_val)
 809                 goto release;
 810
 811         /* Clear bits that enable EEE in various speeds */
 812         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 813
 814         /* Enable EEE if not disabled by user */
 815         if (!dev_spec->eee_disable) {
 816                 /* Save off link partner's EEE ability */
 817                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 818                                                     &dev_spec->eee_lp_ability);
 819                 if (ret_val)
 820                         goto release;
 821
 822                 /* Read EEE advertisement */
 823                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 824                 if (ret_val)
 825                         goto release;
 826
 827                 /* Enable EEE only for speeds in which the link partner is
 828                  * EEE capable and for which we advertise EEE.
 829                  */
 830                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 831                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 832
 833                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 834                         e1e_rphy_locked(hw, MII_LPA, &data);
 835                         if (data & LPA_100FULL)
 836                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 837                         else
 838                                 /* EEE is not supported in 100Half, so ignore
 839                                  * partner's EEE in 100 ability if full-duplex
 840                                  * is not advertised.
 841                                  */
 842                                 dev_spec->eee_lp_ability &=
 843                                     ~I82579_EEE_100_SUPPORTED;
 844                 }
 845         }
 846
 847         if (hw->phy.type == e1000_phy_82579) {
 848                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 849                                                     &data);
 850                 if (ret_val)
 851                         goto release;
 852
 853                 data &= ~I82579_LPI_100_PLL_SHUT;
 854                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 855                                                      data);
 856         }
 857
 858         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 859         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 860         if (ret_val)
 861                 goto release;
 862
 863         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 864 release:
 865         hw->phy.ops.release(hw);
 866
 867         return ret_val;
 868 }
 869
 870 /**
 871  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 872  *  @hw:   pointer to the HW structure
 873  *  @link: link up bool flag
 874  *
 875  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 876  *  preventing further DMA write requests.  Workaround the issue by disabling
 877  *  the de-assertion of the clock request when in 1Gpbs mode.
 878  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 879  *  speeds in order to avoid Tx hangs.
 880  **/
 881 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 882 {
 883         u32 fextnvm6 = er32(FEXTNVM6);
 884         u32 status = er32(STATUS);
 885         s32 ret_val = 0;
 886         u16 reg;
 887
 888         if (link && (status & E1000_STATUS_SPEED_1000)) {
 889                 ret_val = hw->phy.ops.acquire(hw);
 890                 if (ret_val)
 891                         return ret_val;
 892
 893                 ret_val =
 894                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 895                                                 &reg);
 896                 if (ret_val)
 897                         goto release;
 898
 899                 ret_val =
 900                     e1000e_write_kmrn_reg_locked(hw,
 901                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 902                                                  reg &
 903                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 904                 if (ret_val)
 905                         goto release;
 906
 907                 usleep_range(10, 20);
 908
 909                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 910
 911                 ret_val =
 912                     e1000e_write_kmrn_reg_locked(hw,
 913                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 914                                                  reg);
 915 release:
 916                 hw->phy.ops.release(hw);
 917         } else {
 918                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 919                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 920
 921                 if (!link || ((status & E1000_STATUS_SPEED_100) &&
 922                               (status & E1000_STATUS_FD)))
 923                         goto update_fextnvm6;
 924
 925                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 926                 if (ret_val)
 927                         return ret_val;
 928
 929                 /* Clear link status transmit timeout */
 930                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 931
 932                 if (status & E1000_STATUS_SPEED_100) {
 933                         /* Set inband Tx timeout to 5x10us for 100Half */
 934                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 935
 936                         /* Do not extend the K1 entry latency for 100Half */
 937                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 938                 } else {
 939                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 940                         reg |= 50 <<
 941                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 942
 943                         /* Extend the K1 entry latency for 10 Mbps */
 944                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 945                 }
 946
 947                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 948                 if (ret_val)
 949                         return ret_val;
 950
 951 update_fextnvm6:
 952                 ew32(FEXTNVM6, fextnvm6);
 953         }
 954
 955         return ret_val;
 956 }
 957
 958 /**
 959  *  e1000_platform_pm_pch_lpt - Set platform power management values
 960  *  @hw: pointer to the HW structure
 961  *  @link: bool indicating link status
 962  *
 963  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 964  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
 965  *  when link is up (which must not exceed the maximum latency supported
 966  *  by the platform), otherwise specify there is no LTR requirement.
 967  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
 968  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
 969  *  Capability register set, on this device LTR is set by writing the
 970  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
 971  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
 972  *  message to the PMC.
 973  **/
 974 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
 975 {
 976         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
 977             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
 978         u16 lat_enc = 0;        /* latency encoded */
 979
 980         if (link) {
 981                 u16 speed, duplex, scale = 0;
 982                 u16 max_snoop, max_nosnoop;
 983                 u16 max_ltr_enc;        /* max LTR latency encoded */
 984                 s64 lat_ns;     /* latency (ns) */
 985                 s64 value;
 986                 u32 rxa;
 987
 988                 if (!hw->adapter->max_frame_size) {
 989                         e_dbg("max_frame_size not set.\n");
 990                         return -E1000_ERR_CONFIG;
 991                 }
 992
 993                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
 994                 if (!speed) {
 995                         e_dbg("Speed not set.\n");
 996                         return -E1000_ERR_CONFIG;
 997                 }
 998
 999                 /* Rx Packet Buffer Allocation size (KB) */
1000                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1001
1002                 /* Determine the maximum latency tolerated by the device.
1003                  *
1004                  * Per the PCIe spec, the tolerated latencies are encoded as
1005                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1006                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1007                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1008                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1009                  */
1010                 lat_ns = ((s64)rxa * 1024 -
1011                           (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;
1012                 if (lat_ns < 0)
1013                         lat_ns = 0;
1014                 else
1015                         do_div(lat_ns, speed);
1016
1017                 value = lat_ns;
1018                 while (value > PCI_LTR_VALUE_MASK) {
1019                         scale++;
1020                         value = DIV_ROUND_UP(value, (1 << 5));
1021                 }
1022                 if (scale > E1000_LTRV_SCALE_MAX) {
1023                         e_dbg("Invalid LTR latency scale %d\n", scale);
1024                         return -E1000_ERR_CONFIG;
1025                 }
1026                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1027
1028                 /* Determine the maximum latency tolerated by the platform */
1029                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1030                                      &max_snoop);
1031                 pci_read_config_word(hw->adapter->pdev,
1032                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1033                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1034
1035                 if (lat_enc > max_ltr_enc)
1036                         lat_enc = max_ltr_enc;
1037         }
1038
1039         /* Set Snoop and No-Snoop latencies the same */
1040         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1041         ew32(LTRV, reg);
1042
1043         return 0;
1044 }
1045
1046 /**
1047  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1048  *  @hw: pointer to the HW structure
1049  *  @to_sx: boolean indicating a system power state transition to Sx
1050  *
1051  *  When link is down, configure ULP mode to significantly reduce the power
1052  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1053  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1054  *  system, configure the ULP mode by software.
1055  */
1056 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1057 {
1058         u32 mac_reg;
1059         s32 ret_val = 0;
1060         u16 phy_reg;
1061
1062         if ((hw->mac.type < e1000_pch_lpt) ||
1063             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1064             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1065             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1066             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1067             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1068                 return 0;
1069
1070         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1071                 /* Request ME configure ULP mode in the PHY */
1072                 mac_reg = er32(H2ME);
1073                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1074                 ew32(H2ME, mac_reg);
1075
1076                 goto out;
1077         }
1078
1079         if (!to_sx) {
1080                 int i = 0;
1081
1082                 /* Poll up to 5 seconds for Cable Disconnected indication */
1083                 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1084                         /* Bail if link is re-acquired */
1085                         if (er32(STATUS) & E1000_STATUS_LU)
1086                                 return -E1000_ERR_PHY;
1087
1088                         if (i++ == 100)
1089                                 break;
1090
1091                         msleep(50);
1092                 }
1093                 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1094                       (er32(FEXT) &
1095                        E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1096         }
1097
1098         ret_val = hw->phy.ops.acquire(hw);
1099         if (ret_val)
1100                 goto out;
1101
1102         /* Force SMBus mode in PHY */
1103         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1104         if (ret_val)
1105                 goto release;
1106         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1107         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1108
1109         /* Force SMBus mode in MAC */
1110         mac_reg = er32(CTRL_EXT);
1111         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1112         ew32(CTRL_EXT, mac_reg);
1113
1114         /* Set Inband ULP Exit, Reset to SMBus mode and
1115          * Disable SMBus Release on PERST# in PHY
1116          */
1117         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1118         if (ret_val)
1119                 goto release;
1120         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1121                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1122         if (to_sx) {
1123                 if (er32(WUFC) & E1000_WUFC_LNKC)
1124                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1125
1126                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1127         } else {
1128                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1129         }
1130         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1131
1132         /* Set Disable SMBus Release on PERST# in MAC */
1133         mac_reg = er32(FEXTNVM7);
1134         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1135         ew32(FEXTNVM7, mac_reg);
1136
1137         /* Commit ULP changes in PHY by starting auto ULP configuration */
1138         phy_reg |= I218_ULP_CONFIG1_START;
1139         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1140 release:
1141         hw->phy.ops.release(hw);
1142 out:
1143         if (ret_val)
1144                 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1145         else
1146                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1147
1148         return ret_val;
1149 }
1150
1151 /**
1152  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1153  *  @hw: pointer to the HW structure
1154  *  @force: boolean indicating whether or not to force disabling ULP
1155  *
1156  *  Un-configure ULP mode when link is up, the system is transitioned from
1157  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1158  *  system, poll for an indication from ME that ULP has been un-configured.
1159  *  If not on an ME enabled system, un-configure the ULP mode by software.
1160  *
1161  *  During nominal operation, this function is called when link is acquired
1162  *  to disable ULP mode (force=false); otherwise, for example when unloading
1163  *  the driver or during Sx->S0 transitions, this is called with force=true
1164  *  to forcibly disable ULP.
1165  */
1166 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1167 {
1168         s32 ret_val = 0;
1169         u32 mac_reg;
1170         u16 phy_reg;
1171         int i = 0;
1172
1173         if ((hw->mac.type < e1000_pch_lpt) ||
1174             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1175             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1176             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1177             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1178             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1179                 return 0;
1180
1181         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1182                 if (force) {
1183                         /* Request ME un-configure ULP mode in the PHY */
1184                         mac_reg = er32(H2ME);
1185                         mac_reg &= ~E1000_H2ME_ULP;
1186                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1187                         ew32(H2ME, mac_reg);
1188                 }
1189
1190                 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1191                 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1192                         if (i++ == 10) {
1193                                 ret_val = -E1000_ERR_PHY;
1194                                 goto out;
1195                         }
1196
1197                         usleep_range(10000, 20000);
1198                 }
1199                 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1200
1201                 if (force) {
1202                         mac_reg = er32(H2ME);
1203                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1204                         ew32(H2ME, mac_reg);
1205                 } else {
1206                         /* Clear H2ME.ULP after ME ULP configuration */
1207                         mac_reg = er32(H2ME);
1208                         mac_reg &= ~E1000_H2ME_ULP;
1209                         ew32(H2ME, mac_reg);
1210                 }
1211
1212                 goto out;
1213         }
1214
1215         ret_val = hw->phy.ops.acquire(hw);
1216         if (ret_val)
1217                 goto out;
1218
1219         if (force)
1220                 /* Toggle LANPHYPC Value bit */
1221                 e1000_toggle_lanphypc_pch_lpt(hw);
1222
1223         /* Unforce SMBus mode in PHY */
1224         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1225         if (ret_val) {
1226                 /* The MAC might be in PCIe mode, so temporarily force to
1227                  * SMBus mode in order to access the PHY.
1228                  */
1229                 mac_reg = er32(CTRL_EXT);
1230                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1231                 ew32(CTRL_EXT, mac_reg);
1232
1233                 msleep(50);
1234
1235                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1236                                                        &phy_reg);
1237                 if (ret_val)
1238                         goto release;
1239         }
1240         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1241         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1242
1243         /* Unforce SMBus mode in MAC */
1244         mac_reg = er32(CTRL_EXT);
1245         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1246         ew32(CTRL_EXT, mac_reg);
1247
1248         /* When ULP mode was previously entered, K1 was disabled by the
1249          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1250          */
1251         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1252         if (ret_val)
1253                 goto release;
1254         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1255         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1256
1257         /* Clear ULP enabled configuration */
1258         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1259         if (ret_val)
1260                 goto release;
1261         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1262                      I218_ULP_CONFIG1_STICKY_ULP |
1263                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1264                      I218_ULP_CONFIG1_WOL_HOST |
1265                      I218_ULP_CONFIG1_INBAND_EXIT |
1266                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1267         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1268
1269         /* Commit ULP changes by starting auto ULP configuration */
1270         phy_reg |= I218_ULP_CONFIG1_START;
1271         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1272
1273         /* Clear Disable SMBus Release on PERST# in MAC */
1274         mac_reg = er32(FEXTNVM7);
1275         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1276         ew32(FEXTNVM7, mac_reg);
1277
1278 release:
1279         hw->phy.ops.release(hw);
1280         if (force) {
1281                 e1000_phy_hw_reset(hw);
1282                 msleep(50);
1283         }
1284 out:
1285         if (ret_val)
1286                 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1287         else
1288                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1289
1290         return ret_val;
1291 }
1292
1293 /**
1294  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1295  *  @hw: pointer to the HW structure
1296  *
1297  *  Checks to see of the link status of the hardware has changed.  If a
1298  *  change in link status has been detected, then we read the PHY registers
1299  *  to get the current speed/duplex if link exists.
1300  **/
1301 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1302 {
1303         struct e1000_mac_info *mac = &hw->mac;
1304         s32 ret_val;
1305         bool link;
1306         u16 phy_reg;
1307
1308         /* We only want to go out to the PHY registers to see if Auto-Neg
1309          * has completed and/or if our link status has changed.  The
1310          * get_link_status flag is set upon receiving a Link Status
1311          * Change or Rx Sequence Error interrupt.
1312          */
1313         if (!mac->get_link_status)
1314                 return 0;
1315
1316         /* First we want to see if the MII Status Register reports
1317          * link.  If so, then we want to get the current speed/duplex
1318          * of the PHY.
1319          */
1320         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1321         if (ret_val)
1322                 return ret_val;
1323
1324         if (hw->mac.type == e1000_pchlan) {
1325                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1326                 if (ret_val)
1327                         return ret_val;
1328         }
1329
1330         /* When connected at 10Mbps half-duplex, some parts are excessively
1331          * aggressive resulting in many collisions. To avoid this, increase
1332          * the IPG and reduce Rx latency in the PHY.
1333          */
1334         if (((hw->mac.type == e1000_pch2lan) ||
1335              (hw->mac.type == e1000_pch_lpt)) && link) {
1336                 u32 reg;
1337                 reg = er32(STATUS);
1338                 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1339                         u16 emi_addr;
1340
1341                         reg = er32(TIPG);
1342                         reg &= ~E1000_TIPG_IPGT_MASK;
1343                         reg |= 0xFF;
1344                         ew32(TIPG, reg);
1345
1346                         /* Reduce Rx latency in analog PHY */
1347                         ret_val = hw->phy.ops.acquire(hw);
1348                         if (ret_val)
1349                                 return ret_val;
1350
1351                         if (hw->mac.type == e1000_pch2lan)
1352                                 emi_addr = I82579_RX_CONFIG;
1353                         else
1354                                 emi_addr = I217_RX_CONFIG;
1355
1356                         ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1357
1358                         hw->phy.ops.release(hw);
1359
1360                         if (ret_val)
1361                                 return ret_val;
1362                 }
1363         }
1364
1365         /* Work-around I218 hang issue */
1366         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1367             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1368             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1369             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1370                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1371                 if (ret_val)
1372                         return ret_val;
1373         }
1374
1375         if (hw->mac.type == e1000_pch_lpt) {
1376                 /* Set platform power management values for
1377                  * Latency Tolerance Reporting (LTR)
1378                  */
1379                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1380                 if (ret_val)
1381                         return ret_val;
1382         }
1383
1384         /* Clear link partner's EEE ability */
1385         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1386
1387         if (!link)
1388                 return 0;       /* No link detected */
1389
1390         mac->get_link_status = false;
1391
1392         switch (hw->mac.type) {
1393         case e1000_pch2lan:
1394                 ret_val = e1000_k1_workaround_lv(hw);
1395                 if (ret_val)
1396                         return ret_val;
1397                 /* fall-thru */
1398         case e1000_pchlan:
1399                 if (hw->phy.type == e1000_phy_82578) {
1400                         ret_val = e1000_link_stall_workaround_hv(hw);
1401                         if (ret_val)
1402                                 return ret_val;
1403                 }
1404
1405                 /* Workaround for PCHx parts in half-duplex:
1406                  * Set the number of preambles removed from the packet
1407                  * when it is passed from the PHY to the MAC to prevent
1408                  * the MAC from misinterpreting the packet type.
1409                  */
1410                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1411                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1412
1413                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1414                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1415
1416                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1417                 break;
1418         default:
1419                 break;
1420         }
1421
1422         /* Check if there was DownShift, must be checked
1423          * immediately after link-up
1424          */
1425         e1000e_check_downshift(hw);
1426
1427         /* Enable/Disable EEE after link up */
1428         if (hw->phy.type > e1000_phy_82579) {
1429                 ret_val = e1000_set_eee_pchlan(hw);
1430                 if (ret_val)
1431                         return ret_val;
1432         }
1433
1434         /* If we are forcing speed/duplex, then we simply return since
1435          * we have already determined whether we have link or not.
1436          */
1437         if (!mac->autoneg)
1438                 return -E1000_ERR_CONFIG;
1439
1440         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1441          * of MAC speed/duplex configuration.  So we only need to
1442          * configure Collision Distance in the MAC.
1443          */
1444         mac->ops.config_collision_dist(hw);
1445
1446         /* Configure Flow Control now that Auto-Neg has completed.
1447          * First, we need to restore the desired flow control
1448          * settings because we may have had to re-autoneg with a
1449          * different link partner.
1450          */
1451         ret_val = e1000e_config_fc_after_link_up(hw);
1452         if (ret_val)
1453                 e_dbg("Error configuring flow control\n");
1454
1455         return ret_val;
1456 }
1457
1458 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1459 {
1460         struct e1000_hw *hw = &adapter->hw;
1461         s32 rc;
1462
1463         rc = e1000_init_mac_params_ich8lan(hw);
1464         if (rc)
1465                 return rc;
1466
1467         rc = e1000_init_nvm_params_ich8lan(hw);
1468         if (rc)
1469                 return rc;
1470
1471         switch (hw->mac.type) {
1472         case e1000_ich8lan:
1473         case e1000_ich9lan:
1474         case e1000_ich10lan:
1475                 rc = e1000_init_phy_params_ich8lan(hw);
1476                 break;
1477         case e1000_pchlan:
1478         case e1000_pch2lan:
1479         case e1000_pch_lpt:
1480                 rc = e1000_init_phy_params_pchlan(hw);
1481                 break;
1482         default:
1483                 break;
1484         }
1485         if (rc)
1486                 return rc;
1487
1488         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1489          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1490          */
1491         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1492             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1493              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1494                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1495                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
1496
1497                 hw->mac.ops.blink_led = NULL;
1498         }
1499
1500         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1501             (adapter->hw.phy.type != e1000_phy_ife))
1502                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1503
1504         /* Enable workaround for 82579 w/ ME enabled */
1505         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1506             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1507                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1508
1509         return 0;
1510 }
1511
1512 static DEFINE_MUTEX(nvm_mutex);
1513
1514 /**
1515  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1516  *  @hw: pointer to the HW structure
1517  *
1518  *  Acquires the mutex for performing NVM operations.
1519  **/
1520 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1521 {
1522         mutex_lock(&nvm_mutex);
1523
1524         return 0;
1525 }
1526
1527 /**
1528  *  e1000_release_nvm_ich8lan - Release NVM mutex
1529  *  @hw: pointer to the HW structure
1530  *
1531  *  Releases the mutex used while performing NVM operations.
1532  **/
1533 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1534 {
1535         mutex_unlock(&nvm_mutex);
1536 }
1537
1538 /**
1539  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1540  *  @hw: pointer to the HW structure
1541  *
1542  *  Acquires the software control flag for performing PHY and select
1543  *  MAC CSR accesses.
1544  **/
1545 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1546 {
1547         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1548         s32 ret_val = 0;
1549
1550         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1551                              &hw->adapter->state)) {
1552                 e_dbg("contention for Phy access\n");
1553                 return -E1000_ERR_PHY;
1554         }
1555
1556         while (timeout) {
1557                 extcnf_ctrl = er32(EXTCNF_CTRL);
1558                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1559                         break;
1560
1561                 mdelay(1);
1562                 timeout--;
1563         }
1564
1565         if (!timeout) {
1566                 e_dbg("SW has already locked the resource.\n");
1567                 ret_val = -E1000_ERR_CONFIG;
1568                 goto out;
1569         }
1570
1571         timeout = SW_FLAG_TIMEOUT;
1572
1573         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1574         ew32(EXTCNF_CTRL, extcnf_ctrl);
1575
1576         while (timeout) {
1577                 extcnf_ctrl = er32(EXTCNF_CTRL);
1578                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1579                         break;
1580
1581                 mdelay(1);
1582                 timeout--;
1583         }
1584
1585         if (!timeout) {
1586                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1587                       er32(FWSM), extcnf_ctrl);
1588                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1589                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1590                 ret_val = -E1000_ERR_CONFIG;
1591                 goto out;
1592         }
1593
1594 out:
1595         if (ret_val)
1596                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1597
1598         return ret_val;
1599 }
1600
1601 /**
1602  *  e1000_release_swflag_ich8lan - Release software control flag
1603  *  @hw: pointer to the HW structure
1604  *
1605  *  Releases the software control flag for performing PHY and select
1606  *  MAC CSR accesses.
1607  **/
1608 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1609 {
1610         u32 extcnf_ctrl;
1611
1612         extcnf_ctrl = er32(EXTCNF_CTRL);
1613
1614         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1615                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1616                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1617         } else {
1618                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1619         }
1620
1621         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1622 }
1623
1624 /**
1625  *  e1000_check_mng_mode_ich8lan - Checks management mode
1626  *  @hw: pointer to the HW structure
1627  *
1628  *  This checks if the adapter has any manageability enabled.
1629  *  This is a function pointer entry point only called by read/write
1630  *  routines for the PHY and NVM parts.
1631  **/
1632 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1633 {
1634         u32 fwsm;
1635
1636         fwsm = er32(FWSM);
1637         return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
1638                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1639                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
1640 }
1641
1642 /**
1643  *  e1000_check_mng_mode_pchlan - Checks management mode
1644  *  @hw: pointer to the HW structure
1645  *
1646  *  This checks if the adapter has iAMT enabled.
1647  *  This is a function pointer entry point only called by read/write
1648  *  routines for the PHY and NVM parts.
1649  **/
1650 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1651 {
1652         u32 fwsm;
1653
1654         fwsm = er32(FWSM);
1655         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1656             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1657 }
1658
1659 /**
1660  *  e1000_rar_set_pch2lan - Set receive address register
1661  *  @hw: pointer to the HW structure
1662  *  @addr: pointer to the receive address
1663  *  @index: receive address array register
1664  *
1665  *  Sets the receive address array register at index to the address passed
1666  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1667  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1668  *  Use SHRA[0-3] in place of those reserved for ME.
1669  **/
1670 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1671 {
1672         u32 rar_low, rar_high;
1673
1674         /* HW expects these in little endian so we reverse the byte order
1675          * from network order (big endian) to little endian
1676          */
1677         rar_low = ((u32)addr[0] |
1678                    ((u32)addr[1] << 8) |
1679                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1680
1681         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1682
1683         /* If MAC address zero, no need to set the AV bit */
1684         if (rar_low || rar_high)
1685                 rar_high |= E1000_RAH_AV;
1686
1687         if (index == 0) {
1688                 ew32(RAL(index), rar_low);
1689                 e1e_flush();
1690                 ew32(RAH(index), rar_high);
1691                 e1e_flush();
1692                 return;
1693         }
1694
1695         /* RAR[1-6] are owned by manageability.  Skip those and program the
1696          * next address into the SHRA register array.
1697          */
1698         if (index < (u32)(hw->mac.rar_entry_count)) {
1699                 s32 ret_val;
1700
1701                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1702                 if (ret_val)
1703                         goto out;
1704
1705                 ew32(SHRAL(index - 1), rar_low);
1706                 e1e_flush();
1707                 ew32(SHRAH(index - 1), rar_high);
1708                 e1e_flush();
1709
1710                 e1000_release_swflag_ich8lan(hw);
1711
1712                 /* verify the register updates */
1713                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1714                     (er32(SHRAH(index - 1)) == rar_high))
1715                         return;
1716
1717                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1718                       (index - 1), er32(FWSM));
1719         }
1720
1721 out:
1722         e_dbg("Failed to write receive address at index %d\n", index);
1723 }
1724
1725 /**
1726  *  e1000_rar_set_pch_lpt - Set receive address registers
1727  *  @hw: pointer to the HW structure
1728  *  @addr: pointer to the receive address
1729  *  @index: receive address array register
1730  *
1731  *  Sets the receive address register array at index to the address passed
1732  *  in by addr. For LPT, RAR[0] is the base address register that is to
1733  *  contain the MAC address. SHRA[0-10] are the shared receive address
1734  *  registers that are shared between the Host and manageability engine (ME).
1735  **/
1736 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1737 {
1738         u32 rar_low, rar_high;
1739         u32 wlock_mac;
1740
1741         /* HW expects these in little endian so we reverse the byte order
1742          * from network order (big endian) to little endian
1743          */
1744         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1745                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1746
1747         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1748
1749         /* If MAC address zero, no need to set the AV bit */
1750         if (rar_low || rar_high)
1751                 rar_high |= E1000_RAH_AV;
1752
1753         if (index == 0) {
1754                 ew32(RAL(index), rar_low);
1755                 e1e_flush();
1756                 ew32(RAH(index), rar_high);
1757                 e1e_flush();
1758                 return;
1759         }
1760
1761         /* The manageability engine (ME) can lock certain SHRAR registers that
1762          * it is using - those registers are unavailable for use.
1763          */
1764         if (index < hw->mac.rar_entry_count) {
1765                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1766                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1767
1768                 /* Check if all SHRAR registers are locked */
1769                 if (wlock_mac == 1)
1770                         goto out;
1771
1772                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1773                         s32 ret_val;
1774
1775                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1776
1777                         if (ret_val)
1778                                 goto out;
1779
1780                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1781                         e1e_flush();
1782                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1783                         e1e_flush();
1784
1785                         e1000_release_swflag_ich8lan(hw);
1786
1787                         /* verify the register updates */
1788                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1789                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1790                                 return;
1791                 }
1792         }
1793
1794 out:
1795         e_dbg("Failed to write receive address at index %d\n", index);
1796 }
1797
1798 /**
1799  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1800  *  @hw: pointer to the HW structure
1801  *
1802  *  Checks if firmware is blocking the reset of the PHY.
1803  *  This is a function pointer entry point only called by
1804  *  reset routines.
1805  **/
1806 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1807 {
1808         bool blocked = false;
1809         int i = 0;
1810
1811         while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
1812                (i++ < 10))
1813                 usleep_range(10000, 20000);
1814         return blocked ? E1000_BLK_PHY_RESET : 0;
1815 }
1816
1817 /**
1818  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1819  *  @hw: pointer to the HW structure
1820  *
1821  *  Assumes semaphore already acquired.
1822  *
1823  **/
1824 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1825 {
1826         u16 phy_data;
1827         u32 strap = er32(STRAP);
1828         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1829             E1000_STRAP_SMT_FREQ_SHIFT;
1830         s32 ret_val;
1831
1832         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1833
1834         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1835         if (ret_val)
1836                 return ret_val;
1837
1838         phy_data &= ~HV_SMB_ADDR_MASK;
1839         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1840         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1841
1842         if (hw->phy.type == e1000_phy_i217) {
1843                 /* Restore SMBus frequency */
1844                 if (freq--) {
1845                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1846                         phy_data |= (freq & (1 << 0)) <<
1847                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
1848                         phy_data |= (freq & (1 << 1)) <<
1849                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1850                 } else {
1851                         e_dbg("Unsupported SMB frequency in PHY\n");
1852                 }
1853         }
1854
1855         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1856 }
1857
1858 /**
1859  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1860  *  @hw:   pointer to the HW structure
1861  *
1862  *  SW should configure the LCD from the NVM extended configuration region
1863  *  as a workaround for certain parts.
1864  **/
1865 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1866 {
1867         struct e1000_phy_info *phy = &hw->phy;
1868         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1869         s32 ret_val = 0;
1870         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1871
1872         /* Initialize the PHY from the NVM on ICH platforms.  This
1873          * is needed due to an issue where the NVM configuration is
1874          * not properly autoloaded after power transitions.
1875          * Therefore, after each PHY reset, we will load the
1876          * configuration data out of the NVM manually.
1877          */
1878         switch (hw->mac.type) {
1879         case e1000_ich8lan:
1880                 if (phy->type != e1000_phy_igp_3)
1881                         return ret_val;
1882
1883                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1884                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1885                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1886                         break;
1887                 }
1888                 /* Fall-thru */
1889         case e1000_pchlan:
1890         case e1000_pch2lan:
1891         case e1000_pch_lpt:
1892                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1893                 break;
1894         default:
1895                 return ret_val;
1896         }
1897
1898         ret_val = hw->phy.ops.acquire(hw);
1899         if (ret_val)
1900                 return ret_val;
1901
1902         data = er32(FEXTNVM);
1903         if (!(data & sw_cfg_mask))
1904                 goto release;
1905
1906         /* Make sure HW does not configure LCD from PHY
1907          * extended configuration before SW configuration
1908          */
1909         data = er32(EXTCNF_CTRL);
1910         if ((hw->mac.type < e1000_pch2lan) &&
1911             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1912                 goto release;
1913
1914         cnf_size = er32(EXTCNF_SIZE);
1915         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1916         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1917         if (!cnf_size)
1918                 goto release;
1919
1920         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1921         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1922
1923         if (((hw->mac.type == e1000_pchlan) &&
1924              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1925             (hw->mac.type > e1000_pchlan)) {
1926                 /* HW configures the SMBus address and LEDs when the
1927                  * OEM and LCD Write Enable bits are set in the NVM.
1928                  * When both NVM bits are cleared, SW will configure
1929                  * them instead.
1930                  */
1931                 ret_val = e1000_write_smbus_addr(hw);
1932                 if (ret_val)
1933                         goto release;
1934
1935                 data = er32(LEDCTL);
1936                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1937                                                         (u16)data);
1938                 if (ret_val)
1939                         goto release;
1940         }
1941
1942         /* Configure LCD from extended configuration region. */
1943
1944         /* cnf_base_addr is in DWORD */
1945         word_addr = (u16)(cnf_base_addr << 1);
1946
1947         for (i = 0; i < cnf_size; i++) {
1948                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
1949                 if (ret_val)
1950                         goto release;
1951
1952                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1953                                          1, &reg_addr);
1954                 if (ret_val)
1955                         goto release;
1956
1957                 /* Save off the PHY page for future writes. */
1958                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1959                         phy_page = reg_data;
1960                         continue;
1961                 }
1962
1963                 reg_addr &= PHY_REG_MASK;
1964                 reg_addr |= phy_page;
1965
1966                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
1967                 if (ret_val)
1968                         goto release;
1969         }
1970
1971 release:
1972         hw->phy.ops.release(hw);
1973         return ret_val;
1974 }
1975
1976 /**
1977  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1978  *  @hw:   pointer to the HW structure
1979  *  @link: link up bool flag
1980  *
1981  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1982  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1983  *  If link is down, the function will restore the default K1 setting located
1984  *  in the NVM.
1985  **/
1986 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1987 {
1988         s32 ret_val = 0;
1989         u16 status_reg = 0;
1990         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1991
1992         if (hw->mac.type != e1000_pchlan)
1993                 return 0;
1994
1995         /* Wrap the whole flow with the sw flag */
1996         ret_val = hw->phy.ops.acquire(hw);
1997         if (ret_val)
1998                 return ret_val;
1999
2000         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2001         if (link) {
2002                 if (hw->phy.type == e1000_phy_82578) {
2003                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2004                                                   &status_reg);
2005                         if (ret_val)
2006                                 goto release;
2007
2008                         status_reg &= (BM_CS_STATUS_LINK_UP |
2009                                        BM_CS_STATUS_RESOLVED |
2010                                        BM_CS_STATUS_SPEED_MASK);
2011
2012                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2013                                            BM_CS_STATUS_RESOLVED |
2014                                            BM_CS_STATUS_SPEED_1000))
2015                                 k1_enable = false;
2016                 }
2017
2018                 if (hw->phy.type == e1000_phy_82577) {
2019                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2020                         if (ret_val)
2021                                 goto release;
2022
2023                         status_reg &= (HV_M_STATUS_LINK_UP |
2024                                        HV_M_STATUS_AUTONEG_COMPLETE |
2025                                        HV_M_STATUS_SPEED_MASK);
2026
2027                         if (status_reg == (HV_M_STATUS_LINK_UP |
2028                                            HV_M_STATUS_AUTONEG_COMPLETE |
2029                                            HV_M_STATUS_SPEED_1000))
2030                                 k1_enable = false;
2031                 }
2032
2033                 /* Link stall fix for link up */
2034                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2035                 if (ret_val)
2036                         goto release;
2037
2038         } else {
2039                 /* Link stall fix for link down */
2040                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2041                 if (ret_val)
2042                         goto release;
2043         }
2044
2045         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2046
2047 release:
2048         hw->phy.ops.release(hw);
2049
2050         return ret_val;
2051 }
2052
2053 /**
2054  *  e1000_configure_k1_ich8lan - Configure K1 power state
2055  *  @hw: pointer to the HW structure
2056  *  @enable: K1 state to configure
2057  *
2058  *  Configure the K1 power state based on the provided parameter.
2059  *  Assumes semaphore already acquired.
2060  *
2061  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2062  **/
2063 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2064 {
2065         s32 ret_val;
2066         u32 ctrl_reg = 0;
2067         u32 ctrl_ext = 0;
2068         u32 reg = 0;
2069         u16 kmrn_reg = 0;
2070
2071         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2072                                               &kmrn_reg);
2073         if (ret_val)
2074                 return ret_val;
2075
2076         if (k1_enable)
2077                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2078         else
2079                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2080
2081         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2082                                                kmrn_reg);
2083         if (ret_val)
2084                 return ret_val;
2085
2086         usleep_range(20, 40);
2087         ctrl_ext = er32(CTRL_EXT);
2088         ctrl_reg = er32(CTRL);
2089
2090         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2091         reg |= E1000_CTRL_FRCSPD;
2092         ew32(CTRL, reg);
2093
2094         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2095         e1e_flush();
2096         usleep_range(20, 40);
2097         ew32(CTRL, ctrl_reg);
2098         ew32(CTRL_EXT, ctrl_ext);
2099         e1e_flush();
2100         usleep_range(20, 40);
2101
2102         return 0;
2103 }
2104
2105 /**
2106  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2107  *  @hw:       pointer to the HW structure
2108  *  @d0_state: boolean if entering d0 or d3 device state
2109  *
2110  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2111  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2112  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2113  **/
2114 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2115 {
2116         s32 ret_val = 0;
2117         u32 mac_reg;
2118         u16 oem_reg;
2119
2120         if (hw->mac.type < e1000_pchlan)
2121                 return ret_val;
2122
2123         ret_val = hw->phy.ops.acquire(hw);
2124         if (ret_val)
2125                 return ret_val;
2126
2127         if (hw->mac.type == e1000_pchlan) {
2128                 mac_reg = er32(EXTCNF_CTRL);
2129                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2130                         goto release;
2131         }
2132
2133         mac_reg = er32(FEXTNVM);
2134         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2135                 goto release;
2136
2137         mac_reg = er32(PHY_CTRL);
2138
2139         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2140         if (ret_val)
2141                 goto release;
2142
2143         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2144
2145         if (d0_state) {
2146                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2147                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2148
2149                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2150                         oem_reg |= HV_OEM_BITS_LPLU;
2151         } else {
2152                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2153                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2154                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2155
2156                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2157                                E1000_PHY_CTRL_NOND0A_LPLU))
2158                         oem_reg |= HV_OEM_BITS_LPLU;
2159         }
2160
2161         /* Set Restart auto-neg to activate the bits */
2162         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2163             !hw->phy.ops.check_reset_block(hw))
2164                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2165
2166         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2167
2168 release:
2169         hw->phy.ops.release(hw);
2170
2171         return ret_val;
2172 }
2173
2174 /**
2175  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2176  *  @hw:   pointer to the HW structure
2177  **/
2178 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2179 {
2180         s32 ret_val;
2181         u16 data;
2182
2183         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2184         if (ret_val)
2185                 return ret_val;
2186
2187         data |= HV_KMRN_MDIO_SLOW;
2188
2189         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2190
2191         return ret_val;
2192 }
2193
2194 /**
2195  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2196  *  done after every PHY reset.
2197  **/
2198 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2199 {
2200         s32 ret_val = 0;
2201         u16 phy_data;
2202
2203         if (hw->mac.type != e1000_pchlan)
2204                 return 0;
2205
2206         /* Set MDIO slow mode before any other MDIO access */
2207         if (hw->phy.type == e1000_phy_82577) {
2208                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2209                 if (ret_val)
2210                         return ret_val;
2211         }
2212
2213         if (((hw->phy.type == e1000_phy_82577) &&
2214              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2215             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2216                 /* Disable generation of early preamble */
2217                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2218                 if (ret_val)
2219                         return ret_val;
2220
2221                 /* Preamble tuning for SSC */
2222                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2223                 if (ret_val)
2224                         return ret_val;
2225         }
2226
2227         if (hw->phy.type == e1000_phy_82578) {
2228                 /* Return registers to default by doing a soft reset then
2229                  * writing 0x3140 to the control register.
2230                  */
2231                 if (hw->phy.revision < 2) {
2232                         e1000e_phy_sw_reset(hw);
2233                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2234                 }
2235         }
2236
2237         /* Select page 0 */
2238         ret_val = hw->phy.ops.acquire(hw);
2239         if (ret_val)
2240                 return ret_val;
2241
2242         hw->phy.addr = 1;
2243         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2244         hw->phy.ops.release(hw);
2245         if (ret_val)
2246                 return ret_val;
2247
2248         /* Configure the K1 Si workaround during phy reset assuming there is
2249          * link so that it disables K1 if link is in 1Gbps.
2250          */
2251         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2252         if (ret_val)
2253                 return ret_val;
2254
2255         /* Workaround for link disconnects on a busy hub in half duplex */
2256         ret_val = hw->phy.ops.acquire(hw);
2257         if (ret_val)
2258                 return ret_val;
2259         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2260         if (ret_val)
2261                 goto release;
2262         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2263         if (ret_val)
2264                 goto release;
2265
2266         /* set MSE higher to enable link to stay up when noise is high */
2267         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2268 release:
2269         hw->phy.ops.release(hw);
2270
2271         return ret_val;
2272 }
2273
2274 /**
2275  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2276  *  @hw:   pointer to the HW structure
2277  **/
2278 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2279 {
2280         u32 mac_reg;
2281         u16 i, phy_reg = 0;
2282         s32 ret_val;
2283
2284         ret_val = hw->phy.ops.acquire(hw);
2285         if (ret_val)
2286                 return;
2287         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2288         if (ret_val)
2289                 goto release;
2290
2291         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2292         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2293                 mac_reg = er32(RAL(i));
2294                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2295                                            (u16)(mac_reg & 0xFFFF));
2296                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2297                                            (u16)((mac_reg >> 16) & 0xFFFF));
2298
2299                 mac_reg = er32(RAH(i));
2300                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2301                                            (u16)(mac_reg & 0xFFFF));
2302                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2303                                            (u16)((mac_reg & E1000_RAH_AV)
2304                                                  >> 16));
2305         }
2306
2307         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2308
2309 release:
2310         hw->phy.ops.release(hw);
2311 }
2312
2313 /**
2314  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2315  *  with 82579 PHY
2316  *  @hw: pointer to the HW structure
2317  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2318  **/
2319 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2320 {
2321         s32 ret_val = 0;
2322         u16 phy_reg, data;
2323         u32 mac_reg;
2324         u16 i;
2325
2326         if (hw->mac.type < e1000_pch2lan)
2327                 return 0;
2328
2329         /* disable Rx path while enabling/disabling workaround */
2330         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2331         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
2332         if (ret_val)
2333                 return ret_val;
2334
2335         if (enable) {
2336                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2337                  * SHRAL/H) and initial CRC values to the MAC
2338                  */
2339                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2340                         u8 mac_addr[ETH_ALEN] = { 0 };
2341                         u32 addr_high, addr_low;
2342
2343                         addr_high = er32(RAH(i));
2344                         if (!(addr_high & E1000_RAH_AV))
2345                                 continue;
2346                         addr_low = er32(RAL(i));
2347                         mac_addr[0] = (addr_low & 0xFF);
2348                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2349                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2350                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2351                         mac_addr[4] = (addr_high & 0xFF);
2352                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2353
2354                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2355                 }
2356
2357                 /* Write Rx addresses to the PHY */
2358                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2359
2360                 /* Enable jumbo frame workaround in the MAC */
2361                 mac_reg = er32(FFLT_DBG);
2362                 mac_reg &= ~(1 << 14);
2363                 mac_reg |= (7 << 15);
2364                 ew32(FFLT_DBG, mac_reg);
2365
2366                 mac_reg = er32(RCTL);
2367                 mac_reg |= E1000_RCTL_SECRC;
2368                 ew32(RCTL, mac_reg);
2369
2370                 ret_val = e1000e_read_kmrn_reg(hw,
2371                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2372                                                &data);
2373                 if (ret_val)
2374                         return ret_val;
2375                 ret_val = e1000e_write_kmrn_reg(hw,
2376                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2377                                                 data | (1 << 0));
2378                 if (ret_val)
2379                         return ret_val;
2380                 ret_val = e1000e_read_kmrn_reg(hw,
2381                                                E1000_KMRNCTRLSTA_HD_CTRL,
2382                                                &data);
2383                 if (ret_val)
2384                         return ret_val;
2385                 data &= ~(0xF << 8);
2386                 data |= (0xB << 8);
2387                 ret_val = e1000e_write_kmrn_reg(hw,
2388                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2389                                                 data);
2390                 if (ret_val)
2391                         return ret_val;
2392
2393                 /* Enable jumbo frame workaround in the PHY */
2394                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2395                 data &= ~(0x7F << 5);
2396                 data |= (0x37 << 5);
2397                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2398                 if (ret_val)
2399                         return ret_val;
2400                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2401                 data &= ~(1 << 13);
2402                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2403                 if (ret_val)
2404                         return ret_val;
2405                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2406                 data &= ~(0x3FF << 2);
2407                 data |= (0x1A << 2);
2408                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2409                 if (ret_val)
2410                         return ret_val;
2411                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2412                 if (ret_val)
2413                         return ret_val;
2414                 e1e_rphy(hw, HV_PM_CTRL, &data);
2415                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2416                 if (ret_val)
2417                         return ret_val;
2418         } else {
2419                 /* Write MAC register values back to h/w defaults */
2420                 mac_reg = er32(FFLT_DBG);
2421                 mac_reg &= ~(0xF << 14);
2422                 ew32(FFLT_DBG, mac_reg);
2423
2424                 mac_reg = er32(RCTL);
2425                 mac_reg &= ~E1000_RCTL_SECRC;
2426                 ew32(RCTL, mac_reg);
2427
2428                 ret_val = e1000e_read_kmrn_reg(hw,
2429                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2430                                                &data);
2431                 if (ret_val)
2432                         return ret_val;
2433                 ret_val = e1000e_write_kmrn_reg(hw,
2434                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2435                                                 data & ~(1 << 0));
2436                 if (ret_val)
2437                         return ret_val;
2438                 ret_val = e1000e_read_kmrn_reg(hw,
2439                                                E1000_KMRNCTRLSTA_HD_CTRL,
2440                                                &data);
2441                 if (ret_val)
2442                         return ret_val;
2443                 data &= ~(0xF << 8);
2444                 data |= (0xB << 8);
2445                 ret_val = e1000e_write_kmrn_reg(hw,
2446                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2447                                                 data);
2448                 if (ret_val)
2449                         return ret_val;
2450
2451                 /* Write PHY register values back to h/w defaults */
2452                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2453                 data &= ~(0x7F << 5);
2454                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2455                 if (ret_val)
2456                         return ret_val;
2457                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2458                 data |= (1 << 13);
2459                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2460                 if (ret_val)
2461                         return ret_val;
2462                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2463                 data &= ~(0x3FF << 2);
2464                 data |= (0x8 << 2);
2465                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2466                 if (ret_val)
2467                         return ret_val;
2468                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2469                 if (ret_val)
2470                         return ret_val;
2471                 e1e_rphy(hw, HV_PM_CTRL, &data);
2472                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2473                 if (ret_val)
2474                         return ret_val;
2475         }
2476
2477         /* re-enable Rx path after enabling/disabling workaround */
2478         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2479 }
2480
2481 /**
2482  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2483  *  done after every PHY reset.
2484  **/
2485 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2486 {
2487         s32 ret_val = 0;
2488
2489         if (hw->mac.type != e1000_pch2lan)
2490                 return 0;
2491
2492         /* Set MDIO slow mode before any other MDIO access */
2493         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2494         if (ret_val)
2495                 return ret_val;
2496
2497         ret_val = hw->phy.ops.acquire(hw);
2498         if (ret_val)
2499                 return ret_val;
2500         /* set MSE higher to enable link to stay up when noise is high */
2501         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2502         if (ret_val)
2503                 goto release;
2504         /* drop link after 5 times MSE threshold was reached */
2505         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2506 release:
2507         hw->phy.ops.release(hw);
2508
2509         return ret_val;
2510 }
2511
2512 /**
2513  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2514  *  @hw:   pointer to the HW structure
2515  *
2516  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2517  *  Disable K1 in 1000Mbps and 100Mbps
2518  **/
2519 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2520 {
2521         s32 ret_val = 0;
2522         u16 status_reg = 0;
2523
2524         if (hw->mac.type != e1000_pch2lan)
2525                 return 0;
2526
2527         /* Set K1 beacon duration based on 10Mbs speed */
2528         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2529         if (ret_val)
2530                 return ret_val;
2531
2532         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2533             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2534                 if (status_reg &
2535                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2536                         u16 pm_phy_reg;
2537
2538                         /* LV 1G/100 Packet drop issue wa  */
2539                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2540                         if (ret_val)
2541                                 return ret_val;
2542                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2543                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2544                         if (ret_val)
2545                                 return ret_val;
2546                 } else {
2547                         u32 mac_reg;
2548
2549                         mac_reg = er32(FEXTNVM4);
2550                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2551                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2552                         ew32(FEXTNVM4, mac_reg);
2553                 }
2554         }
2555
2556         return ret_val;
2557 }
2558
2559 /**
2560  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2561  *  @hw:   pointer to the HW structure
2562  *  @gate: boolean set to true to gate, false to ungate
2563  *
2564  *  Gate/ungate the automatic PHY configuration via hardware; perform
2565  *  the configuration via software instead.
2566  **/
2567 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2568 {
2569         u32 extcnf_ctrl;
2570
2571         if (hw->mac.type < e1000_pch2lan)
2572                 return;
2573
2574         extcnf_ctrl = er32(EXTCNF_CTRL);
2575
2576         if (gate)
2577                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2578         else
2579                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2580
2581         ew32(EXTCNF_CTRL, extcnf_ctrl);
2582 }
2583
2584 /**
2585  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2586  *  @hw: pointer to the HW structure
2587  *
2588  *  Check the appropriate indication the MAC has finished configuring the
2589  *  PHY after a software reset.
2590  **/
2591 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2592 {
2593         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2594
2595         /* Wait for basic configuration completes before proceeding */
2596         do {
2597                 data = er32(STATUS);
2598                 data &= E1000_STATUS_LAN_INIT_DONE;
2599                 usleep_range(100, 200);
2600         } while ((!data) && --loop);
2601
2602         /* If basic configuration is incomplete before the above loop
2603          * count reaches 0, loading the configuration from NVM will
2604          * leave the PHY in a bad state possibly resulting in no link.
2605          */
2606         if (loop == 0)
2607                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2608
2609         /* Clear the Init Done bit for the next init event */
2610         data = er32(STATUS);
2611         data &= ~E1000_STATUS_LAN_INIT_DONE;
2612         ew32(STATUS, data);
2613 }
2614
2615 /**
2616  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2617  *  @hw: pointer to the HW structure
2618  **/
2619 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2620 {
2621         s32 ret_val = 0;
2622         u16 reg;
2623
2624         if (hw->phy.ops.check_reset_block(hw))
2625                 return 0;
2626
2627         /* Allow time for h/w to get to quiescent state after reset */
2628         usleep_range(10000, 20000);
2629
2630         /* Perform any necessary post-reset workarounds */
2631         switch (hw->mac.type) {
2632         case e1000_pchlan:
2633                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2634                 if (ret_val)
2635                         return ret_val;
2636                 break;
2637         case e1000_pch2lan:
2638                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2639                 if (ret_val)
2640                         return ret_val;
2641                 break;
2642         default:
2643                 break;
2644         }
2645
2646         /* Clear the host wakeup bit after lcd reset */
2647         if (hw->mac.type >= e1000_pchlan) {
2648                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2649                 reg &= ~BM_WUC_HOST_WU_BIT;
2650                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2651         }
2652
2653         /* Configure the LCD with the extended configuration region in NVM */
2654         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2655         if (ret_val)
2656                 return ret_val;
2657
2658         /* Configure the LCD with the OEM bits in NVM */
2659         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2660
2661         if (hw->mac.type == e1000_pch2lan) {
2662                 /* Ungate automatic PHY configuration on non-managed 82579 */
2663                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2664                         usleep_range(10000, 20000);
2665                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2666                 }
2667
2668                 /* Set EEE LPI Update Timer to 200usec */
2669                 ret_val = hw->phy.ops.acquire(hw);
2670                 if (ret_val)
2671                         return ret_val;
2672                 ret_val = e1000_write_emi_reg_locked(hw,
2673                                                      I82579_LPI_UPDATE_TIMER,
2674                                                      0x1387);
2675                 hw->phy.ops.release(hw);
2676         }
2677
2678         return ret_val;
2679 }
2680
2681 /**
2682  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2683  *  @hw: pointer to the HW structure
2684  *
2685  *  Resets the PHY
2686  *  This is a function pointer entry point called by drivers
2687  *  or other shared routines.
2688  **/
2689 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2690 {
2691         s32 ret_val = 0;
2692
2693         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2694         if ((hw->mac.type == e1000_pch2lan) &&
2695             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2696                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2697
2698         ret_val = e1000e_phy_hw_reset_generic(hw);
2699         if (ret_val)
2700                 return ret_val;
2701
2702         return e1000_post_phy_reset_ich8lan(hw);
2703 }
2704
2705 /**
2706  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2707  *  @hw: pointer to the HW structure
2708  *  @active: true to enable LPLU, false to disable
2709  *
2710  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2711  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2712  *  the phy speed. This function will manually set the LPLU bit and restart
2713  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2714  *  since it configures the same bit.
2715  **/
2716 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2717 {
2718         s32 ret_val;
2719         u16 oem_reg;
2720
2721         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2722         if (ret_val)
2723                 return ret_val;
2724
2725         if (active)
2726                 oem_reg |= HV_OEM_BITS_LPLU;
2727         else
2728                 oem_reg &= ~HV_OEM_BITS_LPLU;
2729
2730         if (!hw->phy.ops.check_reset_block(hw))
2731                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2732
2733         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2734 }
2735
2736 /**
2737  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2738  *  @hw: pointer to the HW structure
2739  *  @active: true to enable LPLU, false to disable
2740  *
2741  *  Sets the LPLU D0 state according to the active flag.  When
2742  *  activating LPLU this function also disables smart speed
2743  *  and vice versa.  LPLU will not be activated unless the
2744  *  device autonegotiation advertisement meets standards of
2745  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2746  *  This is a function pointer entry point only called by
2747  *  PHY setup routines.
2748  **/
2749 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2750 {
2751         struct e1000_phy_info *phy = &hw->phy;
2752         u32 phy_ctrl;
2753         s32 ret_val = 0;
2754         u16 data;
2755
2756         if (phy->type == e1000_phy_ife)
2757                 return 0;
2758
2759         phy_ctrl = er32(PHY_CTRL);
2760
2761         if (active) {
2762                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2763                 ew32(PHY_CTRL, phy_ctrl);
2764
2765                 if (phy->type != e1000_phy_igp_3)
2766                         return 0;
2767
2768                 /* Call gig speed drop workaround on LPLU before accessing
2769                  * any PHY registers
2770                  */
2771                 if (hw->mac.type == e1000_ich8lan)
2772                         e1000e_gig_downshift_workaround_ich8lan(hw);
2773
2774                 /* When LPLU is enabled, we should disable SmartSpeed */
2775                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2776                 if (ret_val)
2777                         return ret_val;
2778                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2779                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2780                 if (ret_val)
2781                         return ret_val;
2782         } else {
2783                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2784                 ew32(PHY_CTRL, phy_ctrl);
2785
2786                 if (phy->type != e1000_phy_igp_3)
2787                         return 0;
2788
2789                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2790                  * during Dx states where the power conservation is most
2791                  * important.  During driver activity we should enable
2792                  * SmartSpeed, so performance is maintained.
2793                  */
2794                 if (phy->smart_speed == e1000_smart_speed_on) {
2795                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2796                                            &data);
2797                         if (ret_val)
2798                                 return ret_val;
2799
2800                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2801                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2802                                            data);
2803                         if (ret_val)
2804                                 return ret_val;
2805                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2806                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2807                                            &data);
2808                         if (ret_val)
2809                                 return ret_val;
2810
2811                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2812                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2813                                            data);
2814                         if (ret_val)
2815                                 return ret_val;
2816                 }
2817         }
2818
2819         return 0;
2820 }
2821
2822 /**
2823  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2824  *  @hw: pointer to the HW structure
2825  *  @active: true to enable LPLU, false to disable
2826  *
2827  *  Sets the LPLU D3 state according to the active flag.  When
2828  *  activating LPLU this function also disables smart speed
2829  *  and vice versa.  LPLU will not be activated unless the
2830  *  device autonegotiation advertisement meets standards of
2831  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2832  *  This is a function pointer entry point only called by
2833  *  PHY setup routines.
2834  **/
2835 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2836 {
2837         struct e1000_phy_info *phy = &hw->phy;
2838         u32 phy_ctrl;
2839         s32 ret_val = 0;
2840         u16 data;
2841
2842         phy_ctrl = er32(PHY_CTRL);
2843
2844         if (!active) {
2845                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2846                 ew32(PHY_CTRL, phy_ctrl);
2847
2848                 if (phy->type != e1000_phy_igp_3)
2849                         return 0;
2850
2851                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2852                  * during Dx states where the power conservation is most
2853                  * important.  During driver activity we should enable
2854                  * SmartSpeed, so performance is maintained.
2855                  */
2856                 if (phy->smart_speed == e1000_smart_speed_on) {
2857                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2858                                            &data);
2859                         if (ret_val)
2860                                 return ret_val;
2861
2862                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2863                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2864                                            data);
2865                         if (ret_val)
2866                                 return ret_val;
2867                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2868                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2869                                            &data);
2870                         if (ret_val)
2871                                 return ret_val;
2872
2873                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2874                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2875                                            data);
2876                         if (ret_val)
2877                                 return ret_val;
2878                 }
2879         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2880                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2881                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2882                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2883                 ew32(PHY_CTRL, phy_ctrl);
2884
2885                 if (phy->type != e1000_phy_igp_3)
2886                         return 0;
2887
2888                 /* Call gig speed drop workaround on LPLU before accessing
2889                  * any PHY registers
2890                  */
2891                 if (hw->mac.type == e1000_ich8lan)
2892                         e1000e_gig_downshift_workaround_ich8lan(hw);
2893
2894                 /* When LPLU is enabled, we should disable SmartSpeed */
2895                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2896                 if (ret_val)
2897                         return ret_val;
2898
2899                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2900                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2901         }
2902
2903         return ret_val;
2904 }
2905
2906 /**
2907  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2908  *  @hw: pointer to the HW structure
2909  *  @bank:  pointer to the variable that returns the active bank
2910  *
2911  *  Reads signature byte from the NVM using the flash access registers.
2912  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2913  **/
2914 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2915 {
2916         u32 eecd;
2917         struct e1000_nvm_info *nvm = &hw->nvm;
2918         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2919         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2920         u8 sig_byte = 0;
2921         s32 ret_val;
2922
2923         switch (hw->mac.type) {
2924         case e1000_ich8lan:
2925         case e1000_ich9lan:
2926                 eecd = er32(EECD);
2927                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2928                     E1000_EECD_SEC1VAL_VALID_MASK) {
2929                         if (eecd & E1000_EECD_SEC1VAL)
2930                                 *bank = 1;
2931                         else
2932                                 *bank = 0;
2933
2934                         return 0;
2935                 }
2936                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2937                 /* fall-thru */
2938         default:
2939                 /* set bank to 0 in case flash read fails */
2940                 *bank = 0;
2941
2942                 /* Check bank 0 */
2943                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2944                                                         &sig_byte);
2945                 if (ret_val)
2946                         return ret_val;
2947                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2948                     E1000_ICH_NVM_SIG_VALUE) {
2949                         *bank = 0;
2950                         return 0;
2951                 }
2952
2953                 /* Check bank 1 */
2954                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2955                                                         bank1_offset,
2956                                                         &sig_byte);
2957                 if (ret_val)
2958                         return ret_val;
2959                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2960                     E1000_ICH_NVM_SIG_VALUE) {
2961                         *bank = 1;
2962                         return 0;
2963                 }
2964
2965                 e_dbg("ERROR: No valid NVM bank present\n");
2966                 return -E1000_ERR_NVM;
2967         }
2968 }
2969
2970 /**
2971  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2972  *  @hw: pointer to the HW structure
2973  *  @offset: The offset (in bytes) of the word(s) to read.
2974  *  @words: Size of data to read in words
2975  *  @data: Pointer to the word(s) to read at offset.
2976  *
2977  *  Reads a word(s) from the NVM using the flash access registers.
2978  **/
2979 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2980                                   u16 *data)
2981 {
2982         struct e1000_nvm_info *nvm = &hw->nvm;
2983         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2984         u32 act_offset;
2985         s32 ret_val = 0;
2986         u32 bank = 0;
2987         u16 i, word;
2988
2989         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2990             (words == 0)) {
2991                 e_dbg("nvm parameter(s) out of bounds\n");
2992                 ret_val = -E1000_ERR_NVM;
2993                 goto out;
2994         }
2995
2996         nvm->ops.acquire(hw);
2997
2998         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2999         if (ret_val) {
3000                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3001                 bank = 0;
3002         }
3003
3004         act_offset = (bank) ? nvm->flash_bank_size : 0;
3005         act_offset += offset;
3006
3007         ret_val = 0;
3008         for (i = 0; i < words; i++) {
3009                 if (dev_spec->shadow_ram[offset + i].modified) {
3010                         data[i] = dev_spec->shadow_ram[offset + i].value;
3011                 } else {
3012                         ret_val = e1000_read_flash_word_ich8lan(hw,
3013                                                                 act_offset + i,
3014                                                                 &word);
3015                         if (ret_val)
3016                                 break;
3017                         data[i] = word;
3018                 }
3019         }
3020
3021         nvm->ops.release(hw);
3022
3023 out:
3024         if (ret_val)
3025                 e_dbg("NVM read error: %d\n", ret_val);
3026
3027         return ret_val;
3028 }
3029
3030 /**
3031  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3032  *  @hw: pointer to the HW structure
3033  *
3034  *  This function does initial flash setup so that a new read/write/erase cycle
3035  *  can be started.
3036  **/
3037 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3038 {
3039         union ich8_hws_flash_status hsfsts;
3040         s32 ret_val = -E1000_ERR_NVM;
3041
3042         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3043
3044         /* Check if the flash descriptor is valid */
3045         if (!hsfsts.hsf_status.fldesvalid) {
3046                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
3047                 return -E1000_ERR_NVM;
3048         }
3049
3050         /* Clear FCERR and DAEL in hw status by writing 1 */
3051         hsfsts.hsf_status.flcerr = 1;
3052         hsfsts.hsf_status.dael = 1;
3053
3054         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3055
3056         /* Either we should have a hardware SPI cycle in progress
3057          * bit to check against, in order to start a new cycle or
3058          * FDONE bit should be changed in the hardware so that it
3059          * is 1 after hardware reset, which can then be used as an
3060          * indication whether a cycle is in progress or has been
3061          * completed.
3062          */
3063
3064         if (!hsfsts.hsf_status.flcinprog) {
3065                 /* There is no cycle running at present,
3066                  * so we can start a cycle.
3067                  * Begin by setting Flash Cycle Done.
3068                  */
3069                 hsfsts.hsf_status.flcdone = 1;
3070                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3071                 ret_val = 0;
3072         } else {
3073                 s32 i;
3074
3075                 /* Otherwise poll for sometime so the current
3076                  * cycle has a chance to end before giving up.
3077                  */
3078                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3079                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3080                         if (!hsfsts.hsf_status.flcinprog) {
3081                                 ret_val = 0;
3082                                 break;
3083                         }
3084                         udelay(1);
3085                 }
3086                 if (!ret_val) {
3087                         /* Successful in waiting for previous cycle to timeout,
3088                          * now set the Flash Cycle Done.
3089                          */
3090                         hsfsts.hsf_status.flcdone = 1;
3091                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3092                 } else {
3093                         e_dbg("Flash controller busy, cannot get access\n");
3094                 }
3095         }
3096
3097         return ret_val;
3098 }
3099
3100 /**
3101  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3102  *  @hw: pointer to the HW structure
3103  *  @timeout: maximum time to wait for completion
3104  *
3105  *  This function starts a flash cycle and waits for its completion.
3106  **/
3107 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3108 {
3109         union ich8_hws_flash_ctrl hsflctl;
3110         union ich8_hws_flash_status hsfsts;
3111         u32 i = 0;
3112
3113         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3114         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3115         hsflctl.hsf_ctrl.flcgo = 1;
3116         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3117
3118         /* wait till FDONE bit is set to 1 */
3119         do {
3120                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3121                 if (hsfsts.hsf_status.flcdone)
3122                         break;
3123                 udelay(1);
3124         } while (i++ < timeout);
3125
3126         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3127                 return 0;
3128
3129         return -E1000_ERR_NVM;
3130 }
3131
3132 /**
3133  *  e1000_read_flash_word_ich8lan - Read word from flash
3134  *  @hw: pointer to the HW structure
3135  *  @offset: offset to data location
3136  *  @data: pointer to the location for storing the data
3137  *
3138  *  Reads the flash word at offset into data.  Offset is converted
3139  *  to bytes before read.
3140  **/
3141 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3142                                          u16 *data)
3143 {
3144         /* Must convert offset into bytes. */
3145         offset <<= 1;
3146
3147         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3148 }
3149
3150 /**
3151  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3152  *  @hw: pointer to the HW structure
3153  *  @offset: The offset of the byte to read.
3154  *  @data: Pointer to a byte to store the value read.
3155  *
3156  *  Reads a single byte from the NVM using the flash access registers.
3157  **/
3158 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3159                                          u8 *data)
3160 {
3161         s32 ret_val;
3162         u16 word = 0;
3163
3164         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3165         if (ret_val)
3166                 return ret_val;
3167
3168         *data = (u8)word;
3169
3170         return 0;
3171 }
3172
3173 /**
3174  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3175  *  @hw: pointer to the HW structure
3176  *  @offset: The offset (in bytes) of the byte or word to read.
3177  *  @size: Size of data to read, 1=byte 2=word
3178  *  @data: Pointer to the word to store the value read.
3179  *
3180  *  Reads a byte or word from the NVM using the flash access registers.
3181  **/
3182 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3183                                          u8 size, u16 *data)
3184 {
3185         union ich8_hws_flash_status hsfsts;
3186         union ich8_hws_flash_ctrl hsflctl;
3187         u32 flash_linear_addr;
3188         u32 flash_data = 0;
3189         s32 ret_val = -E1000_ERR_NVM;
3190         u8 count = 0;
3191
3192         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3193                 return -E1000_ERR_NVM;
3194
3195         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3196                              hw->nvm.flash_base_addr);
3197
3198         do {
3199                 udelay(1);
3200                 /* Steps */
3201                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3202                 if (ret_val)
3203                         break;
3204
3205                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3206                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3207                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3208                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3209                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3210
3211                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3212
3213                 ret_val =
3214                     e1000_flash_cycle_ich8lan(hw,
3215                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3216
3217                 /* Check if FCERR is set to 1, if set to 1, clear it
3218                  * and try the whole sequence a few more times, else
3219                  * read in (shift in) the Flash Data0, the order is
3220                  * least significant byte first msb to lsb
3221                  */
3222                 if (!ret_val) {
3223                         flash_data = er32flash(ICH_FLASH_FDATA0);
3224                         if (size == 1)
3225                                 *data = (u8)(flash_data & 0x000000FF);
3226                         else if (size == 2)
3227                                 *data = (u16)(flash_data & 0x0000FFFF);
3228                         break;
3229                 } else {
3230                         /* If we've gotten here, then things are probably
3231                          * completely hosed, but if the error condition is
3232                          * detected, it won't hurt to give it another try...
3233                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3234                          */
3235                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3236                         if (hsfsts.hsf_status.flcerr) {
3237                                 /* Repeat for some time before giving up. */
3238                                 continue;
3239                         } else if (!hsfsts.hsf_status.flcdone) {
3240                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3241                                 break;
3242                         }
3243                 }
3244         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3245
3246         return ret_val;
3247 }
3248
3249 /**
3250  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3251  *  @hw: pointer to the HW structure
3252  *  @offset: The offset (in bytes) of the word(s) to write.
3253  *  @words: Size of data to write in words
3254  *  @data: Pointer to the word(s) to write at offset.
3255  *
3256  *  Writes a byte or word to the NVM using the flash access registers.
3257  **/
3258 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3259                                    u16 *data)
3260 {
3261         struct e1000_nvm_info *nvm = &hw->nvm;
3262         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3263         u16 i;
3264
3265         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3266             (words == 0)) {
3267                 e_dbg("nvm parameter(s) out of bounds\n");
3268                 return -E1000_ERR_NVM;
3269         }
3270
3271         nvm->ops.acquire(hw);
3272
3273         for (i = 0; i < words; i++) {
3274                 dev_spec->shadow_ram[offset + i].modified = true;
3275                 dev_spec->shadow_ram[offset + i].value = data[i];
3276         }
3277
3278         nvm->ops.release(hw);
3279
3280         return 0;
3281 }
3282
3283 /**
3284  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3285  *  @hw: pointer to the HW structure
3286  *
3287  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3288  *  which writes the checksum to the shadow ram.  The changes in the shadow
3289  *  ram are then committed to the EEPROM by processing each bank at a time
3290  *  checking for the modified bit and writing only the pending changes.
3291  *  After a successful commit, the shadow ram is cleared and is ready for
3292  *  future writes.
3293  **/
3294 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3295 {
3296         struct e1000_nvm_info *nvm = &hw->nvm;
3297         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3298         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3299         s32 ret_val;
3300         u16 data;
3301
3302         ret_val = e1000e_update_nvm_checksum_generic(hw);
3303         if (ret_val)
3304                 goto out;
3305
3306         if (nvm->type != e1000_nvm_flash_sw)
3307                 goto out;
3308
3309         nvm->ops.acquire(hw);
3310
3311         /* We're writing to the opposite bank so if we're on bank 1,
3312          * write to bank 0 etc.  We also need to erase the segment that
3313          * is going to be written
3314          */
3315         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3316         if (ret_val) {
3317                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3318                 bank = 0;
3319         }
3320
3321         if (bank == 0) {
3322                 new_bank_offset = nvm->flash_bank_size;
3323                 old_bank_offset = 0;
3324                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3325                 if (ret_val)
3326                         goto release;
3327         } else {
3328                 old_bank_offset = nvm->flash_bank_size;
3329                 new_bank_offset = 0;
3330                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3331                 if (ret_val)
3332                         goto release;
3333         }
3334
3335         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3336                 /* Determine whether to write the value stored
3337                  * in the other NVM bank or a modified value stored
3338                  * in the shadow RAM
3339                  */
3340                 if (dev_spec->shadow_ram[i].modified) {
3341                         data = dev_spec->shadow_ram[i].value;
3342                 } else {
3343                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3344                                                                 old_bank_offset,
3345                                                                 &data);
3346                         if (ret_val)
3347                                 break;
3348                 }
3349
3350                 /* If the word is 0x13, then make sure the signature bits
3351                  * (15:14) are 11b until the commit has completed.
3352                  * This will allow us to write 10b which indicates the
3353                  * signature is valid.  We want to do this after the write
3354                  * has completed so that we don't mark the segment valid
3355                  * while the write is still in progress
3356                  */
3357                 if (i == E1000_ICH_NVM_SIG_WORD)
3358                         data |= E1000_ICH_NVM_SIG_MASK;
3359
3360                 /* Convert offset to bytes. */
3361                 act_offset = (i + new_bank_offset) << 1;
3362
3363                 usleep_range(100, 200);
3364                 /* Write the bytes to the new bank. */
3365                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3366                                                                act_offset,
3367                                                                (u8)data);
3368                 if (ret_val)
3369                         break;
3370
3371                 usleep_range(100, 200);
3372                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3373                                                                act_offset + 1,
3374                                                                (u8)(data >> 8));
3375                 if (ret_val)
3376                         break;
3377         }
3378
3379         /* Don't bother writing the segment valid bits if sector
3380          * programming failed.
3381          */
3382         if (ret_val) {
3383                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3384                 e_dbg("Flash commit failed.\n");
3385                 goto release;
3386         }
3387
3388         /* Finally validate the new segment by setting bit 15:14
3389          * to 10b in word 0x13 , this can be done without an
3390          * erase as well since these bits are 11 to start with
3391          * and we need to change bit 14 to 0b
3392          */
3393         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3394         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3395         if (ret_val)
3396                 goto release;
3397
3398         data &= 0xBFFF;
3399         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3400                                                        act_offset * 2 + 1,
3401                                                        (u8)(data >> 8));
3402         if (ret_val)
3403                 goto release;
3404
3405         /* And invalidate the previously valid segment by setting
3406          * its signature word (0x13) high_byte to 0b. This can be
3407          * done without an erase because flash erase sets all bits
3408          * to 1's. We can write 1's to 0's without an erase
3409          */
3410         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3411         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3412         if (ret_val)
3413                 goto release;
3414
3415         /* Great!  Everything worked, we can now clear the cached entries. */
3416         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3417                 dev_spec->shadow_ram[i].modified = false;
3418                 dev_spec->shadow_ram[i].value = 0xFFFF;
3419         }
3420
3421 release:
3422         nvm->ops.release(hw);
3423
3424         /* Reload the EEPROM, or else modifications will not appear
3425          * until after the next adapter reset.
3426          */
3427         if (!ret_val) {
3428                 nvm->ops.reload(hw);
3429                 usleep_range(10000, 20000);
3430         }
3431
3432 out:
3433         if (ret_val)
3434                 e_dbg("NVM update error: %d\n", ret_val);
3435
3436         return ret_val;
3437 }
3438
3439 /**
3440  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3441  *  @hw: pointer to the HW structure
3442  *
3443  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3444  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3445  *  calculated, in which case we need to calculate the checksum and set bit 6.
3446  **/
3447 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3448 {
3449         s32 ret_val;
3450         u16 data;
3451         u16 word;
3452         u16 valid_csum_mask;
3453
3454         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3455          * the checksum needs to be fixed.  This bit is an indication that
3456          * the NVM was prepared by OEM software and did not calculate
3457          * the checksum...a likely scenario.
3458          */
3459         switch (hw->mac.type) {
3460         case e1000_pch_lpt:
3461                 word = NVM_COMPAT;
3462                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3463                 break;
3464         default:
3465                 word = NVM_FUTURE_INIT_WORD1;
3466                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3467                 break;
3468         }
3469
3470         ret_val = e1000_read_nvm(hw, word, 1, &data);
3471         if (ret_val)
3472                 return ret_val;
3473
3474         if (!(data & valid_csum_mask)) {
3475                 data |= valid_csum_mask;
3476                 ret_val = e1000_write_nvm(hw, word, 1, &data);
3477                 if (ret_val)
3478                         return ret_val;
3479                 ret_val = e1000e_update_nvm_checksum(hw);
3480                 if (ret_val)
3481                         return ret_val;
3482         }
3483
3484         return e1000e_validate_nvm_checksum_generic(hw);
3485 }
3486
3487 /**
3488  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3489  *  @hw: pointer to the HW structure
3490  *
3491  *  To prevent malicious write/erase of the NVM, set it to be read-only
3492  *  so that the hardware ignores all write/erase cycles of the NVM via
3493  *  the flash control registers.  The shadow-ram copy of the NVM will
3494  *  still be updated, however any updates to this copy will not stick
3495  *  across driver reloads.
3496  **/
3497 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3498 {
3499         struct e1000_nvm_info *nvm = &hw->nvm;
3500         union ich8_flash_protected_range pr0;
3501         union ich8_hws_flash_status hsfsts;
3502         u32 gfpreg;
3503
3504         nvm->ops.acquire(hw);
3505
3506         gfpreg = er32flash(ICH_FLASH_GFPREG);
3507
3508         /* Write-protect GbE Sector of NVM */
3509         pr0.regval = er32flash(ICH_FLASH_PR0);
3510         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3511         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3512         pr0.range.wpe = true;
3513         ew32flash(ICH_FLASH_PR0, pr0.regval);
3514
3515         /* Lock down a subset of GbE Flash Control Registers, e.g.
3516          * PR0 to prevent the write-protection from being lifted.
3517          * Once FLOCKDN is set, the registers protected by it cannot
3518          * be written until FLOCKDN is cleared by a hardware reset.
3519          */
3520         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3521         hsfsts.hsf_status.flockdn = true;
3522         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3523
3524         nvm->ops.release(hw);
3525 }
3526
3527 /**
3528  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3529  *  @hw: pointer to the HW structure
3530  *  @offset: The offset (in bytes) of the byte/word to read.
3531  *  @size: Size of data to read, 1=byte 2=word
3532  *  @data: The byte(s) to write to the NVM.
3533  *
3534  *  Writes one/two bytes to the NVM using the flash access registers.
3535  **/
3536 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3537                                           u8 size, u16 data)
3538 {
3539         union ich8_hws_flash_status hsfsts;
3540         union ich8_hws_flash_ctrl hsflctl;
3541         u32 flash_linear_addr;
3542         u32 flash_data = 0;
3543         s32 ret_val;
3544         u8 count = 0;
3545
3546         if (size < 1 || size > 2 || data > size * 0xff ||
3547             offset > ICH_FLASH_LINEAR_ADDR_MASK)
3548                 return -E1000_ERR_NVM;
3549
3550         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3551                              hw->nvm.flash_base_addr);
3552
3553         do {
3554                 udelay(1);
3555                 /* Steps */
3556                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3557                 if (ret_val)
3558                         break;
3559
3560                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3561                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3562                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3563                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3564                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3565
3566                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3567
3568                 if (size == 1)
3569                         flash_data = (u32)data & 0x00FF;
3570                 else
3571                         flash_data = (u32)data;
3572
3573                 ew32flash(ICH_FLASH_FDATA0, flash_data);
3574
3575                 /* check if FCERR is set to 1 , if set to 1, clear it
3576                  * and try the whole sequence a few more times else done
3577                  */
3578                 ret_val =
3579                     e1000_flash_cycle_ich8lan(hw,
3580                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3581                 if (!ret_val)
3582                         break;
3583
3584                 /* If we're here, then things are most likely
3585                  * completely hosed, but if the error condition
3586                  * is detected, it won't hurt to give it another
3587                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3588                  */
3589                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3590                 if (hsfsts.hsf_status.flcerr)
3591                         /* Repeat for some time before giving up. */
3592                         continue;
3593                 if (!hsfsts.hsf_status.flcdone) {
3594                         e_dbg("Timeout error - flash cycle did not complete.\n");
3595                         break;
3596                 }
3597         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3598
3599         return ret_val;
3600 }
3601
3602 /**
3603  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3604  *  @hw: pointer to the HW structure
3605  *  @offset: The index of the byte to read.
3606  *  @data: The byte to write to the NVM.
3607  *
3608  *  Writes a single byte to the NVM using the flash access registers.
3609  **/
3610 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3611                                           u8 data)
3612 {
3613         u16 word = (u16)data;
3614
3615         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3616 }
3617
3618 /**
3619  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3620  *  @hw: pointer to the HW structure
3621  *  @offset: The offset of the byte to write.
3622  *  @byte: The byte to write to the NVM.
3623  *
3624  *  Writes a single byte to the NVM using the flash access registers.
3625  *  Goes through a retry algorithm before giving up.
3626  **/
3627 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3628                                                 u32 offset, u8 byte)
3629 {
3630         s32 ret_val;
3631         u16 program_retries;
3632
3633         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3634         if (!ret_val)
3635                 return ret_val;
3636
3637         for (program_retries = 0; program_retries < 100; program_retries++) {
3638                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3639                 usleep_range(100, 200);
3640                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3641                 if (!ret_val)
3642                         break;
3643         }
3644         if (program_retries == 100)
3645                 return -E1000_ERR_NVM;
3646
3647         return 0;
3648 }
3649
3650 /**
3651  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3652  *  @hw: pointer to the HW structure
3653  *  @bank: 0 for first bank, 1 for second bank, etc.
3654  *
3655  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3656  *  bank N is 4096 * N + flash_reg_addr.
3657  **/
3658 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3659 {
3660         struct e1000_nvm_info *nvm = &hw->nvm;
3661         union ich8_hws_flash_status hsfsts;
3662         union ich8_hws_flash_ctrl hsflctl;
3663         u32 flash_linear_addr;
3664         /* bank size is in 16bit words - adjust to bytes */
3665         u32 flash_bank_size = nvm->flash_bank_size * 2;
3666         s32 ret_val;
3667         s32 count = 0;
3668         s32 j, iteration, sector_size;
3669
3670         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3671
3672         /* Determine HW Sector size: Read BERASE bits of hw flash status
3673          * register
3674          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3675          *     consecutive sectors.  The start index for the nth Hw sector
3676          *     can be calculated as = bank * 4096 + n * 256
3677          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3678          *     The start index for the nth Hw sector can be calculated
3679          *     as = bank * 4096
3680          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3681          *     (ich9 only, otherwise error condition)
3682          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3683          */
3684         switch (hsfsts.hsf_status.berasesz) {
3685         case 0:
3686                 /* Hw sector size 256 */
3687                 sector_size = ICH_FLASH_SEG_SIZE_256;
3688                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3689                 break;
3690         case 1:
3691                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3692                 iteration = 1;
3693                 break;
3694         case 2:
3695                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3696                 iteration = 1;
3697                 break;
3698         case 3:
3699                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3700                 iteration = 1;
3701                 break;
3702         default:
3703                 return -E1000_ERR_NVM;
3704         }
3705
3706         /* Start with the base address, then add the sector offset. */
3707         flash_linear_addr = hw->nvm.flash_base_addr;
3708         flash_linear_addr += (bank) ? flash_bank_size : 0;
3709
3710         for (j = 0; j < iteration; j++) {
3711                 do {
3712                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3713
3714                         /* Steps */
3715                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3716                         if (ret_val)
3717                                 return ret_val;
3718
3719                         /* Write a value 11 (block Erase) in Flash
3720                          * Cycle field in hw flash control
3721                          */
3722                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3723                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3724                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3725
3726                         /* Write the last 24 bits of an index within the
3727                          * block into Flash Linear address field in Flash
3728                          * Address.
3729                          */
3730                         flash_linear_addr += (j * sector_size);
3731                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3732
3733                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3734                         if (!ret_val)
3735                                 break;
3736
3737                         /* Check if FCERR is set to 1.  If 1,
3738                          * clear it and try the whole sequence
3739                          * a few more times else Done
3740                          */
3741                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3742                         if (hsfsts.hsf_status.flcerr)
3743                                 /* repeat for some time before giving up */
3744                                 continue;
3745                         else if (!hsfsts.hsf_status.flcdone)
3746                                 return ret_val;
3747                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3748         }
3749
3750         return 0;
3751 }
3752
3753 /**
3754  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3755  *  @hw: pointer to the HW structure
3756  *  @data: Pointer to the LED settings
3757  *
3758  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3759  *  settings is all 0's or F's, set the LED default to a valid LED default
3760  *  setting.
3761  **/
3762 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3763 {
3764         s32 ret_val;
3765
3766         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3767         if (ret_val) {
3768                 e_dbg("NVM Read Error\n");
3769                 return ret_val;
3770         }
3771
3772         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3773                 *data = ID_LED_DEFAULT_ICH8LAN;
3774
3775         return 0;
3776 }
3777
3778 /**
3779  *  e1000_id_led_init_pchlan - store LED configurations
3780  *  @hw: pointer to the HW structure
3781  *
3782  *  PCH does not control LEDs via the LEDCTL register, rather it uses
3783  *  the PHY LED configuration register.
3784  *
3785  *  PCH also does not have an "always on" or "always off" mode which
3786  *  complicates the ID feature.  Instead of using the "on" mode to indicate
3787  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3788  *  use "link_up" mode.  The LEDs will still ID on request if there is no
3789  *  link based on logic in e1000_led_[on|off]_pchlan().
3790  **/
3791 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3792 {
3793         struct e1000_mac_info *mac = &hw->mac;
3794         s32 ret_val;
3795         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3796         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3797         u16 data, i, temp, shift;
3798
3799         /* Get default ID LED modes */
3800         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3801         if (ret_val)
3802                 return ret_val;
3803
3804         mac->ledctl_default = er32(LEDCTL);
3805         mac->ledctl_mode1 = mac->ledctl_default;
3806         mac->ledctl_mode2 = mac->ledctl_default;
3807
3808         for (i = 0; i < 4; i++) {
3809                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3810                 shift = (i * 5);
3811                 switch (temp) {
3812                 case ID_LED_ON1_DEF2:
3813                 case ID_LED_ON1_ON2:
3814                 case ID_LED_ON1_OFF2:
3815                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3816                         mac->ledctl_mode1 |= (ledctl_on << shift);
3817                         break;
3818                 case ID_LED_OFF1_DEF2:
3819                 case ID_LED_OFF1_ON2:
3820                 case ID_LED_OFF1_OFF2:
3821                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3822                         mac->ledctl_mode1 |= (ledctl_off << shift);
3823                         break;
3824                 default:
3825                         /* Do nothing */
3826                         break;
3827                 }
3828                 switch (temp) {
3829                 case ID_LED_DEF1_ON2:
3830                 case ID_LED_ON1_ON2:
3831                 case ID_LED_OFF1_ON2:
3832                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3833                         mac->ledctl_mode2 |= (ledctl_on << shift);
3834                         break;
3835                 case ID_LED_DEF1_OFF2:
3836                 case ID_LED_ON1_OFF2:
3837                 case ID_LED_OFF1_OFF2:
3838                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3839                         mac->ledctl_mode2 |= (ledctl_off << shift);
3840                         break;
3841                 default:
3842                         /* Do nothing */
3843                         break;
3844                 }
3845         }
3846
3847         return 0;
3848 }
3849
3850 /**
3851  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3852  *  @hw: pointer to the HW structure
3853  *
3854  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3855  *  register, so the the bus width is hard coded.
3856  **/
3857 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3858 {
3859         struct e1000_bus_info *bus = &hw->bus;
3860         s32 ret_val;
3861
3862         ret_val = e1000e_get_bus_info_pcie(hw);
3863
3864         /* ICH devices are "PCI Express"-ish.  They have
3865          * a configuration space, but do not contain
3866          * PCI Express Capability registers, so bus width
3867          * must be hardcoded.
3868          */
3869         if (bus->width == e1000_bus_width_unknown)
3870                 bus->width = e1000_bus_width_pcie_x1;
3871
3872         return ret_val;
3873 }
3874
3875 /**
3876  *  e1000_reset_hw_ich8lan - Reset the hardware
3877  *  @hw: pointer to the HW structure
3878  *
3879  *  Does a full reset of the hardware which includes a reset of the PHY and
3880  *  MAC.
3881  **/
3882 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3883 {
3884         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3885         u16 kum_cfg;
3886         u32 ctrl, reg;
3887         s32 ret_val;
3888
3889         /* Prevent the PCI-E bus from sticking if there is no TLP connection
3890          * on the last TLP read/write transaction when MAC is reset.
3891          */
3892         ret_val = e1000e_disable_pcie_master(hw);
3893         if (ret_val)
3894                 e_dbg("PCI-E Master disable polling has failed.\n");
3895
3896         e_dbg("Masking off all interrupts\n");
3897         ew32(IMC, 0xffffffff);
3898
3899         /* Disable the Transmit and Receive units.  Then delay to allow
3900          * any pending transactions to complete before we hit the MAC
3901          * with the global reset.
3902          */
3903         ew32(RCTL, 0);
3904         ew32(TCTL, E1000_TCTL_PSP);
3905         e1e_flush();
3906
3907         usleep_range(10000, 20000);
3908
3909         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3910         if (hw->mac.type == e1000_ich8lan) {
3911                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3912                 ew32(PBA, E1000_PBA_8K);
3913                 /* Set Packet Buffer Size to 16k. */
3914                 ew32(PBS, E1000_PBS_16K);
3915         }
3916
3917         if (hw->mac.type == e1000_pchlan) {
3918                 /* Save the NVM K1 bit setting */
3919                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3920                 if (ret_val)
3921                         return ret_val;
3922
3923                 if (kum_cfg & E1000_NVM_K1_ENABLE)
3924                         dev_spec->nvm_k1_enabled = true;
3925                 else
3926                         dev_spec->nvm_k1_enabled = false;
3927         }
3928
3929         ctrl = er32(CTRL);
3930
3931         if (!hw->phy.ops.check_reset_block(hw)) {
3932                 /* Full-chip reset requires MAC and PHY reset at the same
3933                  * time to make sure the interface between MAC and the
3934                  * external PHY is reset.
3935                  */
3936                 ctrl |= E1000_CTRL_PHY_RST;
3937
3938                 /* Gate automatic PHY configuration by hardware on
3939                  * non-managed 82579
3940                  */
3941                 if ((hw->mac.type == e1000_pch2lan) &&
3942                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3943                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3944         }
3945         ret_val = e1000_acquire_swflag_ich8lan(hw);
3946         e_dbg("Issuing a global reset to ich8lan\n");
3947         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3948         /* cannot issue a flush here because it hangs the hardware */
3949         msleep(20);
3950
3951         /* Set Phy Config Counter to 50msec */
3952         if (hw->mac.type == e1000_pch2lan) {
3953                 reg = er32(FEXTNVM3);
3954                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3955                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3956                 ew32(FEXTNVM3, reg);
3957         }
3958
3959         if (!ret_val)
3960                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3961
3962         if (ctrl & E1000_CTRL_PHY_RST) {
3963                 ret_val = hw->phy.ops.get_cfg_done(hw);
3964                 if (ret_val)
3965                         return ret_val;
3966
3967                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3968                 if (ret_val)
3969                         return ret_val;
3970         }
3971
3972         /* For PCH, this write will make sure that any noise
3973          * will be detected as a CRC error and be dropped rather than show up
3974          * as a bad packet to the DMA engine.
3975          */
3976         if (hw->mac.type == e1000_pchlan)
3977                 ew32(CRC_OFFSET, 0x65656565);
3978
3979         ew32(IMC, 0xffffffff);
3980         er32(ICR);
3981
3982         reg = er32(KABGTXD);
3983         reg |= E1000_KABGTXD_BGSQLBIAS;
3984         ew32(KABGTXD, reg);
3985
3986         return 0;
3987 }
3988
3989 /**
3990  *  e1000_init_hw_ich8lan - Initialize the hardware
3991  *  @hw: pointer to the HW structure
3992  *
3993  *  Prepares the hardware for transmit and receive by doing the following:
3994  *   - initialize hardware bits
3995  *   - initialize LED identification
3996  *   - setup receive address registers
3997  *   - setup flow control
3998  *   - setup transmit descriptors
3999  *   - clear statistics
4000  **/
4001 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4002 {
4003         struct e1000_mac_info *mac = &hw->mac;
4004         u32 ctrl_ext, txdctl, snoop;
4005         s32 ret_val;
4006         u16 i;
4007
4008         e1000_initialize_hw_bits_ich8lan(hw);
4009
4010         /* Initialize identification LED */
4011         ret_val = mac->ops.id_led_init(hw);
4012         /* An error is not fatal and we should not stop init due to this */
4013         if (ret_val)
4014                 e_dbg("Error initializing identification LED\n");
4015
4016         /* Setup the receive address. */
4017         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4018
4019         /* Zero out the Multicast HASH table */
4020         e_dbg("Zeroing the MTA\n");
4021         for (i = 0; i < mac->mta_reg_count; i++)
4022                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4023
4024         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4025          * the ME.  Disable wakeup by clearing the host wakeup bit.
4026          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4027          */
4028         if (hw->phy.type == e1000_phy_82578) {
4029                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4030                 i &= ~BM_WUC_HOST_WU_BIT;
4031                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4032                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4033                 if (ret_val)
4034                         return ret_val;
4035         }
4036
4037         /* Setup link and flow control */
4038         ret_val = mac->ops.setup_link(hw);
4039
4040         /* Set the transmit descriptor write-back policy for both queues */
4041         txdctl = er32(TXDCTL(0));
4042         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4043                   E1000_TXDCTL_FULL_TX_DESC_WB);
4044         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4045                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4046         ew32(TXDCTL(0), txdctl);
4047         txdctl = er32(TXDCTL(1));
4048         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4049                   E1000_TXDCTL_FULL_TX_DESC_WB);
4050         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4051                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4052         ew32(TXDCTL(1), txdctl);
4053
4054         /* ICH8 has opposite polarity of no_snoop bits.
4055          * By default, we should use snoop behavior.
4056          */
4057         if (mac->type == e1000_ich8lan)
4058                 snoop = PCIE_ICH8_SNOOP_ALL;
4059         else
4060                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4061         e1000e_set_pcie_no_snoop(hw, snoop);
4062
4063         ctrl_ext = er32(CTRL_EXT);
4064         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4065         ew32(CTRL_EXT, ctrl_ext);
4066
4067         /* Clear all of the statistics registers (clear on read).  It is
4068          * important that we do this after we have tried to establish link
4069          * because the symbol error count will increment wildly if there
4070          * is no link.
4071          */
4072         e1000_clear_hw_cntrs_ich8lan(hw);
4073
4074         return ret_val;
4075 }
4076
4077 /**
4078  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4079  *  @hw: pointer to the HW structure
4080  *
4081  *  Sets/Clears required hardware bits necessary for correctly setting up the
4082  *  hardware for transmit and receive.
4083  **/
4084 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4085 {
4086         u32 reg;
4087
4088         /* Extended Device Control */
4089         reg = er32(CTRL_EXT);
4090         reg |= (1 << 22);
4091         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4092         if (hw->mac.type >= e1000_pchlan)
4093                 reg |= E1000_CTRL_EXT_PHYPDEN;
4094         ew32(CTRL_EXT, reg);
4095
4096         /* Transmit Descriptor Control 0 */
4097         reg = er32(TXDCTL(0));
4098         reg |= (1 << 22);
4099         ew32(TXDCTL(0), reg);
4100
4101         /* Transmit Descriptor Control 1 */
4102         reg = er32(TXDCTL(1));
4103         reg |= (1 << 22);
4104         ew32(TXDCTL(1), reg);
4105
4106         /* Transmit Arbitration Control 0 */
4107         reg = er32(TARC(0));
4108         if (hw->mac.type == e1000_ich8lan)
4109                 reg |= (1 << 28) | (1 << 29);
4110         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4111         ew32(TARC(0), reg);
4112
4113         /* Transmit Arbitration Control 1 */
4114         reg = er32(TARC(1));
4115         if (er32(TCTL) & E1000_TCTL_MULR)
4116                 reg &= ~(1 << 28);
4117         else
4118                 reg |= (1 << 28);
4119         reg |= (1 << 24) | (1 << 26) | (1 << 30);
4120         ew32(TARC(1), reg);
4121
4122         /* Device Status */
4123         if (hw->mac.type == e1000_ich8lan) {
4124                 reg = er32(STATUS);
4125                 reg &= ~(1 << 31);
4126                 ew32(STATUS, reg);
4127         }
4128
4129         /* work-around descriptor data corruption issue during nfs v2 udp
4130          * traffic, just disable the nfs filtering capability
4131          */
4132         reg = er32(RFCTL);
4133         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4134
4135         /* Disable IPv6 extension header parsing because some malformed
4136          * IPv6 headers can hang the Rx.
4137          */
4138         if (hw->mac.type == e1000_ich8lan)
4139                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4140         ew32(RFCTL, reg);
4141
4142         /* Enable ECC on Lynxpoint */
4143         if (hw->mac.type == e1000_pch_lpt) {
4144                 reg = er32(PBECCSTS);
4145                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4146                 ew32(PBECCSTS, reg);
4147
4148                 reg = er32(CTRL);
4149                 reg |= E1000_CTRL_MEHE;
4150                 ew32(CTRL, reg);
4151         }
4152 }
4153
4154 /**
4155  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4156  *  @hw: pointer to the HW structure
4157  *
4158  *  Determines which flow control settings to use, then configures flow
4159  *  control.  Calls the appropriate media-specific link configuration
4160  *  function.  Assuming the adapter has a valid link partner, a valid link
4161  *  should be established.  Assumes the hardware has previously been reset
4162  *  and the transmitter and receiver are not enabled.
4163  **/
4164 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4165 {
4166         s32 ret_val;
4167
4168         if (hw->phy.ops.check_reset_block(hw))
4169                 return 0;
4170
4171         /* ICH parts do not have a word in the NVM to determine
4172          * the default flow control setting, so we explicitly
4173          * set it to full.
4174          */
4175         if (hw->fc.requested_mode == e1000_fc_default) {
4176                 /* Workaround h/w hang when Tx flow control enabled */
4177                 if (hw->mac.type == e1000_pchlan)
4178                         hw->fc.requested_mode = e1000_fc_rx_pause;
4179                 else
4180                         hw->fc.requested_mode = e1000_fc_full;
4181         }
4182
4183         /* Save off the requested flow control mode for use later.  Depending
4184          * on the link partner's capabilities, we may or may not use this mode.
4185          */
4186         hw->fc.current_mode = hw->fc.requested_mode;
4187
4188         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4189
4190         /* Continue to configure the copper link. */
4191         ret_val = hw->mac.ops.setup_physical_interface(hw);
4192         if (ret_val)
4193                 return ret_val;
4194
4195         ew32(FCTTV, hw->fc.pause_time);
4196         if ((hw->phy.type == e1000_phy_82578) ||
4197             (hw->phy.type == e1000_phy_82579) ||
4198             (hw->phy.type == e1000_phy_i217) ||
4199             (hw->phy.type == e1000_phy_82577)) {
4200                 ew32(FCRTV_PCH, hw->fc.refresh_time);
4201
4202                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4203                                    hw->fc.pause_time);
4204                 if (ret_val)
4205                         return ret_val;
4206         }
4207
4208         return e1000e_set_fc_watermarks(hw);
4209 }
4210
4211 /**
4212  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4213  *  @hw: pointer to the HW structure
4214  *
4215  *  Configures the kumeran interface to the PHY to wait the appropriate time
4216  *  when polling the PHY, then call the generic setup_copper_link to finish
4217  *  configuring the copper link.
4218  **/
4219 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4220 {
4221         u32 ctrl;
4222         s32 ret_val;
4223         u16 reg_data;
4224
4225         ctrl = er32(CTRL);
4226         ctrl |= E1000_CTRL_SLU;
4227         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4228         ew32(CTRL, ctrl);
4229
4230         /* Set the mac to wait the maximum time between each iteration
4231          * and increase the max iterations when polling the phy;
4232          * this fixes erroneous timeouts at 10Mbps.
4233          */
4234         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
4235         if (ret_val)
4236                 return ret_val;
4237         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4238                                        &reg_data);
4239         if (ret_val)
4240                 return ret_val;
4241         reg_data |= 0x3F;
4242         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4243                                         reg_data);
4244         if (ret_val)
4245                 return ret_val;
4246
4247         switch (hw->phy.type) {
4248         case e1000_phy_igp_3:
4249                 ret_val = e1000e_copper_link_setup_igp(hw);
4250                 if (ret_val)
4251                         return ret_val;
4252                 break;
4253         case e1000_phy_bm:
4254         case e1000_phy_82578:
4255                 ret_val = e1000e_copper_link_setup_m88(hw);
4256                 if (ret_val)
4257                         return ret_val;
4258                 break;
4259         case e1000_phy_82577:
4260         case e1000_phy_82579:
4261                 ret_val = e1000_copper_link_setup_82577(hw);
4262                 if (ret_val)
4263                         return ret_val;
4264                 break;
4265         case e1000_phy_ife:
4266                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
4267                 if (ret_val)
4268                         return ret_val;
4269
4270                 reg_data &= ~IFE_PMC_AUTO_MDIX;
4271
4272                 switch (hw->phy.mdix) {
4273                 case 1:
4274                         reg_data &= ~IFE_PMC_FORCE_MDIX;
4275                         break;
4276                 case 2:
4277                         reg_data |= IFE_PMC_FORCE_MDIX;
4278                         break;
4279                 case 0:
4280                 default:
4281                         reg_data |= IFE_PMC_AUTO_MDIX;
4282                         break;
4283                 }
4284                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
4285                 if (ret_val)
4286                         return ret_val;
4287                 break;
4288         default:
4289                 break;
4290         }
4291
4292         return e1000e_setup_copper_link(hw);
4293 }
4294
4295 /**
4296  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4297  *  @hw: pointer to the HW structure
4298  *
4299  *  Calls the PHY specific link setup function and then calls the
4300  *  generic setup_copper_link to finish configuring the link for
4301  *  Lynxpoint PCH devices
4302  **/
4303 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4304 {
4305         u32 ctrl;
4306         s32 ret_val;
4307
4308         ctrl = er32(CTRL);
4309         ctrl |= E1000_CTRL_SLU;
4310         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4311         ew32(CTRL, ctrl);
4312
4313         ret_val = e1000_copper_link_setup_82577(hw);
4314         if (ret_val)
4315                 return ret_val;
4316
4317         return e1000e_setup_copper_link(hw);
4318 }
4319
4320 /**
4321  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4322  *  @hw: pointer to the HW structure
4323  *  @speed: pointer to store current link speed
4324  *  @duplex: pointer to store the current link duplex
4325  *
4326  *  Calls the generic get_speed_and_duplex to retrieve the current link
4327  *  information and then calls the Kumeran lock loss workaround for links at
4328  *  gigabit speeds.
4329  **/
4330 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4331                                           u16 *duplex)
4332 {
4333         s32 ret_val;
4334
4335         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
4336         if (ret_val)
4337                 return ret_val;
4338
4339         if ((hw->mac.type == e1000_ich8lan) &&
4340             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
4341                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4342         }
4343
4344         return ret_val;
4345 }
4346
4347 /**
4348  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4349  *  @hw: pointer to the HW structure
4350  *
4351  *  Work-around for 82566 Kumeran PCS lock loss:
4352  *  On link status change (i.e. PCI reset, speed change) and link is up and
4353  *  speed is gigabit-
4354  *    0) if workaround is optionally disabled do nothing
4355  *    1) wait 1ms for Kumeran link to come up
4356  *    2) check Kumeran Diagnostic register PCS lock loss bit
4357  *    3) if not set the link is locked (all is good), otherwise...
4358  *    4) reset the PHY
4359  *    5) repeat up to 10 times
4360  *  Note: this is only called for IGP3 copper when speed is 1gb.
4361  **/
4362 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4363 {
4364         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4365         u32 phy_ctrl;
4366         s32 ret_val;
4367         u16 i, data;
4368         bool link;
4369
4370         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4371                 return 0;
4372
4373         /* Make sure link is up before proceeding.  If not just return.
4374          * Attempting this while link is negotiating fouled up link
4375          * stability
4376          */
4377         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
4378         if (!link)
4379                 return 0;
4380
4381         for (i = 0; i < 10; i++) {
4382                 /* read once to clear */
4383                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4384                 if (ret_val)
4385                         return ret_val;
4386                 /* and again to get new status */
4387                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4388                 if (ret_val)
4389                         return ret_val;
4390
4391                 /* check for PCS lock */
4392                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4393                         return 0;
4394
4395                 /* Issue PHY reset */
4396                 e1000_phy_hw_reset(hw);
4397                 mdelay(5);
4398         }
4399         /* Disable GigE link negotiation */
4400         phy_ctrl = er32(PHY_CTRL);
4401         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4402                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4403         ew32(PHY_CTRL, phy_ctrl);
4404
4405         /* Call gig speed drop workaround on Gig disable before accessing
4406          * any PHY registers
4407          */
4408         e1000e_gig_downshift_workaround_ich8lan(hw);
4409
4410         /* unable to acquire PCS lock */
4411         return -E1000_ERR_PHY;
4412 }
4413
4414 /**
4415  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4416  *  @hw: pointer to the HW structure
4417  *  @state: boolean value used to set the current Kumeran workaround state
4418  *
4419  *  If ICH8, set the current Kumeran workaround state (enabled - true
4420  *  /disabled - false).
4421  **/
4422 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4423                                                   bool state)
4424 {
4425         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4426
4427         if (hw->mac.type != e1000_ich8lan) {
4428                 e_dbg("Workaround applies to ICH8 only.\n");
4429                 return;
4430         }
4431
4432         dev_spec->kmrn_lock_loss_workaround_enabled = state;
4433 }
4434
4435 /**
4436  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4437  *  @hw: pointer to the HW structure
4438  *
4439  *  Workaround for 82566 power-down on D3 entry:
4440  *    1) disable gigabit link
4441  *    2) write VR power-down enable
4442  *    3) read it back
4443  *  Continue if successful, else issue LCD reset and repeat
4444  **/
4445 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4446 {
4447         u32 reg;
4448         u16 data;
4449         u8 retry = 0;
4450
4451         if (hw->phy.type != e1000_phy_igp_3)
4452                 return;
4453
4454         /* Try the workaround twice (if needed) */
4455         do {
4456                 /* Disable link */
4457                 reg = er32(PHY_CTRL);
4458                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4459                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4460                 ew32(PHY_CTRL, reg);
4461
4462                 /* Call gig speed drop workaround on Gig disable before
4463                  * accessing any PHY registers
4464                  */
4465                 if (hw->mac.type == e1000_ich8lan)
4466                         e1000e_gig_downshift_workaround_ich8lan(hw);
4467
4468                 /* Write VR power-down enable */
4469                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4470                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4471                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4472
4473                 /* Read it back and test */
4474                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4475                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4476                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4477                         break;
4478
4479                 /* Issue PHY reset and repeat at most one more time */
4480                 reg = er32(CTRL);
4481                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4482                 retry++;
4483         } while (retry);
4484 }
4485
4486 /**
4487  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4488  *  @hw: pointer to the HW structure
4489  *
4490  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4491  *  LPLU, Gig disable, MDIC PHY reset):
4492  *    1) Set Kumeran Near-end loopback
4493  *    2) Clear Kumeran Near-end loopback
4494  *  Should only be called for ICH8[m] devices with any 1G Phy.
4495  **/
4496 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4497 {
4498         s32 ret_val;
4499         u16 reg_data;
4500
4501         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
4502                 return;
4503
4504         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4505                                        &reg_data);
4506         if (ret_val)
4507                 return;
4508         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4509         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4510                                         reg_data);
4511         if (ret_val)
4512                 return;
4513         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4514         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
4515 }
4516
4517 /**
4518  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4519  *  @hw: pointer to the HW structure
4520  *
4521  *  During S0 to Sx transition, it is possible the link remains at gig
4522  *  instead of negotiating to a lower speed.  Before going to Sx, set
4523  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4524  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4525  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4526  *  needs to be written.
4527  *  Parts that support (and are linked to a partner which support) EEE in
4528  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4529  *  than 10Mbps w/o EEE.
4530  **/
4531 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4532 {
4533         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4534         u32 phy_ctrl;
4535         s32 ret_val;
4536
4537         phy_ctrl = er32(PHY_CTRL);
4538         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4539
4540         if (hw->phy.type == e1000_phy_i217) {
4541                 u16 phy_reg, device_id = hw->adapter->pdev->device;
4542
4543                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4544                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4545                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4546                     (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4547                         u32 fextnvm6 = er32(FEXTNVM6);
4548
4549                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4550                 }
4551
4552                 ret_val = hw->phy.ops.acquire(hw);
4553                 if (ret_val)
4554                         goto out;
4555
4556                 if (!dev_spec->eee_disable) {
4557                         u16 eee_advert;
4558
4559                         ret_val =
4560                             e1000_read_emi_reg_locked(hw,
4561                                                       I217_EEE_ADVERTISEMENT,
4562                                                       &eee_advert);
4563                         if (ret_val)
4564                                 goto release;
4565
4566                         /* Disable LPLU if both link partners support 100BaseT
4567                          * EEE and 100Full is advertised on both ends of the
4568                          * link.
4569                          */
4570                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4571                             (dev_spec->eee_lp_ability &
4572                              I82579_EEE_100_SUPPORTED) &&
4573                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4574                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4575                                               E1000_PHY_CTRL_NOND0A_LPLU);
4576                 }
4577
4578                 /* For i217 Intel Rapid Start Technology support,
4579                  * when the system is going into Sx and no manageability engine
4580                  * is present, the driver must configure proxy to reset only on
4581                  * power good.  LPI (Low Power Idle) state must also reset only
4582                  * on power good, as well as the MTA (Multicast table array).
4583                  * The SMBus release must also be disabled on LCD reset.
4584                  */
4585                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4586                         /* Enable proxy to reset only on power good. */
4587                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4588                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4589                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4590
4591                         /* Set bit enable LPI (EEE) to reset only on
4592                          * power good.
4593                          */
4594                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4595                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4596                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4597
4598                         /* Disable the SMB release on LCD reset. */
4599                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4600                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4601                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4602                 }
4603
4604                 /* Enable MTA to reset for Intel Rapid Start Technology
4605                  * Support
4606                  */
4607                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4608                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4609                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4610
4611 release:
4612                 hw->phy.ops.release(hw);
4613         }
4614 out:
4615         ew32(PHY_CTRL, phy_ctrl);
4616
4617         if (hw->mac.type == e1000_ich8lan)
4618                 e1000e_gig_downshift_workaround_ich8lan(hw);
4619
4620         if (hw->mac.type >= e1000_pchlan) {
4621                 e1000_oem_bits_config_ich8lan(hw, false);
4622
4623                 /* Reset PHY to activate OEM bits on 82577/8 */
4624                 if (hw->mac.type == e1000_pchlan)
4625                         e1000e_phy_hw_reset_generic(hw);
4626
4627                 ret_val = hw->phy.ops.acquire(hw);
4628                 if (ret_val)
4629                         return;
4630                 e1000_write_smbus_addr(hw);
4631                 hw->phy.ops.release(hw);
4632         }
4633 }
4634
4635 /**
4636  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4637  *  @hw: pointer to the HW structure
4638  *
4639  *  During Sx to S0 transitions on non-managed devices or managed devices
4640  *  on which PHY resets are not blocked, if the PHY registers cannot be
4641  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4642  *  the PHY.
4643  *  On i217, setup Intel Rapid Start Technology.
4644  **/
4645 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4646 {
4647         s32 ret_val;
4648
4649         if (hw->mac.type < e1000_pch2lan)
4650                 return;
4651
4652         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4653         if (ret_val) {
4654                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4655                 return;
4656         }
4657
4658         /* For i217 Intel Rapid Start Technology support when the system
4659          * is transitioning from Sx and no manageability engine is present
4660          * configure SMBus to restore on reset, disable proxy, and enable
4661          * the reset on MTA (Multicast table array).
4662          */
4663         if (hw->phy.type == e1000_phy_i217) {
4664                 u16 phy_reg;
4665
4666                 ret_val = hw->phy.ops.acquire(hw);
4667                 if (ret_val) {
4668                         e_dbg("Failed to setup iRST\n");
4669                         return;
4670                 }
4671
4672                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4673                         /* Restore clear on SMB if no manageability engine
4674                          * is present
4675                          */
4676                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4677                         if (ret_val)
4678                                 goto release;
4679                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4680                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4681
4682                         /* Disable Proxy */
4683                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4684                 }
4685                 /* Enable reset on MTA */
4686                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4687                 if (ret_val)
4688                         goto release;
4689                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4690                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4691 release:
4692                 if (ret_val)
4693                         e_dbg("Error %d in resume workarounds\n", ret_val);
4694                 hw->phy.ops.release(hw);
4695         }
4696 }
4697
4698 /**
4699  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4700  *  @hw: pointer to the HW structure
4701  *
4702  *  Return the LED back to the default configuration.
4703  **/
4704 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4705 {
4706         if (hw->phy.type == e1000_phy_ife)
4707                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4708
4709         ew32(LEDCTL, hw->mac.ledctl_default);
4710         return 0;
4711 }
4712
4713 /**
4714  *  e1000_led_on_ich8lan - Turn LEDs on
4715  *  @hw: pointer to the HW structure
4716  *
4717  *  Turn on the LEDs.
4718  **/
4719 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4720 {
4721         if (hw->phy.type == e1000_phy_ife)
4722                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4723                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4724
4725         ew32(LEDCTL, hw->mac.ledctl_mode2);
4726         return 0;
4727 }
4728
4729 /**
4730  *  e1000_led_off_ich8lan - Turn LEDs off
4731  *  @hw: pointer to the HW structure
4732  *
4733  *  Turn off the LEDs.
4734  **/
4735 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4736 {
4737         if (hw->phy.type == e1000_phy_ife)
4738                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4739                                 (IFE_PSCL_PROBE_MODE |
4740                                  IFE_PSCL_PROBE_LEDS_OFF));
4741
4742         ew32(LEDCTL, hw->mac.ledctl_mode1);
4743         return 0;
4744 }
4745
4746 /**
4747  *  e1000_setup_led_pchlan - Configures SW controllable LED
4748  *  @hw: pointer to the HW structure
4749  *
4750  *  This prepares the SW controllable LED for use.
4751  **/
4752 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4753 {
4754         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4755 }
4756
4757 /**
4758  *  e1000_cleanup_led_pchlan - Restore the default LED operation
4759  *  @hw: pointer to the HW structure
4760  *
4761  *  Return the LED back to the default configuration.
4762  **/
4763 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4764 {
4765         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4766 }
4767
4768 /**
4769  *  e1000_led_on_pchlan - Turn LEDs on
4770  *  @hw: pointer to the HW structure
4771  *
4772  *  Turn on the LEDs.
4773  **/
4774 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4775 {
4776         u16 data = (u16)hw->mac.ledctl_mode2;
4777         u32 i, led;
4778
4779         /* If no link, then turn LED on by setting the invert bit
4780          * for each LED that's mode is "link_up" in ledctl_mode2.
4781          */
4782         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4783                 for (i = 0; i < 3; i++) {
4784                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4785                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4786                             E1000_LEDCTL_MODE_LINK_UP)
4787                                 continue;
4788                         if (led & E1000_PHY_LED0_IVRT)
4789                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4790                         else
4791                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4792                 }
4793         }
4794
4795         return e1e_wphy(hw, HV_LED_CONFIG, data);
4796 }
4797
4798 /**
4799  *  e1000_led_off_pchlan - Turn LEDs off
4800  *  @hw: pointer to the HW structure
4801  *
4802  *  Turn off the LEDs.
4803  **/
4804 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4805 {
4806         u16 data = (u16)hw->mac.ledctl_mode1;
4807         u32 i, led;
4808
4809         /* If no link, then turn LED off by clearing the invert bit
4810          * for each LED that's mode is "link_up" in ledctl_mode1.
4811          */
4812         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4813                 for (i = 0; i < 3; i++) {
4814                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4815                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4816                             E1000_LEDCTL_MODE_LINK_UP)
4817                                 continue;
4818                         if (led & E1000_PHY_LED0_IVRT)
4819                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4820                         else
4821                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4822                 }
4823         }
4824
4825         return e1e_wphy(hw, HV_LED_CONFIG, data);
4826 }
4827
4828 /**
4829  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4830  *  @hw: pointer to the HW structure
4831  *
4832  *  Read appropriate register for the config done bit for completion status
4833  *  and configure the PHY through s/w for EEPROM-less parts.
4834  *
4835  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
4836  *  config done bit, so only an error is logged and continues.  If we were
4837  *  to return with error, EEPROM-less silicon would not be able to be reset
4838  *  or change link.
4839  **/
4840 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4841 {
4842         s32 ret_val = 0;
4843         u32 bank = 0;
4844         u32 status;
4845
4846         e1000e_get_cfg_done_generic(hw);
4847
4848         /* Wait for indication from h/w that it has completed basic config */
4849         if (hw->mac.type >= e1000_ich10lan) {
4850                 e1000_lan_init_done_ich8lan(hw);
4851         } else {
4852                 ret_val = e1000e_get_auto_rd_done(hw);
4853                 if (ret_val) {
4854                         /* When auto config read does not complete, do not
4855                          * return with an error. This can happen in situations
4856                          * where there is no eeprom and prevents getting link.
4857                          */
4858                         e_dbg("Auto Read Done did not complete\n");
4859                         ret_val = 0;
4860                 }
4861         }
4862
4863         /* Clear PHY Reset Asserted bit */
4864         status = er32(STATUS);
4865         if (status & E1000_STATUS_PHYRA)
4866                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4867         else
4868                 e_dbg("PHY Reset Asserted not set - needs delay\n");
4869
4870         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4871         if (hw->mac.type <= e1000_ich9lan) {
4872                 if (!(er32(EECD) & E1000_EECD_PRES) &&
4873                     (hw->phy.type == e1000_phy_igp_3)) {
4874                         e1000e_phy_init_script_igp3(hw);
4875                 }
4876         } else {
4877                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4878                         /* Maybe we should do a basic PHY config */
4879                         e_dbg("EEPROM not present\n");
4880                         ret_val = -E1000_ERR_CONFIG;
4881                 }
4882         }
4883
4884         return ret_val;
4885 }
4886
4887 /**
4888  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4889  * @hw: pointer to the HW structure
4890  *
4891  * In the case of a PHY power down to save power, or to turn off link during a
4892  * driver unload, or wake on lan is not enabled, remove the link.
4893  **/
4894 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4895 {
4896         /* If the management interface is not enabled, then power down */
4897         if (!(hw->mac.ops.check_mng_mode(hw) ||
4898               hw->phy.ops.check_reset_block(hw)))
4899                 e1000_power_down_phy_copper(hw);
4900 }
4901
4902 /**
4903  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4904  *  @hw: pointer to the HW structure
4905  *
4906  *  Clears hardware counters specific to the silicon family and calls
4907  *  clear_hw_cntrs_generic to clear all general purpose counters.
4908  **/
4909 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4910 {
4911         u16 phy_data;
4912         s32 ret_val;
4913
4914         e1000e_clear_hw_cntrs_base(hw);
4915
4916         er32(ALGNERRC);
4917         er32(RXERRC);
4918         er32(TNCRS);
4919         er32(CEXTERR);
4920         er32(TSCTC);
4921         er32(TSCTFC);
4922
4923         er32(MGTPRC);
4924         er32(MGTPDC);
4925         er32(MGTPTC);
4926
4927         er32(IAC);
4928         er32(ICRXOC);
4929
4930         /* Clear PHY statistics registers */
4931         if ((hw->phy.type == e1000_phy_82578) ||
4932             (hw->phy.type == e1000_phy_82579) ||
4933             (hw->phy.type == e1000_phy_i217) ||
4934             (hw->phy.type == e1000_phy_82577)) {
4935                 ret_val = hw->phy.ops.acquire(hw);
4936                 if (ret_val)
4937                         return;
4938                 ret_val = hw->phy.ops.set_page(hw,
4939                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4940                 if (ret_val)
4941                         goto release;
4942                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4943                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4944                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4945                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4946                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4947                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4948                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4949                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4950                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4951                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4952                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4953                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4954                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4955                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4956 release:
4957                 hw->phy.ops.release(hw);
4958         }
4959 }
4960
4961 static const struct e1000_mac_operations ich8_mac_ops = {
4962         /* check_mng_mode dependent on mac type */
4963         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4964         /* cleanup_led dependent on mac type */
4965         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4966         .get_bus_info           = e1000_get_bus_info_ich8lan,
4967         .set_lan_id             = e1000_set_lan_id_single_port,
4968         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4969         /* led_on dependent on mac type */
4970         /* led_off dependent on mac type */
4971         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4972         .reset_hw               = e1000_reset_hw_ich8lan,
4973         .init_hw                = e1000_init_hw_ich8lan,
4974         .setup_link             = e1000_setup_link_ich8lan,
4975         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
4976         /* id_led_init dependent on mac type */
4977         .config_collision_dist  = e1000e_config_collision_dist_generic,
4978         .rar_set                = e1000e_rar_set_generic,
4979 };
4980
4981 static const struct e1000_phy_operations ich8_phy_ops = {
4982         .acquire                = e1000_acquire_swflag_ich8lan,
4983         .check_reset_block      = e1000_check_reset_block_ich8lan,
4984         .commit                 = NULL,
4985         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4986         .get_cable_length       = e1000e_get_cable_length_igp_2,
4987         .read_reg               = e1000e_read_phy_reg_igp,
4988         .release                = e1000_release_swflag_ich8lan,
4989         .reset                  = e1000_phy_hw_reset_ich8lan,
4990         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4991         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4992         .write_reg              = e1000e_write_phy_reg_igp,
4993 };
4994
4995 static const struct e1000_nvm_operations ich8_nvm_ops = {
4996         .acquire                = e1000_acquire_nvm_ich8lan,
4997         .read                   = e1000_read_nvm_ich8lan,
4998         .release                = e1000_release_nvm_ich8lan,
4999         .reload                 = e1000e_reload_nvm_generic,
5000         .update                 = e1000_update_nvm_checksum_ich8lan,
5001         .valid_led_default      = e1000_valid_led_default_ich8lan,
5002         .validate               = e1000_validate_nvm_checksum_ich8lan,
5003         .write                  = e1000_write_nvm_ich8lan,
5004 };
5005
5006 const struct e1000_info e1000_ich8_info = {
5007         .mac                    = e1000_ich8lan,
5008         .flags                  = FLAG_HAS_WOL
5009                                   | FLAG_IS_ICH
5010                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5011                                   | FLAG_HAS_AMT
5012                                   | FLAG_HAS_FLASH
5013                                   | FLAG_APME_IN_WUC,
5014         .pba                    = 8,
5015         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
5016         .get_variants           = e1000_get_variants_ich8lan,
5017         .mac_ops                = &ich8_mac_ops,
5018         .phy_ops                = &ich8_phy_ops,
5019         .nvm_ops                = &ich8_nvm_ops,
5020 };
5021
5022 const struct e1000_info e1000_ich9_info = {
5023         .mac                    = e1000_ich9lan,
5024         .flags                  = FLAG_HAS_JUMBO_FRAMES
5025                                   | FLAG_IS_ICH
5026                                   | FLAG_HAS_WOL
5027                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5028                                   | FLAG_HAS_AMT
5029                                   | FLAG_HAS_FLASH
5030                                   | FLAG_APME_IN_WUC,
5031         .pba                    = 18,
5032         .max_hw_frame_size      = DEFAULT_JUMBO,
5033         .get_variants           = e1000_get_variants_ich8lan,
5034         .mac_ops                = &ich8_mac_ops,
5035         .phy_ops                = &ich8_phy_ops,
5036         .nvm_ops                = &ich8_nvm_ops,
5037 };
5038
5039 const struct e1000_info e1000_ich10_info = {
5040         .mac                    = e1000_ich10lan,
5041         .flags                  = FLAG_HAS_JUMBO_FRAMES
5042                                   | FLAG_IS_ICH
5043                                   | FLAG_HAS_WOL
5044                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5045                                   | FLAG_HAS_AMT
5046                                   | FLAG_HAS_FLASH
5047                                   | FLAG_APME_IN_WUC,
5048         .pba                    = 18,
5049         .max_hw_frame_size      = DEFAULT_JUMBO,
5050         .get_variants           = e1000_get_variants_ich8lan,
5051         .mac_ops                = &ich8_mac_ops,
5052         .phy_ops                = &ich8_phy_ops,
5053         .nvm_ops                = &ich8_nvm_ops,
5054 };
5055
5056 const struct e1000_info e1000_pch_info = {
5057         .mac                    = e1000_pchlan,
5058         .flags                  = FLAG_IS_ICH
5059                                   | FLAG_HAS_WOL
5060                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5061                                   | FLAG_HAS_AMT
5062                                   | FLAG_HAS_FLASH
5063                                   | FLAG_HAS_JUMBO_FRAMES
5064                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5065                                   | FLAG_APME_IN_WUC,
5066         .flags2                 = FLAG2_HAS_PHY_STATS,
5067         .pba                    = 26,
5068         .max_hw_frame_size      = 4096,
5069         .get_variants           = e1000_get_variants_ich8lan,
5070         .mac_ops                = &ich8_mac_ops,
5071         .phy_ops                = &ich8_phy_ops,
5072         .nvm_ops                = &ich8_nvm_ops,
5073 };
5074
5075 const struct e1000_info e1000_pch2_info = {
5076         .mac                    = e1000_pch2lan,
5077         .flags                  = FLAG_IS_ICH
5078                                   | FLAG_HAS_WOL
5079                                   | FLAG_HAS_HW_TIMESTAMP
5080                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5081                                   | FLAG_HAS_AMT
5082                                   | FLAG_HAS_FLASH
5083                                   | FLAG_HAS_JUMBO_FRAMES
5084                                   | FLAG_APME_IN_WUC,
5085         .flags2                 = FLAG2_HAS_PHY_STATS
5086                                   | FLAG2_HAS_EEE,
5087         .pba                    = 26,
5088         .max_hw_frame_size      = 9018,
5089         .get_variants           = e1000_get_variants_ich8lan,
5090         .mac_ops                = &ich8_mac_ops,
5091         .phy_ops                = &ich8_phy_ops,
5092         .nvm_ops                = &ich8_nvm_ops,
5093 };
5094
5095 const struct e1000_info e1000_pch_lpt_info = {
5096         .mac                    = e1000_pch_lpt,
5097         .flags                  = FLAG_IS_ICH
5098                                   | FLAG_HAS_WOL
5099                                   | FLAG_HAS_HW_TIMESTAMP
5100                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5101                                   | FLAG_HAS_AMT
5102                                   | FLAG_HAS_FLASH
5103                                   | FLAG_HAS_JUMBO_FRAMES
5104                                   | FLAG_APME_IN_WUC,
5105         .flags2                 = FLAG2_HAS_PHY_STATS
5106                                   | FLAG2_HAS_EEE,
5107         .pba                    = 26,
5108         .max_hw_frame_size      = 9018,
5109         .get_variants           = e1000_get_variants_ich8lan,
5110         .mac_ops                = &ich8_mac_ops,
5111         .phy_ops                = &ich8_phy_ops,
5112         .nvm_ops                = &ich8_nvm_ops,
5113 };