1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/errno.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/aer.h>
37 #include <linux/netdevice.h>
38 #include <linux/ioport.h>
39 #include <linux/iommu.h>
40 #include <linux/slab.h>
41 #include <linux/list.h>
42 #include <linux/hashtable.h>
43 #include <linux/string.h>
46 #include <linux/sctp.h>
47 #include <linux/pkt_sched.h>
48 #include <linux/ipv6.h>
49 #include <net/checksum.h>
50 #include <net/ip6_checksum.h>
51 #include <linux/ethtool.h>
52 #include <linux/if_vlan.h>
53 #include <linux/if_bridge.h>
54 #include <linux/clocksource.h>
55 #include <linux/net_tstamp.h>
56 #include <linux/ptp_clock_kernel.h>
57 #include "i40e_type.h"
58 #include "i40e_prototype.h"
59 #include "i40e_client.h"
60 #include "i40e_virtchnl.h"
61 #include "i40e_virtchnl_pf.h"
62 #include "i40e_txrx.h"
65 /* Useful i40e defaults */
66 #define I40E_MAX_VEB 16
68 #define I40E_MAX_NUM_DESCRIPTORS 4096
69 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
70 #define I40E_DEFAULT_NUM_DESCRIPTORS 512
71 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32
72 #define I40E_MIN_NUM_DESCRIPTORS 64
73 #define I40E_MIN_MSIX 2
74 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
75 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
77 #define i40e_default_queues_per_vmdq(pf) \
78 (((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1)
79 #define I40E_DEFAULT_QUEUES_PER_VF 4
80 #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
81 #define i40e_pf_get_max_q_per_tc(pf) \
82 (((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64)
83 #define I40E_FDIR_RING 0
84 #define I40E_FDIR_RING_COUNT 32
85 #define I40E_MAX_AQ_BUF_SIZE 4096
86 #define I40E_AQ_LEN 256
87 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
88 #define I40E_MAX_USER_PRIORITY 8
89 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
90 #define I40E_DEFAULT_MSG_ENABLE 4
91 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10
92 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
94 #define I40E_NVM_VERSION_LO_SHIFT 0
95 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
96 #define I40E_NVM_VERSION_HI_SHIFT 12
97 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
98 #define I40E_OEM_VER_BUILD_MASK 0xffff
99 #define I40E_OEM_VER_PATCH_MASK 0xff
100 #define I40E_OEM_VER_BUILD_SHIFT 8
101 #define I40E_OEM_VER_SHIFT 24
102 #define I40E_PHY_DEBUG_ALL \
103 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
104 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
106 /* The values in here are decimal coded as hex as is the case in the NVM map*/
107 #define I40E_CURRENT_NVM_VERSION_HI 0x2
108 #define I40E_CURRENT_NVM_VERSION_LO 0x40
110 #define I40E_RX_DESC(R, i) \
111 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))
112 #define I40E_TX_DESC(R, i) \
113 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
114 #define I40E_TX_CTXTDESC(R, i) \
115 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
116 #define I40E_TX_FDIRDESC(R, i) \
117 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
119 /* default to trying for four seconds */
120 #define I40E_TRY_LINK_TIMEOUT (4 * HZ)
122 /* driver state flags */
128 __I40E_NEEDS_RESTART,
129 __I40E_SERVICE_SCHED,
130 __I40E_ADMINQ_EVENT_PENDING,
131 __I40E_MDD_EVENT_PENDING,
132 __I40E_VFLR_EVENT_PENDING,
133 __I40E_RESET_RECOVERY_PENDING,
134 __I40E_RESET_INTR_RECEIVED,
135 __I40E_REINIT_REQUESTED,
136 __I40E_PF_RESET_REQUESTED,
137 __I40E_CORE_RESET_REQUESTED,
138 __I40E_GLOBAL_RESET_REQUESTED,
139 __I40E_EMP_RESET_REQUESTED,
140 __I40E_EMP_RESET_INTR_RECEIVED,
141 __I40E_FILTER_OVERFLOW_PROMISC,
143 __I40E_PTP_TX_IN_PROGRESS,
145 __I40E_DOWN_REQUESTED,
146 __I40E_FD_FLUSH_REQUESTED,
148 __I40E_PORT_TX_SUSPENDED,
152 enum i40e_interrupt_policy {
153 I40E_INTERRUPT_BEST_CASE,
154 I40E_INTERRUPT_MEDIUM,
155 I40E_INTERRUPT_LOWEST
158 struct i40e_lump_tracking {
162 #define I40E_PILE_VALID_BIT 0x8000
163 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
166 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20
167 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
168 #define I40E_FDIR_BUFFER_FULL_MARGIN 10
169 #define I40E_FDIR_BUFFER_HEAD_ROOM 32
170 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
172 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
173 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
174 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
176 enum i40e_fd_stat_idx {
179 I40E_FD_STAT_ATR_TUNNEL,
180 I40E_FD_STAT_PF_COUNT
182 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
183 #define I40E_FD_ATR_STAT_IDX(pf_id) \
184 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
185 #define I40E_FD_SB_STAT_IDX(pf_id) \
186 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
187 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
188 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
190 /* The following structure contains the data parsed from the user-defined
191 * field of the ethtool_rx_flow_spec structure.
193 struct i40e_rx_flow_userdef {
199 struct i40e_fdir_filter {
200 struct hlist_node fdir_node;
201 /* filter ipnut set */
204 /* TX packet view of src and dst */
211 /* Flexible data to match within the packet payload */
227 #define I40E_ETH_P_LLDP 0x88cc
229 #define I40E_DCB_PRIO_TYPE_STRICT 0
230 #define I40E_DCB_PRIO_TYPE_ETS 1
231 #define I40E_DCB_STRICT_PRIO_CREDITS 127
232 /* DCB per TC information data structure */
233 struct i40e_tc_info {
234 u16 qoffset; /* Queue offset from base queue */
235 u16 qcount; /* Total Queues */
236 u8 netdev_tc; /* Netdev TC index if netdev associated */
239 /* TC configuration data structure */
240 struct i40e_tc_configuration {
241 u8 numtc; /* Total number of enabled TCs */
242 u8 enabled_tc; /* TC map */
243 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
246 struct i40e_udp_port_config {
247 /* AdminQ command interface expects port number in Host byte order */
252 /* macros related to FLX_PIT */
253 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
254 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
255 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
256 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
257 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
258 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
259 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
260 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
261 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
262 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
263 I40E_FLEX_SET_FSIZE(fsize) | \
264 I40E_FLEX_SET_SRC_WORD(src))
266 #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \
267 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \
268 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
269 #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \
270 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \
271 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
272 #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \
273 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \
274 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
276 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
278 /* macros related to GLQF_ORT */
279 #define I40E_ORT_SET_IDX(idx) (((idx) << \
280 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
281 I40E_GLQF_ORT_PIT_INDX_MASK)
283 #define I40E_ORT_SET_COUNT(count) (((count) << \
284 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
285 I40E_GLQF_ORT_FIELD_CNT_MASK)
287 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
288 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
289 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
291 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
292 I40E_ORT_SET_COUNT(count) | \
293 I40E_ORT_SET_PAYLOAD(payload))
295 #define I40E_L3_GLQF_ORT_IDX 34
296 #define I40E_L4_GLQF_ORT_IDX 35
298 /* Flex PIT register index */
299 #define I40E_FLEX_PIT_IDX_START_L2 0
300 #define I40E_FLEX_PIT_IDX_START_L3 3
301 #define I40E_FLEX_PIT_IDX_START_L4 6
303 #define I40E_FLEX_PIT_TABLE_SIZE 3
305 #define I40E_FLEX_DEST_UNUSED 63
307 #define I40E_FLEX_INDEX_ENTRIES 8
309 /* Flex MASK to disable all flexible entries */
310 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
311 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
312 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
313 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
315 struct i40e_flex_pit {
316 struct list_head list;
321 /* struct that defines the Ethernet device */
323 struct pci_dev *pdev;
326 struct msix_entry *msix_entries;
327 bool fc_autoneg_status;
330 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
331 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
332 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
333 u16 num_req_vfs; /* num VFs requested for this VF */
334 u16 num_vf_qps; /* num queue pairs per VF */
335 u16 num_lan_qps; /* num lan queues this PF has set up */
336 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
337 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
338 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
339 int iwarp_base_vector;
340 int queues_left; /* queues left unclaimed */
341 u16 alloc_rss_size; /* allocated RSS queues */
342 u16 rss_size_max; /* HW defined max RSS queues */
343 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
344 u16 num_alloc_vsi; /* num VSIs this driver supports */
348 struct hlist_head fdir_filter_list;
349 u16 fdir_pf_active_filters;
350 unsigned long fd_flush_timestamp;
355 /* Book-keeping of side-band filter count per flow-type.
356 * This is used to detect and handle input set changes for
357 * respective flow-type.
359 u16 fd_tcp4_filter_cnt;
360 u16 fd_udp4_filter_cnt;
361 u16 fd_sctp4_filter_cnt;
362 u16 fd_ip4_filter_cnt;
364 /* Flexible filter table values that need to be programmed into
365 * hardware, which expects L3 and L4 to be programmed separately. We
366 * need to ensure that the values are in ascended order and don't have
367 * duplicates, so we track each L3 and L4 values in separate lists.
369 struct list_head l3_flex_pit_list;
370 struct list_head l4_flex_pit_list;
372 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
373 u16 pending_udp_bitmap;
375 enum i40e_interrupt_policy int_policy;
379 char int_name[I40E_INT_NAME_STR_LEN];
380 u16 adminq_work_limit; /* num of admin receive queue desc to process */
381 unsigned long service_timer_period;
382 unsigned long service_timer_previous;
383 struct timer_list service_timer;
384 struct work_struct service_task;
387 #define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)
388 #define I40E_FLAG_MSI_ENABLED BIT_ULL(2)
389 #define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)
390 #define I40E_FLAG_RSS_ENABLED BIT_ULL(6)
391 #define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
392 #define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)
393 #define I40E_FLAG_NEED_LINK_UPDATE BIT_ULL(9)
394 #define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)
395 #define I40E_FLAG_CLEAN_ADMINQ BIT_ULL(14)
396 #define I40E_FLAG_FILTER_SYNC BIT_ULL(15)
397 #define I40E_FLAG_SERVICE_CLIENT_REQUESTED BIT_ULL(16)
398 #define I40E_FLAG_PROCESS_MDD_EVENT BIT_ULL(17)
399 #define I40E_FLAG_PROCESS_VFLR_EVENT BIT_ULL(18)
400 #define I40E_FLAG_SRIOV_ENABLED BIT_ULL(19)
401 #define I40E_FLAG_DCB_ENABLED BIT_ULL(20)
402 #define I40E_FLAG_FD_SB_ENABLED BIT_ULL(21)
403 #define I40E_FLAG_FD_ATR_ENABLED BIT_ULL(22)
404 #define I40E_FLAG_PTP BIT_ULL(25)
405 #define I40E_FLAG_MFP_ENABLED BIT_ULL(26)
406 #define I40E_FLAG_UDP_FILTER_SYNC BIT_ULL(27)
407 #define I40E_FLAG_PORT_ID_VALID BIT_ULL(28)
408 #define I40E_FLAG_DCB_CAPABLE BIT_ULL(29)
409 #define I40E_FLAG_RSS_AQ_CAPABLE BIT_ULL(31)
410 #define I40E_FLAG_HW_ATR_EVICT_CAPABLE BIT_ULL(32)
411 #define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE BIT_ULL(33)
412 #define I40E_FLAG_128_QP_RSS_CAPABLE BIT_ULL(34)
413 #define I40E_FLAG_WB_ON_ITR_CAPABLE BIT_ULL(35)
414 #define I40E_FLAG_VEB_STATS_ENABLED BIT_ULL(37)
415 #define I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT_ULL(38)
416 #define I40E_FLAG_LINK_POLLING_ENABLED BIT_ULL(39)
417 #define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40)
418 #define I40E_FLAG_GENEVE_OFFLOAD_CAPABLE BIT_ULL(41)
419 #define I40E_FLAG_NO_PCI_LINK_CHECK BIT_ULL(42)
420 #define I40E_FLAG_100M_SGMII_CAPABLE BIT_ULL(43)
421 #define I40E_FLAG_RESTART_AUTONEG BIT_ULL(44)
422 #define I40E_FLAG_NO_DCB_SUPPORT BIT_ULL(45)
423 #define I40E_FLAG_USE_SET_LLDP_MIB BIT_ULL(46)
424 #define I40E_FLAG_STOP_FW_LLDP BIT_ULL(47)
425 #define I40E_FLAG_PHY_CONTROLS_LEDS BIT_ULL(48)
426 #define I40E_FLAG_PF_MAC BIT_ULL(50)
427 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT_ULL(51)
428 #define I40E_FLAG_HAVE_CRT_RETIMER BIT_ULL(52)
429 #define I40E_FLAG_PTP_L4_CAPABLE BIT_ULL(53)
430 #define I40E_FLAG_CLIENT_RESET BIT_ULL(54)
431 #define I40E_FLAG_TEMP_LINK_POLLING BIT_ULL(55)
432 #define I40E_FLAG_CLIENT_L2_CHANGE BIT_ULL(56)
433 #define I40E_FLAG_WOL_MC_MAGIC_PKT_WAKE BIT_ULL(57)
435 /* Tracks features that are disabled due to hw limitations.
436 * If a bit is set here, it means that the corresponding
437 * bit in the 'flags' field is cleared i.e that feature
440 u64 hw_disabled_flags;
442 struct i40e_client_instance *cinst;
443 bool stat_offsets_loaded;
444 struct i40e_hw_port_stats stats;
445 struct i40e_hw_port_stats stats_offsets;
446 u32 tx_timeout_count;
447 u32 tx_timeout_recovery_level;
448 unsigned long tx_timeout_last_recovery;
449 u32 tx_sluggish_count;
450 u32 hw_csum_rx_error;
452 u16 corer_count; /* Core reset count */
453 u16 globr_count; /* Global reset count */
454 u16 empr_count; /* EMP reset count */
455 u16 pfr_count; /* PF reset count */
456 u16 sw_int_count; /* SW interrupt count */
458 struct mutex switch_mutex;
459 u16 lan_vsi; /* our default LAN VSI */
460 u16 lan_veb; /* initial relay, if exists */
461 #define I40E_NO_VEB 0xffff
462 #define I40E_NO_VSI 0xffff
463 u16 next_vsi; /* Next unallocated VSI - 0-based! */
464 struct i40e_vsi **vsi;
465 struct i40e_veb *veb[I40E_MAX_VEB];
467 struct i40e_lump_tracking *qp_pile;
468 struct i40e_lump_tracking *irq_pile;
470 /* switch config info */
474 struct kobject *switch_kobj;
475 #ifdef CONFIG_DEBUG_FS
476 struct dentry *i40e_dbg_pf;
477 #endif /* CONFIG_DEBUG_FS */
480 u16 instance; /* A unique number per i40e_pf instance in the system */
482 /* sr-iov config info */
484 int num_alloc_vfs; /* actual number of VFs allocated */
486 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
488 /* DCBx/DCBNL capability for PF that indicates
489 * whether DCBx is managed by firmware or host
490 * based agent (LLDPAD). Also, indicates what
491 * flavor of DCBx protocol (IEEE/CEE) is supported
492 * by the device. For now we're supporting IEEE
497 struct i40e_filter_control_settings filter_settings;
499 struct ptp_clock *ptp_clock;
500 struct ptp_clock_info ptp_caps;
501 struct sk_buff *ptp_tx_skb;
502 struct hwtstamp_config tstamp_config;
503 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
505 u32 tx_hwtstamp_timeouts;
506 u32 rx_hwtstamp_cleared;
507 u32 latch_event_flags;
508 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
509 unsigned long latch_events[4];
512 u16 rss_table_size; /* HW RSS table size */
513 /* These are only valid in NPAR modes */
523 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
524 * @macaddr: the MAC Address as the base key
526 * Simply copies the address and returns it as a u64 for hashing
528 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
532 ether_addr_copy((u8 *)&key, macaddr);
536 enum i40e_filter_state {
537 I40E_FILTER_INVALID = 0, /* Invalid state */
538 I40E_FILTER_NEW, /* New, not sent to FW yet */
539 I40E_FILTER_ACTIVE, /* Added to switch by FW */
540 I40E_FILTER_FAILED, /* Rejected by FW */
541 I40E_FILTER_REMOVE, /* To be removed */
542 /* There is no 'removed' state; the filter struct is freed */
544 struct i40e_mac_filter {
545 struct hlist_node hlist;
546 u8 macaddr[ETH_ALEN];
547 #define I40E_VLAN_ANY -1
549 enum i40e_filter_state state;
552 /* Wrapper structure to keep track of filters while we are preparing to send
553 * firmware commands. We cannot send firmware commands while holding a
554 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
555 * a separate structure, which will track the state change and update the real
556 * filter while under lock. We can't simply hold the filters in a separate
557 * list, as this opens a window for a race condition when adding new MAC
558 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
560 struct i40e_new_mac_filter {
561 struct hlist_node hlist;
562 struct i40e_mac_filter *f;
564 /* Track future changes to state separately */
565 enum i40e_filter_state state;
571 u16 veb_idx; /* index of VEB parent */
574 u16 stats_idx; /* index of VEB parent */
576 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
581 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
582 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
583 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
584 struct kobject *kobj;
585 bool stat_offsets_loaded;
586 struct i40e_eth_stats stats;
587 struct i40e_eth_stats stats_offsets;
588 struct i40e_veb_tc_stats tc_stats;
589 struct i40e_veb_tc_stats tc_stats_offsets;
592 /* struct that defines a VSI, associated with a dev */
594 struct net_device *netdev;
595 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
596 bool netdev_registered;
597 bool stat_offsets_loaded;
599 u32 current_netdev_flags;
601 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
602 #define I40E_VSI_FLAG_VEB_OWNER BIT(1)
605 /* Per VSI lock to protect elements/hash (MAC filter) */
606 spinlock_t mac_filter_hash_lock;
607 /* Fixed size hash table with 2^8 buckets for MAC filters */
608 DECLARE_HASHTABLE(mac_filter_hash, 8);
609 bool has_vlan_filter;
612 struct rtnl_link_stats64 net_stats;
613 struct rtnl_link_stats64 net_stats_offsets;
614 struct i40e_eth_stats eth_stats;
615 struct i40e_eth_stats eth_stats_offsets;
620 u64 tx_lost_interrupt;
624 /* These are containers of ring pointers, allocated at run-time */
625 struct i40e_ring **rx_rings;
626 struct i40e_ring **tx_rings;
629 u32 promisc_threshold;
632 u16 int_rate_limit; /* value in usecs */
634 u16 rss_table_size; /* HW RSS table size */
635 u16 rss_size; /* Allocated RSS queues */
636 u8 *rss_hkey_user; /* User configured hash keys */
637 u8 *rss_lut_user; /* User configured lookup table entries */
643 /* List of q_vectors allocated to this VSI */
644 struct i40e_q_vector **q_vectors;
649 u16 seid; /* HW index of this VSI (absolute index) */
650 u16 id; /* VSI number */
653 u16 base_queue; /* vsi's first queue in hw array */
654 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
655 u16 req_queue_pairs; /* User requested queue pairs */
656 u16 num_queue_pairs; /* Used tx and rx pairs */
658 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
659 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
661 struct i40e_tc_configuration tc_config;
662 struct i40e_aqc_vsi_properties_data info;
664 /* VSI BW limit (absolute across all TCs) */
665 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
666 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
668 /* Relative TC credits across VSIs */
669 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
670 /* TC BW limit credits within VSI */
671 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
672 /* TC BW limit max quanta within VSI */
673 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
675 struct i40e_pf *back; /* Backreference to associated PF */
676 u16 idx; /* index in pf->vsi[] */
677 u16 veb_idx; /* index of VEB parent */
678 struct kobject *kobj; /* sysfs object */
679 bool current_isup; /* Sync 'link up' logging */
680 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
682 void *priv; /* client driver data reference. */
684 /* VSI specific handlers */
685 irqreturn_t (*irq_handler)(int irq, void *data);
686 } ____cacheline_internodealigned_in_smp;
688 struct i40e_netdev_priv {
689 struct i40e_vsi *vsi;
692 /* struct that defines an interrupt vector */
693 struct i40e_q_vector {
694 struct i40e_vsi *vsi;
696 u16 v_idx; /* index in the vsi->q_vector array. */
697 u16 reg_idx; /* register index of the interrupt */
699 struct napi_struct napi;
701 struct i40e_ring_container rx;
702 struct i40e_ring_container tx;
704 u8 num_ringpairs; /* total number of ring pairs in vector */
706 #define I40E_Q_VECTOR_HUNG_DETECT 0 /* Bit Index for hung detection logic */
707 unsigned long hung_detected; /* Set/Reset for hung_detection logic */
709 cpumask_t affinity_mask;
710 struct irq_affinity_notify affinity_notify;
712 struct rcu_head rcu; /* to avoid race with update stats on free */
713 char name[I40E_INT_NAME_STR_LEN];
715 #define ITR_COUNTDOWN_START 100
716 u8 itr_countdown; /* when 0 should adjust ITR */
717 } ____cacheline_internodealigned_in_smp;
721 struct list_head list;
726 * i40e_nvm_version_str - format the NVM version strings
727 * @hw: ptr to the hardware info
729 static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
736 full_ver = hw->nvm.oem_ver;
737 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
738 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
739 I40E_OEM_VER_BUILD_MASK);
740 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
742 snprintf(buf, sizeof(buf),
743 "%x.%02x 0x%x %d.%d.%d",
744 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
745 I40E_NVM_VERSION_HI_SHIFT,
746 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
747 I40E_NVM_VERSION_LO_SHIFT,
748 hw->nvm.eetrack, ver, build, patch);
754 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
755 * @netdev: the corresponding netdev
757 * Return the PF struct for the given netdev
759 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
761 struct i40e_netdev_priv *np = netdev_priv(netdev);
762 struct i40e_vsi *vsi = np->vsi;
767 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
768 irqreturn_t (*irq_handler)(int, void *))
770 vsi->irq_handler = irq_handler;
774 * i40e_rx_is_programming_status - check for programming status descriptor
775 * @qw: the first quad word of the program status descriptor
777 * The value of in the descriptor length field indicate if this
778 * is a programming status descriptor for flow director or FCoE
779 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
780 * it is a packet descriptor.
782 static inline bool i40e_rx_is_programming_status(u64 qw)
784 return I40E_RX_PROG_STATUS_DESC_LENGTH ==
785 (qw >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT);
789 * i40e_get_fd_cnt_all - get the total FD filter space available
790 * @pf: pointer to the PF struct
792 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
794 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
798 * i40e_read_fd_input_set - reads value of flow director input set register
799 * @pf: pointer to the PF struct
800 * @addr: register addr
802 * This function reads value of flow director input set register
803 * specified by 'addr' (which is specific to flow-type)
805 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
809 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
811 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
817 * i40e_write_fd_input_set - writes value into flow director input set register
818 * @pf: pointer to the PF struct
819 * @addr: register addr
820 * @val: value to be written
822 * This function writes specified value to the register specified by 'addr'.
823 * This register is input set register based on flow-type.
825 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
828 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
830 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
831 (u32)(val & 0xFFFFFFFFULL));
834 /* needed by i40e_ethtool.c */
835 int i40e_up(struct i40e_vsi *vsi);
836 void i40e_down(struct i40e_vsi *vsi);
837 extern const char i40e_driver_name[];
838 extern const char i40e_driver_version_str[];
839 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
840 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags);
841 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
842 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
843 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
844 u16 rss_table_size, u16 rss_size);
845 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
847 * i40e_find_vsi_by_type - Find and return Flow Director VSI
848 * @pf: PF to search for VSI
849 * @type: Value indicating type of VSI we are looking for
851 static inline struct i40e_vsi *
852 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
856 for (i = 0; i < pf->num_alloc_vsi; i++) {
857 struct i40e_vsi *vsi = pf->vsi[i];
859 if (vsi && vsi->type == type)
865 void i40e_update_stats(struct i40e_vsi *vsi);
866 void i40e_update_eth_stats(struct i40e_vsi *vsi);
867 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
868 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
871 int i40e_add_del_fdir(struct i40e_vsi *vsi,
872 struct i40e_fdir_filter *input, bool add);
873 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
874 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
875 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
876 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
877 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
878 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
879 void i40e_set_ethtool_ops(struct net_device *netdev);
880 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
881 const u8 *macaddr, s16 vlan);
882 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
883 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
884 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
885 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
886 u16 uplink, u32 param1);
887 int i40e_vsi_release(struct i40e_vsi *vsi);
888 void i40e_service_event_schedule(struct i40e_pf *pf);
889 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
892 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
893 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
894 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
895 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
896 u16 downlink_seid, u8 enabled_tc);
897 void i40e_veb_release(struct i40e_veb *veb);
899 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
900 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
901 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
902 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
903 void i40e_pf_reset_stats(struct i40e_pf *pf);
904 #ifdef CONFIG_DEBUG_FS
905 void i40e_dbg_pf_init(struct i40e_pf *pf);
906 void i40e_dbg_pf_exit(struct i40e_pf *pf);
907 void i40e_dbg_init(void);
908 void i40e_dbg_exit(void);
910 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
911 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
912 static inline void i40e_dbg_init(void) {}
913 static inline void i40e_dbg_exit(void) {}
914 #endif /* CONFIG_DEBUG_FS*/
915 /* needed by client drivers */
916 int i40e_lan_add_device(struct i40e_pf *pf);
917 int i40e_lan_del_device(struct i40e_pf *pf);
918 void i40e_client_subtask(struct i40e_pf *pf);
919 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
920 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
921 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
922 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
923 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
925 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
926 * @vsi: pointer to a vsi
927 * @vector: enable a particular Hw Interrupt vector, without base_vector
929 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
931 struct i40e_pf *pf = vsi->back;
932 struct i40e_hw *hw = &pf->hw;
935 /* definitely clear the PBA here, as this function is meant to
936 * clean out all previous interrupts AND enable the interrupt
938 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
939 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
940 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
941 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
945 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
946 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba);
947 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
948 int i40e_open(struct net_device *netdev);
949 int i40e_close(struct net_device *netdev);
950 int i40e_vsi_open(struct i40e_vsi *vsi);
951 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
952 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
953 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
954 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
955 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
956 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
958 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
959 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
960 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
961 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
962 #ifdef CONFIG_I40E_DCB
963 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
964 struct i40e_dcbx_config *old_cfg,
965 struct i40e_dcbx_config *new_cfg);
966 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
967 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
968 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
969 struct i40e_dcbx_config *old_cfg,
970 struct i40e_dcbx_config *new_cfg);
971 #endif /* CONFIG_I40E_DCB */
972 void i40e_ptp_rx_hang(struct i40e_vsi *vsi);
973 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
974 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
975 void i40e_ptp_set_increment(struct i40e_pf *pf);
976 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
977 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
978 void i40e_ptp_init(struct i40e_pf *pf);
979 void i40e_ptp_stop(struct i40e_pf *pf);
980 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
981 i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf);
982 i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf);
983 i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf);
984 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
985 #endif /* _I40E_H_ */