1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
30 /* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
33 * This file needs to comply with the Linux Kernel coding style.
36 #define I40E_FW_API_VERSION_MAJOR 0x0001
37 #define I40E_FW_API_VERSION_MINOR 0x0004
63 /* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
68 /* command flags and offsets*/
69 #define I40E_AQ_FLAG_DD_SHIFT 0
70 #define I40E_AQ_FLAG_CMP_SHIFT 1
71 #define I40E_AQ_FLAG_ERR_SHIFT 2
72 #define I40E_AQ_FLAG_VFE_SHIFT 3
73 #define I40E_AQ_FLAG_LB_SHIFT 9
74 #define I40E_AQ_FLAG_RD_SHIFT 10
75 #define I40E_AQ_FLAG_VFC_SHIFT 11
76 #define I40E_AQ_FLAG_BUF_SHIFT 12
77 #define I40E_AQ_FLAG_SI_SHIFT 13
78 #define I40E_AQ_FLAG_EI_SHIFT 14
79 #define I40E_AQ_FLAG_FE_SHIFT 15
81 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
94 enum i40e_admin_queue_err {
95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
120 /* Admin Queue command opcodes */
121 enum i40e_admin_queue_opc {
123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
128 /* resource ownership */
129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
136 i40e_aqc_opc_mac_address_read = 0x0107,
137 i40e_aqc_opc_mac_address_write = 0x0108,
140 i40e_aqc_opc_clear_pxe_mode = 0x0110,
142 /* internal switch commands */
143 i40e_aqc_opc_get_switch_config = 0x0200,
144 i40e_aqc_opc_add_statistics = 0x0201,
145 i40e_aqc_opc_remove_statistics = 0x0202,
146 i40e_aqc_opc_set_port_parameters = 0x0203,
147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
149 i40e_aqc_opc_add_vsi = 0x0210,
150 i40e_aqc_opc_update_vsi_parameters = 0x0211,
151 i40e_aqc_opc_get_vsi_parameters = 0x0212,
153 i40e_aqc_opc_add_pv = 0x0220,
154 i40e_aqc_opc_update_pv_parameters = 0x0221,
155 i40e_aqc_opc_get_pv_parameters = 0x0222,
157 i40e_aqc_opc_add_veb = 0x0230,
158 i40e_aqc_opc_update_veb_parameters = 0x0231,
159 i40e_aqc_opc_get_veb_parameters = 0x0232,
161 i40e_aqc_opc_delete_element = 0x0243,
163 i40e_aqc_opc_add_macvlan = 0x0250,
164 i40e_aqc_opc_remove_macvlan = 0x0251,
165 i40e_aqc_opc_add_vlan = 0x0252,
166 i40e_aqc_opc_remove_vlan = 0x0253,
167 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
168 i40e_aqc_opc_add_tag = 0x0255,
169 i40e_aqc_opc_remove_tag = 0x0256,
170 i40e_aqc_opc_add_multicast_etag = 0x0257,
171 i40e_aqc_opc_remove_multicast_etag = 0x0258,
172 i40e_aqc_opc_update_tag = 0x0259,
173 i40e_aqc_opc_add_control_packet_filter = 0x025A,
174 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
175 i40e_aqc_opc_add_cloud_filters = 0x025C,
176 i40e_aqc_opc_remove_cloud_filters = 0x025D,
178 i40e_aqc_opc_add_mirror_rule = 0x0260,
179 i40e_aqc_opc_delete_mirror_rule = 0x0261,
182 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
183 i40e_aqc_opc_dcb_updated = 0x0302,
186 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
187 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
188 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
189 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
190 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
191 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
193 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
194 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
195 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
196 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
197 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
198 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
199 i40e_aqc_opc_query_port_ets_config = 0x0419,
200 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
201 i40e_aqc_opc_suspend_port_tx = 0x041B,
202 i40e_aqc_opc_resume_port_tx = 0x041C,
203 i40e_aqc_opc_configure_partition_bw = 0x041D,
206 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
207 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
210 i40e_aqc_opc_get_phy_abilities = 0x0600,
211 i40e_aqc_opc_set_phy_config = 0x0601,
212 i40e_aqc_opc_set_mac_config = 0x0603,
213 i40e_aqc_opc_set_link_restart_an = 0x0605,
214 i40e_aqc_opc_get_link_status = 0x0607,
215 i40e_aqc_opc_set_phy_int_mask = 0x0613,
216 i40e_aqc_opc_get_local_advt_reg = 0x0614,
217 i40e_aqc_opc_set_local_advt_reg = 0x0615,
218 i40e_aqc_opc_get_partner_advt = 0x0616,
219 i40e_aqc_opc_set_lb_modes = 0x0618,
220 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
221 i40e_aqc_opc_set_phy_debug = 0x0622,
222 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
223 i40e_aqc_opc_run_phy_activity = 0x0626,
226 i40e_aqc_opc_nvm_read = 0x0701,
227 i40e_aqc_opc_nvm_erase = 0x0702,
228 i40e_aqc_opc_nvm_update = 0x0703,
229 i40e_aqc_opc_nvm_config_read = 0x0704,
230 i40e_aqc_opc_nvm_config_write = 0x0705,
231 i40e_aqc_opc_oem_post_update = 0x0720,
233 /* virtualization commands */
234 i40e_aqc_opc_send_msg_to_pf = 0x0801,
235 i40e_aqc_opc_send_msg_to_vf = 0x0802,
236 i40e_aqc_opc_send_msg_to_peer = 0x0803,
238 /* alternate structure */
239 i40e_aqc_opc_alternate_write = 0x0900,
240 i40e_aqc_opc_alternate_write_indirect = 0x0901,
241 i40e_aqc_opc_alternate_read = 0x0902,
242 i40e_aqc_opc_alternate_read_indirect = 0x0903,
243 i40e_aqc_opc_alternate_write_done = 0x0904,
244 i40e_aqc_opc_alternate_set_mode = 0x0905,
245 i40e_aqc_opc_alternate_clear_port = 0x0906,
248 i40e_aqc_opc_lldp_get_mib = 0x0A00,
249 i40e_aqc_opc_lldp_update_mib = 0x0A01,
250 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
251 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
252 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
253 i40e_aqc_opc_lldp_stop = 0x0A05,
254 i40e_aqc_opc_lldp_start = 0x0A06,
255 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
256 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
257 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
259 /* Tunnel commands */
260 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
261 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
262 i40e_aqc_opc_set_rss_key = 0x0B02,
263 i40e_aqc_opc_set_rss_lut = 0x0B03,
264 i40e_aqc_opc_get_rss_key = 0x0B04,
265 i40e_aqc_opc_get_rss_lut = 0x0B05,
268 i40e_aqc_opc_event_lan_overflow = 0x1001,
271 i40e_aqc_opc_oem_parameter_change = 0xFE00,
272 i40e_aqc_opc_oem_device_status_change = 0xFE01,
273 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
274 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
277 i40e_aqc_opc_debug_read_reg = 0xFF03,
278 i40e_aqc_opc_debug_write_reg = 0xFF04,
279 i40e_aqc_opc_debug_modify_reg = 0xFF07,
280 i40e_aqc_opc_debug_dump_internals = 0xFF08,
283 /* command structures and indirect data structures */
285 /* Structure naming conventions:
286 * - no suffix for direct command descriptor structures
287 * - _data for indirect sent data
288 * - _resp for indirect return data (data which is both will use _data)
289 * - _completion for direct return data
290 * - _element_ for repeated elements (may also be _data or _resp)
292 * Command structures are expected to overlay the params.raw member of the basic
293 * descriptor, and as such cannot exceed 16 bytes in length.
296 /* This macro is used to generate a compilation error if a structure
297 * is not exactly the correct length. It gives a divide by zero error if the
298 * structure is not of the correct size, otherwise it creates an enum that is
301 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
302 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
304 /* This macro is used extensively to ensure that command structures are 16
305 * bytes in length as they have to map to the raw array of that size.
307 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
309 /* internal (0x00XX) commands */
311 /* Get version (direct 0x0001) */
312 struct i40e_aqc_get_version {
321 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
323 /* Send driver version (indirect 0x0002) */
324 struct i40e_aqc_driver_version {
328 u8 driver_subbuild_ver;
334 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
336 /* Queue Shutdown (direct 0x0003) */
337 struct i40e_aqc_queue_shutdown {
338 __le32 driver_unloading;
339 #define I40E_AQ_DRIVER_UNLOADING 0x1
343 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
345 /* Set PF context (0x0004, direct) */
346 struct i40e_aqc_set_pf_context {
351 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
353 /* Request resource ownership (direct 0x0008)
354 * Release resource ownership (direct 0x0009)
356 #define I40E_AQ_RESOURCE_NVM 1
357 #define I40E_AQ_RESOURCE_SDP 2
358 #define I40E_AQ_RESOURCE_ACCESS_READ 1
359 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
360 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
361 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
363 struct i40e_aqc_request_resource {
367 __le32 resource_number;
371 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
373 /* Get function capabilities (indirect 0x000A)
374 * Get device capabilities (indirect 0x000B)
376 struct i40e_aqc_list_capabilites {
378 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
386 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
388 struct i40e_aqc_list_capabilities_element_resp {
400 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
401 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
402 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
403 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
404 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
405 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
406 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
407 #define I40E_AQ_CAP_ID_SRIOV 0x0012
408 #define I40E_AQ_CAP_ID_VF 0x0013
409 #define I40E_AQ_CAP_ID_VMDQ 0x0014
410 #define I40E_AQ_CAP_ID_8021QBG 0x0015
411 #define I40E_AQ_CAP_ID_8021QBR 0x0016
412 #define I40E_AQ_CAP_ID_VSI 0x0017
413 #define I40E_AQ_CAP_ID_DCB 0x0018
414 #define I40E_AQ_CAP_ID_FCOE 0x0021
415 #define I40E_AQ_CAP_ID_ISCSI 0x0022
416 #define I40E_AQ_CAP_ID_RSS 0x0040
417 #define I40E_AQ_CAP_ID_RXQ 0x0041
418 #define I40E_AQ_CAP_ID_TXQ 0x0042
419 #define I40E_AQ_CAP_ID_MSIX 0x0043
420 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
421 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
422 #define I40E_AQ_CAP_ID_1588 0x0046
423 #define I40E_AQ_CAP_ID_IWARP 0x0051
424 #define I40E_AQ_CAP_ID_LED 0x0061
425 #define I40E_AQ_CAP_ID_SDP 0x0062
426 #define I40E_AQ_CAP_ID_MDIO 0x0063
427 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
428 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
429 #define I40E_AQ_CAP_ID_CEM 0x00F2
431 /* Set CPPM Configuration (direct 0x0103) */
432 struct i40e_aqc_cppm_configuration {
433 __le16 command_flags;
434 #define I40E_AQ_CPPM_EN_LTRC 0x0800
435 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
436 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
437 #define I40E_AQ_CPPM_EN_HPTC 0x4000
438 #define I40E_AQ_CPPM_EN_DMARC 0x8000
447 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
449 /* Set ARP Proxy command / response (indirect 0x0104) */
450 struct i40e_aqc_arp_proxy_data {
451 __le16 command_flags;
452 #define I40E_AQ_ARP_INIT_IPV4 0x0008
453 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
454 #define I40E_AQ_ARP_ENA 0x0020
455 #define I40E_AQ_ARP_ADD_IPV4 0x0040
456 #define I40E_AQ_ARP_DEL_IPV4 0x0080
464 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
466 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
467 struct i40e_aqc_ns_proxy_data {
468 __le16 table_idx_mac_addr_0;
469 __le16 table_idx_mac_addr_1;
470 __le16 table_idx_ipv6_0;
471 __le16 table_idx_ipv6_1;
473 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
474 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
475 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
476 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
477 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
478 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
479 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
480 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
481 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
482 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
483 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
486 u8 local_mac_addr[6];
487 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
491 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
493 /* Manage LAA Command (0x0106) - obsolete */
494 struct i40e_aqc_mng_laa {
495 __le16 command_flags;
496 #define I40E_AQ_LAA_FLAG_WR 0x8000
503 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
505 /* Manage MAC Address Read Command (indirect 0x0107) */
506 struct i40e_aqc_mac_address_read {
507 __le16 command_flags;
508 #define I40E_AQC_LAN_ADDR_VALID 0x10
509 #define I40E_AQC_SAN_ADDR_VALID 0x20
510 #define I40E_AQC_PORT_ADDR_VALID 0x40
511 #define I40E_AQC_WOL_ADDR_VALID 0x80
512 #define I40E_AQC_MC_MAG_EN_VALID 0x100
513 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
519 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
521 struct i40e_aqc_mac_address_read_data {
528 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
530 /* Manage MAC Address Write Command (0x0108) */
531 struct i40e_aqc_mac_address_write {
532 __le16 command_flags;
533 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
534 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
535 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
536 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
537 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
544 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
546 /* PXE commands (0x011x) */
548 /* Clear PXE Command and response (direct 0x0110) */
549 struct i40e_aqc_clear_pxe {
554 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
556 /* Switch configuration commands (0x02xx) */
558 /* Used by many indirect commands that only pass an seid and a buffer in the
561 struct i40e_aqc_switch_seid {
568 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
570 /* Get Switch Configuration command (indirect 0x0200)
571 * uses i40e_aqc_switch_seid for the descriptor
573 struct i40e_aqc_get_switch_config_header_resp {
579 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
581 struct i40e_aqc_switch_config_element_resp {
583 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
584 #define I40E_AQ_SW_ELEM_TYPE_PF 2
585 #define I40E_AQ_SW_ELEM_TYPE_VF 3
586 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
587 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
588 #define I40E_AQ_SW_ELEM_TYPE_PV 16
589 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
590 #define I40E_AQ_SW_ELEM_TYPE_PA 18
591 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
593 #define I40E_AQ_SW_ELEM_REV_1 1
596 __le16 downlink_seid;
599 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
600 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
601 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
606 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
608 /* Get Switch Configuration (indirect 0x0200)
609 * an array of elements are returned in the response buffer
610 * the first in the array is the header, remainder are elements
612 struct i40e_aqc_get_switch_config_resp {
613 struct i40e_aqc_get_switch_config_header_resp header;
614 struct i40e_aqc_switch_config_element_resp element[1];
617 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
619 /* Add Statistics (direct 0x0201)
620 * Remove Statistics (direct 0x0202)
622 struct i40e_aqc_add_remove_statistics {
629 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
631 /* Set Port Parameters command (direct 0x0203) */
632 struct i40e_aqc_set_port_parameters {
633 __le16 command_flags;
634 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
635 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
636 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
637 __le16 bad_frame_vsi;
638 __le16 default_seid; /* reserved for command */
642 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
644 /* Get Switch Resource Allocation (indirect 0x0204) */
645 struct i40e_aqc_get_switch_resource_alloc {
646 u8 num_entries; /* reserved for command */
652 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
654 /* expect an array of these structs in the response buffer */
655 struct i40e_aqc_switch_resource_alloc_element_resp {
657 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
658 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
659 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
660 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
661 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
662 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
663 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
664 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
665 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
666 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
667 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
668 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
669 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
670 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
671 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
672 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
673 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
674 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
675 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
680 __le16 total_unalloced;
684 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
686 /* Add VSI (indirect 0x0210)
687 * this indirect command uses struct i40e_aqc_vsi_properties_data
688 * as the indirect buffer (128 bytes)
690 * Update VSI (indirect 0x211)
691 * uses the same data structure as Add VSI
693 * Get VSI (indirect 0x0212)
694 * uses the same completion and data structure as Add VSI
696 struct i40e_aqc_add_get_update_vsi {
699 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
700 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
701 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
706 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
707 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
708 #define I40E_AQ_VSI_TYPE_VF 0x0
709 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
710 #define I40E_AQ_VSI_TYPE_PF 0x2
711 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
712 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
717 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
719 struct i40e_aqc_add_get_update_vsi_completion {
728 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
730 struct i40e_aqc_vsi_properties_data {
731 /* first 96 byte are written by SW */
732 __le16 valid_sections;
733 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
734 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
735 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
736 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
737 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
738 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
739 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
740 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
741 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
742 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
744 __le16 switch_id; /* 12bit id combined with flags below */
745 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
746 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
747 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
748 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
749 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
751 /* security section */
753 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
754 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
755 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
758 __le16 pvid; /* VLANS include priority bits */
761 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
762 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
763 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
764 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
765 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
766 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
767 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
768 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
769 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
770 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
771 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
772 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
773 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
774 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
775 u8 pvlan_reserved[3];
776 /* ingress egress up sections */
777 __le32 ingress_table; /* bitmap, 3 bits per up */
778 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
779 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
780 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
781 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
782 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
783 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
784 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
785 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
786 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
787 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
788 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
789 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
790 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
791 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
792 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
793 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
794 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
795 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
796 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
797 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
798 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
799 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
800 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
801 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
802 __le32 egress_table; /* same defines as for ingress table */
803 /* cascaded PV section */
806 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
807 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
808 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
809 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
810 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
811 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
812 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
813 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
814 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
816 /* queue mapping section */
817 __le16 mapping_flags;
818 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
819 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
820 __le16 queue_mapping[16];
821 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
822 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
823 __le16 tc_mapping[8];
824 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
825 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
826 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
827 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
828 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
829 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
830 /* queueing option section */
831 u8 queueing_opt_flags;
832 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
833 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
834 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
835 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
836 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
837 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
838 u8 queueing_opt_reserved[3];
839 /* scheduler section */
842 /* outer up section */
843 __le32 outer_up_table; /* same structure and defines as ingress tbl */
845 /* last 32 bytes are written by FW */
847 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
848 __le16 stat_counter_idx;
850 u8 resp_reserved[12];
853 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
855 /* Add Port Virtualizer (direct 0x0220)
856 * also used for update PV (direct 0x0221) but only flags are used
857 * (IS_CTRL_PORT only works on add PV)
859 struct i40e_aqc_add_update_pv {
860 __le16 command_flags;
861 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
862 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
863 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
864 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
866 __le16 connected_seid;
870 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
872 struct i40e_aqc_add_update_pv_completion {
873 /* reserved for update; for add also encodes error if rc == ENOSPC */
875 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
876 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
877 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
878 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
882 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
884 /* Get PV Params (direct 0x0222)
885 * uses i40e_aqc_switch_seid for the descriptor
888 struct i40e_aqc_get_pv_params_completion {
891 __le16 pv_flags; /* same flags as add_pv */
892 #define I40E_AQC_GET_PV_PV_TYPE 0x1
893 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
894 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
896 __le16 default_port_seid;
899 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
901 /* Add VEB (direct 0x0230) */
902 struct i40e_aqc_add_veb {
904 __le16 downlink_seid;
906 #define I40E_AQC_ADD_VEB_FLOATING 0x1
907 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
908 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
909 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
910 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
911 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
912 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
917 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
919 struct i40e_aqc_add_veb_completion {
922 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
924 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
925 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
926 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
927 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
928 __le16 statistic_index;
933 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
935 /* Get VEB Parameters (direct 0x0232)
936 * uses i40e_aqc_switch_seid for the descriptor
938 struct i40e_aqc_get_veb_parameters_completion {
941 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
942 __le16 statistic_index;
948 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
950 /* Delete Element (direct 0x0243)
951 * uses the generic i40e_aqc_switch_seid
954 /* Add MAC-VLAN (indirect 0x0250) */
956 /* used for the command for most vlan commands */
957 struct i40e_aqc_macvlan {
958 __le16 num_addresses;
960 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
961 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
962 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
963 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
968 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
970 /* indirect data for command and response */
971 struct i40e_aqc_add_macvlan_element_data {
975 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
976 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
977 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
978 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
980 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
981 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
982 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
983 /* response section */
985 #define I40E_AQC_MM_PERFECT_MATCH 0x01
986 #define I40E_AQC_MM_HASH_MATCH 0x02
987 #define I40E_AQC_MM_ERR_NO_RES 0xFF
991 struct i40e_aqc_add_remove_macvlan_completion {
992 __le16 perfect_mac_used;
993 __le16 perfect_mac_free;
994 __le16 unicast_hash_free;
995 __le16 multicast_hash_free;
1000 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1002 /* Remove MAC-VLAN (indirect 0x0251)
1003 * uses i40e_aqc_macvlan for the descriptor
1004 * data points to an array of num_addresses of elements
1007 struct i40e_aqc_remove_macvlan_element_data {
1011 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1012 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1013 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1014 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1018 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1019 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1020 u8 reply_reserved[3];
1023 /* Add VLAN (indirect 0x0252)
1024 * Remove VLAN (indirect 0x0253)
1025 * use the generic i40e_aqc_macvlan for the command
1027 struct i40e_aqc_add_remove_vlan_element_data {
1030 /* flags for add VLAN */
1031 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1032 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1033 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1034 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1035 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1036 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1037 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1038 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1039 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1040 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1041 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1042 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1043 /* flags for remove VLAN */
1044 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1047 /* flags for add VLAN */
1048 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1049 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1050 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1051 /* flags for remove VLAN */
1052 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1053 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1057 struct i40e_aqc_add_remove_vlan_completion {
1065 /* Set VSI Promiscuous Modes (direct 0x0254) */
1066 struct i40e_aqc_set_vsi_promiscuous_modes {
1067 __le16 promiscuous_flags;
1069 /* flags used for both fields above */
1070 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1071 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1072 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1073 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1074 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1076 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1078 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1079 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1083 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1085 /* Add S/E-tag command (direct 0x0255)
1086 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1088 struct i40e_aqc_add_tag {
1090 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1092 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1093 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1094 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1096 __le16 queue_number;
1100 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1102 struct i40e_aqc_add_remove_tag_completion {
1108 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1110 /* Remove S/E-tag command (direct 0x0256)
1111 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1113 struct i40e_aqc_remove_tag {
1115 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1116 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1117 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1122 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1124 /* Add multicast E-Tag (direct 0x0257)
1125 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1126 * and no external data
1128 struct i40e_aqc_add_remove_mcast_etag {
1131 u8 num_unicast_etags;
1133 __le32 addr_high; /* address of array of 2-byte s-tags */
1137 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1139 struct i40e_aqc_add_remove_mcast_etag_completion {
1141 __le16 mcast_etags_used;
1142 __le16 mcast_etags_free;
1148 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1150 /* Update S/E-Tag (direct 0x0259) */
1151 struct i40e_aqc_update_tag {
1153 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1154 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1155 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1161 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1163 struct i40e_aqc_update_tag_completion {
1169 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1171 /* Add Control Packet filter (direct 0x025A)
1172 * Remove Control Packet filter (direct 0x025B)
1173 * uses the i40e_aqc_add_oveb_cloud,
1174 * and the generic direct completion structure
1176 struct i40e_aqc_add_remove_control_packet_filter {
1180 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1181 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1182 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1183 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1184 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1186 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1187 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1188 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1193 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1195 struct i40e_aqc_add_remove_control_packet_filter_completion {
1196 __le16 mac_etype_used;
1198 __le16 mac_etype_free;
1203 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1205 /* Add Cloud filters (indirect 0x025C)
1206 * Remove Cloud filters (indirect 0x025D)
1207 * uses the i40e_aqc_add_remove_cloud_filters,
1208 * and the generic indirect completion structure
1210 struct i40e_aqc_add_remove_cloud_filters {
1214 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1215 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1216 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1222 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1224 struct i40e_aqc_add_remove_cloud_filters_element_data {
1238 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1239 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1240 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1241 /* 0x0000 reserved */
1242 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1243 /* 0x0002 reserved */
1244 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1245 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1246 /* 0x0005 reserved */
1247 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1248 /* 0x0007 reserved */
1249 /* 0x0008 reserved */
1250 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1251 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1252 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1253 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1255 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1256 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1257 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1258 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1259 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1261 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1262 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1263 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1264 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1265 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1266 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1270 __le16 queue_number;
1271 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1272 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1273 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1275 /* response section */
1276 u8 allocation_result;
1277 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1278 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1279 u8 response_reserved[7];
1282 struct i40e_aqc_remove_cloud_filters_completion {
1283 __le16 perfect_ovlan_used;
1284 __le16 perfect_ovlan_free;
1291 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1293 /* Add Mirror Rule (indirect or direct 0x0260)
1294 * Delete Mirror Rule (indirect or direct 0x0261)
1295 * note: some rule types (4,5) do not use an external buffer.
1296 * take care to set the flags correctly.
1298 struct i40e_aqc_add_delete_mirror_rule {
1301 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1302 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1303 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1304 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1305 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1306 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1307 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1308 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1310 __le16 destination; /* VSI for add, rule id for delete */
1311 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1315 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1317 struct i40e_aqc_add_delete_mirror_rule_completion {
1319 __le16 rule_id; /* only used on add */
1320 __le16 mirror_rules_used;
1321 __le16 mirror_rules_free;
1326 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1330 /* PFC Ignore (direct 0x0301)
1331 * the command and response use the same descriptor structure
1333 struct i40e_aqc_pfc_ignore {
1335 u8 command_flags; /* unused on response */
1336 #define I40E_AQC_PFC_IGNORE_SET 0x80
1337 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1341 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1343 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1344 * with no parameters
1347 /* TX scheduler 0x04xx */
1349 /* Almost all the indirect commands use
1350 * this generic struct to pass the SEID in param0
1352 struct i40e_aqc_tx_sched_ind {
1359 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1361 /* Several commands respond with a set of queue set handles */
1362 struct i40e_aqc_qs_handles_resp {
1363 __le16 qs_handles[8];
1366 /* Configure VSI BW limits (direct 0x0400) */
1367 struct i40e_aqc_configure_vsi_bw_limit {
1372 u8 max_credit; /* 0-3, limit = 2^max */
1376 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1378 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1379 * responds with i40e_aqc_qs_handles_resp
1381 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1384 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1386 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1387 __le16 tc_bw_max[2];
1391 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1393 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1394 * responds with i40e_aqc_qs_handles_resp
1396 struct i40e_aqc_configure_vsi_tc_bw_data {
1399 u8 tc_bw_credits[8];
1401 __le16 qs_handles[8];
1404 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1406 /* Query vsi bw configuration (indirect 0x0408) */
1407 struct i40e_aqc_query_vsi_bw_config_resp {
1409 u8 tc_suspended_bits;
1411 __le16 qs_handles[8];
1413 __le16 port_bw_limit;
1415 u8 max_bw; /* 0-3, limit = 2^max */
1419 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1421 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1422 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1425 u8 share_credits[8];
1428 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1429 __le16 tc_bw_max[2];
1432 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1434 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1435 struct i40e_aqc_configure_switching_comp_bw_limit {
1440 u8 max_bw; /* 0-3, limit = 2^max */
1444 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1446 /* Enable Physical Port ETS (indirect 0x0413)
1447 * Modify Physical Port ETS (indirect 0x0414)
1448 * Disable Physical Port ETS (indirect 0x0415)
1450 struct i40e_aqc_configure_switching_comp_ets_data {
1454 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1455 u8 tc_strict_priority_flags;
1457 u8 tc_bw_share_credits[8];
1461 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1463 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1464 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1467 __le16 tc_bw_credit[8];
1469 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1470 __le16 tc_bw_max[2];
1474 I40E_CHECK_STRUCT_LEN(0x40,
1475 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1477 /* Configure Switching Component Bandwidth Allocation per Tc
1480 struct i40e_aqc_configure_switching_comp_bw_config_data {
1483 u8 absolute_credits; /* bool */
1484 u8 tc_bw_share_credits[8];
1488 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1490 /* Query Switching Component Configuration (indirect 0x0418) */
1491 struct i40e_aqc_query_switching_comp_ets_config_resp {
1494 __le16 port_bw_limit;
1496 u8 tc_bw_max; /* 0-3, limit = 2^max */
1500 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1502 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1503 struct i40e_aqc_query_port_ets_config_resp {
1507 u8 tc_strict_priority_bits;
1509 u8 tc_bw_share_credits[8];
1510 __le16 tc_bw_limits[8];
1512 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1513 __le16 tc_bw_max[2];
1517 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1519 /* Query Switching Component Bandwidth Allocation per Traffic Type
1522 struct i40e_aqc_query_switching_comp_bw_config_resp {
1525 u8 absolute_credits_enable; /* bool */
1526 u8 tc_bw_share_credits[8];
1527 __le16 tc_bw_limits[8];
1529 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1530 __le16 tc_bw_max[2];
1533 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1535 /* Suspend/resume port TX traffic
1536 * (direct 0x041B and 0x041C) uses the generic SEID struct
1539 /* Configure partition BW
1542 struct i40e_aqc_configure_partition_bw_data {
1543 __le16 pf_valid_bits;
1544 u8 min_bw[16]; /* guaranteed bandwidth */
1545 u8 max_bw[16]; /* bandwidth limit */
1548 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1550 /* Get and set the active HMC resource profile and status.
1551 * (direct 0x0500) and (direct 0x0501)
1553 struct i40e_aq_get_set_hmc_resource_profile {
1559 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1561 enum i40e_aq_hmc_profile {
1562 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1563 I40E_HMC_PROFILE_DEFAULT = 1,
1564 I40E_HMC_PROFILE_FAVOR_VF = 2,
1565 I40E_HMC_PROFILE_EQUAL = 3,
1568 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1569 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1571 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1573 /* set in param0 for get phy abilities to report qualified modules */
1574 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1575 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1577 enum i40e_aq_phy_type {
1578 I40E_PHY_TYPE_SGMII = 0x0,
1579 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1580 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1581 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1582 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1583 I40E_PHY_TYPE_XAUI = 0x5,
1584 I40E_PHY_TYPE_XFI = 0x6,
1585 I40E_PHY_TYPE_SFI = 0x7,
1586 I40E_PHY_TYPE_XLAUI = 0x8,
1587 I40E_PHY_TYPE_XLPPI = 0x9,
1588 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1589 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1590 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1591 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1592 I40E_PHY_TYPE_100BASE_TX = 0x11,
1593 I40E_PHY_TYPE_1000BASE_T = 0x12,
1594 I40E_PHY_TYPE_10GBASE_T = 0x13,
1595 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1596 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1597 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1598 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1599 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1600 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1601 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1602 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1603 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1604 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1605 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1609 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1610 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1611 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1612 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1613 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1615 enum i40e_aq_link_speed {
1616 I40E_LINK_SPEED_UNKNOWN = 0,
1617 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1618 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1619 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1620 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1621 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1624 struct i40e_aqc_module_desc {
1632 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1634 struct i40e_aq_get_phy_abilities_resp {
1635 __le32 phy_type; /* bitmap using the above enum for offsets */
1636 u8 link_speed; /* bitmap using the above enum bit patterns */
1638 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1639 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1640 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1641 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1642 #define I40E_AQ_PHY_AN_ENABLED 0x10
1643 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1644 __le16 eee_capability;
1645 #define I40E_AQ_EEE_100BASE_TX 0x0002
1646 #define I40E_AQ_EEE_1000BASE_T 0x0004
1647 #define I40E_AQ_EEE_10GBASE_T 0x0008
1648 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1649 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1650 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1653 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1657 u8 qualified_module_count;
1658 #define I40E_AQ_PHY_MAX_QMS 16
1659 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1662 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1664 /* Set PHY Config (direct 0x0601) */
1665 struct i40e_aq_set_phy_config { /* same bits as above in all */
1669 /* bits 0-2 use the values from get_phy_abilities_resp */
1670 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1671 #define I40E_AQ_PHY_ENABLE_AN 0x10
1672 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1673 __le16 eee_capability;
1679 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1681 /* Set MAC Config command data structure (direct 0x0603) */
1682 struct i40e_aq_set_mac_config {
1683 __le16 max_frame_size;
1685 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1691 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1692 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1693 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1694 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1695 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1696 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1697 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1698 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1699 u8 tx_timer_priority; /* bitmap */
1700 __le16 tx_timer_value;
1701 __le16 fc_refresh_threshold;
1705 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1707 /* Restart Auto-Negotiation (direct 0x605) */
1708 struct i40e_aqc_set_link_restart_an {
1710 #define I40E_AQ_PHY_RESTART_AN 0x02
1711 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1715 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1717 /* Get Link Status cmd & response data structure (direct 0x0607) */
1718 struct i40e_aqc_get_link_status {
1719 __le16 command_flags; /* only field set on command */
1720 #define I40E_AQ_LSE_MASK 0x3
1721 #define I40E_AQ_LSE_NOP 0x0
1722 #define I40E_AQ_LSE_DISABLE 0x2
1723 #define I40E_AQ_LSE_ENABLE 0x3
1724 /* only response uses this flag */
1725 #define I40E_AQ_LSE_IS_ENABLED 0x1
1726 u8 phy_type; /* i40e_aq_phy_type */
1727 u8 link_speed; /* i40e_aq_link_speed */
1729 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1730 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1731 #define I40E_AQ_LINK_FAULT 0x02
1732 #define I40E_AQ_LINK_FAULT_TX 0x04
1733 #define I40E_AQ_LINK_FAULT_RX 0x08
1734 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1735 #define I40E_AQ_LINK_UP_PORT 0x20
1736 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1737 #define I40E_AQ_SIGNAL_DETECT 0x80
1739 #define I40E_AQ_AN_COMPLETED 0x01
1740 #define I40E_AQ_LP_AN_ABILITY 0x02
1741 #define I40E_AQ_PD_FAULT 0x04
1742 #define I40E_AQ_FEC_EN 0x08
1743 #define I40E_AQ_PHY_LOW_POWER 0x10
1744 #define I40E_AQ_LINK_PAUSE_TX 0x20
1745 #define I40E_AQ_LINK_PAUSE_RX 0x40
1746 #define I40E_AQ_QUALIFIED_MODULE 0x80
1748 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1749 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1750 #define I40E_AQ_LINK_TX_SHIFT 0x02
1751 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1752 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1753 #define I40E_AQ_LINK_TX_DRAINED 0x01
1754 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1755 #define I40E_AQ_LINK_FORCED_40G 0x10
1756 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1757 __le16 max_frame_size;
1759 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1760 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1761 u8 external_power_ability;
1762 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1763 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1764 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1765 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1769 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1771 /* Set event mask command (direct 0x613) */
1772 struct i40e_aqc_set_phy_int_mask {
1775 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1776 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1777 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1778 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1779 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1780 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1781 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1782 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1783 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1787 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1789 /* Get Local AN advt register (direct 0x0614)
1790 * Set Local AN advt register (direct 0x0615)
1791 * Get Link Partner AN advt register (direct 0x0616)
1793 struct i40e_aqc_an_advt_reg {
1794 __le32 local_an_reg0;
1795 __le16 local_an_reg1;
1799 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1801 /* Set Loopback mode (0x0618) */
1802 struct i40e_aqc_set_lb_mode {
1804 #define I40E_AQ_LB_PHY_LOCAL 0x01
1805 #define I40E_AQ_LB_PHY_REMOTE 0x02
1806 #define I40E_AQ_LB_MAC_LOCAL 0x04
1810 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1812 /* Set PHY Debug command (0x0622) */
1813 struct i40e_aqc_set_phy_debug {
1815 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1816 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1817 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1818 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1819 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1820 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1821 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1822 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1826 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1828 enum i40e_aq_phy_reg_type {
1829 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1830 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1831 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1834 /* Run PHY Activity (0x0626) */
1835 struct i40e_aqc_run_phy_activity {
1844 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1846 /* NVM Read command (indirect 0x0701)
1847 * NVM Erase commands (direct 0x0702)
1848 * NVM Update commands (indirect 0x0703)
1850 struct i40e_aqc_nvm_update {
1852 #define I40E_AQ_NVM_LAST_CMD 0x01
1853 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1861 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1863 /* NVM Config Read (indirect 0x0704) */
1864 struct i40e_aqc_nvm_config_read {
1866 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1867 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1868 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1869 __le16 element_count;
1870 __le16 element_id; /* Feature/field ID */
1871 __le16 element_id_msw; /* MSWord of field ID */
1872 __le32 address_high;
1876 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1878 /* NVM Config Write (indirect 0x0705) */
1879 struct i40e_aqc_nvm_config_write {
1881 __le16 element_count;
1883 __le32 address_high;
1887 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1889 /* Used for 0x0704 as well as for 0x0705 commands */
1890 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1891 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1892 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1893 #define I40E_AQ_ANVM_FEATURE 0
1894 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1895 struct i40e_aqc_nvm_config_data_feature {
1897 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1898 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1899 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1900 __le16 feature_options;
1901 __le16 feature_selection;
1904 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1906 struct i40e_aqc_nvm_config_data_immediate_field {
1909 __le16 field_options;
1913 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1915 /* OEM Post Update (indirect 0x0720)
1916 * no command data struct used
1918 struct i40e_aqc_nvm_oem_post_update {
1919 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1924 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1926 struct i40e_aqc_nvm_oem_post_update_buffer {
1933 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1935 /* Send to PF command (indirect 0x0801) id is only used by PF
1936 * Send to VF command (indirect 0x0802) id is only used by PF
1937 * Send to Peer PF command (indirect 0x0803)
1939 struct i40e_aqc_pf_vf_message {
1946 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1948 /* Alternate structure */
1950 /* Direct write (direct 0x0900)
1951 * Direct read (direct 0x0902)
1953 struct i40e_aqc_alternate_write {
1960 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1962 /* Indirect write (indirect 0x0901)
1963 * Indirect read (indirect 0x0903)
1966 struct i40e_aqc_alternate_ind_write {
1973 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1975 /* Done alternate write (direct 0x0904)
1978 struct i40e_aqc_alternate_write_done {
1980 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1981 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1982 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1983 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1987 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1989 /* Set OEM mode (direct 0x0905) */
1990 struct i40e_aqc_alternate_set_mode {
1992 #define I40E_AQ_ALTERNATE_MODE_NONE 0
1993 #define I40E_AQ_ALTERNATE_MODE_OEM 1
1997 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1999 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2001 /* async events 0x10xx */
2003 /* Lan Queue Overflow Event (direct, 0x1001) */
2004 struct i40e_aqc_lan_overflow {
2005 __le32 prtdcb_rupto;
2010 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2012 /* Get LLDP MIB (indirect 0x0A00) */
2013 struct i40e_aqc_lldp_get_mib {
2016 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2017 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2018 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2019 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2020 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2021 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2022 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2023 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2024 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2025 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2026 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2034 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2036 /* Configure LLDP MIB Change Event (direct 0x0A01)
2037 * also used for the event (with type in the command field)
2039 struct i40e_aqc_lldp_update_mib {
2041 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2042 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2048 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2050 /* Add LLDP TLV (indirect 0x0A02)
2051 * Delete LLDP TLV (indirect 0x0A04)
2053 struct i40e_aqc_lldp_add_tlv {
2054 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2062 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2064 /* Update LLDP TLV (indirect 0x0A03) */
2065 struct i40e_aqc_lldp_update_tlv {
2066 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2075 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2077 /* Stop LLDP (direct 0x0A05) */
2078 struct i40e_aqc_lldp_stop {
2080 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2081 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2085 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2087 /* Start LLDP (direct 0x0A06) */
2089 struct i40e_aqc_lldp_start {
2091 #define I40E_AQ_LLDP_AGENT_START 0x1
2095 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2097 /* Get CEE DCBX Oper Config (0x0A07)
2098 * uses the generic descriptor struct
2099 * returns below as indirect response
2102 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2103 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2104 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2105 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2106 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2107 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2109 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2110 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2111 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2112 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2113 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2114 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2115 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2116 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2117 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2118 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2119 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2120 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2122 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2123 * word boundary layout issues, which the Linux compilers silently deal
2124 * with by adding padding, making the actual struct larger than designed.
2125 * However, the FW compiler for the NIC is less lenient and complains
2126 * about the struct. Hence, the struct defined here has an extra byte in
2127 * fields reserved3 and reserved4 to directly acknowledge that padding,
2128 * and the new length is used in the length check macro.
2130 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2138 __le16 oper_app_prio;
2143 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2145 struct i40e_aqc_get_cee_dcb_cfg_resp {
2150 __le16 oper_app_prio;
2151 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2152 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2153 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2154 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2155 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2156 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2157 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2159 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2160 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2161 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2162 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2163 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2164 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2168 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2170 /* Set Local LLDP MIB (indirect 0x0A08)
2171 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2173 struct i40e_aqc_lldp_set_local_mib {
2174 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2175 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2176 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2177 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2178 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2179 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2180 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2181 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2182 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2187 __le32 address_high;
2191 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2193 /* Stop/Start LLDP Agent (direct 0x0A09)
2194 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2196 struct i40e_aqc_lldp_stop_start_specific_agent {
2197 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2198 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2199 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2204 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2206 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2207 struct i40e_aqc_add_udp_tunnel {
2211 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2212 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2213 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2217 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2219 struct i40e_aqc_add_udp_tunnel_completion {
2221 u8 filter_entry_index;
2223 #define I40E_AQC_SINGLE_PF 0x0
2224 #define I40E_AQC_MULTIPLE_PFS 0x1
2229 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2231 /* remove UDP Tunnel command (0x0B01) */
2232 struct i40e_aqc_remove_udp_tunnel {
2234 u8 index; /* 0 to 15 */
2238 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2240 struct i40e_aqc_del_udp_tunnel_completion {
2242 u8 index; /* 0 to 15 */
2244 u8 total_filters_used;
2248 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2250 struct i40e_aqc_get_set_rss_key {
2251 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2252 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2253 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2254 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2261 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2263 struct i40e_aqc_get_set_rss_key_data {
2264 u8 standard_rss_key[0x28];
2265 u8 extended_hash_key[0xc];
2268 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2270 struct i40e_aqc_get_set_rss_lut {
2271 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2272 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2273 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2274 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2276 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2277 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2278 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2280 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2281 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2288 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2290 /* tunnel key structure 0x0B10 */
2292 struct i40e_aqc_tunnel_key_structure {
2295 u8 key1_len; /* 0 to 15 */
2296 u8 key2_len; /* 0 to 15 */
2298 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2299 /* response flags */
2300 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2301 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2302 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2303 u8 network_key_index;
2304 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2305 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2306 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2307 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2311 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2313 /* OEM mode commands (direct 0xFE0x) */
2314 struct i40e_aqc_oem_param_change {
2316 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2317 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2318 #define I40E_AQ_OEM_PARAM_MAC 2
2319 __le32 param_value1;
2320 __le16 param_value2;
2324 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2326 struct i40e_aqc_oem_state_change {
2328 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2329 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2333 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2335 /* Initialize OCSD (0xFE02, direct) */
2336 struct i40e_aqc_opc_oem_ocsd_initialize {
2339 __le32 ocsd_memory_block_addr_high;
2340 __le32 ocsd_memory_block_addr_low;
2341 __le32 requested_update_interval;
2344 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2346 /* Initialize OCBB (0xFE03, direct) */
2347 struct i40e_aqc_opc_oem_ocbb_initialize {
2350 __le32 ocbb_memory_block_addr_high;
2351 __le32 ocbb_memory_block_addr_low;
2355 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2357 /* debug commands */
2359 /* get device id (0xFF00) uses the generic structure */
2361 /* set test more (0xFF01, internal) */
2363 struct i40e_acq_set_test_mode {
2365 #define I40E_AQ_TEST_PARTIAL 0
2366 #define I40E_AQ_TEST_FULL 1
2367 #define I40E_AQ_TEST_NVM 2
2370 #define I40E_AQ_TEST_OPEN 0
2371 #define I40E_AQ_TEST_CLOSE 1
2372 #define I40E_AQ_TEST_INC 2
2374 __le32 address_high;
2378 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2380 /* Debug Read Register command (0xFF03)
2381 * Debug Write Register command (0xFF04)
2383 struct i40e_aqc_debug_reg_read_write {
2390 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2392 /* Scatter/gather Reg Read (indirect 0xFF05)
2393 * Scatter/gather Reg Write (indirect 0xFF06)
2396 /* i40e_aq_desc is used for the command */
2397 struct i40e_aqc_debug_reg_sg_element_data {
2402 /* Debug Modify register (direct 0xFF07) */
2403 struct i40e_aqc_debug_modify_reg {
2410 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2412 /* dump internal data (0xFF08, indirect) */
2414 #define I40E_AQ_CLUSTER_ID_AUX 0
2415 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2416 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2417 #define I40E_AQ_CLUSTER_ID_HMC 3
2418 #define I40E_AQ_CLUSTER_ID_MAC0 4
2419 #define I40E_AQ_CLUSTER_ID_MAC1 5
2420 #define I40E_AQ_CLUSTER_ID_MAC2 6
2421 #define I40E_AQ_CLUSTER_ID_MAC3 7
2422 #define I40E_AQ_CLUSTER_ID_DCB 8
2423 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2424 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2425 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2427 struct i40e_aqc_debug_dump_internals {
2432 __le32 address_high;
2436 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2438 struct i40e_aqc_debug_modify_internals {
2440 u8 cluster_specific_params[7];
2441 __le32 address_high;
2445 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2447 #endif /* _I40E_ADMINQ_CMD_H_ */