1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
30 /* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
33 * This file needs to comply with the Linux Kernel coding style.
36 #define I40E_FW_API_VERSION_MAJOR 0x0001
37 #define I40E_FW_API_VERSION_MINOR 0x0004
63 /* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
68 /* command flags and offsets*/
69 #define I40E_AQ_FLAG_DD_SHIFT 0
70 #define I40E_AQ_FLAG_CMP_SHIFT 1
71 #define I40E_AQ_FLAG_ERR_SHIFT 2
72 #define I40E_AQ_FLAG_VFE_SHIFT 3
73 #define I40E_AQ_FLAG_LB_SHIFT 9
74 #define I40E_AQ_FLAG_RD_SHIFT 10
75 #define I40E_AQ_FLAG_VFC_SHIFT 11
76 #define I40E_AQ_FLAG_BUF_SHIFT 12
77 #define I40E_AQ_FLAG_SI_SHIFT 13
78 #define I40E_AQ_FLAG_EI_SHIFT 14
79 #define I40E_AQ_FLAG_FE_SHIFT 15
81 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
94 enum i40e_admin_queue_err {
95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
120 /* Admin Queue command opcodes */
121 enum i40e_admin_queue_opc {
123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
128 /* resource ownership */
129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
136 i40e_aqc_opc_mac_address_read = 0x0107,
137 i40e_aqc_opc_mac_address_write = 0x0108,
140 i40e_aqc_opc_clear_pxe_mode = 0x0110,
142 /* internal switch commands */
143 i40e_aqc_opc_get_switch_config = 0x0200,
144 i40e_aqc_opc_add_statistics = 0x0201,
145 i40e_aqc_opc_remove_statistics = 0x0202,
146 i40e_aqc_opc_set_port_parameters = 0x0203,
147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
149 i40e_aqc_opc_add_vsi = 0x0210,
150 i40e_aqc_opc_update_vsi_parameters = 0x0211,
151 i40e_aqc_opc_get_vsi_parameters = 0x0212,
153 i40e_aqc_opc_add_pv = 0x0220,
154 i40e_aqc_opc_update_pv_parameters = 0x0221,
155 i40e_aqc_opc_get_pv_parameters = 0x0222,
157 i40e_aqc_opc_add_veb = 0x0230,
158 i40e_aqc_opc_update_veb_parameters = 0x0231,
159 i40e_aqc_opc_get_veb_parameters = 0x0232,
161 i40e_aqc_opc_delete_element = 0x0243,
163 i40e_aqc_opc_add_macvlan = 0x0250,
164 i40e_aqc_opc_remove_macvlan = 0x0251,
165 i40e_aqc_opc_add_vlan = 0x0252,
166 i40e_aqc_opc_remove_vlan = 0x0253,
167 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
168 i40e_aqc_opc_add_tag = 0x0255,
169 i40e_aqc_opc_remove_tag = 0x0256,
170 i40e_aqc_opc_add_multicast_etag = 0x0257,
171 i40e_aqc_opc_remove_multicast_etag = 0x0258,
172 i40e_aqc_opc_update_tag = 0x0259,
173 i40e_aqc_opc_add_control_packet_filter = 0x025A,
174 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
175 i40e_aqc_opc_add_cloud_filters = 0x025C,
176 i40e_aqc_opc_remove_cloud_filters = 0x025D,
178 i40e_aqc_opc_add_mirror_rule = 0x0260,
179 i40e_aqc_opc_delete_mirror_rule = 0x0261,
182 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
183 i40e_aqc_opc_dcb_updated = 0x0302,
186 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
187 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
188 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
189 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
190 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
191 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
193 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
194 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
195 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
196 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
197 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
198 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
199 i40e_aqc_opc_query_port_ets_config = 0x0419,
200 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
201 i40e_aqc_opc_suspend_port_tx = 0x041B,
202 i40e_aqc_opc_resume_port_tx = 0x041C,
203 i40e_aqc_opc_configure_partition_bw = 0x041D,
206 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
207 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
210 i40e_aqc_opc_get_phy_abilities = 0x0600,
211 i40e_aqc_opc_set_phy_config = 0x0601,
212 i40e_aqc_opc_set_mac_config = 0x0603,
213 i40e_aqc_opc_set_link_restart_an = 0x0605,
214 i40e_aqc_opc_get_link_status = 0x0607,
215 i40e_aqc_opc_set_phy_int_mask = 0x0613,
216 i40e_aqc_opc_get_local_advt_reg = 0x0614,
217 i40e_aqc_opc_set_local_advt_reg = 0x0615,
218 i40e_aqc_opc_get_partner_advt = 0x0616,
219 i40e_aqc_opc_set_lb_modes = 0x0618,
220 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
221 i40e_aqc_opc_set_phy_debug = 0x0622,
222 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
225 i40e_aqc_opc_nvm_read = 0x0701,
226 i40e_aqc_opc_nvm_erase = 0x0702,
227 i40e_aqc_opc_nvm_update = 0x0703,
228 i40e_aqc_opc_nvm_config_read = 0x0704,
229 i40e_aqc_opc_nvm_config_write = 0x0705,
230 i40e_aqc_opc_oem_post_update = 0x0720,
232 /* virtualization commands */
233 i40e_aqc_opc_send_msg_to_pf = 0x0801,
234 i40e_aqc_opc_send_msg_to_vf = 0x0802,
235 i40e_aqc_opc_send_msg_to_peer = 0x0803,
237 /* alternate structure */
238 i40e_aqc_opc_alternate_write = 0x0900,
239 i40e_aqc_opc_alternate_write_indirect = 0x0901,
240 i40e_aqc_opc_alternate_read = 0x0902,
241 i40e_aqc_opc_alternate_read_indirect = 0x0903,
242 i40e_aqc_opc_alternate_write_done = 0x0904,
243 i40e_aqc_opc_alternate_set_mode = 0x0905,
244 i40e_aqc_opc_alternate_clear_port = 0x0906,
247 i40e_aqc_opc_lldp_get_mib = 0x0A00,
248 i40e_aqc_opc_lldp_update_mib = 0x0A01,
249 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
250 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
251 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
252 i40e_aqc_opc_lldp_stop = 0x0A05,
253 i40e_aqc_opc_lldp_start = 0x0A06,
254 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
255 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
256 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
258 /* Tunnel commands */
259 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
260 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
261 i40e_aqc_opc_set_rss_key = 0x0B02,
262 i40e_aqc_opc_set_rss_lut = 0x0B03,
263 i40e_aqc_opc_get_rss_key = 0x0B04,
264 i40e_aqc_opc_get_rss_lut = 0x0B05,
267 i40e_aqc_opc_event_lan_overflow = 0x1001,
270 i40e_aqc_opc_oem_parameter_change = 0xFE00,
271 i40e_aqc_opc_oem_device_status_change = 0xFE01,
272 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
273 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
276 i40e_aqc_opc_debug_read_reg = 0xFF03,
277 i40e_aqc_opc_debug_write_reg = 0xFF04,
278 i40e_aqc_opc_debug_modify_reg = 0xFF07,
279 i40e_aqc_opc_debug_dump_internals = 0xFF08,
282 /* command structures and indirect data structures */
284 /* Structure naming conventions:
285 * - no suffix for direct command descriptor structures
286 * - _data for indirect sent data
287 * - _resp for indirect return data (data which is both will use _data)
288 * - _completion for direct return data
289 * - _element_ for repeated elements (may also be _data or _resp)
291 * Command structures are expected to overlay the params.raw member of the basic
292 * descriptor, and as such cannot exceed 16 bytes in length.
295 /* This macro is used to generate a compilation error if a structure
296 * is not exactly the correct length. It gives a divide by zero error if the
297 * structure is not of the correct size, otherwise it creates an enum that is
300 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
301 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
303 /* This macro is used extensively to ensure that command structures are 16
304 * bytes in length as they have to map to the raw array of that size.
306 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
308 /* internal (0x00XX) commands */
310 /* Get version (direct 0x0001) */
311 struct i40e_aqc_get_version {
320 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
322 /* Send driver version (indirect 0x0002) */
323 struct i40e_aqc_driver_version {
327 u8 driver_subbuild_ver;
333 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
335 /* Queue Shutdown (direct 0x0003) */
336 struct i40e_aqc_queue_shutdown {
337 __le32 driver_unloading;
338 #define I40E_AQ_DRIVER_UNLOADING 0x1
342 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
344 /* Set PF context (0x0004, direct) */
345 struct i40e_aqc_set_pf_context {
350 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
352 /* Request resource ownership (direct 0x0008)
353 * Release resource ownership (direct 0x0009)
355 #define I40E_AQ_RESOURCE_NVM 1
356 #define I40E_AQ_RESOURCE_SDP 2
357 #define I40E_AQ_RESOURCE_ACCESS_READ 1
358 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
359 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
360 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
362 struct i40e_aqc_request_resource {
366 __le32 resource_number;
370 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
372 /* Get function capabilities (indirect 0x000A)
373 * Get device capabilities (indirect 0x000B)
375 struct i40e_aqc_list_capabilites {
377 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
385 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
387 struct i40e_aqc_list_capabilities_element_resp {
399 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
400 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
401 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
402 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
403 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
404 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
405 #define I40E_AQ_CAP_ID_SRIOV 0x0012
406 #define I40E_AQ_CAP_ID_VF 0x0013
407 #define I40E_AQ_CAP_ID_VMDQ 0x0014
408 #define I40E_AQ_CAP_ID_8021QBG 0x0015
409 #define I40E_AQ_CAP_ID_8021QBR 0x0016
410 #define I40E_AQ_CAP_ID_VSI 0x0017
411 #define I40E_AQ_CAP_ID_DCB 0x0018
412 #define I40E_AQ_CAP_ID_FCOE 0x0021
413 #define I40E_AQ_CAP_ID_ISCSI 0x0022
414 #define I40E_AQ_CAP_ID_RSS 0x0040
415 #define I40E_AQ_CAP_ID_RXQ 0x0041
416 #define I40E_AQ_CAP_ID_TXQ 0x0042
417 #define I40E_AQ_CAP_ID_MSIX 0x0043
418 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
419 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
420 #define I40E_AQ_CAP_ID_1588 0x0046
421 #define I40E_AQ_CAP_ID_IWARP 0x0051
422 #define I40E_AQ_CAP_ID_LED 0x0061
423 #define I40E_AQ_CAP_ID_SDP 0x0062
424 #define I40E_AQ_CAP_ID_MDIO 0x0063
425 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
426 #define I40E_AQ_CAP_ID_CEM 0x00F2
428 /* Set CPPM Configuration (direct 0x0103) */
429 struct i40e_aqc_cppm_configuration {
430 __le16 command_flags;
431 #define I40E_AQ_CPPM_EN_LTRC 0x0800
432 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
433 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
434 #define I40E_AQ_CPPM_EN_HPTC 0x4000
435 #define I40E_AQ_CPPM_EN_DMARC 0x8000
444 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
446 /* Set ARP Proxy command / response (indirect 0x0104) */
447 struct i40e_aqc_arp_proxy_data {
448 __le16 command_flags;
449 #define I40E_AQ_ARP_INIT_IPV4 0x0008
450 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
451 #define I40E_AQ_ARP_ENA 0x0020
452 #define I40E_AQ_ARP_ADD_IPV4 0x0040
453 #define I40E_AQ_ARP_DEL_IPV4 0x0080
461 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
463 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
464 struct i40e_aqc_ns_proxy_data {
465 __le16 table_idx_mac_addr_0;
466 __le16 table_idx_mac_addr_1;
467 __le16 table_idx_ipv6_0;
468 __le16 table_idx_ipv6_1;
470 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
471 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
472 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
473 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
474 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
475 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
476 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
477 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
478 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
479 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
480 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
483 u8 local_mac_addr[6];
484 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
488 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
490 /* Manage LAA Command (0x0106) - obsolete */
491 struct i40e_aqc_mng_laa {
492 __le16 command_flags;
493 #define I40E_AQ_LAA_FLAG_WR 0x8000
500 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
502 /* Manage MAC Address Read Command (indirect 0x0107) */
503 struct i40e_aqc_mac_address_read {
504 __le16 command_flags;
505 #define I40E_AQC_LAN_ADDR_VALID 0x10
506 #define I40E_AQC_SAN_ADDR_VALID 0x20
507 #define I40E_AQC_PORT_ADDR_VALID 0x40
508 #define I40E_AQC_WOL_ADDR_VALID 0x80
509 #define I40E_AQC_MC_MAG_EN_VALID 0x100
510 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
516 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
518 struct i40e_aqc_mac_address_read_data {
525 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
527 /* Manage MAC Address Write Command (0x0108) */
528 struct i40e_aqc_mac_address_write {
529 __le16 command_flags;
530 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
531 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
532 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
533 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
534 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
541 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
543 /* PXE commands (0x011x) */
545 /* Clear PXE Command and response (direct 0x0110) */
546 struct i40e_aqc_clear_pxe {
551 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
553 /* Switch configuration commands (0x02xx) */
555 /* Used by many indirect commands that only pass an seid and a buffer in the
558 struct i40e_aqc_switch_seid {
565 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
567 /* Get Switch Configuration command (indirect 0x0200)
568 * uses i40e_aqc_switch_seid for the descriptor
570 struct i40e_aqc_get_switch_config_header_resp {
576 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
578 struct i40e_aqc_switch_config_element_resp {
580 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
581 #define I40E_AQ_SW_ELEM_TYPE_PF 2
582 #define I40E_AQ_SW_ELEM_TYPE_VF 3
583 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
584 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
585 #define I40E_AQ_SW_ELEM_TYPE_PV 16
586 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
587 #define I40E_AQ_SW_ELEM_TYPE_PA 18
588 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
590 #define I40E_AQ_SW_ELEM_REV_1 1
593 __le16 downlink_seid;
596 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
597 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
598 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
603 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
605 /* Get Switch Configuration (indirect 0x0200)
606 * an array of elements are returned in the response buffer
607 * the first in the array is the header, remainder are elements
609 struct i40e_aqc_get_switch_config_resp {
610 struct i40e_aqc_get_switch_config_header_resp header;
611 struct i40e_aqc_switch_config_element_resp element[1];
614 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
616 /* Add Statistics (direct 0x0201)
617 * Remove Statistics (direct 0x0202)
619 struct i40e_aqc_add_remove_statistics {
626 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
628 /* Set Port Parameters command (direct 0x0203) */
629 struct i40e_aqc_set_port_parameters {
630 __le16 command_flags;
631 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
632 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
633 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
634 __le16 bad_frame_vsi;
635 __le16 default_seid; /* reserved for command */
639 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
641 /* Get Switch Resource Allocation (indirect 0x0204) */
642 struct i40e_aqc_get_switch_resource_alloc {
643 u8 num_entries; /* reserved for command */
649 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
651 /* expect an array of these structs in the response buffer */
652 struct i40e_aqc_switch_resource_alloc_element_resp {
654 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
655 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
656 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
657 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
658 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
659 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
660 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
661 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
662 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
663 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
664 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
665 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
666 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
667 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
668 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
669 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
670 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
671 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
672 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
677 __le16 total_unalloced;
681 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
683 /* Add VSI (indirect 0x0210)
684 * this indirect command uses struct i40e_aqc_vsi_properties_data
685 * as the indirect buffer (128 bytes)
687 * Update VSI (indirect 0x211)
688 * uses the same data structure as Add VSI
690 * Get VSI (indirect 0x0212)
691 * uses the same completion and data structure as Add VSI
693 struct i40e_aqc_add_get_update_vsi {
696 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
697 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
698 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
703 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
704 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
705 #define I40E_AQ_VSI_TYPE_VF 0x0
706 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
707 #define I40E_AQ_VSI_TYPE_PF 0x2
708 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
709 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
714 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
716 struct i40e_aqc_add_get_update_vsi_completion {
725 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
727 struct i40e_aqc_vsi_properties_data {
728 /* first 96 byte are written by SW */
729 __le16 valid_sections;
730 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
731 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
732 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
733 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
734 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
735 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
736 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
737 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
738 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
739 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
741 __le16 switch_id; /* 12bit id combined with flags below */
742 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
743 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
744 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
745 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
746 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
748 /* security section */
750 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
751 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
752 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
755 __le16 pvid; /* VLANS include priority bits */
758 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
759 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
760 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
761 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
762 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
763 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
764 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
765 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
766 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
767 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
768 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
769 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
770 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
771 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
772 u8 pvlan_reserved[3];
773 /* ingress egress up sections */
774 __le32 ingress_table; /* bitmap, 3 bits per up */
775 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
776 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
777 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
778 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
779 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
780 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
781 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
782 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
783 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
784 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
785 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
786 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
787 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
788 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
789 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
790 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
791 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
792 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
793 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
794 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
795 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
796 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
797 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
798 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
799 __le32 egress_table; /* same defines as for ingress table */
800 /* cascaded PV section */
803 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
804 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
805 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
806 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
807 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
808 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
809 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
810 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
811 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
813 /* queue mapping section */
814 __le16 mapping_flags;
815 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
816 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
817 __le16 queue_mapping[16];
818 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
819 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
820 __le16 tc_mapping[8];
821 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
822 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
823 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
824 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
825 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
826 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
827 /* queueing option section */
828 u8 queueing_opt_flags;
829 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
830 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
831 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
832 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
833 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
834 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
835 u8 queueing_opt_reserved[3];
836 /* scheduler section */
839 /* outer up section */
840 __le32 outer_up_table; /* same structure and defines as ingress tbl */
842 /* last 32 bytes are written by FW */
844 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
845 __le16 stat_counter_idx;
847 u8 resp_reserved[12];
850 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
852 /* Add Port Virtualizer (direct 0x0220)
853 * also used for update PV (direct 0x0221) but only flags are used
854 * (IS_CTRL_PORT only works on add PV)
856 struct i40e_aqc_add_update_pv {
857 __le16 command_flags;
858 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
859 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
860 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
861 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
863 __le16 connected_seid;
867 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
869 struct i40e_aqc_add_update_pv_completion {
870 /* reserved for update; for add also encodes error if rc == ENOSPC */
872 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
873 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
874 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
875 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
879 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
881 /* Get PV Params (direct 0x0222)
882 * uses i40e_aqc_switch_seid for the descriptor
885 struct i40e_aqc_get_pv_params_completion {
888 __le16 pv_flags; /* same flags as add_pv */
889 #define I40E_AQC_GET_PV_PV_TYPE 0x1
890 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
891 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
893 __le16 default_port_seid;
896 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
898 /* Add VEB (direct 0x0230) */
899 struct i40e_aqc_add_veb {
901 __le16 downlink_seid;
903 #define I40E_AQC_ADD_VEB_FLOATING 0x1
904 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
905 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
906 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
907 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
908 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
909 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
914 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
916 struct i40e_aqc_add_veb_completion {
919 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
921 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
922 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
923 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
924 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
925 __le16 statistic_index;
930 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
932 /* Get VEB Parameters (direct 0x0232)
933 * uses i40e_aqc_switch_seid for the descriptor
935 struct i40e_aqc_get_veb_parameters_completion {
938 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
939 __le16 statistic_index;
945 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
947 /* Delete Element (direct 0x0243)
948 * uses the generic i40e_aqc_switch_seid
951 /* Add MAC-VLAN (indirect 0x0250) */
953 /* used for the command for most vlan commands */
954 struct i40e_aqc_macvlan {
955 __le16 num_addresses;
957 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
958 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
959 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
960 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
965 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
967 /* indirect data for command and response */
968 struct i40e_aqc_add_macvlan_element_data {
972 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
973 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
974 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
975 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
977 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
978 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
979 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
980 /* response section */
982 #define I40E_AQC_MM_PERFECT_MATCH 0x01
983 #define I40E_AQC_MM_HASH_MATCH 0x02
984 #define I40E_AQC_MM_ERR_NO_RES 0xFF
988 struct i40e_aqc_add_remove_macvlan_completion {
989 __le16 perfect_mac_used;
990 __le16 perfect_mac_free;
991 __le16 unicast_hash_free;
992 __le16 multicast_hash_free;
997 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
999 /* Remove MAC-VLAN (indirect 0x0251)
1000 * uses i40e_aqc_macvlan for the descriptor
1001 * data points to an array of num_addresses of elements
1004 struct i40e_aqc_remove_macvlan_element_data {
1008 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1009 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1010 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1011 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1015 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1016 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1017 u8 reply_reserved[3];
1020 /* Add VLAN (indirect 0x0252)
1021 * Remove VLAN (indirect 0x0253)
1022 * use the generic i40e_aqc_macvlan for the command
1024 struct i40e_aqc_add_remove_vlan_element_data {
1027 /* flags for add VLAN */
1028 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1029 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1030 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1031 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1032 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1033 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1034 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1035 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1036 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1037 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1038 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1039 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1040 /* flags for remove VLAN */
1041 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1044 /* flags for add VLAN */
1045 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1046 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1047 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1048 /* flags for remove VLAN */
1049 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1050 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1054 struct i40e_aqc_add_remove_vlan_completion {
1062 /* Set VSI Promiscuous Modes (direct 0x0254) */
1063 struct i40e_aqc_set_vsi_promiscuous_modes {
1064 __le16 promiscuous_flags;
1066 /* flags used for both fields above */
1067 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1068 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1069 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1070 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1071 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1073 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1075 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1076 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1080 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1082 /* Add S/E-tag command (direct 0x0255)
1083 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1085 struct i40e_aqc_add_tag {
1087 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1089 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1090 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1091 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1093 __le16 queue_number;
1097 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1099 struct i40e_aqc_add_remove_tag_completion {
1105 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1107 /* Remove S/E-tag command (direct 0x0256)
1108 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1110 struct i40e_aqc_remove_tag {
1112 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1113 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1114 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1119 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1121 /* Add multicast E-Tag (direct 0x0257)
1122 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1123 * and no external data
1125 struct i40e_aqc_add_remove_mcast_etag {
1128 u8 num_unicast_etags;
1130 __le32 addr_high; /* address of array of 2-byte s-tags */
1134 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1136 struct i40e_aqc_add_remove_mcast_etag_completion {
1138 __le16 mcast_etags_used;
1139 __le16 mcast_etags_free;
1145 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1147 /* Update S/E-Tag (direct 0x0259) */
1148 struct i40e_aqc_update_tag {
1150 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1151 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1152 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1158 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1160 struct i40e_aqc_update_tag_completion {
1166 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1168 /* Add Control Packet filter (direct 0x025A)
1169 * Remove Control Packet filter (direct 0x025B)
1170 * uses the i40e_aqc_add_oveb_cloud,
1171 * and the generic direct completion structure
1173 struct i40e_aqc_add_remove_control_packet_filter {
1177 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1178 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1179 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1180 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1181 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1183 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1184 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1185 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1190 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1192 struct i40e_aqc_add_remove_control_packet_filter_completion {
1193 __le16 mac_etype_used;
1195 __le16 mac_etype_free;
1200 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1202 /* Add Cloud filters (indirect 0x025C)
1203 * Remove Cloud filters (indirect 0x025D)
1204 * uses the i40e_aqc_add_remove_cloud_filters,
1205 * and the generic indirect completion structure
1207 struct i40e_aqc_add_remove_cloud_filters {
1211 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1212 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1213 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1219 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1221 struct i40e_aqc_add_remove_cloud_filters_element_data {
1235 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1236 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1237 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1238 /* 0x0000 reserved */
1239 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1240 /* 0x0002 reserved */
1241 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1242 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1243 /* 0x0005 reserved */
1244 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1245 /* 0x0007 reserved */
1246 /* 0x0008 reserved */
1247 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1248 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1249 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1250 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1252 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1253 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1254 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1255 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1256 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1258 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1259 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1260 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1261 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1262 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1263 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1267 __le16 queue_number;
1268 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1269 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1270 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1272 /* response section */
1273 u8 allocation_result;
1274 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1275 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1276 u8 response_reserved[7];
1279 struct i40e_aqc_remove_cloud_filters_completion {
1280 __le16 perfect_ovlan_used;
1281 __le16 perfect_ovlan_free;
1288 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1290 /* Add Mirror Rule (indirect or direct 0x0260)
1291 * Delete Mirror Rule (indirect or direct 0x0261)
1292 * note: some rule types (4,5) do not use an external buffer.
1293 * take care to set the flags correctly.
1295 struct i40e_aqc_add_delete_mirror_rule {
1298 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1299 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1300 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1301 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1302 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1303 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1304 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1305 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1307 __le16 destination; /* VSI for add, rule id for delete */
1308 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1312 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1314 struct i40e_aqc_add_delete_mirror_rule_completion {
1316 __le16 rule_id; /* only used on add */
1317 __le16 mirror_rules_used;
1318 __le16 mirror_rules_free;
1323 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1327 /* PFC Ignore (direct 0x0301)
1328 * the command and response use the same descriptor structure
1330 struct i40e_aqc_pfc_ignore {
1332 u8 command_flags; /* unused on response */
1333 #define I40E_AQC_PFC_IGNORE_SET 0x80
1334 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1338 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1340 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1341 * with no parameters
1344 /* TX scheduler 0x04xx */
1346 /* Almost all the indirect commands use
1347 * this generic struct to pass the SEID in param0
1349 struct i40e_aqc_tx_sched_ind {
1356 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1358 /* Several commands respond with a set of queue set handles */
1359 struct i40e_aqc_qs_handles_resp {
1360 __le16 qs_handles[8];
1363 /* Configure VSI BW limits (direct 0x0400) */
1364 struct i40e_aqc_configure_vsi_bw_limit {
1369 u8 max_credit; /* 0-3, limit = 2^max */
1373 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1375 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1376 * responds with i40e_aqc_qs_handles_resp
1378 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1381 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1383 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1384 __le16 tc_bw_max[2];
1388 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1390 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1391 * responds with i40e_aqc_qs_handles_resp
1393 struct i40e_aqc_configure_vsi_tc_bw_data {
1396 u8 tc_bw_credits[8];
1398 __le16 qs_handles[8];
1401 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1403 /* Query vsi bw configuration (indirect 0x0408) */
1404 struct i40e_aqc_query_vsi_bw_config_resp {
1406 u8 tc_suspended_bits;
1408 __le16 qs_handles[8];
1410 __le16 port_bw_limit;
1412 u8 max_bw; /* 0-3, limit = 2^max */
1416 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1418 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1419 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1422 u8 share_credits[8];
1425 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1426 __le16 tc_bw_max[2];
1429 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1431 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1432 struct i40e_aqc_configure_switching_comp_bw_limit {
1437 u8 max_bw; /* 0-3, limit = 2^max */
1441 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1443 /* Enable Physical Port ETS (indirect 0x0413)
1444 * Modify Physical Port ETS (indirect 0x0414)
1445 * Disable Physical Port ETS (indirect 0x0415)
1447 struct i40e_aqc_configure_switching_comp_ets_data {
1451 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1452 u8 tc_strict_priority_flags;
1454 u8 tc_bw_share_credits[8];
1458 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1460 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1461 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1464 __le16 tc_bw_credit[8];
1466 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1467 __le16 tc_bw_max[2];
1471 I40E_CHECK_STRUCT_LEN(0x40,
1472 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1474 /* Configure Switching Component Bandwidth Allocation per Tc
1477 struct i40e_aqc_configure_switching_comp_bw_config_data {
1480 u8 absolute_credits; /* bool */
1481 u8 tc_bw_share_credits[8];
1485 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1487 /* Query Switching Component Configuration (indirect 0x0418) */
1488 struct i40e_aqc_query_switching_comp_ets_config_resp {
1491 __le16 port_bw_limit;
1493 u8 tc_bw_max; /* 0-3, limit = 2^max */
1497 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1499 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1500 struct i40e_aqc_query_port_ets_config_resp {
1504 u8 tc_strict_priority_bits;
1506 u8 tc_bw_share_credits[8];
1507 __le16 tc_bw_limits[8];
1509 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1510 __le16 tc_bw_max[2];
1514 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1516 /* Query Switching Component Bandwidth Allocation per Traffic Type
1519 struct i40e_aqc_query_switching_comp_bw_config_resp {
1522 u8 absolute_credits_enable; /* bool */
1523 u8 tc_bw_share_credits[8];
1524 __le16 tc_bw_limits[8];
1526 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1527 __le16 tc_bw_max[2];
1530 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1532 /* Suspend/resume port TX traffic
1533 * (direct 0x041B and 0x041C) uses the generic SEID struct
1536 /* Configure partition BW
1539 struct i40e_aqc_configure_partition_bw_data {
1540 __le16 pf_valid_bits;
1541 u8 min_bw[16]; /* guaranteed bandwidth */
1542 u8 max_bw[16]; /* bandwidth limit */
1545 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1547 /* Get and set the active HMC resource profile and status.
1548 * (direct 0x0500) and (direct 0x0501)
1550 struct i40e_aq_get_set_hmc_resource_profile {
1556 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1558 enum i40e_aq_hmc_profile {
1559 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1560 I40E_HMC_PROFILE_DEFAULT = 1,
1561 I40E_HMC_PROFILE_FAVOR_VF = 2,
1562 I40E_HMC_PROFILE_EQUAL = 3,
1565 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1566 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1568 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1570 /* set in param0 for get phy abilities to report qualified modules */
1571 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1572 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1574 enum i40e_aq_phy_type {
1575 I40E_PHY_TYPE_SGMII = 0x0,
1576 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1577 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1578 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1579 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1580 I40E_PHY_TYPE_XAUI = 0x5,
1581 I40E_PHY_TYPE_XFI = 0x6,
1582 I40E_PHY_TYPE_SFI = 0x7,
1583 I40E_PHY_TYPE_XLAUI = 0x8,
1584 I40E_PHY_TYPE_XLPPI = 0x9,
1585 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1586 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1587 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1588 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1589 I40E_PHY_TYPE_100BASE_TX = 0x11,
1590 I40E_PHY_TYPE_1000BASE_T = 0x12,
1591 I40E_PHY_TYPE_10GBASE_T = 0x13,
1592 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1593 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1594 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1595 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1596 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1597 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1598 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1599 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1600 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1601 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1602 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1606 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1607 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1608 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1609 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1610 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1612 enum i40e_aq_link_speed {
1613 I40E_LINK_SPEED_UNKNOWN = 0,
1614 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1615 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1616 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1617 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1618 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1621 struct i40e_aqc_module_desc {
1629 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1631 struct i40e_aq_get_phy_abilities_resp {
1632 __le32 phy_type; /* bitmap using the above enum for offsets */
1633 u8 link_speed; /* bitmap using the above enum bit patterns */
1635 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1636 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1637 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1638 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1639 #define I40E_AQ_PHY_AN_ENABLED 0x10
1640 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1641 __le16 eee_capability;
1642 #define I40E_AQ_EEE_100BASE_TX 0x0002
1643 #define I40E_AQ_EEE_1000BASE_T 0x0004
1644 #define I40E_AQ_EEE_10GBASE_T 0x0008
1645 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1646 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1647 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1650 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1654 u8 qualified_module_count;
1655 #define I40E_AQ_PHY_MAX_QMS 16
1656 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1659 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1661 /* Set PHY Config (direct 0x0601) */
1662 struct i40e_aq_set_phy_config { /* same bits as above in all */
1666 /* bits 0-2 use the values from get_phy_abilities_resp */
1667 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1668 #define I40E_AQ_PHY_ENABLE_AN 0x10
1669 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1670 __le16 eee_capability;
1676 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1678 /* Set MAC Config command data structure (direct 0x0603) */
1679 struct i40e_aq_set_mac_config {
1680 __le16 max_frame_size;
1682 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1683 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1684 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1685 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1691 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1692 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1693 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1694 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1695 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1696 u8 tx_timer_priority; /* bitmap */
1697 __le16 tx_timer_value;
1698 __le16 fc_refresh_threshold;
1702 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1704 /* Restart Auto-Negotiation (direct 0x605) */
1705 struct i40e_aqc_set_link_restart_an {
1707 #define I40E_AQ_PHY_RESTART_AN 0x02
1708 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1712 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1714 /* Get Link Status cmd & response data structure (direct 0x0607) */
1715 struct i40e_aqc_get_link_status {
1716 __le16 command_flags; /* only field set on command */
1717 #define I40E_AQ_LSE_MASK 0x3
1718 #define I40E_AQ_LSE_NOP 0x0
1719 #define I40E_AQ_LSE_DISABLE 0x2
1720 #define I40E_AQ_LSE_ENABLE 0x3
1721 /* only response uses this flag */
1722 #define I40E_AQ_LSE_IS_ENABLED 0x1
1723 u8 phy_type; /* i40e_aq_phy_type */
1724 u8 link_speed; /* i40e_aq_link_speed */
1726 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1727 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1728 #define I40E_AQ_LINK_FAULT 0x02
1729 #define I40E_AQ_LINK_FAULT_TX 0x04
1730 #define I40E_AQ_LINK_FAULT_RX 0x08
1731 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1732 #define I40E_AQ_LINK_UP_PORT 0x20
1733 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1734 #define I40E_AQ_SIGNAL_DETECT 0x80
1736 #define I40E_AQ_AN_COMPLETED 0x01
1737 #define I40E_AQ_LP_AN_ABILITY 0x02
1738 #define I40E_AQ_PD_FAULT 0x04
1739 #define I40E_AQ_FEC_EN 0x08
1740 #define I40E_AQ_PHY_LOW_POWER 0x10
1741 #define I40E_AQ_LINK_PAUSE_TX 0x20
1742 #define I40E_AQ_LINK_PAUSE_RX 0x40
1743 #define I40E_AQ_QUALIFIED_MODULE 0x80
1745 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1746 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1747 #define I40E_AQ_LINK_TX_SHIFT 0x02
1748 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1749 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1750 #define I40E_AQ_LINK_TX_DRAINED 0x01
1751 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1752 #define I40E_AQ_LINK_FORCED_40G 0x10
1753 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1754 __le16 max_frame_size;
1756 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1757 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1761 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1763 /* Set event mask command (direct 0x613) */
1764 struct i40e_aqc_set_phy_int_mask {
1767 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1768 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1769 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1770 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1771 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1772 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1773 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1774 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1775 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1779 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1781 /* Get Local AN advt register (direct 0x0614)
1782 * Set Local AN advt register (direct 0x0615)
1783 * Get Link Partner AN advt register (direct 0x0616)
1785 struct i40e_aqc_an_advt_reg {
1786 __le32 local_an_reg0;
1787 __le16 local_an_reg1;
1791 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1793 /* Set Loopback mode (0x0618) */
1794 struct i40e_aqc_set_lb_mode {
1796 #define I40E_AQ_LB_PHY_LOCAL 0x01
1797 #define I40E_AQ_LB_PHY_REMOTE 0x02
1798 #define I40E_AQ_LB_MAC_LOCAL 0x04
1802 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1804 /* Set PHY Debug command (0x0622) */
1805 struct i40e_aqc_set_phy_debug {
1807 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1808 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1809 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1810 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1811 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1812 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1813 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1814 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1818 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1820 enum i40e_aq_phy_reg_type {
1821 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1822 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1823 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1826 /* NVM Read command (indirect 0x0701)
1827 * NVM Erase commands (direct 0x0702)
1828 * NVM Update commands (indirect 0x0703)
1830 struct i40e_aqc_nvm_update {
1832 #define I40E_AQ_NVM_LAST_CMD 0x01
1833 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1841 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1843 /* NVM Config Read (indirect 0x0704) */
1844 struct i40e_aqc_nvm_config_read {
1846 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1847 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1848 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1849 __le16 element_count;
1850 __le16 element_id; /* Feature/field ID */
1851 __le16 element_id_msw; /* MSWord of field ID */
1852 __le32 address_high;
1856 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1858 /* NVM Config Write (indirect 0x0705) */
1859 struct i40e_aqc_nvm_config_write {
1861 __le16 element_count;
1863 __le32 address_high;
1867 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1869 /* Used for 0x0704 as well as for 0x0705 commands */
1870 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1871 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1872 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1873 #define I40E_AQ_ANVM_FEATURE 0
1874 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1875 struct i40e_aqc_nvm_config_data_feature {
1877 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1878 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1879 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1880 __le16 feature_options;
1881 __le16 feature_selection;
1884 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1886 struct i40e_aqc_nvm_config_data_immediate_field {
1889 __le16 field_options;
1893 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1895 /* OEM Post Update (indirect 0x0720)
1896 * no command data struct used
1898 struct i40e_aqc_nvm_oem_post_update {
1899 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1904 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1906 struct i40e_aqc_nvm_oem_post_update_buffer {
1913 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1915 /* Send to PF command (indirect 0x0801) id is only used by PF
1916 * Send to VF command (indirect 0x0802) id is only used by PF
1917 * Send to Peer PF command (indirect 0x0803)
1919 struct i40e_aqc_pf_vf_message {
1926 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1928 /* Alternate structure */
1930 /* Direct write (direct 0x0900)
1931 * Direct read (direct 0x0902)
1933 struct i40e_aqc_alternate_write {
1940 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1942 /* Indirect write (indirect 0x0901)
1943 * Indirect read (indirect 0x0903)
1946 struct i40e_aqc_alternate_ind_write {
1953 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1955 /* Done alternate write (direct 0x0904)
1958 struct i40e_aqc_alternate_write_done {
1960 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1961 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1962 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1963 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1967 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1969 /* Set OEM mode (direct 0x0905) */
1970 struct i40e_aqc_alternate_set_mode {
1972 #define I40E_AQ_ALTERNATE_MODE_NONE 0
1973 #define I40E_AQ_ALTERNATE_MODE_OEM 1
1977 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1979 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1981 /* async events 0x10xx */
1983 /* Lan Queue Overflow Event (direct, 0x1001) */
1984 struct i40e_aqc_lan_overflow {
1985 __le32 prtdcb_rupto;
1990 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1992 /* Get LLDP MIB (indirect 0x0A00) */
1993 struct i40e_aqc_lldp_get_mib {
1996 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1997 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
1998 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
1999 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2000 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2001 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2002 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2003 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2004 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2005 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2006 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2014 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2016 /* Configure LLDP MIB Change Event (direct 0x0A01)
2017 * also used for the event (with type in the command field)
2019 struct i40e_aqc_lldp_update_mib {
2021 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2022 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2028 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2030 /* Add LLDP TLV (indirect 0x0A02)
2031 * Delete LLDP TLV (indirect 0x0A04)
2033 struct i40e_aqc_lldp_add_tlv {
2034 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2042 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2044 /* Update LLDP TLV (indirect 0x0A03) */
2045 struct i40e_aqc_lldp_update_tlv {
2046 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2055 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2057 /* Stop LLDP (direct 0x0A05) */
2058 struct i40e_aqc_lldp_stop {
2060 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2061 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2065 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2067 /* Start LLDP (direct 0x0A06) */
2069 struct i40e_aqc_lldp_start {
2071 #define I40E_AQ_LLDP_AGENT_START 0x1
2075 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2077 /* Get CEE DCBX Oper Config (0x0A07)
2078 * uses the generic descriptor struct
2079 * returns below as indirect response
2082 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2083 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2084 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2085 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2086 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2087 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2089 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2090 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2091 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2092 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2093 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2094 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2095 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2096 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2097 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2098 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2099 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2100 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2102 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2103 * word boundary layout issues, which the Linux compilers silently deal
2104 * with by adding padding, making the actual struct larger than designed.
2105 * However, the FW compiler for the NIC is less lenient and complains
2106 * about the struct. Hence, the struct defined here has an extra byte in
2107 * fields reserved3 and reserved4 to directly acknowledge that padding,
2108 * and the new length is used in the length check macro.
2110 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2118 __le16 oper_app_prio;
2123 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2125 struct i40e_aqc_get_cee_dcb_cfg_resp {
2130 __le16 oper_app_prio;
2131 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2132 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2133 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2134 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2135 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2136 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2137 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2139 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2140 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2141 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2142 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2143 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2144 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2148 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2150 /* Set Local LLDP MIB (indirect 0x0A08)
2151 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2153 struct i40e_aqc_lldp_set_local_mib {
2154 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2155 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2156 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2157 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2158 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2159 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2160 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2161 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2162 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2167 __le32 address_high;
2171 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2173 /* Stop/Start LLDP Agent (direct 0x0A09)
2174 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2176 struct i40e_aqc_lldp_stop_start_specific_agent {
2177 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2178 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2179 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2184 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2186 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2187 struct i40e_aqc_add_udp_tunnel {
2191 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2192 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2193 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2197 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2199 struct i40e_aqc_add_udp_tunnel_completion {
2201 u8 filter_entry_index;
2203 #define I40E_AQC_SINGLE_PF 0x0
2204 #define I40E_AQC_MULTIPLE_PFS 0x1
2209 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2211 /* remove UDP Tunnel command (0x0B01) */
2212 struct i40e_aqc_remove_udp_tunnel {
2214 u8 index; /* 0 to 15 */
2218 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2220 struct i40e_aqc_del_udp_tunnel_completion {
2222 u8 index; /* 0 to 15 */
2224 u8 total_filters_used;
2228 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2230 struct i40e_aqc_get_set_rss_key {
2231 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2232 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2233 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2234 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2241 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2243 struct i40e_aqc_get_set_rss_key_data {
2244 u8 standard_rss_key[0x28];
2245 u8 extended_hash_key[0xc];
2248 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2250 struct i40e_aqc_get_set_rss_lut {
2251 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2252 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2253 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2254 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2256 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2257 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2258 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2260 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2261 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2268 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2270 /* tunnel key structure 0x0B10 */
2272 struct i40e_aqc_tunnel_key_structure {
2275 u8 key1_len; /* 0 to 15 */
2276 u8 key2_len; /* 0 to 15 */
2278 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2279 /* response flags */
2280 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2281 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2282 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2283 u8 network_key_index;
2284 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2285 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2286 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2287 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2291 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2293 /* OEM mode commands (direct 0xFE0x) */
2294 struct i40e_aqc_oem_param_change {
2296 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2297 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2298 #define I40E_AQ_OEM_PARAM_MAC 2
2299 __le32 param_value1;
2300 __le16 param_value2;
2304 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2306 struct i40e_aqc_oem_state_change {
2308 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2309 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2313 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2315 /* Initialize OCSD (0xFE02, direct) */
2316 struct i40e_aqc_opc_oem_ocsd_initialize {
2319 __le32 ocsd_memory_block_addr_high;
2320 __le32 ocsd_memory_block_addr_low;
2321 __le32 requested_update_interval;
2324 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2326 /* Initialize OCBB (0xFE03, direct) */
2327 struct i40e_aqc_opc_oem_ocbb_initialize {
2330 __le32 ocbb_memory_block_addr_high;
2331 __le32 ocbb_memory_block_addr_low;
2335 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2337 /* debug commands */
2339 /* get device id (0xFF00) uses the generic structure */
2341 /* set test more (0xFF01, internal) */
2343 struct i40e_acq_set_test_mode {
2345 #define I40E_AQ_TEST_PARTIAL 0
2346 #define I40E_AQ_TEST_FULL 1
2347 #define I40E_AQ_TEST_NVM 2
2350 #define I40E_AQ_TEST_OPEN 0
2351 #define I40E_AQ_TEST_CLOSE 1
2352 #define I40E_AQ_TEST_INC 2
2354 __le32 address_high;
2358 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2360 /* Debug Read Register command (0xFF03)
2361 * Debug Write Register command (0xFF04)
2363 struct i40e_aqc_debug_reg_read_write {
2370 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2372 /* Scatter/gather Reg Read (indirect 0xFF05)
2373 * Scatter/gather Reg Write (indirect 0xFF06)
2376 /* i40e_aq_desc is used for the command */
2377 struct i40e_aqc_debug_reg_sg_element_data {
2382 /* Debug Modify register (direct 0xFF07) */
2383 struct i40e_aqc_debug_modify_reg {
2390 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2392 /* dump internal data (0xFF08, indirect) */
2394 #define I40E_AQ_CLUSTER_ID_AUX 0
2395 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2396 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2397 #define I40E_AQ_CLUSTER_ID_HMC 3
2398 #define I40E_AQ_CLUSTER_ID_MAC0 4
2399 #define I40E_AQ_CLUSTER_ID_MAC1 5
2400 #define I40E_AQ_CLUSTER_ID_MAC2 6
2401 #define I40E_AQ_CLUSTER_ID_MAC3 7
2402 #define I40E_AQ_CLUSTER_ID_DCB 8
2403 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2404 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2405 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2407 struct i40e_aqc_debug_dump_internals {
2412 __le32 address_high;
2416 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2418 struct i40e_aqc_debug_modify_internals {
2420 u8 cluster_specific_params[7];
2421 __le32 address_high;
2425 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2427 #endif /* _I40E_ADMINQ_CMD_H_ */