drivers/net/ethernet/intel/i40e/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2016 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29 #include "i40e.h"
  30 #include "i40e_prototype.h"
  31
  32 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  33                                 u32 td_tag)
  34 {
  35         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  36                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  37                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  38                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  39                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  40 }
  41
  42 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  43 #define I40E_FD_CLEAN_DELAY 10
  44 /**
  45  * i40e_program_fdir_filter - Program a Flow Director filter
  46  * @fdir_data: Packet data that will be filter parameters
  47  * @raw_packet: the pre-allocated packet buffer for FDir
  48  * @pf: The PF pointer
  49  * @add: True for add/update, False for remove
  50  **/
  51 int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
  52                              struct i40e_pf *pf, bool add)
  53 {
  54         struct i40e_filter_program_desc *fdir_desc;
  55         struct i40e_tx_buffer *tx_buf, *first;
  56         struct i40e_tx_desc *tx_desc;
  57         struct i40e_ring *tx_ring;
  58         unsigned int fpt, dcc;
  59         struct i40e_vsi *vsi;
  60         struct device *dev;
  61         dma_addr_t dma;
  62         u32 td_cmd = 0;
  63         u16 delay = 0;
  64         u16 i;
  65
  66         /* find existing FDIR VSI */
  67         vsi = NULL;
  68         for (i = 0; i < pf->num_alloc_vsi; i++)
  69                 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
  70                         vsi = pf->vsi[i];
  71         if (!vsi)
  72                 return -ENOENT;
  73
  74         tx_ring = vsi->tx_rings[0];
  75         dev = tx_ring->dev;
  76
  77         /* we need two descriptors to add/del a filter and we can wait */
  78         do {
  79                 if (I40E_DESC_UNUSED(tx_ring) > 1)
  80                         break;
  81                 msleep_interruptible(1);
  82                 delay++;
  83         } while (delay < I40E_FD_CLEAN_DELAY);
  84
  85         if (!(I40E_DESC_UNUSED(tx_ring) > 1))
  86                 return -EAGAIN;
  87
  88         dma = dma_map_single(dev, raw_packet,
  89                              I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
  90         if (dma_mapping_error(dev, dma))
  91                 goto dma_fail;
  92
  93         /* grab the next descriptor */
  94         i = tx_ring->next_to_use;
  95         fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
  96         first = &tx_ring->tx_bi[i];
  97         memset(first, 0, sizeof(struct i40e_tx_buffer));
  98
  99         tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
 100
 101         fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
 102               I40E_TXD_FLTR_QW0_QINDEX_MASK;
 103
 104         fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
 105                I40E_TXD_FLTR_QW0_FLEXOFF_MASK;
 106
 107         fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
 108                I40E_TXD_FLTR_QW0_PCTYPE_MASK;
 109
 110         /* Use LAN VSI Id if not programmed by user */
 111         if (fdir_data->dest_vsi == 0)
 112                 fpt |= (pf->vsi[pf->lan_vsi]->id) <<
 113                        I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
 114         else
 115                 fpt |= ((u32)fdir_data->dest_vsi <<
 116                         I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
 117                        I40E_TXD_FLTR_QW0_DEST_VSI_MASK;
 118
 119         dcc = I40E_TX_DESC_DTYPE_FILTER_PROG;
 120
 121         if (add)
 122                 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
 123                        I40E_TXD_FLTR_QW1_PCMD_SHIFT;
 124         else
 125                 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
 126                        I40E_TXD_FLTR_QW1_PCMD_SHIFT;
 127
 128         dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) &
 129                I40E_TXD_FLTR_QW1_DEST_MASK;
 130
 131         dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
 132                I40E_TXD_FLTR_QW1_FD_STATUS_MASK;
 133
 134         if (fdir_data->cnt_index != 0) {
 135                 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
 136                 dcc |= ((u32)fdir_data->cnt_index <<
 137                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
 138                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
 139         }
 140
 141         fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt);
 142         fdir_desc->rsvd = cpu_to_le32(0);
 143         fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc);
 144         fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id);
 145
 146         /* Now program a dummy descriptor */
 147         i = tx_ring->next_to_use;
 148         tx_desc = I40E_TX_DESC(tx_ring, i);
 149         tx_buf = &tx_ring->tx_bi[i];
 150
 151         tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
 152
 153         memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
 154
 155         /* record length, and DMA address */
 156         dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
 157         dma_unmap_addr_set(tx_buf, dma, dma);
 158
 159         tx_desc->buffer_addr = cpu_to_le64(dma);
 160         td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
 161
 162         tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
 163         tx_buf->raw_buf = (void *)raw_packet;
 164
 165         tx_desc->cmd_type_offset_bsz =
 166                 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
 167
 168         /* Force memory writes to complete before letting h/w
 169          * know there are new descriptors to fetch.
 170          */
 171         wmb();
 172
 173         /* Mark the data descriptor to be watched */
 174         first->next_to_watch = tx_desc;
 175
 176         writel(tx_ring->next_to_use, tx_ring->tail);
 177         return 0;
 178
 179 dma_fail:
 180         return -1;
 181 }
 182
 183 #define IP_HEADER_OFFSET 14
 184 #define I40E_UDPIP_DUMMY_PACKET_LEN 42
 185 /**
 186  * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
 187  * @vsi: pointer to the targeted VSI
 188  * @fd_data: the flow director data required for the FDir descriptor
 189  * @add: true adds a filter, false removes it
 190  *
 191  * Returns 0 if the filters were successfully added or removed
 192  **/
 193 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
 194                                    struct i40e_fdir_filter *fd_data,
 195                                    bool add)
 196 {
 197         struct i40e_pf *pf = vsi->back;
 198         struct udphdr *udp;
 199         struct iphdr *ip;
 200         bool err = false;
 201         u8 *raw_packet;
 202         int ret;
 203         static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
 204                 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
 205                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 206
 207         raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
 208         if (!raw_packet)
 209                 return -ENOMEM;
 210         memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
 211
 212         ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
 213         udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
 214               + sizeof(struct iphdr));
 215
 216         ip->daddr = fd_data->dst_ip[0];
 217         udp->dest = fd_data->dst_port;
 218         ip->saddr = fd_data->src_ip[0];
 219         udp->source = fd_data->src_port;
 220
 221         fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 222         ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
 223         if (ret) {
 224                 dev_info(&pf->pdev->dev,
 225                          "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
 226                          fd_data->pctype, fd_data->fd_id, ret);
 227                 err = true;
 228         } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
 229                 if (add)
 230                         dev_info(&pf->pdev->dev,
 231                                  "Filter OK for PCTYPE %d loc = %d\n",
 232                                  fd_data->pctype, fd_data->fd_id);
 233                 else
 234                         dev_info(&pf->pdev->dev,
 235                                  "Filter deleted for PCTYPE %d loc = %d\n",
 236                                  fd_data->pctype, fd_data->fd_id);
 237         }
 238         if (err)
 239                 kfree(raw_packet);
 240
 241         return err ? -EOPNOTSUPP : 0;
 242 }
 243
 244 #define I40E_TCPIP_DUMMY_PACKET_LEN 54
 245 /**
 246  * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
 247  * @vsi: pointer to the targeted VSI
 248  * @fd_data: the flow director data required for the FDir descriptor
 249  * @add: true adds a filter, false removes it
 250  *
 251  * Returns 0 if the filters were successfully added or removed
 252  **/
 253 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
 254                                    struct i40e_fdir_filter *fd_data,
 255                                    bool add)
 256 {
 257         struct i40e_pf *pf = vsi->back;
 258         struct tcphdr *tcp;
 259         struct iphdr *ip;
 260         bool err = false;
 261         u8 *raw_packet;
 262         int ret;
 263         /* Dummy packet */
 264         static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
 265                 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
 266                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
 267                 0x0, 0x72, 0, 0, 0, 0};
 268
 269         raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
 270         if (!raw_packet)
 271                 return -ENOMEM;
 272         memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
 273
 274         ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
 275         tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
 276               + sizeof(struct iphdr));
 277
 278         ip->daddr = fd_data->dst_ip[0];
 279         tcp->dest = fd_data->dst_port;
 280         ip->saddr = fd_data->src_ip[0];
 281         tcp->source = fd_data->src_port;
 282
 283         if (add) {
 284                 pf->fd_tcp_rule++;
 285                 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) {
 286                         if (I40E_DEBUG_FD & pf->hw.debug_mask)
 287                                 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
 288                         pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
 289                 }
 290         } else {
 291                 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ?
 292                                   (pf->fd_tcp_rule - 1) : 0;
 293                 if (pf->fd_tcp_rule == 0) {
 294                         pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
 295                         if (I40E_DEBUG_FD & pf->hw.debug_mask)
 296                                 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n");
 297                 }
 298         }
 299
 300         fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
 301         ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
 302
 303         if (ret) {
 304                 dev_info(&pf->pdev->dev,
 305                          "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
 306                          fd_data->pctype, fd_data->fd_id, ret);
 307                 err = true;
 308         } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
 309                 if (add)
 310                         dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
 311                                  fd_data->pctype, fd_data->fd_id);
 312                 else
 313                         dev_info(&pf->pdev->dev,
 314                                  "Filter deleted for PCTYPE %d loc = %d\n",
 315                                  fd_data->pctype, fd_data->fd_id);
 316         }
 317
 318         if (err)
 319                 kfree(raw_packet);
 320
 321         return err ? -EOPNOTSUPP : 0;
 322 }
 323
 324 /**
 325  * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
 326  * a specific flow spec
 327  * @vsi: pointer to the targeted VSI
 328  * @fd_data: the flow director data required for the FDir descriptor
 329  * @add: true adds a filter, false removes it
 330  *
 331  * Returns 0 if the filters were successfully added or removed
 332  **/
 333 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
 334                                     struct i40e_fdir_filter *fd_data,
 335                                     bool add)
 336 {
 337         return -EOPNOTSUPP;
 338 }
 339
 340 #define I40E_IP_DUMMY_PACKET_LEN 34
 341 /**
 342  * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
 343  * a specific flow spec
 344  * @vsi: pointer to the targeted VSI
 345  * @fd_data: the flow director data required for the FDir descriptor
 346  * @add: true adds a filter, false removes it
 347  *
 348  * Returns 0 if the filters were successfully added or removed
 349  **/
 350 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
 351                                   struct i40e_fdir_filter *fd_data,
 352                                   bool add)
 353 {
 354         struct i40e_pf *pf = vsi->back;
 355         struct iphdr *ip;
 356         bool err = false;
 357         u8 *raw_packet;
 358         int ret;
 359         int i;
 360         static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
 361                 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
 362                 0, 0, 0, 0};
 363
 364         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
 365              i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
 366                 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
 367                 if (!raw_packet)
 368                         return -ENOMEM;
 369                 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
 370                 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
 371
 372                 ip->saddr = fd_data->src_ip[0];
 373                 ip->daddr = fd_data->dst_ip[0];
 374                 ip->protocol = 0;
 375
 376                 fd_data->pctype = i;
 377                 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
 378
 379                 if (ret) {
 380                         dev_info(&pf->pdev->dev,
 381                                  "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
 382                                  fd_data->pctype, fd_data->fd_id, ret);
 383                         err = true;
 384                 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
 385                         if (add)
 386                                 dev_info(&pf->pdev->dev,
 387                                          "Filter OK for PCTYPE %d loc = %d\n",
 388                                          fd_data->pctype, fd_data->fd_id);
 389                         else
 390                                 dev_info(&pf->pdev->dev,
 391                                          "Filter deleted for PCTYPE %d loc = %d\n",
 392                                          fd_data->pctype, fd_data->fd_id);
 393                 }
 394         }
 395
 396         if (err)
 397                 kfree(raw_packet);
 398
 399         return err ? -EOPNOTSUPP : 0;
 400 }
 401
 402 /**
 403  * i40e_add_del_fdir - Build raw packets to add/del fdir filter
 404  * @vsi: pointer to the targeted VSI
 405  * @cmd: command to get or set RX flow classification rules
 406  * @add: true adds a filter, false removes it
 407  *
 408  **/
 409 int i40e_add_del_fdir(struct i40e_vsi *vsi,
 410                       struct i40e_fdir_filter *input, bool add)
 411 {
 412         struct i40e_pf *pf = vsi->back;
 413         int ret;
 414
 415         switch (input->flow_type & ~FLOW_EXT) {
 416         case TCP_V4_FLOW:
 417                 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
 418                 break;
 419         case UDP_V4_FLOW:
 420                 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
 421                 break;
 422         case SCTP_V4_FLOW:
 423                 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
 424                 break;
 425         case IPV4_FLOW:
 426                 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
 427                 break;
 428         case IP_USER_FLOW:
 429                 switch (input->ip4_proto) {
 430                 case IPPROTO_TCP:
 431                         ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
 432                         break;
 433                 case IPPROTO_UDP:
 434                         ret = i40e_add_del_fdir_udpv4(vsi, input, add);
 435                         break;
 436                 case IPPROTO_SCTP:
 437                         ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
 438                         break;
 439                 default:
 440                         ret = i40e_add_del_fdir_ipv4(vsi, input, add);
 441                         break;
 442                 }
 443                 break;
 444         default:
 445                 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n",
 446                          input->flow_type);
 447                 ret = -EINVAL;
 448         }
 449
 450         /* The buffer allocated here is freed by the i40e_clean_tx_ring() */
 451         return ret;
 452 }
 453
 454 /**
 455  * i40e_fd_handle_status - check the Programming Status for FD
 456  * @rx_ring: the Rx ring for this descriptor
 457  * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
 458  * @prog_id: the id originally used for programming
 459  *
 460  * This is used to verify if the FD programming or invalidation
 461  * requested by SW to the HW is successful or not and take actions accordingly.
 462  **/
 463 static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
 464                                   union i40e_rx_desc *rx_desc, u8 prog_id)
 465 {
 466         struct i40e_pf *pf = rx_ring->vsi->back;
 467         struct pci_dev *pdev = pf->pdev;
 468         u32 fcnt_prog, fcnt_avail;
 469         u32 error;
 470         u64 qw;
 471
 472         qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 473         error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 474                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 475
 476         if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
 477                 pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id);
 478                 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
 479                     (I40E_DEBUG_FD & pf->hw.debug_mask))
 480                         dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
 481                                  pf->fd_inv);
 482
 483                 /* Check if the programming error is for ATR.
 484                  * If so, auto disable ATR and set a state for
 485                  * flush in progress. Next time we come here if flush is in
 486                  * progress do nothing, once flush is complete the state will
 487                  * be cleared.
 488                  */
 489                 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
 490                         return;
 491
 492                 pf->fd_add_err++;
 493                 /* store the current atr filter count */
 494                 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
 495
 496                 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) &&
 497                     (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
 498                         pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED;
 499                         set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
 500                 }
 501
 502                 /* filter programming failed most likely due to table full */
 503                 fcnt_prog = i40e_get_global_fd_count(pf);
 504                 fcnt_avail = pf->fdir_pf_filter_count;
 505                 /* If ATR is running fcnt_prog can quickly change,
 506                  * if we are very close to full, it makes sense to disable
 507                  * FD ATR/SB and then re-enable it when there is room.
 508                  */
 509                 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
 510                         if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
 511                             !(pf->auto_disable_flags &
 512                                      I40E_FLAG_FD_SB_ENABLED)) {
 513                                 if (I40E_DEBUG_FD & pf->hw.debug_mask)
 514                                         dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
 515                                 pf->auto_disable_flags |=
 516                                                         I40E_FLAG_FD_SB_ENABLED;
 517                         }
 518                 }
 519         } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
 520                 if (I40E_DEBUG_FD & pf->hw.debug_mask)
 521                         dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
 522                                  rx_desc->wb.qword0.hi_dword.fd_id);
 523         }
 524 }
 525
 526 /**
 527  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
 528  * @ring:      the ring that owns the buffer
 529  * @tx_buffer: the buffer to free
 530  **/
 531 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
 532                                             struct i40e_tx_buffer *tx_buffer)
 533 {
 534         if (tx_buffer->skb) {
 535                 dev_kfree_skb_any(tx_buffer->skb);
 536                 if (dma_unmap_len(tx_buffer, len))
 537                         dma_unmap_single(ring->dev,
 538                                          dma_unmap_addr(tx_buffer, dma),
 539                                          dma_unmap_len(tx_buffer, len),
 540                                          DMA_TO_DEVICE);
 541         } else if (dma_unmap_len(tx_buffer, len)) {
 542                 dma_unmap_page(ring->dev,
 543                                dma_unmap_addr(tx_buffer, dma),
 544                                dma_unmap_len(tx_buffer, len),
 545                                DMA_TO_DEVICE);
 546         }
 547
 548         if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
 549                 kfree(tx_buffer->raw_buf);
 550
 551         tx_buffer->next_to_watch = NULL;
 552         tx_buffer->skb = NULL;
 553         dma_unmap_len_set(tx_buffer, len, 0);
 554         /* tx_buffer must be completely set up in the transmit path */
 555 }
 556
 557 /**
 558  * i40e_clean_tx_ring - Free any empty Tx buffers
 559  * @tx_ring: ring to be cleaned
 560  **/
 561 void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
 562 {
 563         unsigned long bi_size;
 564         u16 i;
 565
 566         /* ring already cleared, nothing to do */
 567         if (!tx_ring->tx_bi)
 568                 return;
 569
 570         /* Free all the Tx ring sk_buffs */
 571         for (i = 0; i < tx_ring->count; i++)
 572                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
 573
 574         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 575         memset(tx_ring->tx_bi, 0, bi_size);
 576
 577         /* Zero out the descriptor ring */
 578         memset(tx_ring->desc, 0, tx_ring->size);
 579
 580         tx_ring->next_to_use = 0;
 581         tx_ring->next_to_clean = 0;
 582
 583         if (!tx_ring->netdev)
 584                 return;
 585
 586         /* cleanup Tx queue statistics */
 587         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 588                                                   tx_ring->queue_index));
 589 }
 590
 591 /**
 592  * i40e_free_tx_resources - Free Tx resources per queue
 593  * @tx_ring: Tx descriptor ring for a specific queue
 594  *
 595  * Free all transmit software resources
 596  **/
 597 void i40e_free_tx_resources(struct i40e_ring *tx_ring)
 598 {
 599         i40e_clean_tx_ring(tx_ring);
 600         kfree(tx_ring->tx_bi);
 601         tx_ring->tx_bi = NULL;
 602
 603         if (tx_ring->desc) {
 604                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 605                                   tx_ring->desc, tx_ring->dma);
 606                 tx_ring->desc = NULL;
 607         }
 608 }
 609
 610 /**
 611  * i40e_get_tx_pending - how many tx descriptors not processed
 612  * @tx_ring: the ring of descriptors
 613  *
 614  * Since there is no access to the ring head register
 615  * in XL710, we need to use our local copies
 616  **/
 617 u32 i40e_get_tx_pending(struct i40e_ring *ring)
 618 {
 619         u32 head, tail;
 620
 621         head = i40e_get_head(ring);
 622         tail = readl(ring->tail);
 623
 624         if (head != tail)
 625                 return (head < tail) ?
 626                         tail - head : (tail + ring->count - head);
 627
 628         return 0;
 629 }
 630
 631 #define WB_STRIDE 0x3
 632
 633 /**
 634  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 635  * @tx_ring:  tx ring to clean
 636  * @budget:   how many cleans we're allowed
 637  *
 638  * Returns true if there's any budget left (e.g. the clean is finished)
 639  **/
 640 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 641 {
 642         u16 i = tx_ring->next_to_clean;
 643         struct i40e_tx_buffer *tx_buf;
 644         struct i40e_tx_desc *tx_head;
 645         struct i40e_tx_desc *tx_desc;
 646         unsigned int total_packets = 0;
 647         unsigned int total_bytes = 0;
 648
 649         tx_buf = &tx_ring->tx_bi[i];
 650         tx_desc = I40E_TX_DESC(tx_ring, i);
 651         i -= tx_ring->count;
 652
 653         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 654
 655         do {
 656                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 657
 658                 /* if next_to_watch is not set then there is no work pending */
 659                 if (!eop_desc)
 660                         break;
 661
 662                 /* prevent any other reads prior to eop_desc */
 663                 read_barrier_depends();
 664
 665                 /* we have caught up to head, no work left to do */
 666                 if (tx_head == tx_desc)
 667                         break;
 668
 669                 /* clear next_to_watch to prevent false hangs */
 670                 tx_buf->next_to_watch = NULL;
 671
 672                 /* update the statistics for this packet */
 673                 total_bytes += tx_buf->bytecount;
 674                 total_packets += tx_buf->gso_segs;
 675
 676                 /* free the skb */
 677                 dev_consume_skb_any(tx_buf->skb);
 678
 679                 /* unmap skb header data */
 680                 dma_unmap_single(tx_ring->dev,
 681                                  dma_unmap_addr(tx_buf, dma),
 682                                  dma_unmap_len(tx_buf, len),
 683                                  DMA_TO_DEVICE);
 684
 685                 /* clear tx_buffer data */
 686                 tx_buf->skb = NULL;
 687                 dma_unmap_len_set(tx_buf, len, 0);
 688
 689                 /* unmap remaining buffers */
 690                 while (tx_desc != eop_desc) {
 691
 692                         tx_buf++;
 693                         tx_desc++;
 694                         i++;
 695                         if (unlikely(!i)) {
 696                                 i -= tx_ring->count;
 697                                 tx_buf = tx_ring->tx_bi;
 698                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 699                         }
 700
 701                         /* unmap any remaining paged data */
 702                         if (dma_unmap_len(tx_buf, len)) {
 703                                 dma_unmap_page(tx_ring->dev,
 704                                                dma_unmap_addr(tx_buf, dma),
 705                                                dma_unmap_len(tx_buf, len),
 706                                                DMA_TO_DEVICE);
 707                                 dma_unmap_len_set(tx_buf, len, 0);
 708                         }
 709                 }
 710
 711                 /* move us one more past the eop_desc for start of next pkt */
 712                 tx_buf++;
 713                 tx_desc++;
 714                 i++;
 715                 if (unlikely(!i)) {
 716                         i -= tx_ring->count;
 717                         tx_buf = tx_ring->tx_bi;
 718                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 719                 }
 720
 721                 prefetch(tx_desc);
 722
 723                 /* update budget accounting */
 724                 budget--;
 725         } while (likely(budget));
 726
 727         i += tx_ring->count;
 728         tx_ring->next_to_clean = i;
 729         u64_stats_update_begin(&tx_ring->syncp);
 730         tx_ring->stats.bytes += total_bytes;
 731         tx_ring->stats.packets += total_packets;
 732         u64_stats_update_end(&tx_ring->syncp);
 733         tx_ring->q_vector->tx.total_bytes += total_bytes;
 734         tx_ring->q_vector->tx.total_packets += total_packets;
 735
 736         if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 737                 unsigned int j = 0;
 738
 739                 /* check to see if there are < 4 descriptors
 740                  * waiting to be written back, then kick the hardware to force
 741                  * them to be written back in case we stay in NAPI.
 742                  * In this mode on X722 we do not enable Interrupt.
 743                  */
 744                 j = i40e_get_tx_pending(tx_ring);
 745
 746                 if (budget &&
 747                     ((j / (WB_STRIDE + 1)) == 0) && (j != 0) &&
 748                     !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 749                     (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 750                         tx_ring->arm_wb = true;
 751         }
 752
 753         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 754                                                       tx_ring->queue_index),
 755                                   total_packets, total_bytes);
 756
 757 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 758         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 759                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 760                 /* Make sure that anybody stopping the queue after this
 761                  * sees the new next_to_clean.
 762                  */
 763                 smp_mb();
 764                 if (__netif_subqueue_stopped(tx_ring->netdev,
 765                                              tx_ring->queue_index) &&
 766                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 767                         netif_wake_subqueue(tx_ring->netdev,
 768                                             tx_ring->queue_index);
 769                         ++tx_ring->tx_stats.restart_queue;
 770                 }
 771         }
 772
 773         return !!budget;
 774 }
 775
 776 /**
 777  * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
 778  * @vsi: the VSI we care about
 779  * @q_vector: the vector on which to enable writeback
 780  *
 781  **/
 782 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
 783                                   struct i40e_q_vector *q_vector)
 784 {
 785         u16 flags = q_vector->tx.ring[0].flags;
 786         u32 val;
 787
 788         if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
 789                 return;
 790
 791         if (q_vector->arm_wb_state)
 792                 return;
 793
 794         if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
 795                 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
 796                       I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
 797
 798                 wr32(&vsi->back->hw,
 799                      I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1),
 800                      val);
 801         } else {
 802                 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
 803                       I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
 804
 805                 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
 806         }
 807         q_vector->arm_wb_state = true;
 808 }
 809
 810 /**
 811  * i40e_force_wb - Issue SW Interrupt so HW does a wb
 812  * @vsi: the VSI we care about
 813  * @q_vector: the vector  on which to force writeback
 814  *
 815  **/
 816 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 817 {
 818         if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
 819                 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
 820                           I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
 821                           I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
 822                           I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
 823                           /* allow 00 to be written to the index */
 824
 825                 wr32(&vsi->back->hw,
 826                      I40E_PFINT_DYN_CTLN(q_vector->v_idx +
 827                                          vsi->base_vector - 1), val);
 828         } else {
 829                 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
 830                           I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
 831                           I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
 832                           I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
 833                         /* allow 00 to be written to the index */
 834
 835                 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
 836         }
 837 }
 838
 839 /**
 840  * i40e_set_new_dynamic_itr - Find new ITR level
 841  * @rc: structure containing ring performance data
 842  *
 843  * Returns true if ITR changed, false if not
 844  *
 845  * Stores a new ITR value based on packets and byte counts during
 846  * the last interrupt.  The advantage of per interrupt computation
 847  * is faster updates and more accurate ITR for the current traffic
 848  * pattern.  Constants in this function were computed based on
 849  * theoretical maximum wire speed and thresholds were set based on
 850  * testing data as well as attempting to minimize response time
 851  * while increasing bulk throughput.
 852  **/
 853 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 854 {
 855         enum i40e_latency_range new_latency_range = rc->latency_range;
 856         struct i40e_q_vector *qv = rc->ring->q_vector;
 857         u32 new_itr = rc->itr;
 858         int bytes_per_int;
 859         int usecs;
 860
 861         if (rc->total_packets == 0 || !rc->itr)
 862                 return false;
 863
 864         /* simple throttlerate management
 865          *   0-10MB/s   lowest (50000 ints/s)
 866          *  10-20MB/s   low    (20000 ints/s)
 867          *  20-1249MB/s bulk   (18000 ints/s)
 868          *  > 40000 Rx packets per second (8000 ints/s)
 869          *
 870          * The math works out because the divisor is in 10^(-6) which
 871          * turns the bytes/us input value into MB/s values, but
 872          * make sure to use usecs, as the register values written
 873          * are in 2 usec increments in the ITR registers, and make sure
 874          * to use the smoothed values that the countdown timer gives us.
 875          */
 876         usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
 877         bytes_per_int = rc->total_bytes / usecs;
 878
 879         switch (new_latency_range) {
 880         case I40E_LOWEST_LATENCY:
 881                 if (bytes_per_int > 10)
 882                         new_latency_range = I40E_LOW_LATENCY;
 883                 break;
 884         case I40E_LOW_LATENCY:
 885                 if (bytes_per_int > 20)
 886                         new_latency_range = I40E_BULK_LATENCY;
 887                 else if (bytes_per_int <= 10)
 888                         new_latency_range = I40E_LOWEST_LATENCY;
 889                 break;
 890         case I40E_BULK_LATENCY:
 891         case I40E_ULTRA_LATENCY:
 892         default:
 893                 if (bytes_per_int <= 20)
 894                         new_latency_range = I40E_LOW_LATENCY;
 895                 break;
 896         }
 897
 898         /* this is to adjust RX more aggressively when streaming small
 899          * packets.  The value of 40000 was picked as it is just beyond
 900          * what the hardware can receive per second if in low latency
 901          * mode.
 902          */
 903 #define RX_ULTRA_PACKET_RATE 40000
 904
 905         if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
 906             (&qv->rx == rc))
 907                 new_latency_range = I40E_ULTRA_LATENCY;
 908
 909         rc->latency_range = new_latency_range;
 910
 911         switch (new_latency_range) {
 912         case I40E_LOWEST_LATENCY:
 913                 new_itr = I40E_ITR_50K;
 914                 break;
 915         case I40E_LOW_LATENCY:
 916                 new_itr = I40E_ITR_20K;
 917                 break;
 918         case I40E_BULK_LATENCY:
 919                 new_itr = I40E_ITR_18K;
 920                 break;
 921         case I40E_ULTRA_LATENCY:
 922                 new_itr = I40E_ITR_8K;
 923                 break;
 924         default:
 925                 break;
 926         }
 927
 928         rc->total_bytes = 0;
 929         rc->total_packets = 0;
 930
 931         if (new_itr != rc->itr) {
 932                 rc->itr = new_itr;
 933                 return true;
 934         }
 935
 936         return false;
 937 }
 938
 939 /**
 940  * i40e_clean_programming_status - clean the programming status descriptor
 941  * @rx_ring: the rx ring that has this descriptor
 942  * @rx_desc: the rx descriptor written back by HW
 943  *
 944  * Flow director should handle FD_FILTER_STATUS to check its filter programming
 945  * status being successful or not and take actions accordingly. FCoE should
 946  * handle its context/filter programming/invalidation status and take actions.
 947  *
 948  **/
 949 static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
 950                                           union i40e_rx_desc *rx_desc)
 951 {
 952         u64 qw;
 953         u8 id;
 954
 955         qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 956         id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 957                   I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 958
 959         if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
 960                 i40e_fd_handle_status(rx_ring, rx_desc, id);
 961 #ifdef I40E_FCOE
 962         else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) ||
 963                  (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS))
 964                 i40e_fcoe_handle_status(rx_ring, rx_desc, id);
 965 #endif
 966 }
 967
 968 /**
 969  * i40e_setup_tx_descriptors - Allocate the Tx descriptors
 970  * @tx_ring: the tx ring to set up
 971  *
 972  * Return 0 on success, negative on error
 973  **/
 974 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
 975 {
 976         struct device *dev = tx_ring->dev;
 977         int bi_size;
 978
 979         if (!dev)
 980                 return -ENOMEM;
 981
 982         /* warn if we are about to overwrite the pointer */
 983         WARN_ON(tx_ring->tx_bi);
 984         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 985         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 986         if (!tx_ring->tx_bi)
 987                 goto err;
 988
 989         /* round up to nearest 4K */
 990         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 991         /* add u32 for head writeback, align after this takes care of
 992          * guaranteeing this is at least one cache line in size
 993          */
 994         tx_ring->size += sizeof(u32);
 995         tx_ring->size = ALIGN(tx_ring->size, 4096);
 996         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 997                                            &tx_ring->dma, GFP_KERNEL);
 998         if (!tx_ring->desc) {
 999                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1000                          tx_ring->size);
1001                 goto err;
1002         }
1003
1004         tx_ring->next_to_use = 0;
1005         tx_ring->next_to_clean = 0;
1006         return 0;
1007
1008 err:
1009         kfree(tx_ring->tx_bi);
1010         tx_ring->tx_bi = NULL;
1011         return -ENOMEM;
1012 }
1013
1014 /**
1015  * i40e_clean_rx_ring - Free Rx buffers
1016  * @rx_ring: ring to be cleaned
1017  **/
1018 void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1019 {
1020         struct device *dev = rx_ring->dev;
1021         struct i40e_rx_buffer *rx_bi;
1022         unsigned long bi_size;
1023         u16 i;
1024
1025         /* ring already cleared, nothing to do */
1026         if (!rx_ring->rx_bi)
1027                 return;
1028
1029         if (ring_is_ps_enabled(rx_ring)) {
1030                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
1031
1032                 rx_bi = &rx_ring->rx_bi[0];
1033                 if (rx_bi->hdr_buf) {
1034                         dma_free_coherent(dev,
1035                                           bufsz,
1036                                           rx_bi->hdr_buf,
1037                                           rx_bi->dma);
1038                         for (i = 0; i < rx_ring->count; i++) {
1039                                 rx_bi = &rx_ring->rx_bi[i];
1040                                 rx_bi->dma = 0;
1041                                 rx_bi->hdr_buf = NULL;
1042                         }
1043                 }
1044         }
1045         /* Free all the Rx ring sk_buffs */
1046         for (i = 0; i < rx_ring->count; i++) {
1047                 rx_bi = &rx_ring->rx_bi[i];
1048                 if (rx_bi->dma) {
1049                         dma_unmap_single(dev,
1050                                          rx_bi->dma,
1051                                          rx_ring->rx_buf_len,
1052                                          DMA_FROM_DEVICE);
1053                         rx_bi->dma = 0;
1054                 }
1055                 if (rx_bi->skb) {
1056                         dev_kfree_skb(rx_bi->skb);
1057                         rx_bi->skb = NULL;
1058                 }
1059                 if (rx_bi->page) {
1060                         if (rx_bi->page_dma) {
1061                                 dma_unmap_page(dev,
1062                                                rx_bi->page_dma,
1063                                                PAGE_SIZE / 2,
1064                                                DMA_FROM_DEVICE);
1065                                 rx_bi->page_dma = 0;
1066                         }
1067                         __free_page(rx_bi->page);
1068                         rx_bi->page = NULL;
1069                         rx_bi->page_offset = 0;
1070                 }
1071         }
1072
1073         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1074         memset(rx_ring->rx_bi, 0, bi_size);
1075
1076         /* Zero out the descriptor ring */
1077         memset(rx_ring->desc, 0, rx_ring->size);
1078
1079         rx_ring->next_to_clean = 0;
1080         rx_ring->next_to_use = 0;
1081 }
1082
1083 /**
1084  * i40e_free_rx_resources - Free Rx resources
1085  * @rx_ring: ring to clean the resources from
1086  *
1087  * Free all receive software resources
1088  **/
1089 void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1090 {
1091         i40e_clean_rx_ring(rx_ring);
1092         kfree(rx_ring->rx_bi);
1093         rx_ring->rx_bi = NULL;
1094
1095         if (rx_ring->desc) {
1096                 dma_free_coherent(rx_ring->dev, rx_ring->size,
1097                                   rx_ring->desc, rx_ring->dma);
1098                 rx_ring->desc = NULL;
1099         }
1100 }
1101
1102 /**
1103  * i40e_alloc_rx_headers - allocate rx header buffers
1104  * @rx_ring: ring to alloc buffers
1105  *
1106  * Allocate rx header buffers for the entire ring. As these are static,
1107  * this is only called when setting up a new ring.
1108  **/
1109 void i40e_alloc_rx_headers(struct i40e_ring *rx_ring)
1110 {
1111         struct device *dev = rx_ring->dev;
1112         struct i40e_rx_buffer *rx_bi;
1113         dma_addr_t dma;
1114         void *buffer;
1115         int buf_size;
1116         int i;
1117
1118         if (rx_ring->rx_bi[0].hdr_buf)
1119                 return;
1120         /* Make sure the buffers don't cross cache line boundaries. */
1121         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
1122         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
1123                                     &dma, GFP_KERNEL);
1124         if (!buffer)
1125                 return;
1126         for (i = 0; i < rx_ring->count; i++) {
1127                 rx_bi = &rx_ring->rx_bi[i];
1128                 rx_bi->dma = dma + (i * buf_size);
1129                 rx_bi->hdr_buf = buffer + (i * buf_size);
1130         }
1131 }
1132
1133 /**
1134  * i40e_setup_rx_descriptors - Allocate Rx descriptors
1135  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1136  *
1137  * Returns 0 on success, negative on failure
1138  **/
1139 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1140 {
1141         struct device *dev = rx_ring->dev;
1142         int bi_size;
1143
1144         /* warn if we are about to overwrite the pointer */
1145         WARN_ON(rx_ring->rx_bi);
1146         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1147         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1148         if (!rx_ring->rx_bi)
1149                 goto err;
1150
1151         u64_stats_init(&rx_ring->syncp);
1152
1153         /* Round up to nearest 4K */
1154         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
1155                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
1156                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1157         rx_ring->size = ALIGN(rx_ring->size, 4096);
1158         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1159                                            &rx_ring->dma, GFP_KERNEL);
1160
1161         if (!rx_ring->desc) {
1162                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1163                          rx_ring->size);
1164                 goto err;
1165         }
1166
1167         rx_ring->next_to_clean = 0;
1168         rx_ring->next_to_use = 0;
1169
1170         return 0;
1171 err:
1172         kfree(rx_ring->rx_bi);
1173         rx_ring->rx_bi = NULL;
1174         return -ENOMEM;
1175 }
1176
1177 /**
1178  * i40e_release_rx_desc - Store the new tail and head values
1179  * @rx_ring: ring to bump
1180  * @val: new head index
1181  **/
1182 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1183 {
1184         rx_ring->next_to_use = val;
1185         /* Force memory writes to complete before letting h/w
1186          * know there are new descriptors to fetch.  (Only
1187          * applicable for weak-ordered memory model archs,
1188          * such as IA-64).
1189          */
1190         wmb();
1191         writel(val, rx_ring->tail);
1192 }
1193
1194 /**
1195  * i40e_alloc_rx_buffers_ps - Replace used receive buffers; packet split
1196  * @rx_ring: ring to place buffers on
1197  * @cleaned_count: number of buffers to replace
1198  *
1199  * Returns true if any errors on allocation
1200  **/
1201 bool i40e_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
1202 {
1203         u16 i = rx_ring->next_to_use;
1204         union i40e_rx_desc *rx_desc;
1205         struct i40e_rx_buffer *bi;
1206
1207         /* do nothing if no valid netdev defined */
1208         if (!rx_ring->netdev || !cleaned_count)
1209                 return false;
1210
1211         while (cleaned_count--) {
1212                 rx_desc = I40E_RX_DESC(rx_ring, i);
1213                 bi = &rx_ring->rx_bi[i];
1214
1215                 if (bi->skb) /* desc is in use */
1216                         goto no_buffers;
1217                 if (!bi->page) {
1218                         bi->page = alloc_page(GFP_ATOMIC);
1219                         if (!bi->page) {
1220                                 rx_ring->rx_stats.alloc_page_failed++;
1221                                 goto no_buffers;
1222                         }
1223                 }
1224
1225                 if (!bi->page_dma) {
1226                         /* use a half page if we're re-using */
1227                         bi->page_offset ^= PAGE_SIZE / 2;
1228                         bi->page_dma = dma_map_page(rx_ring->dev,
1229                                                     bi->page,
1230                                                     bi->page_offset,
1231                                                     PAGE_SIZE / 2,
1232                                                     DMA_FROM_DEVICE);
1233                         if (dma_mapping_error(rx_ring->dev,
1234                                               bi->page_dma)) {
1235                                 rx_ring->rx_stats.alloc_page_failed++;
1236                                 bi->page_dma = 0;
1237                                 goto no_buffers;
1238                         }
1239                 }
1240
1241                 dma_sync_single_range_for_device(rx_ring->dev,
1242                                                  rx_ring->rx_bi[0].dma,
1243                                                  i * rx_ring->rx_hdr_len,
1244                                                  rx_ring->rx_hdr_len,
1245                                                  DMA_FROM_DEVICE);
1246                 /* Refresh the desc even if buffer_addrs didn't change
1247                  * because each write-back erases this info.
1248                  */
1249                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1250                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1251                 i++;
1252                 if (i == rx_ring->count)
1253                         i = 0;
1254         }
1255
1256         if (rx_ring->next_to_use != i)
1257                 i40e_release_rx_desc(rx_ring, i);
1258
1259         return false;
1260
1261 no_buffers:
1262         if (rx_ring->next_to_use != i)
1263                 i40e_release_rx_desc(rx_ring, i);
1264
1265         /* make sure to come back via polling to try again after
1266          * allocation failure
1267          */
1268         return true;
1269 }
1270
1271 /**
1272  * i40e_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
1273  * @rx_ring: ring to place buffers on
1274  * @cleaned_count: number of buffers to replace
1275  *
1276  * Returns true if any errors on allocation
1277  **/
1278 bool i40e_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
1279 {
1280         u16 i = rx_ring->next_to_use;
1281         union i40e_rx_desc *rx_desc;
1282         struct i40e_rx_buffer *bi;
1283         struct sk_buff *skb;
1284
1285         /* do nothing if no valid netdev defined */
1286         if (!rx_ring->netdev || !cleaned_count)
1287                 return false;
1288
1289         while (cleaned_count--) {
1290                 rx_desc = I40E_RX_DESC(rx_ring, i);
1291                 bi = &rx_ring->rx_bi[i];
1292                 skb = bi->skb;
1293
1294                 if (!skb) {
1295                         skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
1296                                                           rx_ring->rx_buf_len,
1297                                                           GFP_ATOMIC |
1298                                                           __GFP_NOWARN);
1299                         if (!skb) {
1300                                 rx_ring->rx_stats.alloc_buff_failed++;
1301                                 goto no_buffers;
1302                         }
1303                         /* initialize queue mapping */
1304                         skb_record_rx_queue(skb, rx_ring->queue_index);
1305                         bi->skb = skb;
1306                 }
1307
1308                 if (!bi->dma) {
1309                         bi->dma = dma_map_single(rx_ring->dev,
1310                                                  skb->data,
1311                                                  rx_ring->rx_buf_len,
1312                                                  DMA_FROM_DEVICE);
1313                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1314                                 rx_ring->rx_stats.alloc_buff_failed++;
1315                                 bi->dma = 0;
1316                                 dev_kfree_skb(bi->skb);
1317                                 bi->skb = NULL;
1318                                 goto no_buffers;
1319                         }
1320                 }
1321
1322                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1323                 rx_desc->read.hdr_addr = 0;
1324                 i++;
1325                 if (i == rx_ring->count)
1326                         i = 0;
1327         }
1328
1329         if (rx_ring->next_to_use != i)
1330                 i40e_release_rx_desc(rx_ring, i);
1331
1332         return false;
1333
1334 no_buffers:
1335         if (rx_ring->next_to_use != i)
1336                 i40e_release_rx_desc(rx_ring, i);
1337
1338         /* make sure to come back via polling to try again after
1339          * allocation failure
1340          */
1341         return true;
1342 }
1343
1344 /**
1345  * i40e_receive_skb - Send a completed packet up the stack
1346  * @rx_ring:  rx ring in play
1347  * @skb: packet to send up
1348  * @vlan_tag: vlan tag for packet
1349  **/
1350 static void i40e_receive_skb(struct i40e_ring *rx_ring,
1351                              struct sk_buff *skb, u16 vlan_tag)
1352 {
1353         struct i40e_q_vector *q_vector = rx_ring->q_vector;
1354
1355         if (vlan_tag & VLAN_VID_MASK)
1356                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
1357
1358         napi_gro_receive(&q_vector->napi, skb);
1359 }
1360
1361 /**
1362  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1363  * @vsi: the VSI we care about
1364  * @skb: skb currently being received and modified
1365  * @rx_status: status value of last descriptor in packet
1366  * @rx_error: error value of last descriptor in packet
1367  * @rx_ptype: ptype value of last descriptor in packet
1368  **/
1369 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1370                                     struct sk_buff *skb,
1371                                     u32 rx_status,
1372                                     u32 rx_error,
1373                                     u16 rx_ptype)
1374 {
1375         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
1376         bool ipv4 = false, ipv6 = false;
1377         bool ipv4_tunnel, ipv6_tunnel;
1378         __wsum rx_udp_csum;
1379         struct iphdr *iph;
1380         __sum16 csum;
1381
1382         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
1383                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
1384         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
1385                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
1386
1387         skb->ip_summed = CHECKSUM_NONE;
1388
1389         /* Rx csum enabled and ip headers found? */
1390         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1391                 return;
1392
1393         /* did the hardware decode the packet and checksum? */
1394         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1395                 return;
1396
1397         /* both known and outer_ip must be set for the below code to work */
1398         if (!(decoded.known && decoded.outer_ip))
1399                 return;
1400
1401         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1402             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
1403                 ipv4 = true;
1404         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1405                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
1406                 ipv6 = true;
1407
1408         if (ipv4 &&
1409             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1410                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1411                 goto checksum_fail;
1412
1413         /* likely incorrect csum if alternate IP extension headers found */
1414         if (ipv6 &&
1415             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1416                 /* don't increment checksum err here, non-fatal err */
1417                 return;
1418
1419         /* there was some L4 error, count error and punt packet to the stack */
1420         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1421                 goto checksum_fail;
1422
1423         /* handle packets that were not able to be checksummed due
1424          * to arrival speed, in this case the stack can compute
1425          * the csum.
1426          */
1427         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1428                 return;
1429
1430         /* If VXLAN/GENEVE traffic has an outer UDPv4 checksum we need to check
1431          * it in the driver, hardware does not do it for us.
1432          * Since L3L4P bit was set we assume a valid IHL value (>=5)
1433          * so the total length of IPv4 header is IHL*4 bytes
1434          * The UDP_0 bit *may* bet set if the *inner* header is UDP
1435          */
1436         if (!(vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE) &&
1437             (ipv4_tunnel)) {
1438                 skb->transport_header = skb->mac_header +
1439                                         sizeof(struct ethhdr) +
1440                                         (ip_hdr(skb)->ihl * 4);
1441
1442                 /* Add 4 bytes for VLAN tagged packets */
1443                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
1444                                           skb->protocol == htons(ETH_P_8021AD))
1445                                           ? VLAN_HLEN : 0;
1446
1447                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
1448                     (udp_hdr(skb)->check != 0)) {
1449                         rx_udp_csum = udp_csum(skb);
1450                         iph = ip_hdr(skb);
1451                         csum = csum_tcpudp_magic(
1452                                         iph->saddr, iph->daddr,
1453                                         (skb->len - skb_transport_offset(skb)),
1454                                         IPPROTO_UDP, rx_udp_csum);
1455
1456                         if (udp_hdr(skb)->check != csum)
1457                                 goto checksum_fail;
1458
1459                 } /* else its GRE and so no outer UDP header */
1460         }
1461
1462         skb->ip_summed = CHECKSUM_UNNECESSARY;
1463         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
1464
1465         return;
1466
1467 checksum_fail:
1468         vsi->back->hw_csum_rx_error++;
1469 }
1470
1471 /**
1472  * i40e_ptype_to_htype - get a hash type
1473  * @ptype: the ptype value from the descriptor
1474  *
1475  * Returns a hash type to be used by skb_set_hash
1476  **/
1477 static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
1478 {
1479         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1480
1481         if (!decoded.known)
1482                 return PKT_HASH_TYPE_NONE;
1483
1484         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1485             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1486                 return PKT_HASH_TYPE_L4;
1487         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1488                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1489                 return PKT_HASH_TYPE_L3;
1490         else
1491                 return PKT_HASH_TYPE_L2;
1492 }
1493
1494 /**
1495  * i40e_rx_hash - set the hash value in the skb
1496  * @ring: descriptor ring
1497  * @rx_desc: specific descriptor
1498  **/
1499 static inline void i40e_rx_hash(struct i40e_ring *ring,
1500                                 union i40e_rx_desc *rx_desc,
1501                                 struct sk_buff *skb,
1502                                 u8 rx_ptype)
1503 {
1504         u32 hash;
1505         const __le64 rss_mask  =
1506                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1507                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1508
1509         if (ring->netdev->features & NETIF_F_RXHASH)
1510                 return;
1511
1512         if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1513                 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1514                 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
1515         }
1516 }
1517
1518 /**
1519  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
1520  * @rx_ring:  rx ring to clean
1521  * @budget:   how many cleans we're allowed
1522  *
1523  * Returns true if there's any budget left (e.g. the clean is finished)
1524  **/
1525 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, const int budget)
1526 {
1527         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1528         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1529         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1530         const int current_node = numa_mem_id();
1531         struct i40e_vsi *vsi = rx_ring->vsi;
1532         u16 i = rx_ring->next_to_clean;
1533         union i40e_rx_desc *rx_desc;
1534         u32 rx_error, rx_status;
1535         bool failure = false;
1536         u8 rx_ptype;
1537         u64 qword;
1538
1539         if (budget <= 0)
1540                 return 0;
1541
1542         do {
1543                 struct i40e_rx_buffer *rx_bi;
1544                 struct sk_buff *skb;
1545                 u16 vlan_tag;
1546                 /* return some buffers to hardware, one at a time is too slow */
1547                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1548                         failure = failure ||
1549                                   i40e_alloc_rx_buffers_ps(rx_ring,
1550                                                            cleaned_count);
1551                         cleaned_count = 0;
1552                 }
1553
1554                 i = rx_ring->next_to_clean;
1555                 rx_desc = I40E_RX_DESC(rx_ring, i);
1556                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1557                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1558                         I40E_RXD_QW1_STATUS_SHIFT;
1559
1560                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1561                         break;
1562
1563                 /* This memory barrier is needed to keep us from reading
1564                  * any other fields out of the rx_desc until we know the
1565                  * DD bit is set.
1566                  */
1567                 dma_rmb();
1568                 if (i40e_rx_is_programming_status(qword)) {
1569                         i40e_clean_programming_status(rx_ring, rx_desc);
1570                         I40E_RX_INCREMENT(rx_ring, i);
1571                         continue;
1572                 }
1573                 rx_bi = &rx_ring->rx_bi[i];
1574                 skb = rx_bi->skb;
1575                 if (likely(!skb)) {
1576                         skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
1577                                                           rx_ring->rx_hdr_len,
1578                                                           GFP_ATOMIC |
1579                                                           __GFP_NOWARN);
1580                         if (!skb) {
1581                                 rx_ring->rx_stats.alloc_buff_failed++;
1582                                 failure = true;
1583                                 break;
1584                         }
1585
1586                         /* initialize queue mapping */
1587                         skb_record_rx_queue(skb, rx_ring->queue_index);
1588                         /* we are reusing so sync this buffer for CPU use */
1589                         dma_sync_single_range_for_cpu(rx_ring->dev,
1590                                                       rx_ring->rx_bi[0].dma,
1591                                                       i * rx_ring->rx_hdr_len,
1592                                                       rx_ring->rx_hdr_len,
1593                                                       DMA_FROM_DEVICE);
1594                 }
1595                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1596                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1597                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1598                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1599                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1600                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1601
1602                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1603                            I40E_RXD_QW1_ERROR_SHIFT;
1604                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1605                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1606
1607                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1608                            I40E_RXD_QW1_PTYPE_SHIFT;
1609                 prefetch(rx_bi->page);
1610                 rx_bi->skb = NULL;
1611                 cleaned_count++;
1612                 if (rx_hbo || rx_sph) {
1613                         int len;
1614
1615                         if (rx_hbo)
1616                                 len = I40E_RX_HDR_SIZE;
1617                         else
1618                                 len = rx_header_len;
1619                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1620                 } else if (skb->len == 0) {
1621                         int len;
1622
1623                         len = (rx_packet_len > skb_headlen(skb) ?
1624                                 skb_headlen(skb) : rx_packet_len);
1625                         memcpy(__skb_put(skb, len),
1626                                rx_bi->page + rx_bi->page_offset,
1627                                len);
1628                         rx_bi->page_offset += len;
1629                         rx_packet_len -= len;
1630                 }
1631
1632                 /* Get the rest of the data if this was a header split */
1633                 if (rx_packet_len) {
1634                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1635                                            rx_bi->page,
1636                                            rx_bi->page_offset,
1637                                            rx_packet_len);
1638
1639                         skb->len += rx_packet_len;
1640                         skb->data_len += rx_packet_len;
1641                         skb->truesize += rx_packet_len;
1642
1643                         if ((page_count(rx_bi->page) == 1) &&
1644                             (page_to_nid(rx_bi->page) == current_node))
1645                                 get_page(rx_bi->page);
1646                         else
1647                                 rx_bi->page = NULL;
1648
1649                         dma_unmap_page(rx_ring->dev,
1650                                        rx_bi->page_dma,
1651                                        PAGE_SIZE / 2,
1652                                        DMA_FROM_DEVICE);
1653                         rx_bi->page_dma = 0;
1654                 }
1655                 I40E_RX_INCREMENT(rx_ring, i);
1656
1657                 if (unlikely(
1658                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1659                         struct i40e_rx_buffer *next_buffer;
1660
1661                         next_buffer = &rx_ring->rx_bi[i];
1662                         next_buffer->skb = skb;
1663                         rx_ring->rx_stats.non_eop_descs++;
1664                         continue;
1665                 }
1666
1667                 /* ERR_MASK will only have valid bits if EOP set */
1668                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1669                         dev_kfree_skb_any(skb);
1670                         continue;
1671                 }
1672
1673                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1674
1675                 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1676                         i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1677                                            I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1678                                            I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1679                         rx_ring->last_rx_timestamp = jiffies;
1680                 }
1681
1682                 /* probably a little skewed due to removing CRC */
1683                 total_rx_bytes += skb->len;
1684                 total_rx_packets++;
1685
1686                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1687
1688                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1689
1690                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1691                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1692                          : 0;
1693 #ifdef I40E_FCOE
1694                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1695                         dev_kfree_skb_any(skb);
1696                         continue;
1697                 }
1698 #endif
1699                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1700
1701                 rx_desc->wb.qword1.status_error_len = 0;
1702
1703         } while (likely(total_rx_packets < budget));
1704
1705         u64_stats_update_begin(&rx_ring->syncp);
1706         rx_ring->stats.packets += total_rx_packets;
1707         rx_ring->stats.bytes += total_rx_bytes;
1708         u64_stats_update_end(&rx_ring->syncp);
1709         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1710         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1711
1712         return failure ? budget : total_rx_packets;
1713 }
1714
1715 /**
1716  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1717  * @rx_ring:  rx ring to clean
1718  * @budget:   how many cleans we're allowed
1719  *
1720  * Returns number of packets cleaned
1721  **/
1722 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1723 {
1724         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1725         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1726         struct i40e_vsi *vsi = rx_ring->vsi;
1727         union i40e_rx_desc *rx_desc;
1728         u32 rx_error, rx_status;
1729         u16 rx_packet_len;
1730         bool failure = false;
1731         u8 rx_ptype;
1732         u64 qword;
1733         u16 i;
1734
1735         do {
1736                 struct i40e_rx_buffer *rx_bi;
1737                 struct sk_buff *skb;
1738                 u16 vlan_tag;
1739                 /* return some buffers to hardware, one at a time is too slow */
1740                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1741                         failure = failure ||
1742                                   i40e_alloc_rx_buffers_1buf(rx_ring,
1743                                                              cleaned_count);
1744                         cleaned_count = 0;
1745                 }
1746
1747                 i = rx_ring->next_to_clean;
1748                 rx_desc = I40E_RX_DESC(rx_ring, i);
1749                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1750                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1751                         I40E_RXD_QW1_STATUS_SHIFT;
1752
1753                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1754                         break;
1755
1756                 /* This memory barrier is needed to keep us from reading
1757                  * any other fields out of the rx_desc until we know the
1758                  * DD bit is set.
1759                  */
1760                 dma_rmb();
1761
1762                 if (i40e_rx_is_programming_status(qword)) {
1763                         i40e_clean_programming_status(rx_ring, rx_desc);
1764                         I40E_RX_INCREMENT(rx_ring, i);
1765                         continue;
1766                 }
1767                 rx_bi = &rx_ring->rx_bi[i];
1768                 skb = rx_bi->skb;
1769                 prefetch(skb->data);
1770
1771                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1772                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1773
1774                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1775                            I40E_RXD_QW1_ERROR_SHIFT;
1776                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1777
1778                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1779                            I40E_RXD_QW1_PTYPE_SHIFT;
1780                 rx_bi->skb = NULL;
1781                 cleaned_count++;
1782
1783                 /* Get the header and possibly the whole packet
1784                  * If this is an skb from previous receive dma will be 0
1785                  */
1786                 skb_put(skb, rx_packet_len);
1787                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1788                                  DMA_FROM_DEVICE);
1789                 rx_bi->dma = 0;
1790
1791                 I40E_RX_INCREMENT(rx_ring, i);
1792
1793                 if (unlikely(
1794                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1795                         rx_ring->rx_stats.non_eop_descs++;
1796                         continue;
1797                 }
1798
1799                 /* ERR_MASK will only have valid bits if EOP set */
1800                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1801                         dev_kfree_skb_any(skb);
1802                         continue;
1803                 }
1804
1805                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1806                 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1807                         i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1808                                            I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1809                                            I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1810                         rx_ring->last_rx_timestamp = jiffies;
1811                 }
1812
1813                 /* probably a little skewed due to removing CRC */
1814                 total_rx_bytes += skb->len;
1815                 total_rx_packets++;
1816
1817                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1818
1819                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1820
1821                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1822                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1823                          : 0;
1824 #ifdef I40E_FCOE
1825                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1826                         dev_kfree_skb_any(skb);
1827                         continue;
1828                 }
1829 #endif
1830                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1831
1832                 rx_desc->wb.qword1.status_error_len = 0;
1833         } while (likely(total_rx_packets < budget));
1834
1835         u64_stats_update_begin(&rx_ring->syncp);
1836         rx_ring->stats.packets += total_rx_packets;
1837         rx_ring->stats.bytes += total_rx_bytes;
1838         u64_stats_update_end(&rx_ring->syncp);
1839         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1840         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1841
1842         return failure ? budget : total_rx_packets;
1843 }
1844
1845 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1846 {
1847         u32 val;
1848
1849         val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1850               /* Don't clear PBA because that can cause lost interrupts that
1851                * came in while we were cleaning/polling
1852                */
1853               (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1854               (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
1855
1856         return val;
1857 }
1858
1859 /* a small macro to shorten up some long lines */
1860 #define INTREG I40E_PFINT_DYN_CTLN
1861
1862 /**
1863  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1864  * @vsi: the VSI we care about
1865  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1866  *
1867  **/
1868 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1869                                           struct i40e_q_vector *q_vector)
1870 {
1871         struct i40e_hw *hw = &vsi->back->hw;
1872         bool rx = false, tx = false;
1873         u32 rxval, txval;
1874         int vector;
1875
1876         vector = (q_vector->v_idx + vsi->base_vector);
1877
1878         /* avoid dynamic calculation if in countdown mode OR if
1879          * all dynamic is disabled
1880          */
1881         rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1882
1883         if (q_vector->itr_countdown > 0 ||
1884             (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1885              !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1886                 goto enable_int;
1887         }
1888
1889         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1890                 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1891                 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1892         }
1893
1894         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1895                 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1896                 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1897         }
1898
1899         if (rx || tx) {
1900                 /* get the higher of the two ITR adjustments and
1901                  * use the same value for both ITR registers
1902                  * when in adaptive mode (Rx and/or Tx)
1903                  */
1904                 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1905
1906                 q_vector->tx.itr = q_vector->rx.itr = itr;
1907                 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1908                 tx = true;
1909                 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1910                 rx = true;
1911         }
1912
1913         /* only need to enable the interrupt once, but need
1914          * to possibly update both ITR values
1915          */
1916         if (rx) {
1917                 /* set the INTENA_MSK_MASK so that this first write
1918                  * won't actually enable the interrupt, instead just
1919                  * updating the ITR (it's bit 31 PF and VF)
1920                  */
1921                 rxval |= BIT(31);
1922                 /* don't check _DOWN because interrupt isn't being enabled */
1923                 wr32(hw, INTREG(vector - 1), rxval);
1924         }
1925
1926 enable_int:
1927         if (!test_bit(__I40E_DOWN, &vsi->state))
1928                 wr32(hw, INTREG(vector - 1), txval);
1929
1930         if (q_vector->itr_countdown)
1931                 q_vector->itr_countdown--;
1932         else
1933                 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1934 }
1935
1936 /**
1937  * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
1938  * @napi: napi struct with our devices info in it
1939  * @budget: amount of work driver is allowed to do this pass, in packets
1940  *
1941  * This function will clean all queues associated with a q_vector.
1942  *
1943  * Returns the amount of work done
1944  **/
1945 int i40e_napi_poll(struct napi_struct *napi, int budget)
1946 {
1947         struct i40e_q_vector *q_vector =
1948                                container_of(napi, struct i40e_q_vector, napi);
1949         struct i40e_vsi *vsi = q_vector->vsi;
1950         struct i40e_ring *ring;
1951         bool clean_complete = true;
1952         bool arm_wb = false;
1953         int budget_per_ring;
1954         int work_done = 0;
1955
1956         if (test_bit(__I40E_DOWN, &vsi->state)) {
1957                 napi_complete(napi);
1958                 return 0;
1959         }
1960
1961         /* Clear hung_detected bit */
1962         clear_bit(I40E_Q_VECTOR_HUNG_DETECT, &q_vector->hung_detected);
1963         /* Since the actual Tx work is minimal, we can give the Tx a larger
1964          * budget and be more aggressive about cleaning up the Tx descriptors.
1965          */
1966         i40e_for_each_ring(ring, q_vector->tx) {
1967                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1968                 arm_wb = arm_wb || ring->arm_wb;
1969                 ring->arm_wb = false;
1970         }
1971
1972         /* Handle case where we are called by netpoll with a budget of 0 */
1973         if (budget <= 0)
1974                 goto tx_only;
1975
1976         /* We attempt to distribute budget to each Rx queue fairly, but don't
1977          * allow the budget to go below 1 because that would exit polling early.
1978          */
1979         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1980
1981         i40e_for_each_ring(ring, q_vector->rx) {
1982                 int cleaned;
1983
1984                 if (ring_is_ps_enabled(ring))
1985                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1986                 else
1987                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1988
1989                 work_done += cleaned;
1990                 /* if we didn't clean as many as budgeted, we must be done */
1991                 clean_complete &= (budget_per_ring != cleaned);
1992         }
1993
1994         /* If work not completed, return budget and polling will return */
1995         if (!clean_complete) {
1996 tx_only:
1997                 if (arm_wb) {
1998                         q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1999                         i40e_enable_wb_on_itr(vsi, q_vector);
2000                 }
2001                 return budget;
2002         }
2003
2004         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
2005                 q_vector->arm_wb_state = false;
2006
2007         /* Work is done so exit the polling mode and re-enable the interrupt */
2008         napi_complete_done(napi, work_done);
2009         if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
2010                 i40e_update_enable_itr(vsi, q_vector);
2011         } else { /* Legacy mode */
2012                 struct i40e_hw *hw = &vsi->back->hw;
2013                 /* We re-enable the queue 0 cause, but
2014                  * don't worry about dynamic_enable
2015                  * because we left it on for the other
2016                  * possible interrupts during napi
2017                  */
2018                 u32 qval = rd32(hw, I40E_QINT_RQCTL(0)) |
2019                            I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2020
2021                 wr32(hw, I40E_QINT_RQCTL(0), qval);
2022                 qval = rd32(hw, I40E_QINT_TQCTL(0)) |
2023                        I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2024                 wr32(hw, I40E_QINT_TQCTL(0), qval);
2025                 i40e_irq_dynamic_enable_icr0(vsi->back, false);
2026         }
2027         return 0;
2028 }
2029
2030 /**
2031  * i40e_atr - Add a Flow Director ATR filter
2032  * @tx_ring:  ring to add programming descriptor to
2033  * @skb:      send buffer
2034  * @tx_flags: send tx flags
2035  * @protocol: wire protocol
2036  **/
2037 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2038                      u32 tx_flags, __be16 protocol)
2039 {
2040         struct i40e_filter_program_desc *fdir_desc;
2041         struct i40e_pf *pf = tx_ring->vsi->back;
2042         union {
2043                 unsigned char *network;
2044                 struct iphdr *ipv4;
2045                 struct ipv6hdr *ipv6;
2046         } hdr;
2047         struct tcphdr *th;
2048         unsigned int hlen;
2049         u32 flex_ptype, dtype_cmd;
2050         u16 i;
2051
2052         /* make sure ATR is enabled */
2053         if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
2054                 return;
2055
2056         if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
2057                 return;
2058
2059         /* if sampling is disabled do nothing */
2060         if (!tx_ring->atr_sample_rate)
2061                 return;
2062
2063         if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2064                 return;
2065
2066         if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) {
2067                 /* snag network header to get L4 type and address */
2068                 hdr.network = skb_network_header(skb);
2069
2070                 /* Currently only IPv4/IPv6 with TCP is supported
2071                  * access ihl as u8 to avoid unaligned access on ia64
2072                  */
2073                 if (tx_flags & I40E_TX_FLAGS_IPV4)
2074                         hlen = (hdr.network[0] & 0x0F) << 2;
2075                 else if (protocol == htons(ETH_P_IPV6))
2076                         hlen = sizeof(struct ipv6hdr);
2077                 else
2078                         return;
2079         } else {
2080                 hdr.network = skb_inner_network_header(skb);
2081                 hlen = skb_inner_network_header_len(skb);
2082         }
2083
2084         /* Currently only IPv4/IPv6 with TCP is supported
2085          * Note: tx_flags gets modified to reflect inner protocols in
2086          * tx_enable_csum function if encap is enabled.
2087          */
2088         if ((tx_flags & I40E_TX_FLAGS_IPV4) &&
2089             (hdr.ipv4->protocol != IPPROTO_TCP))
2090                 return;
2091         else if ((tx_flags & I40E_TX_FLAGS_IPV6) &&
2092                  (hdr.ipv6->nexthdr != IPPROTO_TCP))
2093                 return;
2094
2095         th = (struct tcphdr *)(hdr.network + hlen);
2096
2097         /* Due to lack of space, no more new filters can be programmed */
2098         if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
2099                 return;
2100         if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) &&
2101             (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) {
2102                 /* HW ATR eviction will take care of removing filters on FIN
2103                  * and RST packets.
2104                  */
2105                 if (th->fin || th->rst)
2106                         return;
2107         }
2108
2109         tx_ring->atr_count++;
2110
2111         /* sample on all syn/fin/rst packets or once every atr sample rate */
2112         if (!th->fin &&
2113             !th->syn &&
2114             !th->rst &&
2115             (tx_ring->atr_count < tx_ring->atr_sample_rate))
2116                 return;
2117
2118         tx_ring->atr_count = 0;
2119
2120         /* grab the next descriptor */
2121         i = tx_ring->next_to_use;
2122         fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2123
2124         i++;
2125         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2126
2127         flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2128                       I40E_TXD_FLTR_QW0_QINDEX_MASK;
2129         flex_ptype |= (protocol == htons(ETH_P_IP)) ?
2130                       (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2131                        I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2132                       (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2133                        I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2134
2135         flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2136
2137         dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2138
2139         dtype_cmd |= (th->fin || th->rst) ?
2140                      (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2141                       I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2142                      (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2143                       I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2144
2145         dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2146                      I40E_TXD_FLTR_QW1_DEST_SHIFT;
2147
2148         dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2149                      I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2150
2151         dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2152         if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2153                 dtype_cmd |=
2154                         ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2155                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2156                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2157         else
2158                 dtype_cmd |=
2159                         ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2160                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2161                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2162
2163         if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) &&
2164             (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)))
2165                 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2166
2167         fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2168         fdir_desc->rsvd = cpu_to_le32(0);
2169         fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2170         fdir_desc->fd_id = cpu_to_le32(0);
2171 }
2172
2173 /**
2174  * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2175  * @skb:     send buffer
2176  * @tx_ring: ring to send buffer on
2177  * @flags:   the tx flags to be set
2178  *
2179  * Checks the skb and set up correspondingly several generic transmit flags
2180  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2181  *
2182  * Returns error code indicate the frame should be dropped upon error and the
2183  * otherwise  returns 0 to indicate the flags has been set properly.
2184  **/
2185 #ifdef I40E_FCOE
2186 inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2187                                       struct i40e_ring *tx_ring,
2188                                       u32 *flags)
2189 #else
2190 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2191                                              struct i40e_ring *tx_ring,
2192                                              u32 *flags)
2193 #endif
2194 {
2195         __be16 protocol = skb->protocol;
2196         u32  tx_flags = 0;
2197
2198         if (protocol == htons(ETH_P_8021Q) &&
2199             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2200                 /* When HW VLAN acceleration is turned off by the user the
2201                  * stack sets the protocol to 8021q so that the driver
2202                  * can take any steps required to support the SW only
2203                  * VLAN handling.  In our case the driver doesn't need
2204                  * to take any further steps so just set the protocol
2205                  * to the encapsulated ethertype.
2206                  */
2207                 skb->protocol = vlan_get_protocol(skb);
2208                 goto out;
2209         }
2210
2211         /* if we have a HW VLAN tag being added, default to the HW one */
2212         if (skb_vlan_tag_present(skb)) {
2213                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2214                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2215         /* else if it is a SW VLAN, check the next protocol and store the tag */
2216         } else if (protocol == htons(ETH_P_8021Q)) {
2217                 struct vlan_hdr *vhdr, _vhdr;
2218
2219                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2220                 if (!vhdr)
2221                         return -EINVAL;
2222
2223                 protocol = vhdr->h_vlan_encapsulated_proto;
2224                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2225                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2226         }
2227
2228         if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2229                 goto out;
2230
2231         /* Insert 802.1p priority into VLAN header */
2232         if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2233             (skb->priority != TC_PRIO_CONTROL)) {
2234                 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2235                 tx_flags |= (skb->priority & 0x7) <<
2236                                 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2237                 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2238                         struct vlan_ethhdr *vhdr;
2239                         int rc;
2240
2241                         rc = skb_cow_head(skb, 0);
2242                         if (rc < 0)
2243                                 return rc;
2244                         vhdr = (struct vlan_ethhdr *)skb->data;
2245                         vhdr->h_vlan_TCI = htons(tx_flags >>
2246                                                  I40E_TX_FLAGS_VLAN_SHIFT);
2247                 } else {
2248                         tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2249                 }
2250         }
2251
2252 out:
2253         *flags = tx_flags;
2254         return 0;
2255 }
2256
2257 /**
2258  * i40e_tso - set up the tso context descriptor
2259  * @tx_ring:  ptr to the ring to send
2260  * @skb:      ptr to the skb we're sending
2261  * @hdr_len:  ptr to the size of the packet header
2262  * @cd_type_cmd_tso_mss: Quad Word 1
2263  *
2264  * Returns 0 if no TSO can happen, 1 if tso is going, or error
2265  **/
2266 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
2267                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
2268 {
2269         u32 cd_cmd, cd_tso_len, cd_mss;
2270         struct ipv6hdr *ipv6h;
2271         struct tcphdr *tcph;
2272         struct iphdr *iph;
2273         u32 l4len;
2274         int err;
2275
2276         if (skb->ip_summed != CHECKSUM_PARTIAL)
2277                 return 0;
2278
2279         if (!skb_is_gso(skb))
2280                 return 0;
2281
2282         err = skb_cow_head(skb, 0);
2283         if (err < 0)
2284                 return err;
2285
2286         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
2287         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
2288
2289         if (iph->version == 4) {
2290                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2291                 iph->tot_len = 0;
2292                 iph->check = 0;
2293                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
2294                                                  0, IPPROTO_TCP, 0);
2295         } else if (ipv6h->version == 6) {
2296                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2297                 ipv6h->payload_len = 0;
2298                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
2299                                                0, IPPROTO_TCP, 0);
2300         }
2301
2302         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
2303         *hdr_len = (skb->encapsulation
2304                     ? (skb_inner_transport_header(skb) - skb->data)
2305                     : skb_transport_offset(skb)) + l4len;
2306
2307         /* find the field values */
2308         cd_cmd = I40E_TX_CTX_DESC_TSO;
2309         cd_tso_len = skb->len - *hdr_len;
2310         cd_mss = skb_shinfo(skb)->gso_size;
2311         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2312                                 ((u64)cd_tso_len <<
2313                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2314                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
2315         return 1;
2316 }
2317
2318 /**
2319  * i40e_tsyn - set up the tsyn context descriptor
2320  * @tx_ring:  ptr to the ring to send
2321  * @skb:      ptr to the skb we're sending
2322  * @tx_flags: the collected send information
2323  * @cd_type_cmd_tso_mss: Quad Word 1
2324  *
2325  * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
2326  **/
2327 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
2328                      u32 tx_flags, u64 *cd_type_cmd_tso_mss)
2329 {
2330         struct i40e_pf *pf;
2331
2332         if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
2333                 return 0;
2334
2335         /* Tx timestamps cannot be sampled when doing TSO */
2336         if (tx_flags & I40E_TX_FLAGS_TSO)
2337                 return 0;
2338
2339         /* only timestamp the outbound packet if the user has requested it and
2340          * we are not already transmitting a packet to be timestamped
2341          */
2342         pf = i40e_netdev_to_pf(tx_ring->netdev);
2343         if (!(pf->flags & I40E_FLAG_PTP))
2344                 return 0;
2345
2346         if (pf->ptp_tx &&
2347             !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) {
2348                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2349                 pf->ptp_tx_skb = skb_get(skb);
2350         } else {
2351                 return 0;
2352         }
2353
2354         *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
2355                                 I40E_TXD_CTX_QW1_CMD_SHIFT;
2356
2357         return 1;
2358 }
2359
2360 /**
2361  * i40e_tx_enable_csum - Enable Tx checksum offloads
2362  * @skb: send buffer
2363  * @tx_flags: pointer to Tx flags currently set
2364  * @td_cmd: Tx descriptor command bits to set
2365  * @td_offset: Tx descriptor header offsets to set
2366  * @tx_ring: Tx descriptor ring
2367  * @cd_tunneling: ptr to context desc bits
2368  **/
2369 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
2370                                 u32 *td_cmd, u32 *td_offset,
2371                                 struct i40e_ring *tx_ring,
2372                                 u32 *cd_tunneling)
2373 {
2374         struct ipv6hdr *this_ipv6_hdr;
2375         unsigned int this_tcp_hdrlen;
2376         struct iphdr *this_ip_hdr;
2377         u32 network_hdr_len;
2378         u8 l4_hdr = 0;
2379         struct udphdr *oudph = NULL;
2380         struct iphdr *oiph = NULL;
2381         u32 l4_tunnel = 0;
2382
2383         if (skb->encapsulation) {
2384                 switch (ip_hdr(skb)->protocol) {
2385                 case IPPROTO_UDP:
2386                         oudph = udp_hdr(skb);
2387                         oiph = ip_hdr(skb);
2388                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
2389                         *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
2390                         break;
2391                 case IPPROTO_GRE:
2392                         l4_tunnel = I40E_TXD_CTX_GRE_TUNNELING;
2393                         break;
2394                 default:
2395                         return;
2396                 }
2397                 network_hdr_len = skb_inner_network_header_len(skb);
2398                 this_ip_hdr = inner_ip_hdr(skb);
2399                 this_ipv6_hdr = inner_ipv6_hdr(skb);
2400                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
2401
2402                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2403                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
2404                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
2405                                 ip_hdr(skb)->check = 0;
2406                         } else {
2407                                 *cd_tunneling |=
2408                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
2409                         }
2410                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
2411                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
2412                         if (*tx_flags & I40E_TX_FLAGS_TSO)
2413                                 ip_hdr(skb)->check = 0;
2414                 }
2415
2416                 /* Now set the ctx descriptor fields */
2417                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
2418                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
2419                                    l4_tunnel                             |
2420                                    ((skb_inner_network_offset(skb) -
2421                                         skb_transport_offset(skb)) >> 1) <<
2422                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
2423                 if (this_ip_hdr->version == 6) {
2424                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
2425                         *tx_flags |= I40E_TX_FLAGS_IPV6;
2426                 }
2427                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
2428                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
2429                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
2430                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
2431                                         oiph->daddr,
2432                                         (skb->len - skb_transport_offset(skb)),
2433                                         IPPROTO_UDP, 0);
2434                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
2435                 }
2436         } else {
2437                 network_hdr_len = skb_network_header_len(skb);
2438                 this_ip_hdr = ip_hdr(skb);
2439                 this_ipv6_hdr = ipv6_hdr(skb);
2440                 this_tcp_hdrlen = tcp_hdrlen(skb);
2441         }
2442
2443         /* Enable IP checksum offloads */
2444         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2445                 l4_hdr = this_ip_hdr->protocol;
2446                 /* the stack computes the IP header already, the only time we
2447                  * need the hardware to recompute it is in the case of TSO.
2448                  */
2449                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
2450                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
2451                         this_ip_hdr->check = 0;
2452                 } else {
2453                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
2454                 }
2455                 /* Now set the td_offset for IP header length */
2456                 *td_offset = (network_hdr_len >> 2) <<
2457                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2458         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
2459                 l4_hdr = this_ipv6_hdr->nexthdr;
2460                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
2461                 /* Now set the td_offset for IP header length */
2462                 *td_offset = (network_hdr_len >> 2) <<
2463                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2464         }
2465         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
2466         *td_offset |= (skb_network_offset(skb) >> 1) <<
2467                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
2468
2469         /* Enable L4 checksum offloads */
2470         switch (l4_hdr) {
2471         case IPPROTO_TCP:
2472                 /* enable checksum offloads */
2473                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
2474                 *td_offset |= (this_tcp_hdrlen >> 2) <<
2475                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2476                 break;
2477         case IPPROTO_SCTP:
2478                 /* enable SCTP checksum offload */
2479                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
2480                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
2481                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2482                 break;
2483         case IPPROTO_UDP:
2484                 /* enable UDP checksum offload */
2485                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
2486                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
2487                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2488                 break;
2489         default:
2490                 break;
2491         }
2492 }
2493
2494 /**
2495  * i40e_create_tx_ctx Build the Tx context descriptor
2496  * @tx_ring:  ring to create the descriptor on
2497  * @cd_type_cmd_tso_mss: Quad Word 1
2498  * @cd_tunneling: Quad Word 0 - bits 0-31
2499  * @cd_l2tag2: Quad Word 0 - bits 32-63
2500  **/
2501 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
2502                                const u64 cd_type_cmd_tso_mss,
2503                                const u32 cd_tunneling, const u32 cd_l2tag2)
2504 {
2505         struct i40e_tx_context_desc *context_desc;
2506         int i = tx_ring->next_to_use;
2507
2508         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
2509             !cd_tunneling && !cd_l2tag2)
2510                 return;
2511
2512         /* grab the next descriptor */
2513         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
2514
2515         i++;
2516         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2517
2518         /* cpu_to_le32 and assign to struct fields */
2519         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2520         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
2521         context_desc->rsvd = cpu_to_le16(0);
2522         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2523 }
2524
2525 /**
2526  * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
2527  * @tx_ring: the ring to be checked
2528  * @size:    the size buffer we want to assure is available
2529  *
2530  * Returns -EBUSY if a stop is needed, else 0
2531  **/
2532 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2533 {
2534         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2535         /* Memory barrier before checking head and tail */
2536         smp_mb();
2537
2538         /* Check again in a case another CPU has just made room available. */
2539         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
2540                 return -EBUSY;
2541
2542         /* A reprieve! - use start_queue because it doesn't call schedule */
2543         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2544         ++tx_ring->tx_stats.restart_queue;
2545         return 0;
2546 }
2547
2548 /**
2549  * i40e_maybe_stop_tx - 1st level check for tx stop conditions
2550  * @tx_ring: the ring to be checked
2551  * @size:    the size buffer we want to assure is available
2552  *
2553  * Returns 0 if stop is not needed
2554  **/
2555 #ifdef I40E_FCOE
2556 inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2557 #else
2558 static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2559 #endif
2560 {
2561         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
2562                 return 0;
2563         return __i40e_maybe_stop_tx(tx_ring, size);
2564 }
2565
2566 /**
2567  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
2568  * @skb:      send buffer
2569  * @tx_flags: collected send information
2570  *
2571  * Note: Our HW can't scatter-gather more than 8 fragments to build
2572  * a packet on the wire and so we need to figure out the cases where we
2573  * need to linearize the skb.
2574  **/
2575 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
2576 {
2577         struct skb_frag_struct *frag;
2578         bool linearize = false;
2579         unsigned int size = 0;
2580         u16 num_frags;
2581         u16 gso_segs;
2582
2583         num_frags = skb_shinfo(skb)->nr_frags;
2584         gso_segs = skb_shinfo(skb)->gso_segs;
2585
2586         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
2587                 u16 j = 0;
2588
2589                 if (num_frags < (I40E_MAX_BUFFER_TXD))
2590                         goto linearize_chk_done;
2591                 /* try the simple math, if we have too many frags per segment */
2592                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
2593                     I40E_MAX_BUFFER_TXD) {
2594                         linearize = true;
2595                         goto linearize_chk_done;
2596                 }
2597                 frag = &skb_shinfo(skb)->frags[0];
2598                 /* we might still have more fragments per segment */
2599                 do {
2600                         size += skb_frag_size(frag);
2601                         frag++; j++;
2602                         if ((size >= skb_shinfo(skb)->gso_size) &&
2603                             (j < I40E_MAX_BUFFER_TXD)) {
2604                                 size = (size % skb_shinfo(skb)->gso_size);
2605                                 j = (size) ? 1 : 0;
2606                         }
2607                         if (j == I40E_MAX_BUFFER_TXD) {
2608                                 linearize = true;
2609                                 break;
2610                         }
2611                         num_frags--;
2612                 } while (num_frags);
2613         } else {
2614                 if (num_frags >= I40E_MAX_BUFFER_TXD)
2615                         linearize = true;
2616         }
2617
2618 linearize_chk_done:
2619         return linearize;
2620 }
2621
2622 /**
2623  * i40e_tx_map - Build the Tx descriptor
2624  * @tx_ring:  ring to send buffer on
2625  * @skb:      send buffer
2626  * @first:    first buffer info buffer to use
2627  * @tx_flags: collected send information
2628  * @hdr_len:  size of the packet header
2629  * @td_cmd:   the command field in the descriptor
2630  * @td_offset: offset for checksum or crc
2631  **/
2632 #ifdef I40E_FCOE
2633 inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2634                         struct i40e_tx_buffer *first, u32 tx_flags,
2635                         const u8 hdr_len, u32 td_cmd, u32 td_offset)
2636 #else
2637 static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2638                                struct i40e_tx_buffer *first, u32 tx_flags,
2639                                const u8 hdr_len, u32 td_cmd, u32 td_offset)
2640 #endif
2641 {
2642         unsigned int data_len = skb->data_len;
2643         unsigned int size = skb_headlen(skb);
2644         struct skb_frag_struct *frag;
2645         struct i40e_tx_buffer *tx_bi;
2646         struct i40e_tx_desc *tx_desc;
2647         u16 i = tx_ring->next_to_use;
2648         u32 td_tag = 0;
2649         dma_addr_t dma;
2650         u16 gso_segs;
2651         u16 desc_count = 0;
2652         bool tail_bump = true;
2653         bool do_rs = false;
2654
2655         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
2656                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
2657                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
2658                          I40E_TX_FLAGS_VLAN_SHIFT;
2659         }
2660
2661         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
2662                 gso_segs = skb_shinfo(skb)->gso_segs;
2663         else
2664                 gso_segs = 1;
2665
2666         /* multiply data chunks by size of headers */
2667         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
2668         first->gso_segs = gso_segs;
2669         first->skb = skb;
2670         first->tx_flags = tx_flags;
2671
2672         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2673
2674         tx_desc = I40E_TX_DESC(tx_ring, i);
2675         tx_bi = first;
2676
2677         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2678                 if (dma_mapping_error(tx_ring->dev, dma))
2679                         goto dma_error;
2680
2681                 /* record length, and DMA address */
2682                 dma_unmap_len_set(tx_bi, len, size);
2683                 dma_unmap_addr_set(tx_bi, dma, dma);
2684
2685                 tx_desc->buffer_addr = cpu_to_le64(dma);
2686
2687                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
2688                         tx_desc->cmd_type_offset_bsz =
2689                                 build_ctob(td_cmd, td_offset,
2690                                            I40E_MAX_DATA_PER_TXD, td_tag);
2691
2692                         tx_desc++;
2693                         i++;
2694                         desc_count++;
2695
2696                         if (i == tx_ring->count) {
2697                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
2698                                 i = 0;
2699                         }
2700
2701                         dma += I40E_MAX_DATA_PER_TXD;
2702                         size -= I40E_MAX_DATA_PER_TXD;
2703
2704                         tx_desc->buffer_addr = cpu_to_le64(dma);
2705                 }
2706
2707                 if (likely(!data_len))
2708                         break;
2709
2710                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2711                                                           size, td_tag);
2712
2713                 tx_desc++;
2714                 i++;
2715                 desc_count++;
2716
2717                 if (i == tx_ring->count) {
2718                         tx_desc = I40E_TX_DESC(tx_ring, 0);
2719                         i = 0;
2720                 }
2721
2722                 size = skb_frag_size(frag);
2723                 data_len -= size;
2724
2725                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2726                                        DMA_TO_DEVICE);
2727
2728                 tx_bi = &tx_ring->tx_bi[i];
2729         }
2730
2731         /* set next_to_watch value indicating a packet is present */
2732         first->next_to_watch = tx_desc;
2733
2734         i++;
2735         if (i == tx_ring->count)
2736                 i = 0;
2737
2738         tx_ring->next_to_use = i;
2739
2740         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
2741                                                  tx_ring->queue_index),
2742                                                  first->bytecount);
2743         i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
2744
2745         /* Algorithm to optimize tail and RS bit setting:
2746          * if xmit_more is supported
2747          *      if xmit_more is true
2748          *              do not update tail and do not mark RS bit.
2749          *      if xmit_more is false and last xmit_more was false
2750          *              if every packet spanned less than 4 desc
2751          *                      then set RS bit on 4th packet and update tail
2752          *                      on every packet
2753          *              else
2754          *                      update tail and set RS bit on every packet.
2755          *      if xmit_more is false and last_xmit_more was true
2756          *              update tail and set RS bit.
2757          *
2758          * Optimization: wmb to be issued only in case of tail update.
2759          * Also optimize the Descriptor WB path for RS bit with the same
2760          * algorithm.
2761          *
2762          * Note: If there are less than 4 packets
2763          * pending and interrupts were disabled the service task will
2764          * trigger a force WB.
2765          */
2766         if (skb->xmit_more  &&
2767             !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2768                                                     tx_ring->queue_index))) {
2769                 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2770                 tail_bump = false;
2771         } else if (!skb->xmit_more &&
2772                    !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2773                                                        tx_ring->queue_index)) &&
2774                    (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
2775                    (tx_ring->packet_stride < WB_STRIDE) &&
2776                    (desc_count < WB_STRIDE)) {
2777                 tx_ring->packet_stride++;
2778         } else {
2779                 tx_ring->packet_stride = 0;
2780                 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2781                 do_rs = true;
2782         }
2783         if (do_rs)
2784                 tx_ring->packet_stride = 0;
2785
2786         tx_desc->cmd_type_offset_bsz =
2787                         build_ctob(td_cmd, td_offset, size, td_tag) |
2788                         cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
2789                                                   I40E_TX_DESC_CMD_EOP) <<
2790                                                   I40E_TXD_QW1_CMD_SHIFT);
2791
2792         /* notify HW of packet */
2793         if (!tail_bump)
2794                 prefetchw(tx_desc + 1);
2795
2796         if (tail_bump) {
2797                 /* Force memory writes to complete before letting h/w
2798                  * know there are new descriptors to fetch.  (Only
2799                  * applicable for weak-ordered memory model archs,
2800                  * such as IA-64).
2801                  */
2802                 wmb();
2803                 writel(i, tx_ring->tail);
2804         }
2805
2806         return;
2807
2808 dma_error:
2809         dev_info(tx_ring->dev, "TX DMA map failed\n");
2810
2811         /* clear dma mappings for failed tx_bi map */
2812         for (;;) {
2813                 tx_bi = &tx_ring->tx_bi[i];
2814                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2815                 if (tx_bi == first)
2816                         break;
2817                 if (i == 0)
2818                         i = tx_ring->count;
2819                 i--;
2820         }
2821
2822         tx_ring->next_to_use = i;
2823 }
2824
2825 /**
2826  * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
2827  * @skb:     send buffer
2828  * @tx_ring: ring to send buffer on
2829  *
2830  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
2831  * there is not enough descriptors available in this ring since we need at least
2832  * one descriptor.
2833  **/
2834 #ifdef I40E_FCOE
2835 inline int i40e_xmit_descriptor_count(struct sk_buff *skb,
2836                                       struct i40e_ring *tx_ring)
2837 #else
2838 static inline int i40e_xmit_descriptor_count(struct sk_buff *skb,
2839                                              struct i40e_ring *tx_ring)
2840 #endif
2841 {
2842         unsigned int f;
2843         int count = 0;
2844
2845         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2846          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2847          *       + 4 desc gap to avoid the cache line where head is,
2848          *       + 1 desc for context descriptor,
2849          * otherwise try next time
2850          */
2851         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
2852                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
2853
2854         count += TXD_USE_COUNT(skb_headlen(skb));
2855         if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2856                 tx_ring->tx_stats.tx_busy++;
2857                 return 0;
2858         }
2859         return count;
2860 }
2861
2862 /**
2863  * i40e_xmit_frame_ring - Sends buffer on Tx ring
2864  * @skb:     send buffer
2865  * @tx_ring: ring to send buffer on
2866  *
2867  * Returns NETDEV_TX_OK if sent, else an error code
2868  **/
2869 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2870                                         struct i40e_ring *tx_ring)
2871 {
2872         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2873         u32 cd_tunneling = 0, cd_l2tag2 = 0;
2874         struct i40e_tx_buffer *first;
2875         u32 td_offset = 0;
2876         u32 tx_flags = 0;
2877         __be16 protocol;
2878         u32 td_cmd = 0;
2879         u8 hdr_len = 0;
2880         int tsyn;
2881         int tso;
2882
2883         /* prefetch the data, we'll need it later */
2884         prefetch(skb->data);
2885
2886         if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
2887                 return NETDEV_TX_BUSY;
2888
2889         /* prepare the xmit flags */
2890         if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2891                 goto out_drop;
2892
2893         /* obtain protocol of skb */
2894         protocol = vlan_get_protocol(skb);
2895
2896         /* record the location of the first descriptor for this packet */
2897         first = &tx_ring->tx_bi[tx_ring->next_to_use];
2898
2899         /* setup IPv4/IPv6 offloads */
2900         if (protocol == htons(ETH_P_IP))
2901                 tx_flags |= I40E_TX_FLAGS_IPV4;
2902         else if (protocol == htons(ETH_P_IPV6))
2903                 tx_flags |= I40E_TX_FLAGS_IPV6;
2904
2905         tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss);
2906
2907         if (tso < 0)
2908                 goto out_drop;
2909         else if (tso)
2910                 tx_flags |= I40E_TX_FLAGS_TSO;
2911
2912         tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
2913
2914         if (tsyn)
2915                 tx_flags |= I40E_TX_FLAGS_TSYN;
2916
2917         if (i40e_chk_linearize(skb, tx_flags)) {
2918                 if (skb_linearize(skb))
2919                         goto out_drop;
2920                 tx_ring->tx_stats.tx_linearize++;
2921         }
2922         skb_tx_timestamp(skb);
2923
2924         /* always enable CRC insertion offload */
2925         td_cmd |= I40E_TX_DESC_CMD_ICRC;
2926
2927         /* Always offload the checksum, since it's in the data descriptor */
2928         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2929                 tx_flags |= I40E_TX_FLAGS_CSUM;
2930
2931                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2932                                     tx_ring, &cd_tunneling);
2933         }
2934
2935         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2936                            cd_tunneling, cd_l2tag2);
2937
2938         /* Add Flow Director ATR if it's enabled.
2939          *
2940          * NOTE: this must always be directly before the data descriptor.
2941          */
2942         i40e_atr(tx_ring, skb, tx_flags, protocol);
2943
2944         i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2945                     td_cmd, td_offset);
2946
2947         return NETDEV_TX_OK;
2948
2949 out_drop:
2950         dev_kfree_skb_any(skb);
2951         return NETDEV_TX_OK;
2952 }
2953
2954 /**
2955  * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2956  * @skb:    send buffer
2957  * @netdev: network interface device structure
2958  *
2959  * Returns NETDEV_TX_OK if sent, else an error code
2960  **/
2961 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2962 {
2963         struct i40e_netdev_priv *np = netdev_priv(netdev);
2964         struct i40e_vsi *vsi = np->vsi;
2965         struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
2966
2967         /* hardware can't handle really short frames, hardware padding works
2968          * beyond this point
2969          */
2970         if (skb_put_padto(skb, I40E_MIN_TX_LEN))
2971                 return NETDEV_TX_OK;
2972
2973         return i40e_xmit_frame_ring(skb, tx_ring);
2974 }