drivers/net/ethernet/intel/i40e/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2016 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29 #include "i40e.h"
  30 #include "i40e_prototype.h"
  31
  32 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  33                                 u32 td_tag)
  34 {
  35         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  36                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  37                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  38                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  39                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  40 }
  41
  42 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  43 #define I40E_FD_CLEAN_DELAY 10
  44 /**
  45  * i40e_program_fdir_filter - Program a Flow Director filter
  46  * @fdir_data: Packet data that will be filter parameters
  47  * @raw_packet: the pre-allocated packet buffer for FDir
  48  * @pf: The PF pointer
  49  * @add: True for add/update, False for remove
  50  **/
  51 int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
  52                              struct i40e_pf *pf, bool add)
  53 {
  54         struct i40e_filter_program_desc *fdir_desc;
  55         struct i40e_tx_buffer *tx_buf, *first;
  56         struct i40e_tx_desc *tx_desc;
  57         struct i40e_ring *tx_ring;
  58         unsigned int fpt, dcc;
  59         struct i40e_vsi *vsi;
  60         struct device *dev;
  61         dma_addr_t dma;
  62         u32 td_cmd = 0;
  63         u16 delay = 0;
  64         u16 i;
  65
  66         /* find existing FDIR VSI */
  67         vsi = NULL;
  68         for (i = 0; i < pf->num_alloc_vsi; i++)
  69                 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
  70                         vsi = pf->vsi[i];
  71         if (!vsi)
  72                 return -ENOENT;
  73
  74         tx_ring = vsi->tx_rings[0];
  75         dev = tx_ring->dev;
  76
  77         /* we need two descriptors to add/del a filter and we can wait */
  78         do {
  79                 if (I40E_DESC_UNUSED(tx_ring) > 1)
  80                         break;
  81                 msleep_interruptible(1);
  82                 delay++;
  83         } while (delay < I40E_FD_CLEAN_DELAY);
  84
  85         if (!(I40E_DESC_UNUSED(tx_ring) > 1))
  86                 return -EAGAIN;
  87
  88         dma = dma_map_single(dev, raw_packet,
  89                              I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
  90         if (dma_mapping_error(dev, dma))
  91                 goto dma_fail;
  92
  93         /* grab the next descriptor */
  94         i = tx_ring->next_to_use;
  95         fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
  96         first = &tx_ring->tx_bi[i];
  97         memset(first, 0, sizeof(struct i40e_tx_buffer));
  98
  99         tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
 100
 101         fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
 102               I40E_TXD_FLTR_QW0_QINDEX_MASK;
 103
 104         fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
 105                I40E_TXD_FLTR_QW0_FLEXOFF_MASK;
 106
 107         fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
 108                I40E_TXD_FLTR_QW0_PCTYPE_MASK;
 109
 110         /* Use LAN VSI Id if not programmed by user */
 111         if (fdir_data->dest_vsi == 0)
 112                 fpt |= (pf->vsi[pf->lan_vsi]->id) <<
 113                        I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
 114         else
 115                 fpt |= ((u32)fdir_data->dest_vsi <<
 116                         I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
 117                        I40E_TXD_FLTR_QW0_DEST_VSI_MASK;
 118
 119         dcc = I40E_TX_DESC_DTYPE_FILTER_PROG;
 120
 121         if (add)
 122                 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
 123                        I40E_TXD_FLTR_QW1_PCMD_SHIFT;
 124         else
 125                 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
 126                        I40E_TXD_FLTR_QW1_PCMD_SHIFT;
 127
 128         dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) &
 129                I40E_TXD_FLTR_QW1_DEST_MASK;
 130
 131         dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
 132                I40E_TXD_FLTR_QW1_FD_STATUS_MASK;
 133
 134         if (fdir_data->cnt_index != 0) {
 135                 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
 136                 dcc |= ((u32)fdir_data->cnt_index <<
 137                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
 138                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
 139         }
 140
 141         fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt);
 142         fdir_desc->rsvd = cpu_to_le32(0);
 143         fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc);
 144         fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id);
 145
 146         /* Now program a dummy descriptor */
 147         i = tx_ring->next_to_use;
 148         tx_desc = I40E_TX_DESC(tx_ring, i);
 149         tx_buf = &tx_ring->tx_bi[i];
 150
 151         tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
 152
 153         memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
 154
 155         /* record length, and DMA address */
 156         dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
 157         dma_unmap_addr_set(tx_buf, dma, dma);
 158
 159         tx_desc->buffer_addr = cpu_to_le64(dma);
 160         td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
 161
 162         tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
 163         tx_buf->raw_buf = (void *)raw_packet;
 164
 165         tx_desc->cmd_type_offset_bsz =
 166                 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
 167
 168         /* Force memory writes to complete before letting h/w
 169          * know there are new descriptors to fetch.
 170          */
 171         wmb();
 172
 173         /* Mark the data descriptor to be watched */
 174         first->next_to_watch = tx_desc;
 175
 176         writel(tx_ring->next_to_use, tx_ring->tail);
 177         return 0;
 178
 179 dma_fail:
 180         return -1;
 181 }
 182
 183 #define IP_HEADER_OFFSET 14
 184 #define I40E_UDPIP_DUMMY_PACKET_LEN 42
 185 /**
 186  * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
 187  * @vsi: pointer to the targeted VSI
 188  * @fd_data: the flow director data required for the FDir descriptor
 189  * @add: true adds a filter, false removes it
 190  *
 191  * Returns 0 if the filters were successfully added or removed
 192  **/
 193 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
 194                                    struct i40e_fdir_filter *fd_data,
 195                                    bool add)
 196 {
 197         struct i40e_pf *pf = vsi->back;
 198         struct udphdr *udp;
 199         struct iphdr *ip;
 200         bool err = false;
 201         u8 *raw_packet;
 202         int ret;
 203         static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
 204                 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
 205                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 206
 207         raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
 208         if (!raw_packet)
 209                 return -ENOMEM;
 210         memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
 211
 212         ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
 213         udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
 214               + sizeof(struct iphdr));
 215
 216         ip->daddr = fd_data->dst_ip[0];
 217         udp->dest = fd_data->dst_port;
 218         ip->saddr = fd_data->src_ip[0];
 219         udp->source = fd_data->src_port;
 220
 221         fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 222         ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
 223         if (ret) {
 224                 dev_info(&pf->pdev->dev,
 225                          "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
 226                          fd_data->pctype, fd_data->fd_id, ret);
 227                 err = true;
 228         } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
 229                 if (add)
 230                         dev_info(&pf->pdev->dev,
 231                                  "Filter OK for PCTYPE %d loc = %d\n",
 232                                  fd_data->pctype, fd_data->fd_id);
 233                 else
 234                         dev_info(&pf->pdev->dev,
 235                                  "Filter deleted for PCTYPE %d loc = %d\n",
 236                                  fd_data->pctype, fd_data->fd_id);
 237         }
 238         if (err)
 239                 kfree(raw_packet);
 240
 241         return err ? -EOPNOTSUPP : 0;
 242 }
 243
 244 #define I40E_TCPIP_DUMMY_PACKET_LEN 54
 245 /**
 246  * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
 247  * @vsi: pointer to the targeted VSI
 248  * @fd_data: the flow director data required for the FDir descriptor
 249  * @add: true adds a filter, false removes it
 250  *
 251  * Returns 0 if the filters were successfully added or removed
 252  **/
 253 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
 254                                    struct i40e_fdir_filter *fd_data,
 255                                    bool add)
 256 {
 257         struct i40e_pf *pf = vsi->back;
 258         struct tcphdr *tcp;
 259         struct iphdr *ip;
 260         bool err = false;
 261         u8 *raw_packet;
 262         int ret;
 263         /* Dummy packet */
 264         static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
 265                 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
 266                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
 267                 0x0, 0x72, 0, 0, 0, 0};
 268
 269         raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
 270         if (!raw_packet)
 271                 return -ENOMEM;
 272         memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
 273
 274         ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
 275         tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
 276               + sizeof(struct iphdr));
 277
 278         ip->daddr = fd_data->dst_ip[0];
 279         tcp->dest = fd_data->dst_port;
 280         ip->saddr = fd_data->src_ip[0];
 281         tcp->source = fd_data->src_port;
 282
 283         if (add) {
 284                 pf->fd_tcp_rule++;
 285                 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) {
 286                         if (I40E_DEBUG_FD & pf->hw.debug_mask)
 287                                 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
 288                         pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
 289                 }
 290         } else {
 291                 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ?
 292                                   (pf->fd_tcp_rule - 1) : 0;
 293                 if (pf->fd_tcp_rule == 0) {
 294                         pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
 295                         if (I40E_DEBUG_FD & pf->hw.debug_mask)
 296                                 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n");
 297                 }
 298         }
 299
 300         fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
 301         ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
 302
 303         if (ret) {
 304                 dev_info(&pf->pdev->dev,
 305                          "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
 306                          fd_data->pctype, fd_data->fd_id, ret);
 307                 err = true;
 308         } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
 309                 if (add)
 310                         dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
 311                                  fd_data->pctype, fd_data->fd_id);
 312                 else
 313                         dev_info(&pf->pdev->dev,
 314                                  "Filter deleted for PCTYPE %d loc = %d\n",
 315                                  fd_data->pctype, fd_data->fd_id);
 316         }
 317
 318         if (err)
 319                 kfree(raw_packet);
 320
 321         return err ? -EOPNOTSUPP : 0;
 322 }
 323
 324 /**
 325  * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
 326  * a specific flow spec
 327  * @vsi: pointer to the targeted VSI
 328  * @fd_data: the flow director data required for the FDir descriptor
 329  * @add: true adds a filter, false removes it
 330  *
 331  * Returns 0 if the filters were successfully added or removed
 332  **/
 333 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
 334                                     struct i40e_fdir_filter *fd_data,
 335                                     bool add)
 336 {
 337         return -EOPNOTSUPP;
 338 }
 339
 340 #define I40E_IP_DUMMY_PACKET_LEN 34
 341 /**
 342  * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
 343  * a specific flow spec
 344  * @vsi: pointer to the targeted VSI
 345  * @fd_data: the flow director data required for the FDir descriptor
 346  * @add: true adds a filter, false removes it
 347  *
 348  * Returns 0 if the filters were successfully added or removed
 349  **/
 350 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
 351                                   struct i40e_fdir_filter *fd_data,
 352                                   bool add)
 353 {
 354         struct i40e_pf *pf = vsi->back;
 355         struct iphdr *ip;
 356         bool err = false;
 357         u8 *raw_packet;
 358         int ret;
 359         int i;
 360         static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
 361                 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
 362                 0, 0, 0, 0};
 363
 364         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
 365              i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
 366                 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
 367                 if (!raw_packet)
 368                         return -ENOMEM;
 369                 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
 370                 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
 371
 372                 ip->saddr = fd_data->src_ip[0];
 373                 ip->daddr = fd_data->dst_ip[0];
 374                 ip->protocol = 0;
 375
 376                 fd_data->pctype = i;
 377                 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
 378
 379                 if (ret) {
 380                         dev_info(&pf->pdev->dev,
 381                                  "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
 382                                  fd_data->pctype, fd_data->fd_id, ret);
 383                         err = true;
 384                 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
 385                         if (add)
 386                                 dev_info(&pf->pdev->dev,
 387                                          "Filter OK for PCTYPE %d loc = %d\n",
 388                                          fd_data->pctype, fd_data->fd_id);
 389                         else
 390                                 dev_info(&pf->pdev->dev,
 391                                          "Filter deleted for PCTYPE %d loc = %d\n",
 392                                          fd_data->pctype, fd_data->fd_id);
 393                 }
 394         }
 395
 396         if (err)
 397                 kfree(raw_packet);
 398
 399         return err ? -EOPNOTSUPP : 0;
 400 }
 401
 402 /**
 403  * i40e_add_del_fdir - Build raw packets to add/del fdir filter
 404  * @vsi: pointer to the targeted VSI
 405  * @cmd: command to get or set RX flow classification rules
 406  * @add: true adds a filter, false removes it
 407  *
 408  **/
 409 int i40e_add_del_fdir(struct i40e_vsi *vsi,
 410                       struct i40e_fdir_filter *input, bool add)
 411 {
 412         struct i40e_pf *pf = vsi->back;
 413         int ret;
 414
 415         switch (input->flow_type & ~FLOW_EXT) {
 416         case TCP_V4_FLOW:
 417                 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
 418                 break;
 419         case UDP_V4_FLOW:
 420                 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
 421                 break;
 422         case SCTP_V4_FLOW:
 423                 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
 424                 break;
 425         case IPV4_FLOW:
 426                 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
 427                 break;
 428         case IP_USER_FLOW:
 429                 switch (input->ip4_proto) {
 430                 case IPPROTO_TCP:
 431                         ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
 432                         break;
 433                 case IPPROTO_UDP:
 434                         ret = i40e_add_del_fdir_udpv4(vsi, input, add);
 435                         break;
 436                 case IPPROTO_SCTP:
 437                         ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
 438                         break;
 439                 default:
 440                         ret = i40e_add_del_fdir_ipv4(vsi, input, add);
 441                         break;
 442                 }
 443                 break;
 444         default:
 445                 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n",
 446                          input->flow_type);
 447                 ret = -EINVAL;
 448         }
 449
 450         /* The buffer allocated here is freed by the i40e_clean_tx_ring() */
 451         return ret;
 452 }
 453
 454 /**
 455  * i40e_fd_handle_status - check the Programming Status for FD
 456  * @rx_ring: the Rx ring for this descriptor
 457  * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
 458  * @prog_id: the id originally used for programming
 459  *
 460  * This is used to verify if the FD programming or invalidation
 461  * requested by SW to the HW is successful or not and take actions accordingly.
 462  **/
 463 static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
 464                                   union i40e_rx_desc *rx_desc, u8 prog_id)
 465 {
 466         struct i40e_pf *pf = rx_ring->vsi->back;
 467         struct pci_dev *pdev = pf->pdev;
 468         u32 fcnt_prog, fcnt_avail;
 469         u32 error;
 470         u64 qw;
 471
 472         qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 473         error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 474                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 475
 476         if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
 477                 pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id);
 478                 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
 479                     (I40E_DEBUG_FD & pf->hw.debug_mask))
 480                         dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
 481                                  pf->fd_inv);
 482
 483                 /* Check if the programming error is for ATR.
 484                  * If so, auto disable ATR and set a state for
 485                  * flush in progress. Next time we come here if flush is in
 486                  * progress do nothing, once flush is complete the state will
 487                  * be cleared.
 488                  */
 489                 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
 490                         return;
 491
 492                 pf->fd_add_err++;
 493                 /* store the current atr filter count */
 494                 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
 495
 496                 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) &&
 497                     (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
 498                         pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED;
 499                         set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
 500                 }
 501
 502                 /* filter programming failed most likely due to table full */
 503                 fcnt_prog = i40e_get_global_fd_count(pf);
 504                 fcnt_avail = pf->fdir_pf_filter_count;
 505                 /* If ATR is running fcnt_prog can quickly change,
 506                  * if we are very close to full, it makes sense to disable
 507                  * FD ATR/SB and then re-enable it when there is room.
 508                  */
 509                 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
 510                         if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
 511                             !(pf->auto_disable_flags &
 512                                      I40E_FLAG_FD_SB_ENABLED)) {
 513                                 if (I40E_DEBUG_FD & pf->hw.debug_mask)
 514                                         dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
 515                                 pf->auto_disable_flags |=
 516                                                         I40E_FLAG_FD_SB_ENABLED;
 517                         }
 518                 }
 519         } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
 520                 if (I40E_DEBUG_FD & pf->hw.debug_mask)
 521                         dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
 522                                  rx_desc->wb.qword0.hi_dword.fd_id);
 523         }
 524 }
 525
 526 /**
 527  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
 528  * @ring:      the ring that owns the buffer
 529  * @tx_buffer: the buffer to free
 530  **/
 531 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
 532                                             struct i40e_tx_buffer *tx_buffer)
 533 {
 534         if (tx_buffer->skb) {
 535                 dev_kfree_skb_any(tx_buffer->skb);
 536                 if (dma_unmap_len(tx_buffer, len))
 537                         dma_unmap_single(ring->dev,
 538                                          dma_unmap_addr(tx_buffer, dma),
 539                                          dma_unmap_len(tx_buffer, len),
 540                                          DMA_TO_DEVICE);
 541         } else if (dma_unmap_len(tx_buffer, len)) {
 542                 dma_unmap_page(ring->dev,
 543                                dma_unmap_addr(tx_buffer, dma),
 544                                dma_unmap_len(tx_buffer, len),
 545                                DMA_TO_DEVICE);
 546         }
 547
 548         if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
 549                 kfree(tx_buffer->raw_buf);
 550
 551         tx_buffer->next_to_watch = NULL;
 552         tx_buffer->skb = NULL;
 553         dma_unmap_len_set(tx_buffer, len, 0);
 554         /* tx_buffer must be completely set up in the transmit path */
 555 }
 556
 557 /**
 558  * i40e_clean_tx_ring - Free any empty Tx buffers
 559  * @tx_ring: ring to be cleaned
 560  **/
 561 void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
 562 {
 563         unsigned long bi_size;
 564         u16 i;
 565
 566         /* ring already cleared, nothing to do */
 567         if (!tx_ring->tx_bi)
 568                 return;
 569
 570         /* Free all the Tx ring sk_buffs */
 571         for (i = 0; i < tx_ring->count; i++)
 572                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
 573
 574         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 575         memset(tx_ring->tx_bi, 0, bi_size);
 576
 577         /* Zero out the descriptor ring */
 578         memset(tx_ring->desc, 0, tx_ring->size);
 579
 580         tx_ring->next_to_use = 0;
 581         tx_ring->next_to_clean = 0;
 582
 583         if (!tx_ring->netdev)
 584                 return;
 585
 586         /* cleanup Tx queue statistics */
 587         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 588                                                   tx_ring->queue_index));
 589 }
 590
 591 /**
 592  * i40e_free_tx_resources - Free Tx resources per queue
 593  * @tx_ring: Tx descriptor ring for a specific queue
 594  *
 595  * Free all transmit software resources
 596  **/
 597 void i40e_free_tx_resources(struct i40e_ring *tx_ring)
 598 {
 599         i40e_clean_tx_ring(tx_ring);
 600         kfree(tx_ring->tx_bi);
 601         tx_ring->tx_bi = NULL;
 602
 603         if (tx_ring->desc) {
 604                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 605                                   tx_ring->desc, tx_ring->dma);
 606                 tx_ring->desc = NULL;
 607         }
 608 }
 609
 610 /**
 611  * i40e_get_tx_pending - how many tx descriptors not processed
 612  * @tx_ring: the ring of descriptors
 613  *
 614  * Since there is no access to the ring head register
 615  * in XL710, we need to use our local copies
 616  **/
 617 u32 i40e_get_tx_pending(struct i40e_ring *ring)
 618 {
 619         u32 head, tail;
 620
 621         head = i40e_get_head(ring);
 622         tail = readl(ring->tail);
 623
 624         if (head != tail)
 625                 return (head < tail) ?
 626                         tail - head : (tail + ring->count - head);
 627
 628         return 0;
 629 }
 630
 631 #define WB_STRIDE 0x3
 632
 633 /**
 634  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 635  * @tx_ring:  tx ring to clean
 636  * @budget:   how many cleans we're allowed
 637  *
 638  * Returns true if there's any budget left (e.g. the clean is finished)
 639  **/
 640 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 641 {
 642         u16 i = tx_ring->next_to_clean;
 643         struct i40e_tx_buffer *tx_buf;
 644         struct i40e_tx_desc *tx_head;
 645         struct i40e_tx_desc *tx_desc;
 646         unsigned int total_packets = 0;
 647         unsigned int total_bytes = 0;
 648
 649         tx_buf = &tx_ring->tx_bi[i];
 650         tx_desc = I40E_TX_DESC(tx_ring, i);
 651         i -= tx_ring->count;
 652
 653         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 654
 655         do {
 656                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 657
 658                 /* if next_to_watch is not set then there is no work pending */
 659                 if (!eop_desc)
 660                         break;
 661
 662                 /* prevent any other reads prior to eop_desc */
 663                 read_barrier_depends();
 664
 665                 /* we have caught up to head, no work left to do */
 666                 if (tx_head == tx_desc)
 667                         break;
 668
 669                 /* clear next_to_watch to prevent false hangs */
 670                 tx_buf->next_to_watch = NULL;
 671
 672                 /* update the statistics for this packet */
 673                 total_bytes += tx_buf->bytecount;
 674                 total_packets += tx_buf->gso_segs;
 675
 676                 /* free the skb */
 677                 dev_consume_skb_any(tx_buf->skb);
 678
 679                 /* unmap skb header data */
 680                 dma_unmap_single(tx_ring->dev,
 681                                  dma_unmap_addr(tx_buf, dma),
 682                                  dma_unmap_len(tx_buf, len),
 683                                  DMA_TO_DEVICE);
 684
 685                 /* clear tx_buffer data */
 686                 tx_buf->skb = NULL;
 687                 dma_unmap_len_set(tx_buf, len, 0);
 688
 689                 /* unmap remaining buffers */
 690                 while (tx_desc != eop_desc) {
 691
 692                         tx_buf++;
 693                         tx_desc++;
 694                         i++;
 695                         if (unlikely(!i)) {
 696                                 i -= tx_ring->count;
 697                                 tx_buf = tx_ring->tx_bi;
 698                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 699                         }
 700
 701                         /* unmap any remaining paged data */
 702                         if (dma_unmap_len(tx_buf, len)) {
 703                                 dma_unmap_page(tx_ring->dev,
 704                                                dma_unmap_addr(tx_buf, dma),
 705                                                dma_unmap_len(tx_buf, len),
 706                                                DMA_TO_DEVICE);
 707                                 dma_unmap_len_set(tx_buf, len, 0);
 708                         }
 709                 }
 710
 711                 /* move us one more past the eop_desc for start of next pkt */
 712                 tx_buf++;
 713                 tx_desc++;
 714                 i++;
 715                 if (unlikely(!i)) {
 716                         i -= tx_ring->count;
 717                         tx_buf = tx_ring->tx_bi;
 718                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 719                 }
 720
 721                 prefetch(tx_desc);
 722
 723                 /* update budget accounting */
 724                 budget--;
 725         } while (likely(budget));
 726
 727         i += tx_ring->count;
 728         tx_ring->next_to_clean = i;
 729         u64_stats_update_begin(&tx_ring->syncp);
 730         tx_ring->stats.bytes += total_bytes;
 731         tx_ring->stats.packets += total_packets;
 732         u64_stats_update_end(&tx_ring->syncp);
 733         tx_ring->q_vector->tx.total_bytes += total_bytes;
 734         tx_ring->q_vector->tx.total_packets += total_packets;
 735
 736         if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 737                 unsigned int j = 0;
 738
 739                 /* check to see if there are < 4 descriptors
 740                  * waiting to be written back, then kick the hardware to force
 741                  * them to be written back in case we stay in NAPI.
 742                  * In this mode on X722 we do not enable Interrupt.
 743                  */
 744                 j = i40e_get_tx_pending(tx_ring);
 745
 746                 if (budget &&
 747                     ((j / (WB_STRIDE + 1)) == 0) && (j != 0) &&
 748                     !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 749                     (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 750                         tx_ring->arm_wb = true;
 751         }
 752
 753         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 754                                                       tx_ring->queue_index),
 755                                   total_packets, total_bytes);
 756
 757 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 758         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 759                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 760                 /* Make sure that anybody stopping the queue after this
 761                  * sees the new next_to_clean.
 762                  */
 763                 smp_mb();
 764                 if (__netif_subqueue_stopped(tx_ring->netdev,
 765                                              tx_ring->queue_index) &&
 766                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 767                         netif_wake_subqueue(tx_ring->netdev,
 768                                             tx_ring->queue_index);
 769                         ++tx_ring->tx_stats.restart_queue;
 770                 }
 771         }
 772
 773         return !!budget;
 774 }
 775
 776 /**
 777  * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
 778  * @vsi: the VSI we care about
 779  * @q_vector: the vector on which to enable writeback
 780  *
 781  **/
 782 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
 783                                   struct i40e_q_vector *q_vector)
 784 {
 785         u16 flags = q_vector->tx.ring[0].flags;
 786         u32 val;
 787
 788         if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
 789                 return;
 790
 791         if (q_vector->arm_wb_state)
 792                 return;
 793
 794         if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
 795                 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
 796                       I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
 797
 798                 wr32(&vsi->back->hw,
 799                      I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1),
 800                      val);
 801         } else {
 802                 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
 803                       I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
 804
 805                 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
 806         }
 807         q_vector->arm_wb_state = true;
 808 }
 809
 810 /**
 811  * i40e_force_wb - Issue SW Interrupt so HW does a wb
 812  * @vsi: the VSI we care about
 813  * @q_vector: the vector  on which to force writeback
 814  *
 815  **/
 816 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 817 {
 818         if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
 819                 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
 820                           I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
 821                           I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
 822                           I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
 823                           /* allow 00 to be written to the index */
 824
 825                 wr32(&vsi->back->hw,
 826                      I40E_PFINT_DYN_CTLN(q_vector->v_idx +
 827                                          vsi->base_vector - 1), val);
 828         } else {
 829                 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
 830                           I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
 831                           I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
 832                           I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
 833                         /* allow 00 to be written to the index */
 834
 835                 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
 836         }
 837 }
 838
 839 /**
 840  * i40e_set_new_dynamic_itr - Find new ITR level
 841  * @rc: structure containing ring performance data
 842  *
 843  * Returns true if ITR changed, false if not
 844  *
 845  * Stores a new ITR value based on packets and byte counts during
 846  * the last interrupt.  The advantage of per interrupt computation
 847  * is faster updates and more accurate ITR for the current traffic
 848  * pattern.  Constants in this function were computed based on
 849  * theoretical maximum wire speed and thresholds were set based on
 850  * testing data as well as attempting to minimize response time
 851  * while increasing bulk throughput.
 852  **/
 853 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 854 {
 855         enum i40e_latency_range new_latency_range = rc->latency_range;
 856         struct i40e_q_vector *qv = rc->ring->q_vector;
 857         u32 new_itr = rc->itr;
 858         int bytes_per_int;
 859         int usecs;
 860
 861         if (rc->total_packets == 0 || !rc->itr)
 862                 return false;
 863
 864         /* simple throttlerate management
 865          *   0-10MB/s   lowest (50000 ints/s)
 866          *  10-20MB/s   low    (20000 ints/s)
 867          *  20-1249MB/s bulk   (18000 ints/s)
 868          *  > 40000 Rx packets per second (8000 ints/s)
 869          *
 870          * The math works out because the divisor is in 10^(-6) which
 871          * turns the bytes/us input value into MB/s values, but
 872          * make sure to use usecs, as the register values written
 873          * are in 2 usec increments in the ITR registers, and make sure
 874          * to use the smoothed values that the countdown timer gives us.
 875          */
 876         usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
 877         bytes_per_int = rc->total_bytes / usecs;
 878
 879         switch (new_latency_range) {
 880         case I40E_LOWEST_LATENCY:
 881                 if (bytes_per_int > 10)
 882                         new_latency_range = I40E_LOW_LATENCY;
 883                 break;
 884         case I40E_LOW_LATENCY:
 885                 if (bytes_per_int > 20)
 886                         new_latency_range = I40E_BULK_LATENCY;
 887                 else if (bytes_per_int <= 10)
 888                         new_latency_range = I40E_LOWEST_LATENCY;
 889                 break;
 890         case I40E_BULK_LATENCY:
 891         case I40E_ULTRA_LATENCY:
 892         default:
 893                 if (bytes_per_int <= 20)
 894                         new_latency_range = I40E_LOW_LATENCY;
 895                 break;
 896         }
 897
 898         /* this is to adjust RX more aggressively when streaming small
 899          * packets.  The value of 40000 was picked as it is just beyond
 900          * what the hardware can receive per second if in low latency
 901          * mode.
 902          */
 903 #define RX_ULTRA_PACKET_RATE 40000
 904
 905         if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
 906             (&qv->rx == rc))
 907                 new_latency_range = I40E_ULTRA_LATENCY;
 908
 909         rc->latency_range = new_latency_range;
 910
 911         switch (new_latency_range) {
 912         case I40E_LOWEST_LATENCY:
 913                 new_itr = I40E_ITR_50K;
 914                 break;
 915         case I40E_LOW_LATENCY:
 916                 new_itr = I40E_ITR_20K;
 917                 break;
 918         case I40E_BULK_LATENCY:
 919                 new_itr = I40E_ITR_18K;
 920                 break;
 921         case I40E_ULTRA_LATENCY:
 922                 new_itr = I40E_ITR_8K;
 923                 break;
 924         default:
 925                 break;
 926         }
 927
 928         rc->total_bytes = 0;
 929         rc->total_packets = 0;
 930
 931         if (new_itr != rc->itr) {
 932                 rc->itr = new_itr;
 933                 return true;
 934         }
 935
 936         return false;
 937 }
 938
 939 /**
 940  * i40e_clean_programming_status - clean the programming status descriptor
 941  * @rx_ring: the rx ring that has this descriptor
 942  * @rx_desc: the rx descriptor written back by HW
 943  *
 944  * Flow director should handle FD_FILTER_STATUS to check its filter programming
 945  * status being successful or not and take actions accordingly. FCoE should
 946  * handle its context/filter programming/invalidation status and take actions.
 947  *
 948  **/
 949 static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
 950                                           union i40e_rx_desc *rx_desc)
 951 {
 952         u64 qw;
 953         u8 id;
 954
 955         qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 956         id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 957                   I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 958
 959         if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
 960                 i40e_fd_handle_status(rx_ring, rx_desc, id);
 961 #ifdef I40E_FCOE
 962         else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) ||
 963                  (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS))
 964                 i40e_fcoe_handle_status(rx_ring, rx_desc, id);
 965 #endif
 966 }
 967
 968 /**
 969  * i40e_setup_tx_descriptors - Allocate the Tx descriptors
 970  * @tx_ring: the tx ring to set up
 971  *
 972  * Return 0 on success, negative on error
 973  **/
 974 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
 975 {
 976         struct device *dev = tx_ring->dev;
 977         int bi_size;
 978
 979         if (!dev)
 980                 return -ENOMEM;
 981
 982         /* warn if we are about to overwrite the pointer */
 983         WARN_ON(tx_ring->tx_bi);
 984         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 985         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 986         if (!tx_ring->tx_bi)
 987                 goto err;
 988
 989         /* round up to nearest 4K */
 990         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 991         /* add u32 for head writeback, align after this takes care of
 992          * guaranteeing this is at least one cache line in size
 993          */
 994         tx_ring->size += sizeof(u32);
 995         tx_ring->size = ALIGN(tx_ring->size, 4096);
 996         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 997                                            &tx_ring->dma, GFP_KERNEL);
 998         if (!tx_ring->desc) {
 999                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1000                          tx_ring->size);
1001                 goto err;
1002         }
1003
1004         tx_ring->next_to_use = 0;
1005         tx_ring->next_to_clean = 0;
1006         return 0;
1007
1008 err:
1009         kfree(tx_ring->tx_bi);
1010         tx_ring->tx_bi = NULL;
1011         return -ENOMEM;
1012 }
1013
1014 /**
1015  * i40e_clean_rx_ring - Free Rx buffers
1016  * @rx_ring: ring to be cleaned
1017  **/
1018 void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1019 {
1020         struct device *dev = rx_ring->dev;
1021         struct i40e_rx_buffer *rx_bi;
1022         unsigned long bi_size;
1023         u16 i;
1024
1025         /* ring already cleared, nothing to do */
1026         if (!rx_ring->rx_bi)
1027                 return;
1028
1029         if (ring_is_ps_enabled(rx_ring)) {
1030                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
1031
1032                 rx_bi = &rx_ring->rx_bi[0];
1033                 if (rx_bi->hdr_buf) {
1034                         dma_free_coherent(dev,
1035                                           bufsz,
1036                                           rx_bi->hdr_buf,
1037                                           rx_bi->dma);
1038                         for (i = 0; i < rx_ring->count; i++) {
1039                                 rx_bi = &rx_ring->rx_bi[i];
1040                                 rx_bi->dma = 0;
1041                                 rx_bi->hdr_buf = NULL;
1042                         }
1043                 }
1044         }
1045         /* Free all the Rx ring sk_buffs */
1046         for (i = 0; i < rx_ring->count; i++) {
1047                 rx_bi = &rx_ring->rx_bi[i];
1048                 if (rx_bi->dma) {
1049                         dma_unmap_single(dev,
1050                                          rx_bi->dma,
1051                                          rx_ring->rx_buf_len,
1052                                          DMA_FROM_DEVICE);
1053                         rx_bi->dma = 0;
1054                 }
1055                 if (rx_bi->skb) {
1056                         dev_kfree_skb(rx_bi->skb);
1057                         rx_bi->skb = NULL;
1058                 }
1059                 if (rx_bi->page) {
1060                         if (rx_bi->page_dma) {
1061                                 dma_unmap_page(dev,
1062                                                rx_bi->page_dma,
1063                                                PAGE_SIZE / 2,
1064                                                DMA_FROM_DEVICE);
1065                                 rx_bi->page_dma = 0;
1066                         }
1067                         __free_page(rx_bi->page);
1068                         rx_bi->page = NULL;
1069                         rx_bi->page_offset = 0;
1070                 }
1071         }
1072
1073         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1074         memset(rx_ring->rx_bi, 0, bi_size);
1075
1076         /* Zero out the descriptor ring */
1077         memset(rx_ring->desc, 0, rx_ring->size);
1078
1079         rx_ring->next_to_clean = 0;
1080         rx_ring->next_to_use = 0;
1081 }
1082
1083 /**
1084  * i40e_free_rx_resources - Free Rx resources
1085  * @rx_ring: ring to clean the resources from
1086  *
1087  * Free all receive software resources
1088  **/
1089 void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1090 {
1091         i40e_clean_rx_ring(rx_ring);
1092         kfree(rx_ring->rx_bi);
1093         rx_ring->rx_bi = NULL;
1094
1095         if (rx_ring->desc) {
1096                 dma_free_coherent(rx_ring->dev, rx_ring->size,
1097                                   rx_ring->desc, rx_ring->dma);
1098                 rx_ring->desc = NULL;
1099         }
1100 }
1101
1102 /**
1103  * i40e_alloc_rx_headers - allocate rx header buffers
1104  * @rx_ring: ring to alloc buffers
1105  *
1106  * Allocate rx header buffers for the entire ring. As these are static,
1107  * this is only called when setting up a new ring.
1108  **/
1109 void i40e_alloc_rx_headers(struct i40e_ring *rx_ring)
1110 {
1111         struct device *dev = rx_ring->dev;
1112         struct i40e_rx_buffer *rx_bi;
1113         dma_addr_t dma;
1114         void *buffer;
1115         int buf_size;
1116         int i;
1117
1118         if (rx_ring->rx_bi[0].hdr_buf)
1119                 return;
1120         /* Make sure the buffers don't cross cache line boundaries. */
1121         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
1122         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
1123                                     &dma, GFP_KERNEL);
1124         if (!buffer)
1125                 return;
1126         for (i = 0; i < rx_ring->count; i++) {
1127                 rx_bi = &rx_ring->rx_bi[i];
1128                 rx_bi->dma = dma + (i * buf_size);
1129                 rx_bi->hdr_buf = buffer + (i * buf_size);
1130         }
1131 }
1132
1133 /**
1134  * i40e_setup_rx_descriptors - Allocate Rx descriptors
1135  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1136  *
1137  * Returns 0 on success, negative on failure
1138  **/
1139 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1140 {
1141         struct device *dev = rx_ring->dev;
1142         int bi_size;
1143
1144         /* warn if we are about to overwrite the pointer */
1145         WARN_ON(rx_ring->rx_bi);
1146         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1147         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1148         if (!rx_ring->rx_bi)
1149                 goto err;
1150
1151         u64_stats_init(&rx_ring->syncp);
1152
1153         /* Round up to nearest 4K */
1154         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
1155                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
1156                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1157         rx_ring->size = ALIGN(rx_ring->size, 4096);
1158         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1159                                            &rx_ring->dma, GFP_KERNEL);
1160
1161         if (!rx_ring->desc) {
1162                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1163                          rx_ring->size);
1164                 goto err;
1165         }
1166
1167         rx_ring->next_to_clean = 0;
1168         rx_ring->next_to_use = 0;
1169
1170         return 0;
1171 err:
1172         kfree(rx_ring->rx_bi);
1173         rx_ring->rx_bi = NULL;
1174         return -ENOMEM;
1175 }
1176
1177 /**
1178  * i40e_release_rx_desc - Store the new tail and head values
1179  * @rx_ring: ring to bump
1180  * @val: new head index
1181  **/
1182 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1183 {
1184         rx_ring->next_to_use = val;
1185         /* Force memory writes to complete before letting h/w
1186          * know there are new descriptors to fetch.  (Only
1187          * applicable for weak-ordered memory model archs,
1188          * such as IA-64).
1189          */
1190         wmb();
1191         writel(val, rx_ring->tail);
1192 }
1193
1194 /**
1195  * i40e_alloc_rx_buffers_ps - Replace used receive buffers; packet split
1196  * @rx_ring: ring to place buffers on
1197  * @cleaned_count: number of buffers to replace
1198  **/
1199 void i40e_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
1200 {
1201         u16 i = rx_ring->next_to_use;
1202         union i40e_rx_desc *rx_desc;
1203         struct i40e_rx_buffer *bi;
1204
1205         /* do nothing if no valid netdev defined */
1206         if (!rx_ring->netdev || !cleaned_count)
1207                 return;
1208
1209         while (cleaned_count--) {
1210                 rx_desc = I40E_RX_DESC(rx_ring, i);
1211                 bi = &rx_ring->rx_bi[i];
1212
1213                 if (bi->skb) /* desc is in use */
1214                         goto no_buffers;
1215                 if (!bi->page) {
1216                         bi->page = alloc_page(GFP_ATOMIC);
1217                         if (!bi->page) {
1218                                 rx_ring->rx_stats.alloc_page_failed++;
1219                                 goto no_buffers;
1220                         }
1221                 }
1222
1223                 if (!bi->page_dma) {
1224                         /* use a half page if we're re-using */
1225                         bi->page_offset ^= PAGE_SIZE / 2;
1226                         bi->page_dma = dma_map_page(rx_ring->dev,
1227                                                     bi->page,
1228                                                     bi->page_offset,
1229                                                     PAGE_SIZE / 2,
1230                                                     DMA_FROM_DEVICE);
1231                         if (dma_mapping_error(rx_ring->dev,
1232                                               bi->page_dma)) {
1233                                 rx_ring->rx_stats.alloc_page_failed++;
1234                                 bi->page_dma = 0;
1235                                 goto no_buffers;
1236                         }
1237                 }
1238
1239                 dma_sync_single_range_for_device(rx_ring->dev,
1240                                                  rx_ring->rx_bi[0].dma,
1241                                                  i * rx_ring->rx_hdr_len,
1242                                                  rx_ring->rx_hdr_len,
1243                                                  DMA_FROM_DEVICE);
1244                 /* Refresh the desc even if buffer_addrs didn't change
1245                  * because each write-back erases this info.
1246                  */
1247                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1248                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1249                 i++;
1250                 if (i == rx_ring->count)
1251                         i = 0;
1252         }
1253
1254 no_buffers:
1255         if (rx_ring->next_to_use != i)
1256                 i40e_release_rx_desc(rx_ring, i);
1257 }
1258
1259 /**
1260  * i40e_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
1261  * @rx_ring: ring to place buffers on
1262  * @cleaned_count: number of buffers to replace
1263  **/
1264 void i40e_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
1265 {
1266         u16 i = rx_ring->next_to_use;
1267         union i40e_rx_desc *rx_desc;
1268         struct i40e_rx_buffer *bi;
1269         struct sk_buff *skb;
1270
1271         /* do nothing if no valid netdev defined */
1272         if (!rx_ring->netdev || !cleaned_count)
1273                 return;
1274
1275         while (cleaned_count--) {
1276                 rx_desc = I40E_RX_DESC(rx_ring, i);
1277                 bi = &rx_ring->rx_bi[i];
1278                 skb = bi->skb;
1279
1280                 if (!skb) {
1281                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1282                                                         rx_ring->rx_buf_len);
1283                         if (!skb) {
1284                                 rx_ring->rx_stats.alloc_buff_failed++;
1285                                 goto no_buffers;
1286                         }
1287                         /* initialize queue mapping */
1288                         skb_record_rx_queue(skb, rx_ring->queue_index);
1289                         bi->skb = skb;
1290                 }
1291
1292                 if (!bi->dma) {
1293                         bi->dma = dma_map_single(rx_ring->dev,
1294                                                  skb->data,
1295                                                  rx_ring->rx_buf_len,
1296                                                  DMA_FROM_DEVICE);
1297                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1298                                 rx_ring->rx_stats.alloc_buff_failed++;
1299                                 bi->dma = 0;
1300                                 goto no_buffers;
1301                         }
1302                 }
1303
1304                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1305                 rx_desc->read.hdr_addr = 0;
1306                 i++;
1307                 if (i == rx_ring->count)
1308                         i = 0;
1309         }
1310
1311 no_buffers:
1312         if (rx_ring->next_to_use != i)
1313                 i40e_release_rx_desc(rx_ring, i);
1314 }
1315
1316 /**
1317  * i40e_receive_skb - Send a completed packet up the stack
1318  * @rx_ring:  rx ring in play
1319  * @skb: packet to send up
1320  * @vlan_tag: vlan tag for packet
1321  **/
1322 static void i40e_receive_skb(struct i40e_ring *rx_ring,
1323                              struct sk_buff *skb, u16 vlan_tag)
1324 {
1325         struct i40e_q_vector *q_vector = rx_ring->q_vector;
1326
1327         if (vlan_tag & VLAN_VID_MASK)
1328                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
1329
1330         napi_gro_receive(&q_vector->napi, skb);
1331 }
1332
1333 /**
1334  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1335  * @vsi: the VSI we care about
1336  * @skb: skb currently being received and modified
1337  * @rx_status: status value of last descriptor in packet
1338  * @rx_error: error value of last descriptor in packet
1339  * @rx_ptype: ptype value of last descriptor in packet
1340  **/
1341 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1342                                     struct sk_buff *skb,
1343                                     u32 rx_status,
1344                                     u32 rx_error,
1345                                     u16 rx_ptype)
1346 {
1347         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
1348         bool ipv4 = false, ipv6 = false;
1349         bool ipv4_tunnel, ipv6_tunnel;
1350         __wsum rx_udp_csum;
1351         struct iphdr *iph;
1352         __sum16 csum;
1353
1354         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
1355                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
1356         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
1357                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
1358
1359         skb->ip_summed = CHECKSUM_NONE;
1360
1361         /* Rx csum enabled and ip headers found? */
1362         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1363                 return;
1364
1365         /* did the hardware decode the packet and checksum? */
1366         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1367                 return;
1368
1369         /* both known and outer_ip must be set for the below code to work */
1370         if (!(decoded.known && decoded.outer_ip))
1371                 return;
1372
1373         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1374             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
1375                 ipv4 = true;
1376         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1377                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
1378                 ipv6 = true;
1379
1380         if (ipv4 &&
1381             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1382                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1383                 goto checksum_fail;
1384
1385         /* likely incorrect csum if alternate IP extension headers found */
1386         if (ipv6 &&
1387             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1388                 /* don't increment checksum err here, non-fatal err */
1389                 return;
1390
1391         /* there was some L4 error, count error and punt packet to the stack */
1392         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1393                 goto checksum_fail;
1394
1395         /* handle packets that were not able to be checksummed due
1396          * to arrival speed, in this case the stack can compute
1397          * the csum.
1398          */
1399         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1400                 return;
1401
1402         /* If VXLAN/GENEVE traffic has an outer UDPv4 checksum we need to check
1403          * it in the driver, hardware does not do it for us.
1404          * Since L3L4P bit was set we assume a valid IHL value (>=5)
1405          * so the total length of IPv4 header is IHL*4 bytes
1406          * The UDP_0 bit *may* bet set if the *inner* header is UDP
1407          */
1408         if (!(vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE) &&
1409             (ipv4_tunnel)) {
1410                 skb->transport_header = skb->mac_header +
1411                                         sizeof(struct ethhdr) +
1412                                         (ip_hdr(skb)->ihl * 4);
1413
1414                 /* Add 4 bytes for VLAN tagged packets */
1415                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
1416                                           skb->protocol == htons(ETH_P_8021AD))
1417                                           ? VLAN_HLEN : 0;
1418
1419                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
1420                     (udp_hdr(skb)->check != 0)) {
1421                         rx_udp_csum = udp_csum(skb);
1422                         iph = ip_hdr(skb);
1423                         csum = csum_tcpudp_magic(
1424                                         iph->saddr, iph->daddr,
1425                                         (skb->len - skb_transport_offset(skb)),
1426                                         IPPROTO_UDP, rx_udp_csum);
1427
1428                         if (udp_hdr(skb)->check != csum)
1429                                 goto checksum_fail;
1430
1431                 } /* else its GRE and so no outer UDP header */
1432         }
1433
1434         skb->ip_summed = CHECKSUM_UNNECESSARY;
1435         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
1436
1437         return;
1438
1439 checksum_fail:
1440         vsi->back->hw_csum_rx_error++;
1441 }
1442
1443 /**
1444  * i40e_ptype_to_htype - get a hash type
1445  * @ptype: the ptype value from the descriptor
1446  *
1447  * Returns a hash type to be used by skb_set_hash
1448  **/
1449 static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
1450 {
1451         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1452
1453         if (!decoded.known)
1454                 return PKT_HASH_TYPE_NONE;
1455
1456         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1457             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1458                 return PKT_HASH_TYPE_L4;
1459         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1460                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1461                 return PKT_HASH_TYPE_L3;
1462         else
1463                 return PKT_HASH_TYPE_L2;
1464 }
1465
1466 /**
1467  * i40e_rx_hash - set the hash value in the skb
1468  * @ring: descriptor ring
1469  * @rx_desc: specific descriptor
1470  **/
1471 static inline void i40e_rx_hash(struct i40e_ring *ring,
1472                                 union i40e_rx_desc *rx_desc,
1473                                 struct sk_buff *skb,
1474                                 u8 rx_ptype)
1475 {
1476         u32 hash;
1477         const __le64 rss_mask  =
1478                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1479                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1480
1481         if (ring->netdev->features & NETIF_F_RXHASH)
1482                 return;
1483
1484         if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1485                 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1486                 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
1487         }
1488 }
1489
1490 /**
1491  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
1492  * @rx_ring:  rx ring to clean
1493  * @budget:   how many cleans we're allowed
1494  *
1495  * Returns true if there's any budget left (e.g. the clean is finished)
1496  **/
1497 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
1498 {
1499         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1500         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1501         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1502         const int current_node = numa_mem_id();
1503         struct i40e_vsi *vsi = rx_ring->vsi;
1504         u16 i = rx_ring->next_to_clean;
1505         union i40e_rx_desc *rx_desc;
1506         u32 rx_error, rx_status;
1507         u8 rx_ptype;
1508         u64 qword;
1509
1510         if (budget <= 0)
1511                 return 0;
1512
1513         do {
1514                 struct i40e_rx_buffer *rx_bi;
1515                 struct sk_buff *skb;
1516                 u16 vlan_tag;
1517                 /* return some buffers to hardware, one at a time is too slow */
1518                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1519                         i40e_alloc_rx_buffers_ps(rx_ring, cleaned_count);
1520                         cleaned_count = 0;
1521                 }
1522
1523                 i = rx_ring->next_to_clean;
1524                 rx_desc = I40E_RX_DESC(rx_ring, i);
1525                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1526                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1527                         I40E_RXD_QW1_STATUS_SHIFT;
1528
1529                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1530                         break;
1531
1532                 /* This memory barrier is needed to keep us from reading
1533                  * any other fields out of the rx_desc until we know the
1534                  * DD bit is set.
1535                  */
1536                 dma_rmb();
1537                 if (i40e_rx_is_programming_status(qword)) {
1538                         i40e_clean_programming_status(rx_ring, rx_desc);
1539                         I40E_RX_INCREMENT(rx_ring, i);
1540                         continue;
1541                 }
1542                 rx_bi = &rx_ring->rx_bi[i];
1543                 skb = rx_bi->skb;
1544                 if (likely(!skb)) {
1545                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1546                                                         rx_ring->rx_hdr_len);
1547                         if (!skb) {
1548                                 rx_ring->rx_stats.alloc_buff_failed++;
1549                                 break;
1550                         }
1551
1552                         /* initialize queue mapping */
1553                         skb_record_rx_queue(skb, rx_ring->queue_index);
1554                         /* we are reusing so sync this buffer for CPU use */
1555                         dma_sync_single_range_for_cpu(rx_ring->dev,
1556                                                       rx_ring->rx_bi[0].dma,
1557                                                       i * rx_ring->rx_hdr_len,
1558                                                       rx_ring->rx_hdr_len,
1559                                                       DMA_FROM_DEVICE);
1560                 }
1561                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1562                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1563                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1564                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1565                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1566                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1567
1568                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1569                            I40E_RXD_QW1_ERROR_SHIFT;
1570                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1571                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1572
1573                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1574                            I40E_RXD_QW1_PTYPE_SHIFT;
1575                 prefetch(rx_bi->page);
1576                 rx_bi->skb = NULL;
1577                 cleaned_count++;
1578                 if (rx_hbo || rx_sph) {
1579                         int len;
1580
1581                         if (rx_hbo)
1582                                 len = I40E_RX_HDR_SIZE;
1583                         else
1584                                 len = rx_header_len;
1585                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1586                 } else if (skb->len == 0) {
1587                         int len;
1588
1589                         len = (rx_packet_len > skb_headlen(skb) ?
1590                                 skb_headlen(skb) : rx_packet_len);
1591                         memcpy(__skb_put(skb, len),
1592                                rx_bi->page + rx_bi->page_offset,
1593                                len);
1594                         rx_bi->page_offset += len;
1595                         rx_packet_len -= len;
1596                 }
1597
1598                 /* Get the rest of the data if this was a header split */
1599                 if (rx_packet_len) {
1600                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1601                                            rx_bi->page,
1602                                            rx_bi->page_offset,
1603                                            rx_packet_len);
1604
1605                         skb->len += rx_packet_len;
1606                         skb->data_len += rx_packet_len;
1607                         skb->truesize += rx_packet_len;
1608
1609                         if ((page_count(rx_bi->page) == 1) &&
1610                             (page_to_nid(rx_bi->page) == current_node))
1611                                 get_page(rx_bi->page);
1612                         else
1613                                 rx_bi->page = NULL;
1614
1615                         dma_unmap_page(rx_ring->dev,
1616                                        rx_bi->page_dma,
1617                                        PAGE_SIZE / 2,
1618                                        DMA_FROM_DEVICE);
1619                         rx_bi->page_dma = 0;
1620                 }
1621                 I40E_RX_INCREMENT(rx_ring, i);
1622
1623                 if (unlikely(
1624                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1625                         struct i40e_rx_buffer *next_buffer;
1626
1627                         next_buffer = &rx_ring->rx_bi[i];
1628                         next_buffer->skb = skb;
1629                         rx_ring->rx_stats.non_eop_descs++;
1630                         continue;
1631                 }
1632
1633                 /* ERR_MASK will only have valid bits if EOP set */
1634                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1635                         dev_kfree_skb_any(skb);
1636                         continue;
1637                 }
1638
1639                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1640
1641                 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1642                         i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1643                                            I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1644                                            I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1645                         rx_ring->last_rx_timestamp = jiffies;
1646                 }
1647
1648                 /* probably a little skewed due to removing CRC */
1649                 total_rx_bytes += skb->len;
1650                 total_rx_packets++;
1651
1652                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1653
1654                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1655
1656                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1657                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1658                          : 0;
1659 #ifdef I40E_FCOE
1660                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1661                         dev_kfree_skb_any(skb);
1662                         continue;
1663                 }
1664 #endif
1665                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1666
1667                 rx_desc->wb.qword1.status_error_len = 0;
1668
1669         } while (likely(total_rx_packets < budget));
1670
1671         u64_stats_update_begin(&rx_ring->syncp);
1672         rx_ring->stats.packets += total_rx_packets;
1673         rx_ring->stats.bytes += total_rx_bytes;
1674         u64_stats_update_end(&rx_ring->syncp);
1675         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1676         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1677
1678         return total_rx_packets;
1679 }
1680
1681 /**
1682  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1683  * @rx_ring:  rx ring to clean
1684  * @budget:   how many cleans we're allowed
1685  *
1686  * Returns number of packets cleaned
1687  **/
1688 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1689 {
1690         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1691         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1692         struct i40e_vsi *vsi = rx_ring->vsi;
1693         union i40e_rx_desc *rx_desc;
1694         u32 rx_error, rx_status;
1695         u16 rx_packet_len;
1696         u8 rx_ptype;
1697         u64 qword;
1698         u16 i;
1699
1700         do {
1701                 struct i40e_rx_buffer *rx_bi;
1702                 struct sk_buff *skb;
1703                 u16 vlan_tag;
1704                 /* return some buffers to hardware, one at a time is too slow */
1705                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1706                         i40e_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1707                         cleaned_count = 0;
1708                 }
1709
1710                 i = rx_ring->next_to_clean;
1711                 rx_desc = I40E_RX_DESC(rx_ring, i);
1712                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1713                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1714                         I40E_RXD_QW1_STATUS_SHIFT;
1715
1716                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1717                         break;
1718
1719                 /* This memory barrier is needed to keep us from reading
1720                  * any other fields out of the rx_desc until we know the
1721                  * DD bit is set.
1722                  */
1723                 dma_rmb();
1724
1725                 if (i40e_rx_is_programming_status(qword)) {
1726                         i40e_clean_programming_status(rx_ring, rx_desc);
1727                         I40E_RX_INCREMENT(rx_ring, i);
1728                         continue;
1729                 }
1730                 rx_bi = &rx_ring->rx_bi[i];
1731                 skb = rx_bi->skb;
1732                 prefetch(skb->data);
1733
1734                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1735                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1736
1737                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1738                            I40E_RXD_QW1_ERROR_SHIFT;
1739                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1740
1741                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1742                            I40E_RXD_QW1_PTYPE_SHIFT;
1743                 rx_bi->skb = NULL;
1744                 cleaned_count++;
1745
1746                 /* Get the header and possibly the whole packet
1747                  * If this is an skb from previous receive dma will be 0
1748                  */
1749                 skb_put(skb, rx_packet_len);
1750                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1751                                  DMA_FROM_DEVICE);
1752                 rx_bi->dma = 0;
1753
1754                 I40E_RX_INCREMENT(rx_ring, i);
1755
1756                 if (unlikely(
1757                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1758                         rx_ring->rx_stats.non_eop_descs++;
1759                         continue;
1760                 }
1761
1762                 /* ERR_MASK will only have valid bits if EOP set */
1763                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1764                         dev_kfree_skb_any(skb);
1765                         continue;
1766                 }
1767
1768                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1769                 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1770                         i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1771                                            I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1772                                            I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1773                         rx_ring->last_rx_timestamp = jiffies;
1774                 }
1775
1776                 /* probably a little skewed due to removing CRC */
1777                 total_rx_bytes += skb->len;
1778                 total_rx_packets++;
1779
1780                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1781
1782                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1783
1784                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1785                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1786                          : 0;
1787 #ifdef I40E_FCOE
1788                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1789                         dev_kfree_skb_any(skb);
1790                         continue;
1791                 }
1792 #endif
1793                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1794
1795                 rx_desc->wb.qword1.status_error_len = 0;
1796         } while (likely(total_rx_packets < budget));
1797
1798         u64_stats_update_begin(&rx_ring->syncp);
1799         rx_ring->stats.packets += total_rx_packets;
1800         rx_ring->stats.bytes += total_rx_bytes;
1801         u64_stats_update_end(&rx_ring->syncp);
1802         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1803         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1804
1805         return total_rx_packets;
1806 }
1807
1808 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1809 {
1810         u32 val;
1811
1812         val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1813               /* Don't clear PBA because that can cause lost interrupts that
1814                * came in while we were cleaning/polling
1815                */
1816               (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1817               (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
1818
1819         return val;
1820 }
1821
1822 /* a small macro to shorten up some long lines */
1823 #define INTREG I40E_PFINT_DYN_CTLN
1824
1825 /**
1826  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1827  * @vsi: the VSI we care about
1828  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1829  *
1830  **/
1831 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1832                                           struct i40e_q_vector *q_vector)
1833 {
1834         struct i40e_hw *hw = &vsi->back->hw;
1835         bool rx = false, tx = false;
1836         u32 rxval, txval;
1837         int vector;
1838
1839         vector = (q_vector->v_idx + vsi->base_vector);
1840
1841         /* avoid dynamic calculation if in countdown mode OR if
1842          * all dynamic is disabled
1843          */
1844         rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1845
1846         if (q_vector->itr_countdown > 0 ||
1847             (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1848              !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1849                 goto enable_int;
1850         }
1851
1852         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1853                 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1854                 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1855         }
1856
1857         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1858                 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1859                 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1860         }
1861
1862         if (rx || tx) {
1863                 /* get the higher of the two ITR adjustments and
1864                  * use the same value for both ITR registers
1865                  * when in adaptive mode (Rx and/or Tx)
1866                  */
1867                 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1868
1869                 q_vector->tx.itr = q_vector->rx.itr = itr;
1870                 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1871                 tx = true;
1872                 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1873                 rx = true;
1874         }
1875
1876         /* only need to enable the interrupt once, but need
1877          * to possibly update both ITR values
1878          */
1879         if (rx) {
1880                 /* set the INTENA_MSK_MASK so that this first write
1881                  * won't actually enable the interrupt, instead just
1882                  * updating the ITR (it's bit 31 PF and VF)
1883                  */
1884                 rxval |= BIT(31);
1885                 /* don't check _DOWN because interrupt isn't being enabled */
1886                 wr32(hw, INTREG(vector - 1), rxval);
1887         }
1888
1889 enable_int:
1890         if (!test_bit(__I40E_DOWN, &vsi->state))
1891                 wr32(hw, INTREG(vector - 1), txval);
1892
1893         if (q_vector->itr_countdown)
1894                 q_vector->itr_countdown--;
1895         else
1896                 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1897 }
1898
1899 /**
1900  * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
1901  * @napi: napi struct with our devices info in it
1902  * @budget: amount of work driver is allowed to do this pass, in packets
1903  *
1904  * This function will clean all queues associated with a q_vector.
1905  *
1906  * Returns the amount of work done
1907  **/
1908 int i40e_napi_poll(struct napi_struct *napi, int budget)
1909 {
1910         struct i40e_q_vector *q_vector =
1911                                container_of(napi, struct i40e_q_vector, napi);
1912         struct i40e_vsi *vsi = q_vector->vsi;
1913         struct i40e_ring *ring;
1914         bool clean_complete = true;
1915         bool arm_wb = false;
1916         int budget_per_ring;
1917         int work_done = 0;
1918
1919         if (test_bit(__I40E_DOWN, &vsi->state)) {
1920                 napi_complete(napi);
1921                 return 0;
1922         }
1923
1924         /* Clear hung_detected bit */
1925         clear_bit(I40E_Q_VECTOR_HUNG_DETECT, &q_vector->hung_detected);
1926         /* Since the actual Tx work is minimal, we can give the Tx a larger
1927          * budget and be more aggressive about cleaning up the Tx descriptors.
1928          */
1929         i40e_for_each_ring(ring, q_vector->tx) {
1930                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1931                 arm_wb = arm_wb || ring->arm_wb;
1932                 ring->arm_wb = false;
1933         }
1934
1935         /* Handle case where we are called by netpoll with a budget of 0 */
1936         if (budget <= 0)
1937                 goto tx_only;
1938
1939         /* We attempt to distribute budget to each Rx queue fairly, but don't
1940          * allow the budget to go below 1 because that would exit polling early.
1941          */
1942         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1943
1944         i40e_for_each_ring(ring, q_vector->rx) {
1945                 int cleaned;
1946
1947                 if (ring_is_ps_enabled(ring))
1948                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1949                 else
1950                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1951
1952                 work_done += cleaned;
1953                 /* if we didn't clean as many as budgeted, we must be done */
1954                 clean_complete &= (budget_per_ring != cleaned);
1955         }
1956
1957         /* If work not completed, return budget and polling will return */
1958         if (!clean_complete) {
1959 tx_only:
1960                 if (arm_wb) {
1961                         q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1962                         i40e_enable_wb_on_itr(vsi, q_vector);
1963                 }
1964                 return budget;
1965         }
1966
1967         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1968                 q_vector->arm_wb_state = false;
1969
1970         /* Work is done so exit the polling mode and re-enable the interrupt */
1971         napi_complete_done(napi, work_done);
1972         if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1973                 i40e_update_enable_itr(vsi, q_vector);
1974         } else { /* Legacy mode */
1975                 struct i40e_hw *hw = &vsi->back->hw;
1976                 /* We re-enable the queue 0 cause, but
1977                  * don't worry about dynamic_enable
1978                  * because we left it on for the other
1979                  * possible interrupts during napi
1980                  */
1981                 u32 qval = rd32(hw, I40E_QINT_RQCTL(0)) |
1982                            I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1983
1984                 wr32(hw, I40E_QINT_RQCTL(0), qval);
1985                 qval = rd32(hw, I40E_QINT_TQCTL(0)) |
1986                        I40E_QINT_TQCTL_CAUSE_ENA_MASK;
1987                 wr32(hw, I40E_QINT_TQCTL(0), qval);
1988                 i40e_irq_dynamic_enable_icr0(vsi->back, false);
1989         }
1990         return 0;
1991 }
1992
1993 /**
1994  * i40e_atr - Add a Flow Director ATR filter
1995  * @tx_ring:  ring to add programming descriptor to
1996  * @skb:      send buffer
1997  * @tx_flags: send tx flags
1998  * @protocol: wire protocol
1999  **/
2000 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2001                      u32 tx_flags, __be16 protocol)
2002 {
2003         struct i40e_filter_program_desc *fdir_desc;
2004         struct i40e_pf *pf = tx_ring->vsi->back;
2005         union {
2006                 unsigned char *network;
2007                 struct iphdr *ipv4;
2008                 struct ipv6hdr *ipv6;
2009         } hdr;
2010         struct tcphdr *th;
2011         unsigned int hlen;
2012         u32 flex_ptype, dtype_cmd;
2013         u16 i;
2014
2015         /* make sure ATR is enabled */
2016         if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
2017                 return;
2018
2019         if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
2020                 return;
2021
2022         /* if sampling is disabled do nothing */
2023         if (!tx_ring->atr_sample_rate)
2024                 return;
2025
2026         if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2027                 return;
2028
2029         if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) {
2030                 /* snag network header to get L4 type and address */
2031                 hdr.network = skb_network_header(skb);
2032
2033                 /* Currently only IPv4/IPv6 with TCP is supported
2034                  * access ihl as u8 to avoid unaligned access on ia64
2035                  */
2036                 if (tx_flags & I40E_TX_FLAGS_IPV4)
2037                         hlen = (hdr.network[0] & 0x0F) << 2;
2038                 else if (protocol == htons(ETH_P_IPV6))
2039                         hlen = sizeof(struct ipv6hdr);
2040                 else
2041                         return;
2042         } else {
2043                 hdr.network = skb_inner_network_header(skb);
2044                 hlen = skb_inner_network_header_len(skb);
2045         }
2046
2047         /* Currently only IPv4/IPv6 with TCP is supported
2048          * Note: tx_flags gets modified to reflect inner protocols in
2049          * tx_enable_csum function if encap is enabled.
2050          */
2051         if ((tx_flags & I40E_TX_FLAGS_IPV4) &&
2052             (hdr.ipv4->protocol != IPPROTO_TCP))
2053                 return;
2054         else if ((tx_flags & I40E_TX_FLAGS_IPV6) &&
2055                  (hdr.ipv6->nexthdr != IPPROTO_TCP))
2056                 return;
2057
2058         th = (struct tcphdr *)(hdr.network + hlen);
2059
2060         /* Due to lack of space, no more new filters can be programmed */
2061         if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
2062                 return;
2063         if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) &&
2064             (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) {
2065                 /* HW ATR eviction will take care of removing filters on FIN
2066                  * and RST packets.
2067                  */
2068                 if (th->fin || th->rst)
2069                         return;
2070         }
2071
2072         tx_ring->atr_count++;
2073
2074         /* sample on all syn/fin/rst packets or once every atr sample rate */
2075         if (!th->fin &&
2076             !th->syn &&
2077             !th->rst &&
2078             (tx_ring->atr_count < tx_ring->atr_sample_rate))
2079                 return;
2080
2081         tx_ring->atr_count = 0;
2082
2083         /* grab the next descriptor */
2084         i = tx_ring->next_to_use;
2085         fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2086
2087         i++;
2088         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2089
2090         flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2091                       I40E_TXD_FLTR_QW0_QINDEX_MASK;
2092         flex_ptype |= (protocol == htons(ETH_P_IP)) ?
2093                       (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2094                        I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2095                       (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2096                        I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2097
2098         flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2099
2100         dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2101
2102         dtype_cmd |= (th->fin || th->rst) ?
2103                      (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2104                       I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2105                      (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2106                       I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2107
2108         dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2109                      I40E_TXD_FLTR_QW1_DEST_SHIFT;
2110
2111         dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2112                      I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2113
2114         dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2115         if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2116                 dtype_cmd |=
2117                         ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2118                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2119                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2120         else
2121                 dtype_cmd |=
2122                         ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2123                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2124                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2125
2126         if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) &&
2127             (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)))
2128                 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2129
2130         fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2131         fdir_desc->rsvd = cpu_to_le32(0);
2132         fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2133         fdir_desc->fd_id = cpu_to_le32(0);
2134 }
2135
2136 /**
2137  * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2138  * @skb:     send buffer
2139  * @tx_ring: ring to send buffer on
2140  * @flags:   the tx flags to be set
2141  *
2142  * Checks the skb and set up correspondingly several generic transmit flags
2143  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2144  *
2145  * Returns error code indicate the frame should be dropped upon error and the
2146  * otherwise  returns 0 to indicate the flags has been set properly.
2147  **/
2148 #ifdef I40E_FCOE
2149 inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2150                                       struct i40e_ring *tx_ring,
2151                                       u32 *flags)
2152 #else
2153 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2154                                              struct i40e_ring *tx_ring,
2155                                              u32 *flags)
2156 #endif
2157 {
2158         __be16 protocol = skb->protocol;
2159         u32  tx_flags = 0;
2160
2161         if (protocol == htons(ETH_P_8021Q) &&
2162             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2163                 /* When HW VLAN acceleration is turned off by the user the
2164                  * stack sets the protocol to 8021q so that the driver
2165                  * can take any steps required to support the SW only
2166                  * VLAN handling.  In our case the driver doesn't need
2167                  * to take any further steps so just set the protocol
2168                  * to the encapsulated ethertype.
2169                  */
2170                 skb->protocol = vlan_get_protocol(skb);
2171                 goto out;
2172         }
2173
2174         /* if we have a HW VLAN tag being added, default to the HW one */
2175         if (skb_vlan_tag_present(skb)) {
2176                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2177                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2178         /* else if it is a SW VLAN, check the next protocol and store the tag */
2179         } else if (protocol == htons(ETH_P_8021Q)) {
2180                 struct vlan_hdr *vhdr, _vhdr;
2181
2182                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2183                 if (!vhdr)
2184                         return -EINVAL;
2185
2186                 protocol = vhdr->h_vlan_encapsulated_proto;
2187                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2188                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2189         }
2190
2191         if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2192                 goto out;
2193
2194         /* Insert 802.1p priority into VLAN header */
2195         if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2196             (skb->priority != TC_PRIO_CONTROL)) {
2197                 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2198                 tx_flags |= (skb->priority & 0x7) <<
2199                                 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2200                 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2201                         struct vlan_ethhdr *vhdr;
2202                         int rc;
2203
2204                         rc = skb_cow_head(skb, 0);
2205                         if (rc < 0)
2206                                 return rc;
2207                         vhdr = (struct vlan_ethhdr *)skb->data;
2208                         vhdr->h_vlan_TCI = htons(tx_flags >>
2209                                                  I40E_TX_FLAGS_VLAN_SHIFT);
2210                 } else {
2211                         tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2212                 }
2213         }
2214
2215 out:
2216         *flags = tx_flags;
2217         return 0;
2218 }
2219
2220 /**
2221  * i40e_tso - set up the tso context descriptor
2222  * @tx_ring:  ptr to the ring to send
2223  * @skb:      ptr to the skb we're sending
2224  * @hdr_len:  ptr to the size of the packet header
2225  * @cd_type_cmd_tso_mss: Quad Word 1
2226  *
2227  * Returns 0 if no TSO can happen, 1 if tso is going, or error
2228  **/
2229 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
2230                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
2231 {
2232         u32 cd_cmd, cd_tso_len, cd_mss;
2233         struct ipv6hdr *ipv6h;
2234         struct tcphdr *tcph;
2235         struct iphdr *iph;
2236         u32 l4len;
2237         int err;
2238
2239         if (skb->ip_summed != CHECKSUM_PARTIAL)
2240                 return 0;
2241
2242         if (!skb_is_gso(skb))
2243                 return 0;
2244
2245         err = skb_cow_head(skb, 0);
2246         if (err < 0)
2247                 return err;
2248
2249         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
2250         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
2251
2252         if (iph->version == 4) {
2253                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2254                 iph->tot_len = 0;
2255                 iph->check = 0;
2256                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
2257                                                  0, IPPROTO_TCP, 0);
2258         } else if (ipv6h->version == 6) {
2259                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2260                 ipv6h->payload_len = 0;
2261                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
2262                                                0, IPPROTO_TCP, 0);
2263         }
2264
2265         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
2266         *hdr_len = (skb->encapsulation
2267                     ? (skb_inner_transport_header(skb) - skb->data)
2268                     : skb_transport_offset(skb)) + l4len;
2269
2270         /* find the field values */
2271         cd_cmd = I40E_TX_CTX_DESC_TSO;
2272         cd_tso_len = skb->len - *hdr_len;
2273         cd_mss = skb_shinfo(skb)->gso_size;
2274         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2275                                 ((u64)cd_tso_len <<
2276                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2277                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
2278         return 1;
2279 }
2280
2281 /**
2282  * i40e_tsyn - set up the tsyn context descriptor
2283  * @tx_ring:  ptr to the ring to send
2284  * @skb:      ptr to the skb we're sending
2285  * @tx_flags: the collected send information
2286  * @cd_type_cmd_tso_mss: Quad Word 1
2287  *
2288  * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
2289  **/
2290 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
2291                      u32 tx_flags, u64 *cd_type_cmd_tso_mss)
2292 {
2293         struct i40e_pf *pf;
2294
2295         if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
2296                 return 0;
2297
2298         /* Tx timestamps cannot be sampled when doing TSO */
2299         if (tx_flags & I40E_TX_FLAGS_TSO)
2300                 return 0;
2301
2302         /* only timestamp the outbound packet if the user has requested it and
2303          * we are not already transmitting a packet to be timestamped
2304          */
2305         pf = i40e_netdev_to_pf(tx_ring->netdev);
2306         if (!(pf->flags & I40E_FLAG_PTP))
2307                 return 0;
2308
2309         if (pf->ptp_tx &&
2310             !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) {
2311                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2312                 pf->ptp_tx_skb = skb_get(skb);
2313         } else {
2314                 return 0;
2315         }
2316
2317         *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
2318                                 I40E_TXD_CTX_QW1_CMD_SHIFT;
2319
2320         return 1;
2321 }
2322
2323 /**
2324  * i40e_tx_enable_csum - Enable Tx checksum offloads
2325  * @skb: send buffer
2326  * @tx_flags: pointer to Tx flags currently set
2327  * @td_cmd: Tx descriptor command bits to set
2328  * @td_offset: Tx descriptor header offsets to set
2329  * @tx_ring: Tx descriptor ring
2330  * @cd_tunneling: ptr to context desc bits
2331  **/
2332 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
2333                                 u32 *td_cmd, u32 *td_offset,
2334                                 struct i40e_ring *tx_ring,
2335                                 u32 *cd_tunneling)
2336 {
2337         struct ipv6hdr *this_ipv6_hdr;
2338         unsigned int this_tcp_hdrlen;
2339         struct iphdr *this_ip_hdr;
2340         u32 network_hdr_len;
2341         u8 l4_hdr = 0;
2342         struct udphdr *oudph = NULL;
2343         struct iphdr *oiph = NULL;
2344         u32 l4_tunnel = 0;
2345
2346         if (skb->encapsulation) {
2347                 switch (ip_hdr(skb)->protocol) {
2348                 case IPPROTO_UDP:
2349                         oudph = udp_hdr(skb);
2350                         oiph = ip_hdr(skb);
2351                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
2352                         *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
2353                         break;
2354                 case IPPROTO_GRE:
2355                         l4_tunnel = I40E_TXD_CTX_GRE_TUNNELING;
2356                         break;
2357                 default:
2358                         return;
2359                 }
2360                 network_hdr_len = skb_inner_network_header_len(skb);
2361                 this_ip_hdr = inner_ip_hdr(skb);
2362                 this_ipv6_hdr = inner_ipv6_hdr(skb);
2363                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
2364
2365                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2366                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
2367                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
2368                                 ip_hdr(skb)->check = 0;
2369                         } else {
2370                                 *cd_tunneling |=
2371                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
2372                         }
2373                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
2374                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
2375                         if (*tx_flags & I40E_TX_FLAGS_TSO)
2376                                 ip_hdr(skb)->check = 0;
2377                 }
2378
2379                 /* Now set the ctx descriptor fields */
2380                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
2381                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
2382                                    l4_tunnel                             |
2383                                    ((skb_inner_network_offset(skb) -
2384                                         skb_transport_offset(skb)) >> 1) <<
2385                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
2386                 if (this_ip_hdr->version == 6) {
2387                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
2388                         *tx_flags |= I40E_TX_FLAGS_IPV6;
2389                 }
2390                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
2391                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
2392                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
2393                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
2394                                         oiph->daddr,
2395                                         (skb->len - skb_transport_offset(skb)),
2396                                         IPPROTO_UDP, 0);
2397                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
2398                 }
2399         } else {
2400                 network_hdr_len = skb_network_header_len(skb);
2401                 this_ip_hdr = ip_hdr(skb);
2402                 this_ipv6_hdr = ipv6_hdr(skb);
2403                 this_tcp_hdrlen = tcp_hdrlen(skb);
2404         }
2405
2406         /* Enable IP checksum offloads */
2407         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2408                 l4_hdr = this_ip_hdr->protocol;
2409                 /* the stack computes the IP header already, the only time we
2410                  * need the hardware to recompute it is in the case of TSO.
2411                  */
2412                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
2413                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
2414                         this_ip_hdr->check = 0;
2415                 } else {
2416                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
2417                 }
2418                 /* Now set the td_offset for IP header length */
2419                 *td_offset = (network_hdr_len >> 2) <<
2420                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2421         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
2422                 l4_hdr = this_ipv6_hdr->nexthdr;
2423                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
2424                 /* Now set the td_offset for IP header length */
2425                 *td_offset = (network_hdr_len >> 2) <<
2426                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2427         }
2428         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
2429         *td_offset |= (skb_network_offset(skb) >> 1) <<
2430                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
2431
2432         /* Enable L4 checksum offloads */
2433         switch (l4_hdr) {
2434         case IPPROTO_TCP:
2435                 /* enable checksum offloads */
2436                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
2437                 *td_offset |= (this_tcp_hdrlen >> 2) <<
2438                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2439                 break;
2440         case IPPROTO_SCTP:
2441                 /* enable SCTP checksum offload */
2442                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
2443                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
2444                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2445                 break;
2446         case IPPROTO_UDP:
2447                 /* enable UDP checksum offload */
2448                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
2449                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
2450                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2451                 break;
2452         default:
2453                 break;
2454         }
2455 }
2456
2457 /**
2458  * i40e_create_tx_ctx Build the Tx context descriptor
2459  * @tx_ring:  ring to create the descriptor on
2460  * @cd_type_cmd_tso_mss: Quad Word 1
2461  * @cd_tunneling: Quad Word 0 - bits 0-31
2462  * @cd_l2tag2: Quad Word 0 - bits 32-63
2463  **/
2464 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
2465                                const u64 cd_type_cmd_tso_mss,
2466                                const u32 cd_tunneling, const u32 cd_l2tag2)
2467 {
2468         struct i40e_tx_context_desc *context_desc;
2469         int i = tx_ring->next_to_use;
2470
2471         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
2472             !cd_tunneling && !cd_l2tag2)
2473                 return;
2474
2475         /* grab the next descriptor */
2476         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
2477
2478         i++;
2479         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2480
2481         /* cpu_to_le32 and assign to struct fields */
2482         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2483         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
2484         context_desc->rsvd = cpu_to_le16(0);
2485         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2486 }
2487
2488 /**
2489  * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
2490  * @tx_ring: the ring to be checked
2491  * @size:    the size buffer we want to assure is available
2492  *
2493  * Returns -EBUSY if a stop is needed, else 0
2494  **/
2495 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2496 {
2497         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2498         /* Memory barrier before checking head and tail */
2499         smp_mb();
2500
2501         /* Check again in a case another CPU has just made room available. */
2502         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
2503                 return -EBUSY;
2504
2505         /* A reprieve! - use start_queue because it doesn't call schedule */
2506         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2507         ++tx_ring->tx_stats.restart_queue;
2508         return 0;
2509 }
2510
2511 /**
2512  * i40e_maybe_stop_tx - 1st level check for tx stop conditions
2513  * @tx_ring: the ring to be checked
2514  * @size:    the size buffer we want to assure is available
2515  *
2516  * Returns 0 if stop is not needed
2517  **/
2518 #ifdef I40E_FCOE
2519 inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2520 #else
2521 static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2522 #endif
2523 {
2524         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
2525                 return 0;
2526         return __i40e_maybe_stop_tx(tx_ring, size);
2527 }
2528
2529 /**
2530  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
2531  * @skb:      send buffer
2532  * @tx_flags: collected send information
2533  *
2534  * Note: Our HW can't scatter-gather more than 8 fragments to build
2535  * a packet on the wire and so we need to figure out the cases where we
2536  * need to linearize the skb.
2537  **/
2538 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
2539 {
2540         struct skb_frag_struct *frag;
2541         bool linearize = false;
2542         unsigned int size = 0;
2543         u16 num_frags;
2544         u16 gso_segs;
2545
2546         num_frags = skb_shinfo(skb)->nr_frags;
2547         gso_segs = skb_shinfo(skb)->gso_segs;
2548
2549         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
2550                 u16 j = 0;
2551
2552                 if (num_frags < (I40E_MAX_BUFFER_TXD))
2553                         goto linearize_chk_done;
2554                 /* try the simple math, if we have too many frags per segment */
2555                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
2556                     I40E_MAX_BUFFER_TXD) {
2557                         linearize = true;
2558                         goto linearize_chk_done;
2559                 }
2560                 frag = &skb_shinfo(skb)->frags[0];
2561                 /* we might still have more fragments per segment */
2562                 do {
2563                         size += skb_frag_size(frag);
2564                         frag++; j++;
2565                         if ((size >= skb_shinfo(skb)->gso_size) &&
2566                             (j < I40E_MAX_BUFFER_TXD)) {
2567                                 size = (size % skb_shinfo(skb)->gso_size);
2568                                 j = (size) ? 1 : 0;
2569                         }
2570                         if (j == I40E_MAX_BUFFER_TXD) {
2571                                 linearize = true;
2572                                 break;
2573                         }
2574                         num_frags--;
2575                 } while (num_frags);
2576         } else {
2577                 if (num_frags >= I40E_MAX_BUFFER_TXD)
2578                         linearize = true;
2579         }
2580
2581 linearize_chk_done:
2582         return linearize;
2583 }
2584
2585 /**
2586  * i40e_tx_map - Build the Tx descriptor
2587  * @tx_ring:  ring to send buffer on
2588  * @skb:      send buffer
2589  * @first:    first buffer info buffer to use
2590  * @tx_flags: collected send information
2591  * @hdr_len:  size of the packet header
2592  * @td_cmd:   the command field in the descriptor
2593  * @td_offset: offset for checksum or crc
2594  **/
2595 #ifdef I40E_FCOE
2596 inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2597                         struct i40e_tx_buffer *first, u32 tx_flags,
2598                         const u8 hdr_len, u32 td_cmd, u32 td_offset)
2599 #else
2600 static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2601                                struct i40e_tx_buffer *first, u32 tx_flags,
2602                                const u8 hdr_len, u32 td_cmd, u32 td_offset)
2603 #endif
2604 {
2605         unsigned int data_len = skb->data_len;
2606         unsigned int size = skb_headlen(skb);
2607         struct skb_frag_struct *frag;
2608         struct i40e_tx_buffer *tx_bi;
2609         struct i40e_tx_desc *tx_desc;
2610         u16 i = tx_ring->next_to_use;
2611         u32 td_tag = 0;
2612         dma_addr_t dma;
2613         u16 gso_segs;
2614         u16 desc_count = 0;
2615         bool tail_bump = true;
2616         bool do_rs = false;
2617
2618         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
2619                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
2620                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
2621                          I40E_TX_FLAGS_VLAN_SHIFT;
2622         }
2623
2624         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
2625                 gso_segs = skb_shinfo(skb)->gso_segs;
2626         else
2627                 gso_segs = 1;
2628
2629         /* multiply data chunks by size of headers */
2630         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
2631         first->gso_segs = gso_segs;
2632         first->skb = skb;
2633         first->tx_flags = tx_flags;
2634
2635         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2636
2637         tx_desc = I40E_TX_DESC(tx_ring, i);
2638         tx_bi = first;
2639
2640         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2641                 if (dma_mapping_error(tx_ring->dev, dma))
2642                         goto dma_error;
2643
2644                 /* record length, and DMA address */
2645                 dma_unmap_len_set(tx_bi, len, size);
2646                 dma_unmap_addr_set(tx_bi, dma, dma);
2647
2648                 tx_desc->buffer_addr = cpu_to_le64(dma);
2649
2650                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
2651                         tx_desc->cmd_type_offset_bsz =
2652                                 build_ctob(td_cmd, td_offset,
2653                                            I40E_MAX_DATA_PER_TXD, td_tag);
2654
2655                         tx_desc++;
2656                         i++;
2657                         desc_count++;
2658
2659                         if (i == tx_ring->count) {
2660                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
2661                                 i = 0;
2662                         }
2663
2664                         dma += I40E_MAX_DATA_PER_TXD;
2665                         size -= I40E_MAX_DATA_PER_TXD;
2666
2667                         tx_desc->buffer_addr = cpu_to_le64(dma);
2668                 }
2669
2670                 if (likely(!data_len))
2671                         break;
2672
2673                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2674                                                           size, td_tag);
2675
2676                 tx_desc++;
2677                 i++;
2678                 desc_count++;
2679
2680                 if (i == tx_ring->count) {
2681                         tx_desc = I40E_TX_DESC(tx_ring, 0);
2682                         i = 0;
2683                 }
2684
2685                 size = skb_frag_size(frag);
2686                 data_len -= size;
2687
2688                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2689                                        DMA_TO_DEVICE);
2690
2691                 tx_bi = &tx_ring->tx_bi[i];
2692         }
2693
2694         /* set next_to_watch value indicating a packet is present */
2695         first->next_to_watch = tx_desc;
2696
2697         i++;
2698         if (i == tx_ring->count)
2699                 i = 0;
2700
2701         tx_ring->next_to_use = i;
2702
2703         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
2704                                                  tx_ring->queue_index),
2705                                                  first->bytecount);
2706         i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
2707
2708         /* Algorithm to optimize tail and RS bit setting:
2709          * if xmit_more is supported
2710          *      if xmit_more is true
2711          *              do not update tail and do not mark RS bit.
2712          *      if xmit_more is false and last xmit_more was false
2713          *              if every packet spanned less than 4 desc
2714          *                      then set RS bit on 4th packet and update tail
2715          *                      on every packet
2716          *              else
2717          *                      update tail and set RS bit on every packet.
2718          *      if xmit_more is false and last_xmit_more was true
2719          *              update tail and set RS bit.
2720          *
2721          * Optimization: wmb to be issued only in case of tail update.
2722          * Also optimize the Descriptor WB path for RS bit with the same
2723          * algorithm.
2724          *
2725          * Note: If there are less than 4 packets
2726          * pending and interrupts were disabled the service task will
2727          * trigger a force WB.
2728          */
2729         if (skb->xmit_more  &&
2730             !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2731                                                     tx_ring->queue_index))) {
2732                 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2733                 tail_bump = false;
2734         } else if (!skb->xmit_more &&
2735                    !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2736                                                        tx_ring->queue_index)) &&
2737                    (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
2738                    (tx_ring->packet_stride < WB_STRIDE) &&
2739                    (desc_count < WB_STRIDE)) {
2740                 tx_ring->packet_stride++;
2741         } else {
2742                 tx_ring->packet_stride = 0;
2743                 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2744                 do_rs = true;
2745         }
2746         if (do_rs)
2747                 tx_ring->packet_stride = 0;
2748
2749         tx_desc->cmd_type_offset_bsz =
2750                         build_ctob(td_cmd, td_offset, size, td_tag) |
2751                         cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
2752                                                   I40E_TX_DESC_CMD_EOP) <<
2753                                                   I40E_TXD_QW1_CMD_SHIFT);
2754
2755         /* notify HW of packet */
2756         if (!tail_bump)
2757                 prefetchw(tx_desc + 1);
2758
2759         if (tail_bump) {
2760                 /* Force memory writes to complete before letting h/w
2761                  * know there are new descriptors to fetch.  (Only
2762                  * applicable for weak-ordered memory model archs,
2763                  * such as IA-64).
2764                  */
2765                 wmb();
2766                 writel(i, tx_ring->tail);
2767         }
2768
2769         return;
2770
2771 dma_error:
2772         dev_info(tx_ring->dev, "TX DMA map failed\n");
2773
2774         /* clear dma mappings for failed tx_bi map */
2775         for (;;) {
2776                 tx_bi = &tx_ring->tx_bi[i];
2777                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2778                 if (tx_bi == first)
2779                         break;
2780                 if (i == 0)
2781                         i = tx_ring->count;
2782                 i--;
2783         }
2784
2785         tx_ring->next_to_use = i;
2786 }
2787
2788 /**
2789  * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
2790  * @skb:     send buffer
2791  * @tx_ring: ring to send buffer on
2792  *
2793  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
2794  * there is not enough descriptors available in this ring since we need at least
2795  * one descriptor.
2796  **/
2797 #ifdef I40E_FCOE
2798 inline int i40e_xmit_descriptor_count(struct sk_buff *skb,
2799                                       struct i40e_ring *tx_ring)
2800 #else
2801 static inline int i40e_xmit_descriptor_count(struct sk_buff *skb,
2802                                              struct i40e_ring *tx_ring)
2803 #endif
2804 {
2805         unsigned int f;
2806         int count = 0;
2807
2808         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2809          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2810          *       + 4 desc gap to avoid the cache line where head is,
2811          *       + 1 desc for context descriptor,
2812          * otherwise try next time
2813          */
2814         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
2815                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
2816
2817         count += TXD_USE_COUNT(skb_headlen(skb));
2818         if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2819                 tx_ring->tx_stats.tx_busy++;
2820                 return 0;
2821         }
2822         return count;
2823 }
2824
2825 /**
2826  * i40e_xmit_frame_ring - Sends buffer on Tx ring
2827  * @skb:     send buffer
2828  * @tx_ring: ring to send buffer on
2829  *
2830  * Returns NETDEV_TX_OK if sent, else an error code
2831  **/
2832 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2833                                         struct i40e_ring *tx_ring)
2834 {
2835         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2836         u32 cd_tunneling = 0, cd_l2tag2 = 0;
2837         struct i40e_tx_buffer *first;
2838         u32 td_offset = 0;
2839         u32 tx_flags = 0;
2840         __be16 protocol;
2841         u32 td_cmd = 0;
2842         u8 hdr_len = 0;
2843         int tsyn;
2844         int tso;
2845
2846         /* prefetch the data, we'll need it later */
2847         prefetch(skb->data);
2848
2849         if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
2850                 return NETDEV_TX_BUSY;
2851
2852         /* prepare the xmit flags */
2853         if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2854                 goto out_drop;
2855
2856         /* obtain protocol of skb */
2857         protocol = vlan_get_protocol(skb);
2858
2859         /* record the location of the first descriptor for this packet */
2860         first = &tx_ring->tx_bi[tx_ring->next_to_use];
2861
2862         /* setup IPv4/IPv6 offloads */
2863         if (protocol == htons(ETH_P_IP))
2864                 tx_flags |= I40E_TX_FLAGS_IPV4;
2865         else if (protocol == htons(ETH_P_IPV6))
2866                 tx_flags |= I40E_TX_FLAGS_IPV6;
2867
2868         tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss);
2869
2870         if (tso < 0)
2871                 goto out_drop;
2872         else if (tso)
2873                 tx_flags |= I40E_TX_FLAGS_TSO;
2874
2875         tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
2876
2877         if (tsyn)
2878                 tx_flags |= I40E_TX_FLAGS_TSYN;
2879
2880         if (i40e_chk_linearize(skb, tx_flags)) {
2881                 if (skb_linearize(skb))
2882                         goto out_drop;
2883                 tx_ring->tx_stats.tx_linearize++;
2884         }
2885         skb_tx_timestamp(skb);
2886
2887         /* always enable CRC insertion offload */
2888         td_cmd |= I40E_TX_DESC_CMD_ICRC;
2889
2890         /* Always offload the checksum, since it's in the data descriptor */
2891         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2892                 tx_flags |= I40E_TX_FLAGS_CSUM;
2893
2894                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2895                                     tx_ring, &cd_tunneling);
2896         }
2897
2898         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2899                            cd_tunneling, cd_l2tag2);
2900
2901         /* Add Flow Director ATR if it's enabled.
2902          *
2903          * NOTE: this must always be directly before the data descriptor.
2904          */
2905         i40e_atr(tx_ring, skb, tx_flags, protocol);
2906
2907         i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2908                     td_cmd, td_offset);
2909
2910         return NETDEV_TX_OK;
2911
2912 out_drop:
2913         dev_kfree_skb_any(skb);
2914         return NETDEV_TX_OK;
2915 }
2916
2917 /**
2918  * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2919  * @skb:    send buffer
2920  * @netdev: network interface device structure
2921  *
2922  * Returns NETDEV_TX_OK if sent, else an error code
2923  **/
2924 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2925 {
2926         struct i40e_netdev_priv *np = netdev_priv(netdev);
2927         struct i40e_vsi *vsi = np->vsi;
2928         struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
2929
2930         /* hardware can't handle really short frames, hardware padding works
2931          * beyond this point
2932          */
2933         if (skb_put_padto(skb, I40E_MIN_TX_LEN))
2934                 return NETDEV_TX_OK;
2935
2936         return i40e_xmit_frame_ring(skb, tx_ring);
2937 }