1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include <linux/prefetch.h>
28 #include <net/busy_poll.h>
31 #include "i40e_prototype.h"
33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
37 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
38 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
39 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
40 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
51 struct i40e_tx_buffer *tx_buffer)
54 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
55 kfree(tx_buffer->raw_buf);
57 dev_kfree_skb_any(tx_buffer->skb);
59 if (dma_unmap_len(tx_buffer, len))
60 dma_unmap_single(ring->dev,
61 dma_unmap_addr(tx_buffer, dma),
62 dma_unmap_len(tx_buffer, len),
64 } else if (dma_unmap_len(tx_buffer, len)) {
65 dma_unmap_page(ring->dev,
66 dma_unmap_addr(tx_buffer, dma),
67 dma_unmap_len(tx_buffer, len),
70 tx_buffer->next_to_watch = NULL;
71 tx_buffer->skb = NULL;
72 dma_unmap_len_set(tx_buffer, len, 0);
73 /* tx_buffer must be completely set up in the transmit path */
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
82 unsigned long bi_size;
85 /* ring already cleared, nothing to do */
89 /* Free all the Tx ring sk_buffs */
90 for (i = 0; i < tx_ring->count; i++)
91 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
93 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
94 memset(tx_ring->tx_bi, 0, bi_size);
96 /* Zero out the descriptor ring */
97 memset(tx_ring->desc, 0, tx_ring->size);
99 tx_ring->next_to_use = 0;
100 tx_ring->next_to_clean = 0;
102 if (!tx_ring->netdev)
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
107 tx_ring->queue_index));
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
114 * Free all transmit software resources
116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
118 i40evf_clean_tx_ring(tx_ring);
119 kfree(tx_ring->tx_bi);
120 tx_ring->tx_bi = NULL;
123 dma_free_coherent(tx_ring->dev, tx_ring->size,
124 tx_ring->desc, tx_ring->dma);
125 tx_ring->desc = NULL;
130 * i40e_get_head - Retrieve head from head writeback
131 * @tx_ring: tx ring to fetch head of
133 * Returns value of Tx ring head based on value stored
134 * in head write-back location
136 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
138 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
140 return le32_to_cpu(*(volatile __le32 *)head);
144 * i40e_get_tx_pending - how many tx descriptors not processed
145 * @tx_ring: the ring of descriptors
147 * Since there is no access to the ring head register
148 * in XL710, we need to use our local copies
150 static u32 i40e_get_tx_pending(struct i40e_ring *ring)
154 head = i40e_get_head(ring);
155 tail = readl(ring->tail);
158 return (head < tail) ?
159 tail - head : (tail + ring->count - head);
165 * i40e_check_tx_hang - Is there a hang in the Tx queue
166 * @tx_ring: the ring of descriptors
168 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
170 u32 tx_done = tx_ring->stats.packets;
171 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
172 u32 tx_pending = i40e_get_tx_pending(tx_ring);
175 clear_check_for_tx_hang(tx_ring);
177 /* Check for a hung queue, but be thorough. This verifies
178 * that a transmit has been completed since the previous
179 * check AND there is at least one packet pending. The
180 * ARMED bit is set to indicate a potential hang. The
181 * bit is cleared if a pause frame is received to remove
182 * false hang detection due to PFC or 802.3x frames. By
183 * requiring this to fail twice we avoid races with
184 * PFC clearing the ARMED bit and conditions where we
185 * run the check_tx_hang logic with a transmit completion
186 * pending but without time to complete it yet.
188 if ((tx_done_old == tx_done) && tx_pending) {
189 /* make sure it is true for two checks in a row */
190 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
192 } else if (tx_done_old == tx_done &&
193 (tx_pending < I40E_MIN_DESC_PENDING) && (tx_pending > 0)) {
194 /* update completed stats and disarm the hang check */
195 tx_ring->tx_stats.tx_done_old = tx_done;
196 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
202 #define WB_STRIDE 0x3
205 * i40e_clean_tx_irq - Reclaim resources after transmit completes
206 * @tx_ring: tx ring to clean
207 * @budget: how many cleans we're allowed
209 * Returns true if there's any budget left (e.g. the clean is finished)
211 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
213 u16 i = tx_ring->next_to_clean;
214 struct i40e_tx_buffer *tx_buf;
215 struct i40e_tx_desc *tx_head;
216 struct i40e_tx_desc *tx_desc;
217 unsigned int total_packets = 0;
218 unsigned int total_bytes = 0;
220 tx_buf = &tx_ring->tx_bi[i];
221 tx_desc = I40E_TX_DESC(tx_ring, i);
224 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
227 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
229 /* if next_to_watch is not set then there is no work pending */
233 /* prevent any other reads prior to eop_desc */
234 read_barrier_depends();
236 /* we have caught up to head, no work left to do */
237 if (tx_head == tx_desc)
240 /* clear next_to_watch to prevent false hangs */
241 tx_buf->next_to_watch = NULL;
243 /* update the statistics for this packet */
244 total_bytes += tx_buf->bytecount;
245 total_packets += tx_buf->gso_segs;
248 dev_kfree_skb_any(tx_buf->skb);
250 /* unmap skb header data */
251 dma_unmap_single(tx_ring->dev,
252 dma_unmap_addr(tx_buf, dma),
253 dma_unmap_len(tx_buf, len),
256 /* clear tx_buffer data */
258 dma_unmap_len_set(tx_buf, len, 0);
260 /* unmap remaining buffers */
261 while (tx_desc != eop_desc) {
268 tx_buf = tx_ring->tx_bi;
269 tx_desc = I40E_TX_DESC(tx_ring, 0);
272 /* unmap any remaining paged data */
273 if (dma_unmap_len(tx_buf, len)) {
274 dma_unmap_page(tx_ring->dev,
275 dma_unmap_addr(tx_buf, dma),
276 dma_unmap_len(tx_buf, len),
278 dma_unmap_len_set(tx_buf, len, 0);
282 /* move us one more past the eop_desc for start of next pkt */
288 tx_buf = tx_ring->tx_bi;
289 tx_desc = I40E_TX_DESC(tx_ring, 0);
294 /* update budget accounting */
296 } while (likely(budget));
299 tx_ring->next_to_clean = i;
300 u64_stats_update_begin(&tx_ring->syncp);
301 tx_ring->stats.bytes += total_bytes;
302 tx_ring->stats.packets += total_packets;
303 u64_stats_update_end(&tx_ring->syncp);
304 tx_ring->q_vector->tx.total_bytes += total_bytes;
305 tx_ring->q_vector->tx.total_packets += total_packets;
308 !((i & WB_STRIDE) == WB_STRIDE) &&
309 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
310 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
311 tx_ring->arm_wb = true;
313 tx_ring->arm_wb = false;
315 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
316 /* schedule immediate reset if we believe we hung */
317 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
320 " next_to_use <%x>\n"
321 " next_to_clean <%x>\n",
323 tx_ring->queue_index,
324 tx_ring->next_to_use, i);
325 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
326 " time_stamp <%lx>\n"
328 tx_ring->tx_bi[i].time_stamp, jiffies);
330 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
332 dev_info(tx_ring->dev,
333 "tx hang detected on queue %d, resetting adapter\n",
334 tx_ring->queue_index);
336 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
338 /* the adapter is about to reset, no point in enabling stuff */
342 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
343 tx_ring->queue_index),
344 total_packets, total_bytes);
346 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
347 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
348 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
349 /* Make sure that anybody stopping the queue after this
350 * sees the new next_to_clean.
353 if (__netif_subqueue_stopped(tx_ring->netdev,
354 tx_ring->queue_index) &&
355 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
356 netif_wake_subqueue(tx_ring->netdev,
357 tx_ring->queue_index);
358 ++tx_ring->tx_stats.restart_queue;
366 * i40e_force_wb -Arm hardware to do a wb on noncache aligned descriptors
367 * @vsi: the VSI we care about
368 * @q_vector: the vector on which to force writeback
371 static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
373 u32 val = I40E_VFINT_DYN_CTLN_INTENA_MASK |
374 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
375 I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |
376 I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
377 /* allow 00 to be written to the index */
380 I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
385 * i40e_set_new_dynamic_itr - Find new ITR level
386 * @rc: structure containing ring performance data
388 * Stores a new ITR value based on packets and byte counts during
389 * the last interrupt. The advantage of per interrupt computation
390 * is faster updates and more accurate ITR for the current traffic
391 * pattern. Constants in this function were computed based on
392 * theoretical maximum wire speed and thresholds were set based on
393 * testing data as well as attempting to minimize response time
394 * while increasing bulk throughput.
396 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
398 enum i40e_latency_range new_latency_range = rc->latency_range;
399 u32 new_itr = rc->itr;
402 if (rc->total_packets == 0 || !rc->itr)
405 /* simple throttlerate management
406 * 0-10MB/s lowest (100000 ints/s)
407 * 10-20MB/s low (20000 ints/s)
408 * 20-1249MB/s bulk (8000 ints/s)
410 bytes_per_int = rc->total_bytes / rc->itr;
412 case I40E_LOWEST_LATENCY:
413 if (bytes_per_int > 10)
414 new_latency_range = I40E_LOW_LATENCY;
416 case I40E_LOW_LATENCY:
417 if (bytes_per_int > 20)
418 new_latency_range = I40E_BULK_LATENCY;
419 else if (bytes_per_int <= 10)
420 new_latency_range = I40E_LOWEST_LATENCY;
422 case I40E_BULK_LATENCY:
423 if (bytes_per_int <= 20)
424 rc->latency_range = I40E_LOW_LATENCY;
428 switch (new_latency_range) {
429 case I40E_LOWEST_LATENCY:
430 new_itr = I40E_ITR_100K;
432 case I40E_LOW_LATENCY:
433 new_itr = I40E_ITR_20K;
435 case I40E_BULK_LATENCY:
436 new_itr = I40E_ITR_8K;
442 if (new_itr != rc->itr) {
443 /* do an exponential smoothing */
444 new_itr = (10 * new_itr * rc->itr) /
445 ((9 * new_itr) + rc->itr);
446 rc->itr = new_itr & I40E_MAX_ITR;
450 rc->total_packets = 0;
454 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
455 * @q_vector: the vector to adjust
457 static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
459 u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
460 struct i40e_hw *hw = &q_vector->vsi->back->hw;
464 reg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1);
465 old_itr = q_vector->rx.itr;
466 i40e_set_new_dynamic_itr(&q_vector->rx);
467 if (old_itr != q_vector->rx.itr)
468 wr32(hw, reg_addr, q_vector->rx.itr);
470 reg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1);
471 old_itr = q_vector->tx.itr;
472 i40e_set_new_dynamic_itr(&q_vector->tx);
473 if (old_itr != q_vector->tx.itr)
474 wr32(hw, reg_addr, q_vector->tx.itr);
478 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
479 * @tx_ring: the tx ring to set up
481 * Return 0 on success, negative on error
483 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
485 struct device *dev = tx_ring->dev;
491 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
492 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
496 /* round up to nearest 4K */
497 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
498 /* add u32 for head writeback, align after this takes care of
499 * guaranteeing this is at least one cache line in size
501 tx_ring->size += sizeof(u32);
502 tx_ring->size = ALIGN(tx_ring->size, 4096);
503 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
504 &tx_ring->dma, GFP_KERNEL);
505 if (!tx_ring->desc) {
506 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
511 tx_ring->next_to_use = 0;
512 tx_ring->next_to_clean = 0;
516 kfree(tx_ring->tx_bi);
517 tx_ring->tx_bi = NULL;
522 * i40evf_clean_rx_ring - Free Rx buffers
523 * @rx_ring: ring to be cleaned
525 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
527 struct device *dev = rx_ring->dev;
528 struct i40e_rx_buffer *rx_bi;
529 unsigned long bi_size;
532 /* ring already cleared, nothing to do */
536 if (ring_is_ps_enabled(rx_ring)) {
537 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
539 rx_bi = &rx_ring->rx_bi[0];
540 if (rx_bi->hdr_buf) {
541 dma_free_coherent(dev,
545 for (i = 0; i < rx_ring->count; i++) {
546 rx_bi = &rx_ring->rx_bi[i];
548 rx_bi->hdr_buf = NULL;
552 /* Free all the Rx ring sk_buffs */
553 for (i = 0; i < rx_ring->count; i++) {
554 rx_bi = &rx_ring->rx_bi[i];
556 dma_unmap_single(dev,
563 dev_kfree_skb(rx_bi->skb);
567 if (rx_bi->page_dma) {
574 __free_page(rx_bi->page);
576 rx_bi->page_offset = 0;
580 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
581 memset(rx_ring->rx_bi, 0, bi_size);
583 /* Zero out the descriptor ring */
584 memset(rx_ring->desc, 0, rx_ring->size);
586 rx_ring->next_to_clean = 0;
587 rx_ring->next_to_use = 0;
591 * i40evf_free_rx_resources - Free Rx resources
592 * @rx_ring: ring to clean the resources from
594 * Free all receive software resources
596 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
598 i40evf_clean_rx_ring(rx_ring);
599 kfree(rx_ring->rx_bi);
600 rx_ring->rx_bi = NULL;
603 dma_free_coherent(rx_ring->dev, rx_ring->size,
604 rx_ring->desc, rx_ring->dma);
605 rx_ring->desc = NULL;
610 * i40evf_alloc_rx_headers - allocate rx header buffers
611 * @rx_ring: ring to alloc buffers
613 * Allocate rx header buffers for the entire ring. As these are static,
614 * this is only called when setting up a new ring.
616 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
618 struct device *dev = rx_ring->dev;
619 struct i40e_rx_buffer *rx_bi;
625 if (rx_ring->rx_bi[0].hdr_buf)
627 /* Make sure the buffers don't cross cache line boundaries. */
628 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
629 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
633 for (i = 0; i < rx_ring->count; i++) {
634 rx_bi = &rx_ring->rx_bi[i];
635 rx_bi->dma = dma + (i * buf_size);
636 rx_bi->hdr_buf = buffer + (i * buf_size);
641 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
642 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
644 * Returns 0 on success, negative on failure
646 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
648 struct device *dev = rx_ring->dev;
651 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
652 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
656 u64_stats_init(&rx_ring->syncp);
658 /* Round up to nearest 4K */
659 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
660 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
661 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
662 rx_ring->size = ALIGN(rx_ring->size, 4096);
663 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
664 &rx_ring->dma, GFP_KERNEL);
666 if (!rx_ring->desc) {
667 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
672 rx_ring->next_to_clean = 0;
673 rx_ring->next_to_use = 0;
677 kfree(rx_ring->rx_bi);
678 rx_ring->rx_bi = NULL;
683 * i40e_release_rx_desc - Store the new tail and head values
684 * @rx_ring: ring to bump
685 * @val: new head index
687 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
689 rx_ring->next_to_use = val;
690 /* Force memory writes to complete before letting h/w
691 * know there are new descriptors to fetch. (Only
692 * applicable for weak-ordered memory model archs,
696 writel(val, rx_ring->tail);
700 * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
701 * @rx_ring: ring to place buffers on
702 * @cleaned_count: number of buffers to replace
704 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
706 u16 i = rx_ring->next_to_use;
707 union i40e_rx_desc *rx_desc;
708 struct i40e_rx_buffer *bi;
710 /* do nothing if no valid netdev defined */
711 if (!rx_ring->netdev || !cleaned_count)
714 while (cleaned_count--) {
715 rx_desc = I40E_RX_DESC(rx_ring, i);
716 bi = &rx_ring->rx_bi[i];
718 if (bi->skb) /* desc is in use */
721 bi->page = alloc_page(GFP_ATOMIC);
723 rx_ring->rx_stats.alloc_page_failed++;
729 /* use a half page if we're re-using */
730 bi->page_offset ^= PAGE_SIZE / 2;
731 bi->page_dma = dma_map_page(rx_ring->dev,
736 if (dma_mapping_error(rx_ring->dev,
738 rx_ring->rx_stats.alloc_page_failed++;
744 dma_sync_single_range_for_device(rx_ring->dev,
749 /* Refresh the desc even if buffer_addrs didn't change
750 * because each write-back erases this info.
752 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
753 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
755 if (i == rx_ring->count)
760 if (rx_ring->next_to_use != i)
761 i40e_release_rx_desc(rx_ring, i);
765 * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
766 * @rx_ring: ring to place buffers on
767 * @cleaned_count: number of buffers to replace
769 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
771 u16 i = rx_ring->next_to_use;
772 union i40e_rx_desc *rx_desc;
773 struct i40e_rx_buffer *bi;
776 /* do nothing if no valid netdev defined */
777 if (!rx_ring->netdev || !cleaned_count)
780 while (cleaned_count--) {
781 rx_desc = I40E_RX_DESC(rx_ring, i);
782 bi = &rx_ring->rx_bi[i];
786 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
787 rx_ring->rx_buf_len);
789 rx_ring->rx_stats.alloc_buff_failed++;
792 /* initialize queue mapping */
793 skb_record_rx_queue(skb, rx_ring->queue_index);
798 bi->dma = dma_map_single(rx_ring->dev,
802 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
803 rx_ring->rx_stats.alloc_buff_failed++;
809 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
810 rx_desc->read.hdr_addr = 0;
812 if (i == rx_ring->count)
817 if (rx_ring->next_to_use != i)
818 i40e_release_rx_desc(rx_ring, i);
822 * i40e_receive_skb - Send a completed packet up the stack
823 * @rx_ring: rx ring in play
824 * @skb: packet to send up
825 * @vlan_tag: vlan tag for packet
827 static void i40e_receive_skb(struct i40e_ring *rx_ring,
828 struct sk_buff *skb, u16 vlan_tag)
830 struct i40e_q_vector *q_vector = rx_ring->q_vector;
831 struct i40e_vsi *vsi = rx_ring->vsi;
832 u64 flags = vsi->back->flags;
834 if (vlan_tag & VLAN_VID_MASK)
835 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
837 if (flags & I40E_FLAG_IN_NETPOLL)
840 napi_gro_receive(&q_vector->napi, skb);
844 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
845 * @vsi: the VSI we care about
846 * @skb: skb currently being received and modified
847 * @rx_status: status value of last descriptor in packet
848 * @rx_error: error value of last descriptor in packet
849 * @rx_ptype: ptype value of last descriptor in packet
851 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
857 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
858 bool ipv4 = false, ipv6 = false;
859 bool ipv4_tunnel, ipv6_tunnel;
864 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
865 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
866 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
867 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
869 skb->ip_summed = CHECKSUM_NONE;
871 /* Rx csum enabled and ip headers found? */
872 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
875 /* did the hardware decode the packet and checksum? */
876 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
879 /* both known and outer_ip must be set for the below code to work */
880 if (!(decoded.known && decoded.outer_ip))
883 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
884 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
886 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
887 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
891 (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
892 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))))
895 /* likely incorrect csum if alternate IP extension headers found */
897 rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
898 /* don't increment checksum err here, non-fatal err */
901 /* there was some L4 error, count error and punt packet to the stack */
902 if (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))
905 /* handle packets that were not able to be checksummed due
906 * to arrival speed, in this case the stack can compute
909 if (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT))
912 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
913 * it in the driver, hardware does not do it for us.
914 * Since L3L4P bit was set we assume a valid IHL value (>=5)
915 * so the total length of IPv4 header is IHL*4 bytes
916 * The UDP_0 bit *may* bet set if the *inner* header is UDP
919 skb->transport_header = skb->mac_header +
920 sizeof(struct ethhdr) +
921 (ip_hdr(skb)->ihl * 4);
923 /* Add 4 bytes for VLAN tagged packets */
924 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
925 skb->protocol == htons(ETH_P_8021AD))
928 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
929 (udp_hdr(skb)->check != 0)) {
930 rx_udp_csum = udp_csum(skb);
932 csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
934 skb_transport_offset(skb)),
935 IPPROTO_UDP, rx_udp_csum);
937 if (udp_hdr(skb)->check != csum)
940 } /* else its GRE and so no outer UDP header */
943 skb->ip_summed = CHECKSUM_UNNECESSARY;
944 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
949 vsi->back->hw_csum_rx_error++;
953 * i40e_rx_hash - returns the hash value from the Rx descriptor
954 * @ring: descriptor ring
955 * @rx_desc: specific descriptor
957 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
958 union i40e_rx_desc *rx_desc)
960 const __le64 rss_mask =
961 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
962 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
964 if ((ring->netdev->features & NETIF_F_RXHASH) &&
965 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
966 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
972 * i40e_ptype_to_hash - get a hash type
973 * @ptype: the ptype value from the descriptor
975 * Returns a hash type to be used by skb_set_hash
977 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
979 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
982 return PKT_HASH_TYPE_NONE;
984 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
985 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
986 return PKT_HASH_TYPE_L4;
987 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
988 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
989 return PKT_HASH_TYPE_L3;
991 return PKT_HASH_TYPE_L2;
995 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
996 * @rx_ring: rx ring to clean
997 * @budget: how many cleans we're allowed
999 * Returns true if there's any budget left (e.g. the clean is finished)
1001 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
1003 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1004 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1005 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1006 const int current_node = numa_node_id();
1007 struct i40e_vsi *vsi = rx_ring->vsi;
1008 u16 i = rx_ring->next_to_clean;
1009 union i40e_rx_desc *rx_desc;
1010 u32 rx_error, rx_status;
1015 struct i40e_rx_buffer *rx_bi;
1016 struct sk_buff *skb;
1018 /* return some buffers to hardware, one at a time is too slow */
1019 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1020 i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
1024 i = rx_ring->next_to_clean;
1025 rx_desc = I40E_RX_DESC(rx_ring, i);
1026 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1027 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1028 I40E_RXD_QW1_STATUS_SHIFT;
1030 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1033 /* This memory barrier is needed to keep us from reading
1034 * any other fields out of the rx_desc until we know the
1038 rx_bi = &rx_ring->rx_bi[i];
1041 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1042 rx_ring->rx_hdr_len);
1044 rx_ring->rx_stats.alloc_buff_failed++;
1048 /* initialize queue mapping */
1049 skb_record_rx_queue(skb, rx_ring->queue_index);
1050 /* we are reusing so sync this buffer for CPU use */
1051 dma_sync_single_range_for_cpu(rx_ring->dev,
1054 rx_ring->rx_hdr_len,
1057 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1058 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1059 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1060 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1061 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1062 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1064 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1065 I40E_RXD_QW1_ERROR_SHIFT;
1066 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1067 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1069 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1070 I40E_RXD_QW1_PTYPE_SHIFT;
1071 prefetch(rx_bi->page);
1074 if (rx_hbo || rx_sph) {
1077 len = I40E_RX_HDR_SIZE;
1079 len = rx_header_len;
1080 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1081 } else if (skb->len == 0) {
1084 len = (rx_packet_len > skb_headlen(skb) ?
1085 skb_headlen(skb) : rx_packet_len);
1086 memcpy(__skb_put(skb, len),
1087 rx_bi->page + rx_bi->page_offset,
1089 rx_bi->page_offset += len;
1090 rx_packet_len -= len;
1093 /* Get the rest of the data if this was a header split */
1094 if (rx_packet_len) {
1095 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1100 skb->len += rx_packet_len;
1101 skb->data_len += rx_packet_len;
1102 skb->truesize += rx_packet_len;
1104 if ((page_count(rx_bi->page) == 1) &&
1105 (page_to_nid(rx_bi->page) == current_node))
1106 get_page(rx_bi->page);
1110 dma_unmap_page(rx_ring->dev,
1114 rx_bi->page_dma = 0;
1116 I40E_RX_INCREMENT(rx_ring, i);
1119 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1120 struct i40e_rx_buffer *next_buffer;
1122 next_buffer = &rx_ring->rx_bi[i];
1123 next_buffer->skb = skb;
1124 rx_ring->rx_stats.non_eop_descs++;
1128 /* ERR_MASK will only have valid bits if EOP set */
1129 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1130 dev_kfree_skb_any(skb);
1134 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1135 i40e_ptype_to_hash(rx_ptype));
1136 /* probably a little skewed due to removing CRC */
1137 total_rx_bytes += skb->len;
1140 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1142 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1144 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1145 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1148 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1149 dev_kfree_skb_any(skb);
1153 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1154 i40e_receive_skb(rx_ring, skb, vlan_tag);
1156 rx_desc->wb.qword1.status_error_len = 0;
1158 } while (likely(total_rx_packets < budget));
1160 u64_stats_update_begin(&rx_ring->syncp);
1161 rx_ring->stats.packets += total_rx_packets;
1162 rx_ring->stats.bytes += total_rx_bytes;
1163 u64_stats_update_end(&rx_ring->syncp);
1164 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1165 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1167 return total_rx_packets;
1171 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1172 * @rx_ring: rx ring to clean
1173 * @budget: how many cleans we're allowed
1175 * Returns number of packets cleaned
1177 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1179 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1180 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1181 struct i40e_vsi *vsi = rx_ring->vsi;
1182 union i40e_rx_desc *rx_desc;
1183 u32 rx_error, rx_status;
1190 struct i40e_rx_buffer *rx_bi;
1191 struct sk_buff *skb;
1193 /* return some buffers to hardware, one at a time is too slow */
1194 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1195 i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1199 i = rx_ring->next_to_clean;
1200 rx_desc = I40E_RX_DESC(rx_ring, i);
1201 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1202 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1203 I40E_RXD_QW1_STATUS_SHIFT;
1205 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1208 /* This memory barrier is needed to keep us from reading
1209 * any other fields out of the rx_desc until we know the
1214 rx_bi = &rx_ring->rx_bi[i];
1216 prefetch(skb->data);
1218 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1219 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1221 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1222 I40E_RXD_QW1_ERROR_SHIFT;
1223 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1225 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1226 I40E_RXD_QW1_PTYPE_SHIFT;
1230 /* Get the header and possibly the whole packet
1231 * If this is an skb from previous receive dma will be 0
1233 skb_put(skb, rx_packet_len);
1234 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1238 I40E_RX_INCREMENT(rx_ring, i);
1241 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1242 rx_ring->rx_stats.non_eop_descs++;
1246 /* ERR_MASK will only have valid bits if EOP set */
1247 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1248 dev_kfree_skb_any(skb);
1249 /* TODO: shouldn't we increment a counter indicating the
1255 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1256 i40e_ptype_to_hash(rx_ptype));
1257 /* probably a little skewed due to removing CRC */
1258 total_rx_bytes += skb->len;
1261 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1263 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1265 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1266 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1268 i40e_receive_skb(rx_ring, skb, vlan_tag);
1270 rx_desc->wb.qword1.status_error_len = 0;
1271 } while (likely(total_rx_packets < budget));
1273 u64_stats_update_begin(&rx_ring->syncp);
1274 rx_ring->stats.packets += total_rx_packets;
1275 rx_ring->stats.bytes += total_rx_bytes;
1276 u64_stats_update_end(&rx_ring->syncp);
1277 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1278 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1280 return total_rx_packets;
1284 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1285 * @napi: napi struct with our devices info in it
1286 * @budget: amount of work driver is allowed to do this pass, in packets
1288 * This function will clean all queues associated with a q_vector.
1290 * Returns the amount of work done
1292 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1294 struct i40e_q_vector *q_vector =
1295 container_of(napi, struct i40e_q_vector, napi);
1296 struct i40e_vsi *vsi = q_vector->vsi;
1297 struct i40e_ring *ring;
1298 bool clean_complete = true;
1299 bool arm_wb = false;
1300 int budget_per_ring;
1303 if (test_bit(__I40E_DOWN, &vsi->state)) {
1304 napi_complete(napi);
1308 /* Since the actual Tx work is minimal, we can give the Tx a larger
1309 * budget and be more aggressive about cleaning up the Tx descriptors.
1311 i40e_for_each_ring(ring, q_vector->tx) {
1312 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1313 arm_wb |= ring->arm_wb;
1316 /* We attempt to distribute budget to each Rx queue fairly, but don't
1317 * allow the budget to go below 1 because that would exit polling early.
1319 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1321 i40e_for_each_ring(ring, q_vector->rx) {
1322 if (ring_is_ps_enabled(ring))
1323 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1325 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1326 /* if we didn't clean as many as budgeted, we must be done */
1327 clean_complete &= (budget_per_ring != cleaned);
1330 /* If work not completed, return budget and polling will return */
1331 if (!clean_complete) {
1333 i40e_force_wb(vsi, q_vector);
1337 /* Work is done so exit the polling mode and re-enable the interrupt */
1338 napi_complete(napi);
1339 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1340 ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1341 i40e_update_dynamic_itr(q_vector);
1343 if (!test_bit(__I40E_DOWN, &vsi->state))
1344 i40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx);
1350 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1352 * @tx_ring: ring to send buffer on
1353 * @flags: the tx flags to be set
1355 * Checks the skb and set up correspondingly several generic transmit flags
1356 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1358 * Returns error code indicate the frame should be dropped upon error and the
1359 * otherwise returns 0 to indicate the flags has been set properly.
1361 static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
1362 struct i40e_ring *tx_ring,
1365 __be16 protocol = skb->protocol;
1368 if (protocol == htons(ETH_P_8021Q) &&
1369 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1370 /* When HW VLAN acceleration is turned off by the user the
1371 * stack sets the protocol to 8021q so that the driver
1372 * can take any steps required to support the SW only
1373 * VLAN handling. In our case the driver doesn't need
1374 * to take any further steps so just set the protocol
1375 * to the encapsulated ethertype.
1377 skb->protocol = vlan_get_protocol(skb);
1381 /* if we have a HW VLAN tag being added, default to the HW one */
1382 if (skb_vlan_tag_present(skb)) {
1383 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1384 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1385 /* else if it is a SW VLAN, check the next protocol and store the tag */
1386 } else if (protocol == htons(ETH_P_8021Q)) {
1387 struct vlan_hdr *vhdr, _vhdr;
1388 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1392 protocol = vhdr->h_vlan_encapsulated_proto;
1393 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1394 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1403 * i40e_tso - set up the tso context descriptor
1404 * @tx_ring: ptr to the ring to send
1405 * @skb: ptr to the skb we're sending
1406 * @hdr_len: ptr to the size of the packet header
1407 * @cd_tunneling: ptr to context descriptor bits
1409 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1411 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1412 u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
1415 u32 cd_cmd, cd_tso_len, cd_mss;
1416 struct ipv6hdr *ipv6h;
1417 struct tcphdr *tcph;
1422 if (!skb_is_gso(skb))
1425 err = skb_cow_head(skb, 0);
1429 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1430 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1432 if (iph->version == 4) {
1433 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1436 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1438 } else if (ipv6h->version == 6) {
1439 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1440 ipv6h->payload_len = 0;
1441 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1445 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1446 *hdr_len = (skb->encapsulation
1447 ? (skb_inner_transport_header(skb) - skb->data)
1448 : skb_transport_offset(skb)) + l4len;
1450 /* find the field values */
1451 cd_cmd = I40E_TX_CTX_DESC_TSO;
1452 cd_tso_len = skb->len - *hdr_len;
1453 cd_mss = skb_shinfo(skb)->gso_size;
1454 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1456 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1457 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1462 * i40e_tx_enable_csum - Enable Tx checksum offloads
1464 * @tx_flags: pointer to Tx flags currently set
1465 * @td_cmd: Tx descriptor command bits to set
1466 * @td_offset: Tx descriptor header offsets to set
1467 * @cd_tunneling: ptr to context desc bits
1469 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1470 u32 *td_cmd, u32 *td_offset,
1471 struct i40e_ring *tx_ring,
1474 struct ipv6hdr *this_ipv6_hdr;
1475 unsigned int this_tcp_hdrlen;
1476 struct iphdr *this_ip_hdr;
1477 u32 network_hdr_len;
1481 if (skb->encapsulation) {
1482 switch (ip_hdr(skb)->protocol) {
1484 l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1485 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1490 network_hdr_len = skb_inner_network_header_len(skb);
1491 this_ip_hdr = inner_ip_hdr(skb);
1492 this_ipv6_hdr = inner_ipv6_hdr(skb);
1493 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1495 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1496 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1497 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1498 ip_hdr(skb)->check = 0;
1501 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1503 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1504 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1505 if (*tx_flags & I40E_TX_FLAGS_TSO)
1506 ip_hdr(skb)->check = 0;
1509 /* Now set the ctx descriptor fields */
1510 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1511 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1513 ((skb_inner_network_offset(skb) -
1514 skb_transport_offset(skb)) >> 1) <<
1515 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1516 if (this_ip_hdr->version == 6) {
1517 *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1518 *tx_flags |= I40E_TX_FLAGS_IPV6;
1523 network_hdr_len = skb_network_header_len(skb);
1524 this_ip_hdr = ip_hdr(skb);
1525 this_ipv6_hdr = ipv6_hdr(skb);
1526 this_tcp_hdrlen = tcp_hdrlen(skb);
1529 /* Enable IP checksum offloads */
1530 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1531 l4_hdr = this_ip_hdr->protocol;
1532 /* the stack computes the IP header already, the only time we
1533 * need the hardware to recompute it is in the case of TSO.
1535 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1536 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1537 this_ip_hdr->check = 0;
1539 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1541 /* Now set the td_offset for IP header length */
1542 *td_offset = (network_hdr_len >> 2) <<
1543 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1544 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1545 l4_hdr = this_ipv6_hdr->nexthdr;
1546 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1547 /* Now set the td_offset for IP header length */
1548 *td_offset = (network_hdr_len >> 2) <<
1549 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1551 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1552 *td_offset |= (skb_network_offset(skb) >> 1) <<
1553 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1555 /* Enable L4 checksum offloads */
1558 /* enable checksum offloads */
1559 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1560 *td_offset |= (this_tcp_hdrlen >> 2) <<
1561 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1564 /* enable SCTP checksum offload */
1565 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1566 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1567 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1570 /* enable UDP checksum offload */
1571 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1572 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1573 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1581 * i40e_create_tx_ctx Build the Tx context descriptor
1582 * @tx_ring: ring to create the descriptor on
1583 * @cd_type_cmd_tso_mss: Quad Word 1
1584 * @cd_tunneling: Quad Word 0 - bits 0-31
1585 * @cd_l2tag2: Quad Word 0 - bits 32-63
1587 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1588 const u64 cd_type_cmd_tso_mss,
1589 const u32 cd_tunneling, const u32 cd_l2tag2)
1591 struct i40e_tx_context_desc *context_desc;
1592 int i = tx_ring->next_to_use;
1594 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1595 !cd_tunneling && !cd_l2tag2)
1598 /* grab the next descriptor */
1599 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1602 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1604 /* cpu_to_le32 and assign to struct fields */
1605 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1606 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1607 context_desc->rsvd = cpu_to_le16(0);
1608 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1612 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1614 * @tx_flags: collected send information
1615 * @hdr_len: size of the packet header
1617 * Note: Our HW can't scatter-gather more than 8 fragments to build
1618 * a packet on the wire and so we need to figure out the cases where we
1619 * need to linearize the skb.
1621 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags,
1624 struct skb_frag_struct *frag;
1625 bool linearize = false;
1626 unsigned int size = 0;
1630 num_frags = skb_shinfo(skb)->nr_frags;
1631 gso_segs = skb_shinfo(skb)->gso_segs;
1633 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1636 if (num_frags < (I40E_MAX_BUFFER_TXD))
1637 goto linearize_chk_done;
1638 /* try the simple math, if we have too many frags per segment */
1639 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1640 I40E_MAX_BUFFER_TXD) {
1642 goto linearize_chk_done;
1644 frag = &skb_shinfo(skb)->frags[0];
1646 /* we might still have more fragments per segment */
1648 size += skb_frag_size(frag);
1650 if (j == I40E_MAX_BUFFER_TXD) {
1651 if (size < skb_shinfo(skb)->gso_size) {
1656 size -= skb_shinfo(skb)->gso_size;
1662 } while (num_frags);
1664 if (num_frags >= I40E_MAX_BUFFER_TXD)
1673 * i40e_tx_map - Build the Tx descriptor
1674 * @tx_ring: ring to send buffer on
1676 * @first: first buffer info buffer to use
1677 * @tx_flags: collected send information
1678 * @hdr_len: size of the packet header
1679 * @td_cmd: the command field in the descriptor
1680 * @td_offset: offset for checksum or crc
1682 static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1683 struct i40e_tx_buffer *first, u32 tx_flags,
1684 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1686 unsigned int data_len = skb->data_len;
1687 unsigned int size = skb_headlen(skb);
1688 struct skb_frag_struct *frag;
1689 struct i40e_tx_buffer *tx_bi;
1690 struct i40e_tx_desc *tx_desc;
1691 u16 i = tx_ring->next_to_use;
1696 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1697 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1698 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1699 I40E_TX_FLAGS_VLAN_SHIFT;
1702 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1703 gso_segs = skb_shinfo(skb)->gso_segs;
1707 /* multiply data chunks by size of headers */
1708 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1709 first->gso_segs = gso_segs;
1711 first->tx_flags = tx_flags;
1713 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1715 tx_desc = I40E_TX_DESC(tx_ring, i);
1718 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1719 if (dma_mapping_error(tx_ring->dev, dma))
1722 /* record length, and DMA address */
1723 dma_unmap_len_set(tx_bi, len, size);
1724 dma_unmap_addr_set(tx_bi, dma, dma);
1726 tx_desc->buffer_addr = cpu_to_le64(dma);
1728 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1729 tx_desc->cmd_type_offset_bsz =
1730 build_ctob(td_cmd, td_offset,
1731 I40E_MAX_DATA_PER_TXD, td_tag);
1735 if (i == tx_ring->count) {
1736 tx_desc = I40E_TX_DESC(tx_ring, 0);
1740 dma += I40E_MAX_DATA_PER_TXD;
1741 size -= I40E_MAX_DATA_PER_TXD;
1743 tx_desc->buffer_addr = cpu_to_le64(dma);
1746 if (likely(!data_len))
1749 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1754 if (i == tx_ring->count) {
1755 tx_desc = I40E_TX_DESC(tx_ring, 0);
1759 size = skb_frag_size(frag);
1762 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1765 tx_bi = &tx_ring->tx_bi[i];
1768 /* Place RS bit on last descriptor of any packet that spans across the
1769 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1771 #define WB_STRIDE 0x3
1772 if (((i & WB_STRIDE) != WB_STRIDE) &&
1773 (first <= &tx_ring->tx_bi[i]) &&
1774 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1775 tx_desc->cmd_type_offset_bsz =
1776 build_ctob(td_cmd, td_offset, size, td_tag) |
1777 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1778 I40E_TXD_QW1_CMD_SHIFT);
1780 tx_desc->cmd_type_offset_bsz =
1781 build_ctob(td_cmd, td_offset, size, td_tag) |
1782 cpu_to_le64((u64)I40E_TXD_CMD <<
1783 I40E_TXD_QW1_CMD_SHIFT);
1786 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1787 tx_ring->queue_index),
1790 /* set the timestamp */
1791 first->time_stamp = jiffies;
1793 /* Force memory writes to complete before letting h/w
1794 * know there are new descriptors to fetch. (Only
1795 * applicable for weak-ordered memory model archs,
1800 /* set next_to_watch value indicating a packet is present */
1801 first->next_to_watch = tx_desc;
1804 if (i == tx_ring->count)
1807 tx_ring->next_to_use = i;
1809 /* notify HW of packet */
1810 writel(i, tx_ring->tail);
1815 dev_info(tx_ring->dev, "TX DMA map failed\n");
1817 /* clear dma mappings for failed tx_bi map */
1819 tx_bi = &tx_ring->tx_bi[i];
1820 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1828 tx_ring->next_to_use = i;
1832 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1833 * @tx_ring: the ring to be checked
1834 * @size: the size buffer we want to assure is available
1836 * Returns -EBUSY if a stop is needed, else 0
1838 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1840 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1841 /* Memory barrier before checking head and tail */
1844 /* Check again in a case another CPU has just made room available. */
1845 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1848 /* A reprieve! - use start_queue because it doesn't call schedule */
1849 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1850 ++tx_ring->tx_stats.restart_queue;
1855 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1856 * @tx_ring: the ring to be checked
1857 * @size: the size buffer we want to assure is available
1859 * Returns 0 if stop is not needed
1861 static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1863 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1865 return __i40e_maybe_stop_tx(tx_ring, size);
1869 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1871 * @tx_ring: ring to send buffer on
1873 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1874 * there is not enough descriptors available in this ring since we need at least
1877 static int i40e_xmit_descriptor_count(struct sk_buff *skb,
1878 struct i40e_ring *tx_ring)
1883 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1884 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1885 * + 4 desc gap to avoid the cache line where head is,
1886 * + 1 desc for context descriptor,
1887 * otherwise try next time
1889 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1890 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1892 count += TXD_USE_COUNT(skb_headlen(skb));
1893 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1894 tx_ring->tx_stats.tx_busy++;
1901 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1903 * @tx_ring: ring to send buffer on
1905 * Returns NETDEV_TX_OK if sent, else an error code
1907 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1908 struct i40e_ring *tx_ring)
1910 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1911 u32 cd_tunneling = 0, cd_l2tag2 = 0;
1912 struct i40e_tx_buffer *first;
1919 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
1920 return NETDEV_TX_BUSY;
1922 /* prepare the xmit flags */
1923 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1926 /* obtain protocol of skb */
1927 protocol = vlan_get_protocol(skb);
1929 /* record the location of the first descriptor for this packet */
1930 first = &tx_ring->tx_bi[tx_ring->next_to_use];
1932 /* setup IPv4/IPv6 offloads */
1933 if (protocol == htons(ETH_P_IP))
1934 tx_flags |= I40E_TX_FLAGS_IPV4;
1935 else if (protocol == htons(ETH_P_IPV6))
1936 tx_flags |= I40E_TX_FLAGS_IPV6;
1938 tso = i40e_tso(tx_ring, skb, &hdr_len,
1939 &cd_type_cmd_tso_mss, &cd_tunneling);
1944 tx_flags |= I40E_TX_FLAGS_TSO;
1946 if (i40e_chk_linearize(skb, tx_flags, hdr_len))
1947 if (skb_linearize(skb))
1950 skb_tx_timestamp(skb);
1952 /* always enable CRC insertion offload */
1953 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1955 /* Always offload the checksum, since it's in the data descriptor */
1956 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1957 tx_flags |= I40E_TX_FLAGS_CSUM;
1959 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
1960 tx_ring, &cd_tunneling);
1963 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1964 cd_tunneling, cd_l2tag2);
1966 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1969 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
1971 return NETDEV_TX_OK;
1974 dev_kfree_skb_any(skb);
1975 return NETDEV_TX_OK;
1979 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1981 * @netdev: network interface device structure
1983 * Returns NETDEV_TX_OK if sent, else an error code
1985 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1987 struct i40evf_adapter *adapter = netdev_priv(netdev);
1988 struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1990 /* hardware can't handle really short frames, hardware padding works
1993 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1994 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1995 return NETDEV_TX_OK;
1996 skb->len = I40E_MIN_TX_LEN;
1997 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2000 return i40e_xmit_frame_ring(skb, tx_ring);