drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2016 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 dev_kfree_skb_any(tx_buffer->skb);
  55                 if (dma_unmap_len(tx_buffer, len))
  56                         dma_unmap_single(ring->dev,
  57                                          dma_unmap_addr(tx_buffer, dma),
  58                                          dma_unmap_len(tx_buffer, len),
  59                                          DMA_TO_DEVICE);
  60         } else if (dma_unmap_len(tx_buffer, len)) {
  61                 dma_unmap_page(ring->dev,
  62                                dma_unmap_addr(tx_buffer, dma),
  63                                dma_unmap_len(tx_buffer, len),
  64                                DMA_TO_DEVICE);
  65         }
  66
  67         if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  68                 kfree(tx_buffer->raw_buf);
  69
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40evf_get_tx_pending - how many Tx descriptors not processed
 131  * @tx_ring: the ring of descriptors
 132  *
 133  * Since there is no access to the ring head register
 134  * in XL710, we need to use our local copies
 135  **/
 136 u32 i40evf_get_tx_pending(struct i40e_ring *ring)
 137 {
 138         u32 head, tail;
 139
 140         head = i40e_get_head(ring);
 141         tail = readl(ring->tail);
 142
 143         if (head != tail)
 144                 return (head < tail) ?
 145                         tail - head : (tail + ring->count - head);
 146
 147         return 0;
 148 }
 149
 150 #define WB_STRIDE 0x3
 151
 152 /**
 153  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 154  * @tx_ring:  tx ring to clean
 155  * @budget:   how many cleans we're allowed
 156  *
 157  * Returns true if there's any budget left (e.g. the clean is finished)
 158  **/
 159 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 160 {
 161         u16 i = tx_ring->next_to_clean;
 162         struct i40e_tx_buffer *tx_buf;
 163         struct i40e_tx_desc *tx_head;
 164         struct i40e_tx_desc *tx_desc;
 165         unsigned int total_packets = 0;
 166         unsigned int total_bytes = 0;
 167
 168         tx_buf = &tx_ring->tx_bi[i];
 169         tx_desc = I40E_TX_DESC(tx_ring, i);
 170         i -= tx_ring->count;
 171
 172         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 173
 174         do {
 175                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 176
 177                 /* if next_to_watch is not set then there is no work pending */
 178                 if (!eop_desc)
 179                         break;
 180
 181                 /* prevent any other reads prior to eop_desc */
 182                 read_barrier_depends();
 183
 184                 /* we have caught up to head, no work left to do */
 185                 if (tx_head == tx_desc)
 186                         break;
 187
 188                 /* clear next_to_watch to prevent false hangs */
 189                 tx_buf->next_to_watch = NULL;
 190
 191                 /* update the statistics for this packet */
 192                 total_bytes += tx_buf->bytecount;
 193                 total_packets += tx_buf->gso_segs;
 194
 195                 /* free the skb */
 196                 dev_kfree_skb_any(tx_buf->skb);
 197
 198                 /* unmap skb header data */
 199                 dma_unmap_single(tx_ring->dev,
 200                                  dma_unmap_addr(tx_buf, dma),
 201                                  dma_unmap_len(tx_buf, len),
 202                                  DMA_TO_DEVICE);
 203
 204                 /* clear tx_buffer data */
 205                 tx_buf->skb = NULL;
 206                 dma_unmap_len_set(tx_buf, len, 0);
 207
 208                 /* unmap remaining buffers */
 209                 while (tx_desc != eop_desc) {
 210
 211                         tx_buf++;
 212                         tx_desc++;
 213                         i++;
 214                         if (unlikely(!i)) {
 215                                 i -= tx_ring->count;
 216                                 tx_buf = tx_ring->tx_bi;
 217                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 218                         }
 219
 220                         /* unmap any remaining paged data */
 221                         if (dma_unmap_len(tx_buf, len)) {
 222                                 dma_unmap_page(tx_ring->dev,
 223                                                dma_unmap_addr(tx_buf, dma),
 224                                                dma_unmap_len(tx_buf, len),
 225                                                DMA_TO_DEVICE);
 226                                 dma_unmap_len_set(tx_buf, len, 0);
 227                         }
 228                 }
 229
 230                 /* move us one more past the eop_desc for start of next pkt */
 231                 tx_buf++;
 232                 tx_desc++;
 233                 i++;
 234                 if (unlikely(!i)) {
 235                         i -= tx_ring->count;
 236                         tx_buf = tx_ring->tx_bi;
 237                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 238                 }
 239
 240                 prefetch(tx_desc);
 241
 242                 /* update budget accounting */
 243                 budget--;
 244         } while (likely(budget));
 245
 246         i += tx_ring->count;
 247         tx_ring->next_to_clean = i;
 248         u64_stats_update_begin(&tx_ring->syncp);
 249         tx_ring->stats.bytes += total_bytes;
 250         tx_ring->stats.packets += total_packets;
 251         u64_stats_update_end(&tx_ring->syncp);
 252         tx_ring->q_vector->tx.total_bytes += total_bytes;
 253         tx_ring->q_vector->tx.total_packets += total_packets;
 254
 255         if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 256                 unsigned int j = 0;
 257                 /* check to see if there are < 4 descriptors
 258                  * waiting to be written back, then kick the hardware to force
 259                  * them to be written back in case we stay in NAPI.
 260                  * In this mode on X722 we do not enable Interrupt.
 261                  */
 262                 j = i40evf_get_tx_pending(tx_ring);
 263
 264                 if (budget &&
 265                     ((j / (WB_STRIDE + 1)) == 0) && (j > 0) &&
 266                     !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 267                     (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 268                         tx_ring->arm_wb = true;
 269         }
 270
 271         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 272                                                       tx_ring->queue_index),
 273                                   total_packets, total_bytes);
 274
 275 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 276         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 277                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 278                 /* Make sure that anybody stopping the queue after this
 279                  * sees the new next_to_clean.
 280                  */
 281                 smp_mb();
 282                 if (__netif_subqueue_stopped(tx_ring->netdev,
 283                                              tx_ring->queue_index) &&
 284                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 285                         netif_wake_subqueue(tx_ring->netdev,
 286                                             tx_ring->queue_index);
 287                         ++tx_ring->tx_stats.restart_queue;
 288                 }
 289         }
 290
 291         return !!budget;
 292 }
 293
 294 /**
 295  * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
 296  * @vsi: the VSI we care about
 297  * @q_vector: the vector on which to enable writeback
 298  *
 299  **/
 300 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
 301                                   struct i40e_q_vector *q_vector)
 302 {
 303         u16 flags = q_vector->tx.ring[0].flags;
 304         u32 val;
 305
 306         if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
 307                 return;
 308
 309         if (q_vector->arm_wb_state)
 310                 return;
 311
 312         val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
 313               I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
 314
 315         wr32(&vsi->back->hw,
 316              I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 317                                   vsi->base_vector - 1), val);
 318         q_vector->arm_wb_state = true;
 319 }
 320
 321 /**
 322  * i40evf_force_wb - Issue SW Interrupt so HW does a wb
 323  * @vsi: the VSI we care about
 324  * @q_vector: the vector  on which to force writeback
 325  *
 326  **/
 327 void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 328 {
 329         u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 330                   I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 331                   I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 332                   I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
 333                   /* allow 00 to be written to the index */;
 334
 335         wr32(&vsi->back->hw,
 336              I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
 337              val);
 338 }
 339
 340 /**
 341  * i40e_set_new_dynamic_itr - Find new ITR level
 342  * @rc: structure containing ring performance data
 343  *
 344  * Returns true if ITR changed, false if not
 345  *
 346  * Stores a new ITR value based on packets and byte counts during
 347  * the last interrupt.  The advantage of per interrupt computation
 348  * is faster updates and more accurate ITR for the current traffic
 349  * pattern.  Constants in this function were computed based on
 350  * theoretical maximum wire speed and thresholds were set based on
 351  * testing data as well as attempting to minimize response time
 352  * while increasing bulk throughput.
 353  **/
 354 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 355 {
 356         enum i40e_latency_range new_latency_range = rc->latency_range;
 357         struct i40e_q_vector *qv = rc->ring->q_vector;
 358         u32 new_itr = rc->itr;
 359         int bytes_per_int;
 360         int usecs;
 361
 362         if (rc->total_packets == 0 || !rc->itr)
 363                 return false;
 364
 365         /* simple throttlerate management
 366          *   0-10MB/s   lowest (50000 ints/s)
 367          *  10-20MB/s   low    (20000 ints/s)
 368          *  20-1249MB/s bulk   (18000 ints/s)
 369          *  > 40000 Rx packets per second (8000 ints/s)
 370          *
 371          * The math works out because the divisor is in 10^(-6) which
 372          * turns the bytes/us input value into MB/s values, but
 373          * make sure to use usecs, as the register values written
 374          * are in 2 usec increments in the ITR registers, and make sure
 375          * to use the smoothed values that the countdown timer gives us.
 376          */
 377         usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
 378         bytes_per_int = rc->total_bytes / usecs;
 379
 380         switch (new_latency_range) {
 381         case I40E_LOWEST_LATENCY:
 382                 if (bytes_per_int > 10)
 383                         new_latency_range = I40E_LOW_LATENCY;
 384                 break;
 385         case I40E_LOW_LATENCY:
 386                 if (bytes_per_int > 20)
 387                         new_latency_range = I40E_BULK_LATENCY;
 388                 else if (bytes_per_int <= 10)
 389                         new_latency_range = I40E_LOWEST_LATENCY;
 390                 break;
 391         case I40E_BULK_LATENCY:
 392         case I40E_ULTRA_LATENCY:
 393         default:
 394                 if (bytes_per_int <= 20)
 395                         new_latency_range = I40E_LOW_LATENCY;
 396                 break;
 397         }
 398
 399         /* this is to adjust RX more aggressively when streaming small
 400          * packets.  The value of 40000 was picked as it is just beyond
 401          * what the hardware can receive per second if in low latency
 402          * mode.
 403          */
 404 #define RX_ULTRA_PACKET_RATE 40000
 405
 406         if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
 407             (&qv->rx == rc))
 408                 new_latency_range = I40E_ULTRA_LATENCY;
 409
 410         rc->latency_range = new_latency_range;
 411
 412         switch (new_latency_range) {
 413         case I40E_LOWEST_LATENCY:
 414                 new_itr = I40E_ITR_50K;
 415                 break;
 416         case I40E_LOW_LATENCY:
 417                 new_itr = I40E_ITR_20K;
 418                 break;
 419         case I40E_BULK_LATENCY:
 420                 new_itr = I40E_ITR_18K;
 421                 break;
 422         case I40E_ULTRA_LATENCY:
 423                 new_itr = I40E_ITR_8K;
 424                 break;
 425         default:
 426                 break;
 427         }
 428
 429         rc->total_bytes = 0;
 430         rc->total_packets = 0;
 431
 432         if (new_itr != rc->itr) {
 433                 rc->itr = new_itr;
 434                 return true;
 435         }
 436
 437         return false;
 438 }
 439
 440 /**
 441  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 442  * @tx_ring: the tx ring to set up
 443  *
 444  * Return 0 on success, negative on error
 445  **/
 446 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 447 {
 448         struct device *dev = tx_ring->dev;
 449         int bi_size;
 450
 451         if (!dev)
 452                 return -ENOMEM;
 453
 454         /* warn if we are about to overwrite the pointer */
 455         WARN_ON(tx_ring->tx_bi);
 456         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 457         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 458         if (!tx_ring->tx_bi)
 459                 goto err;
 460
 461         /* round up to nearest 4K */
 462         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 463         /* add u32 for head writeback, align after this takes care of
 464          * guaranteeing this is at least one cache line in size
 465          */
 466         tx_ring->size += sizeof(u32);
 467         tx_ring->size = ALIGN(tx_ring->size, 4096);
 468         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 469                                            &tx_ring->dma, GFP_KERNEL);
 470         if (!tx_ring->desc) {
 471                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 472                          tx_ring->size);
 473                 goto err;
 474         }
 475
 476         tx_ring->next_to_use = 0;
 477         tx_ring->next_to_clean = 0;
 478         return 0;
 479
 480 err:
 481         kfree(tx_ring->tx_bi);
 482         tx_ring->tx_bi = NULL;
 483         return -ENOMEM;
 484 }
 485
 486 /**
 487  * i40evf_clean_rx_ring - Free Rx buffers
 488  * @rx_ring: ring to be cleaned
 489  **/
 490 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 491 {
 492         struct device *dev = rx_ring->dev;
 493         struct i40e_rx_buffer *rx_bi;
 494         unsigned long bi_size;
 495         u16 i;
 496
 497         /* ring already cleared, nothing to do */
 498         if (!rx_ring->rx_bi)
 499                 return;
 500
 501         if (ring_is_ps_enabled(rx_ring)) {
 502                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 503
 504                 rx_bi = &rx_ring->rx_bi[0];
 505                 if (rx_bi->hdr_buf) {
 506                         dma_free_coherent(dev,
 507                                           bufsz,
 508                                           rx_bi->hdr_buf,
 509                                           rx_bi->dma);
 510                         for (i = 0; i < rx_ring->count; i++) {
 511                                 rx_bi = &rx_ring->rx_bi[i];
 512                                 rx_bi->dma = 0;
 513                                 rx_bi->hdr_buf = NULL;
 514                         }
 515                 }
 516         }
 517         /* Free all the Rx ring sk_buffs */
 518         for (i = 0; i < rx_ring->count; i++) {
 519                 rx_bi = &rx_ring->rx_bi[i];
 520                 if (rx_bi->dma) {
 521                         dma_unmap_single(dev,
 522                                          rx_bi->dma,
 523                                          rx_ring->rx_buf_len,
 524                                          DMA_FROM_DEVICE);
 525                         rx_bi->dma = 0;
 526                 }
 527                 if (rx_bi->skb) {
 528                         dev_kfree_skb(rx_bi->skb);
 529                         rx_bi->skb = NULL;
 530                 }
 531                 if (rx_bi->page) {
 532                         if (rx_bi->page_dma) {
 533                                 dma_unmap_page(dev,
 534                                                rx_bi->page_dma,
 535                                                PAGE_SIZE / 2,
 536                                                DMA_FROM_DEVICE);
 537                                 rx_bi->page_dma = 0;
 538                         }
 539                         __free_page(rx_bi->page);
 540                         rx_bi->page = NULL;
 541                         rx_bi->page_offset = 0;
 542                 }
 543         }
 544
 545         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 546         memset(rx_ring->rx_bi, 0, bi_size);
 547
 548         /* Zero out the descriptor ring */
 549         memset(rx_ring->desc, 0, rx_ring->size);
 550
 551         rx_ring->next_to_clean = 0;
 552         rx_ring->next_to_use = 0;
 553 }
 554
 555 /**
 556  * i40evf_free_rx_resources - Free Rx resources
 557  * @rx_ring: ring to clean the resources from
 558  *
 559  * Free all receive software resources
 560  **/
 561 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 562 {
 563         i40evf_clean_rx_ring(rx_ring);
 564         kfree(rx_ring->rx_bi);
 565         rx_ring->rx_bi = NULL;
 566
 567         if (rx_ring->desc) {
 568                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 569                                   rx_ring->desc, rx_ring->dma);
 570                 rx_ring->desc = NULL;
 571         }
 572 }
 573
 574 /**
 575  * i40evf_alloc_rx_headers - allocate rx header buffers
 576  * @rx_ring: ring to alloc buffers
 577  *
 578  * Allocate rx header buffers for the entire ring. As these are static,
 579  * this is only called when setting up a new ring.
 580  **/
 581 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 582 {
 583         struct device *dev = rx_ring->dev;
 584         struct i40e_rx_buffer *rx_bi;
 585         dma_addr_t dma;
 586         void *buffer;
 587         int buf_size;
 588         int i;
 589
 590         if (rx_ring->rx_bi[0].hdr_buf)
 591                 return;
 592         /* Make sure the buffers don't cross cache line boundaries. */
 593         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 594         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 595                                     &dma, GFP_KERNEL);
 596         if (!buffer)
 597                 return;
 598         for (i = 0; i < rx_ring->count; i++) {
 599                 rx_bi = &rx_ring->rx_bi[i];
 600                 rx_bi->dma = dma + (i * buf_size);
 601                 rx_bi->hdr_buf = buffer + (i * buf_size);
 602         }
 603 }
 604
 605 /**
 606  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 607  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 608  *
 609  * Returns 0 on success, negative on failure
 610  **/
 611 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 612 {
 613         struct device *dev = rx_ring->dev;
 614         int bi_size;
 615
 616         /* warn if we are about to overwrite the pointer */
 617         WARN_ON(rx_ring->rx_bi);
 618         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 619         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 620         if (!rx_ring->rx_bi)
 621                 goto err;
 622
 623         u64_stats_init(&rx_ring->syncp);
 624
 625         /* Round up to nearest 4K */
 626         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 627                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 628                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 629         rx_ring->size = ALIGN(rx_ring->size, 4096);
 630         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 631                                            &rx_ring->dma, GFP_KERNEL);
 632
 633         if (!rx_ring->desc) {
 634                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 635                          rx_ring->size);
 636                 goto err;
 637         }
 638
 639         rx_ring->next_to_clean = 0;
 640         rx_ring->next_to_use = 0;
 641
 642         return 0;
 643 err:
 644         kfree(rx_ring->rx_bi);
 645         rx_ring->rx_bi = NULL;
 646         return -ENOMEM;
 647 }
 648
 649 /**
 650  * i40e_release_rx_desc - Store the new tail and head values
 651  * @rx_ring: ring to bump
 652  * @val: new head index
 653  **/
 654 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 655 {
 656         rx_ring->next_to_use = val;
 657         /* Force memory writes to complete before letting h/w
 658          * know there are new descriptors to fetch.  (Only
 659          * applicable for weak-ordered memory model archs,
 660          * such as IA-64).
 661          */
 662         wmb();
 663         writel(val, rx_ring->tail);
 664 }
 665
 666 /**
 667  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 668  * @rx_ring: ring to place buffers on
 669  * @cleaned_count: number of buffers to replace
 670  *
 671  * Returns true if any errors on allocation
 672  **/
 673 bool i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 674 {
 675         u16 i = rx_ring->next_to_use;
 676         union i40e_rx_desc *rx_desc;
 677         struct i40e_rx_buffer *bi;
 678
 679         /* do nothing if no valid netdev defined */
 680         if (!rx_ring->netdev || !cleaned_count)
 681                 return false;
 682
 683         while (cleaned_count--) {
 684                 rx_desc = I40E_RX_DESC(rx_ring, i);
 685                 bi = &rx_ring->rx_bi[i];
 686
 687                 if (bi->skb) /* desc is in use */
 688                         goto no_buffers;
 689                 if (!bi->page) {
 690                         bi->page = alloc_page(GFP_ATOMIC);
 691                         if (!bi->page) {
 692                                 rx_ring->rx_stats.alloc_page_failed++;
 693                                 goto no_buffers;
 694                         }
 695                 }
 696
 697                 if (!bi->page_dma) {
 698                         /* use a half page if we're re-using */
 699                         bi->page_offset ^= PAGE_SIZE / 2;
 700                         bi->page_dma = dma_map_page(rx_ring->dev,
 701                                                     bi->page,
 702                                                     bi->page_offset,
 703                                                     PAGE_SIZE / 2,
 704                                                     DMA_FROM_DEVICE);
 705                         if (dma_mapping_error(rx_ring->dev,
 706                                               bi->page_dma)) {
 707                                 rx_ring->rx_stats.alloc_page_failed++;
 708                                 bi->page_dma = 0;
 709                                 goto no_buffers;
 710                         }
 711                 }
 712
 713                 dma_sync_single_range_for_device(rx_ring->dev,
 714                                                  rx_ring->rx_bi[0].dma,
 715                                                  i * rx_ring->rx_hdr_len,
 716                                                  rx_ring->rx_hdr_len,
 717                                                  DMA_FROM_DEVICE);
 718                 /* Refresh the desc even if buffer_addrs didn't change
 719                  * because each write-back erases this info.
 720                  */
 721                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 722                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 723                 i++;
 724                 if (i == rx_ring->count)
 725                         i = 0;
 726         }
 727
 728         if (rx_ring->next_to_use != i)
 729                 i40e_release_rx_desc(rx_ring, i);
 730
 731         return false;
 732
 733 no_buffers:
 734         if (rx_ring->next_to_use != i)
 735                 i40e_release_rx_desc(rx_ring, i);
 736
 737         /* make sure to come back via polling to try again after
 738          * allocation failure
 739          */
 740         return true;
 741 }
 742
 743 /**
 744  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 745  * @rx_ring: ring to place buffers on
 746  * @cleaned_count: number of buffers to replace
 747  *
 748  * Returns true if any errors on allocation
 749  **/
 750 bool i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 751 {
 752         u16 i = rx_ring->next_to_use;
 753         union i40e_rx_desc *rx_desc;
 754         struct i40e_rx_buffer *bi;
 755         struct sk_buff *skb;
 756
 757         /* do nothing if no valid netdev defined */
 758         if (!rx_ring->netdev || !cleaned_count)
 759                 return false;
 760
 761         while (cleaned_count--) {
 762                 rx_desc = I40E_RX_DESC(rx_ring, i);
 763                 bi = &rx_ring->rx_bi[i];
 764                 skb = bi->skb;
 765
 766                 if (!skb) {
 767                         skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
 768                                                           rx_ring->rx_buf_len,
 769                                                           GFP_ATOMIC |
 770                                                           __GFP_NOWARN);
 771                         if (!skb) {
 772                                 rx_ring->rx_stats.alloc_buff_failed++;
 773                                 goto no_buffers;
 774                         }
 775                         /* initialize queue mapping */
 776                         skb_record_rx_queue(skb, rx_ring->queue_index);
 777                         bi->skb = skb;
 778                 }
 779
 780                 if (!bi->dma) {
 781                         bi->dma = dma_map_single(rx_ring->dev,
 782                                                  skb->data,
 783                                                  rx_ring->rx_buf_len,
 784                                                  DMA_FROM_DEVICE);
 785                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 786                                 rx_ring->rx_stats.alloc_buff_failed++;
 787                                 bi->dma = 0;
 788                                 dev_kfree_skb(bi->skb);
 789                                 bi->skb = NULL;
 790                                 goto no_buffers;
 791                         }
 792                 }
 793
 794                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 795                 rx_desc->read.hdr_addr = 0;
 796                 i++;
 797                 if (i == rx_ring->count)
 798                         i = 0;
 799         }
 800
 801         if (rx_ring->next_to_use != i)
 802                 i40e_release_rx_desc(rx_ring, i);
 803
 804         return false;
 805
 806 no_buffers:
 807         if (rx_ring->next_to_use != i)
 808                 i40e_release_rx_desc(rx_ring, i);
 809
 810         /* make sure to come back via polling to try again after
 811          * allocation failure
 812          */
 813         return true;
 814 }
 815
 816 /**
 817  * i40e_receive_skb - Send a completed packet up the stack
 818  * @rx_ring:  rx ring in play
 819  * @skb: packet to send up
 820  * @vlan_tag: vlan tag for packet
 821  **/
 822 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 823                              struct sk_buff *skb, u16 vlan_tag)
 824 {
 825         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 826
 827         if (vlan_tag & VLAN_VID_MASK)
 828                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 829
 830         napi_gro_receive(&q_vector->napi, skb);
 831 }
 832
 833 /**
 834  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 835  * @vsi: the VSI we care about
 836  * @skb: skb currently being received and modified
 837  * @rx_status: status value of last descriptor in packet
 838  * @rx_error: error value of last descriptor in packet
 839  * @rx_ptype: ptype value of last descriptor in packet
 840  **/
 841 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 842                                     struct sk_buff *skb,
 843                                     u32 rx_status,
 844                                     u32 rx_error,
 845                                     u16 rx_ptype)
 846 {
 847         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 848         bool ipv4 = false, ipv6 = false;
 849         bool ipv4_tunnel, ipv6_tunnel;
 850         __wsum rx_udp_csum;
 851         struct iphdr *iph;
 852         __sum16 csum;
 853
 854         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 855                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 856         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 857                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 858
 859         skb->ip_summed = CHECKSUM_NONE;
 860
 861         /* Rx csum enabled and ip headers found? */
 862         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 863                 return;
 864
 865         /* did the hardware decode the packet and checksum? */
 866         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 867                 return;
 868
 869         /* both known and outer_ip must be set for the below code to work */
 870         if (!(decoded.known && decoded.outer_ip))
 871                 return;
 872
 873         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 874             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 875                 ipv4 = true;
 876         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 877                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 878                 ipv6 = true;
 879
 880         if (ipv4 &&
 881             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
 882                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 883                 goto checksum_fail;
 884
 885         /* likely incorrect csum if alternate IP extension headers found */
 886         if (ipv6 &&
 887             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 888                 /* don't increment checksum err here, non-fatal err */
 889                 return;
 890
 891         /* there was some L4 error, count error and punt packet to the stack */
 892         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
 893                 goto checksum_fail;
 894
 895         /* handle packets that were not able to be checksummed due
 896          * to arrival speed, in this case the stack can compute
 897          * the csum.
 898          */
 899         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
 900                 return;
 901
 902         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 903          * it in the driver, hardware does not do it for us.
 904          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 905          * so the total length of IPv4 header is IHL*4 bytes
 906          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 907          */
 908         if (ipv4_tunnel) {
 909                 skb->transport_header = skb->mac_header +
 910                                         sizeof(struct ethhdr) +
 911                                         (ip_hdr(skb)->ihl * 4);
 912
 913                 /* Add 4 bytes for VLAN tagged packets */
 914                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 915                                           skb->protocol == htons(ETH_P_8021AD))
 916                                           ? VLAN_HLEN : 0;
 917
 918                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
 919                     (udp_hdr(skb)->check != 0)) {
 920                         rx_udp_csum = udp_csum(skb);
 921                         iph = ip_hdr(skb);
 922                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
 923                                                  (skb->len -
 924                                                   skb_transport_offset(skb)),
 925                                                  IPPROTO_UDP, rx_udp_csum);
 926
 927                         if (udp_hdr(skb)->check != csum)
 928                                 goto checksum_fail;
 929
 930                 } /* else its GRE and so no outer UDP header */
 931         }
 932
 933         skb->ip_summed = CHECKSUM_UNNECESSARY;
 934         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 935
 936         return;
 937
 938 checksum_fail:
 939         vsi->back->hw_csum_rx_error++;
 940 }
 941
 942 /**
 943  * i40e_ptype_to_htype - get a hash type
 944  * @ptype: the ptype value from the descriptor
 945  *
 946  * Returns a hash type to be used by skb_set_hash
 947  **/
 948 static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
 949 {
 950         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 951
 952         if (!decoded.known)
 953                 return PKT_HASH_TYPE_NONE;
 954
 955         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 956             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 957                 return PKT_HASH_TYPE_L4;
 958         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 959                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 960                 return PKT_HASH_TYPE_L3;
 961         else
 962                 return PKT_HASH_TYPE_L2;
 963 }
 964
 965 /**
 966  * i40e_rx_hash - set the hash value in the skb
 967  * @ring: descriptor ring
 968  * @rx_desc: specific descriptor
 969  **/
 970 static inline void i40e_rx_hash(struct i40e_ring *ring,
 971                                 union i40e_rx_desc *rx_desc,
 972                                 struct sk_buff *skb,
 973                                 u8 rx_ptype)
 974 {
 975         u32 hash;
 976         const __le64 rss_mask  =
 977                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 978                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 979
 980         if (ring->netdev->features & NETIF_F_RXHASH)
 981                 return;
 982
 983         if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
 984                 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 985                 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
 986         }
 987 }
 988
 989 /**
 990  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
 991  * @rx_ring:  rx ring to clean
 992  * @budget:   how many cleans we're allowed
 993  *
 994  * Returns true if there's any budget left (e.g. the clean is finished)
 995  **/
 996 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, const int budget)
 997 {
 998         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 999         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1000         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1001         const int current_node = numa_mem_id();
1002         struct i40e_vsi *vsi = rx_ring->vsi;
1003         u16 i = rx_ring->next_to_clean;
1004         union i40e_rx_desc *rx_desc;
1005         u32 rx_error, rx_status;
1006         bool failure = false;
1007         u8 rx_ptype;
1008         u64 qword;
1009
1010         do {
1011                 struct i40e_rx_buffer *rx_bi;
1012                 struct sk_buff *skb;
1013                 u16 vlan_tag;
1014                 /* return some buffers to hardware, one at a time is too slow */
1015                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1016                         failure = failure ||
1017                                   i40evf_alloc_rx_buffers_ps(rx_ring,
1018                                                              cleaned_count);
1019                         cleaned_count = 0;
1020                 }
1021
1022                 i = rx_ring->next_to_clean;
1023                 rx_desc = I40E_RX_DESC(rx_ring, i);
1024                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1025                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1026                         I40E_RXD_QW1_STATUS_SHIFT;
1027
1028                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1029                         break;
1030
1031                 /* This memory barrier is needed to keep us from reading
1032                  * any other fields out of the rx_desc until we know the
1033                  * DD bit is set.
1034                  */
1035                 dma_rmb();
1036                 rx_bi = &rx_ring->rx_bi[i];
1037                 skb = rx_bi->skb;
1038                 if (likely(!skb)) {
1039                         skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
1040                                                           rx_ring->rx_hdr_len,
1041                                                           GFP_ATOMIC |
1042                                                           __GFP_NOWARN);
1043                         if (!skb) {
1044                                 rx_ring->rx_stats.alloc_buff_failed++;
1045                                 failure = true;
1046                                 break;
1047                         }
1048
1049                         /* initialize queue mapping */
1050                         skb_record_rx_queue(skb, rx_ring->queue_index);
1051                         /* we are reusing so sync this buffer for CPU use */
1052                         dma_sync_single_range_for_cpu(rx_ring->dev,
1053                                                       rx_ring->rx_bi[0].dma,
1054                                                       i * rx_ring->rx_hdr_len,
1055                                                       rx_ring->rx_hdr_len,
1056                                                       DMA_FROM_DEVICE);
1057                 }
1058                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1059                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1060                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1061                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1062                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1063                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1064
1065                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1066                            I40E_RXD_QW1_ERROR_SHIFT;
1067                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1068                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1069
1070                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1071                            I40E_RXD_QW1_PTYPE_SHIFT;
1072                 prefetch(rx_bi->page);
1073                 rx_bi->skb = NULL;
1074                 cleaned_count++;
1075                 if (rx_hbo || rx_sph) {
1076                         int len;
1077
1078                         if (rx_hbo)
1079                                 len = I40E_RX_HDR_SIZE;
1080                         else
1081                                 len = rx_header_len;
1082                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1083                 } else if (skb->len == 0) {
1084                         int len;
1085
1086                         len = (rx_packet_len > skb_headlen(skb) ?
1087                                 skb_headlen(skb) : rx_packet_len);
1088                         memcpy(__skb_put(skb, len),
1089                                rx_bi->page + rx_bi->page_offset,
1090                                len);
1091                         rx_bi->page_offset += len;
1092                         rx_packet_len -= len;
1093                 }
1094
1095                 /* Get the rest of the data if this was a header split */
1096                 if (rx_packet_len) {
1097                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1098                                            rx_bi->page,
1099                                            rx_bi->page_offset,
1100                                            rx_packet_len);
1101
1102                         skb->len += rx_packet_len;
1103                         skb->data_len += rx_packet_len;
1104                         skb->truesize += rx_packet_len;
1105
1106                         if ((page_count(rx_bi->page) == 1) &&
1107                             (page_to_nid(rx_bi->page) == current_node))
1108                                 get_page(rx_bi->page);
1109                         else
1110                                 rx_bi->page = NULL;
1111
1112                         dma_unmap_page(rx_ring->dev,
1113                                        rx_bi->page_dma,
1114                                        PAGE_SIZE / 2,
1115                                        DMA_FROM_DEVICE);
1116                         rx_bi->page_dma = 0;
1117                 }
1118                 I40E_RX_INCREMENT(rx_ring, i);
1119
1120                 if (unlikely(
1121                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1122                         struct i40e_rx_buffer *next_buffer;
1123
1124                         next_buffer = &rx_ring->rx_bi[i];
1125                         next_buffer->skb = skb;
1126                         rx_ring->rx_stats.non_eop_descs++;
1127                         continue;
1128                 }
1129
1130                 /* ERR_MASK will only have valid bits if EOP set */
1131                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1132                         dev_kfree_skb_any(skb);
1133                         continue;
1134                 }
1135
1136                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1137
1138                 /* probably a little skewed due to removing CRC */
1139                 total_rx_bytes += skb->len;
1140                 total_rx_packets++;
1141
1142                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1143
1144                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1145
1146                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1147                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1148                          : 0;
1149 #ifdef I40E_FCOE
1150                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1151                         dev_kfree_skb_any(skb);
1152                         continue;
1153                 }
1154 #endif
1155                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1156
1157                 rx_desc->wb.qword1.status_error_len = 0;
1158
1159         } while (likely(total_rx_packets < budget));
1160
1161         u64_stats_update_begin(&rx_ring->syncp);
1162         rx_ring->stats.packets += total_rx_packets;
1163         rx_ring->stats.bytes += total_rx_bytes;
1164         u64_stats_update_end(&rx_ring->syncp);
1165         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1166         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1167
1168         return failure ? budget : total_rx_packets;
1169 }
1170
1171 /**
1172  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1173  * @rx_ring:  rx ring to clean
1174  * @budget:   how many cleans we're allowed
1175  *
1176  * Returns number of packets cleaned
1177  **/
1178 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1179 {
1180         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1181         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1182         struct i40e_vsi *vsi = rx_ring->vsi;
1183         union i40e_rx_desc *rx_desc;
1184         u32 rx_error, rx_status;
1185         u16 rx_packet_len;
1186         bool failure = false;
1187         u8 rx_ptype;
1188         u64 qword;
1189         u16 i;
1190
1191         do {
1192                 struct i40e_rx_buffer *rx_bi;
1193                 struct sk_buff *skb;
1194                 u16 vlan_tag;
1195                 /* return some buffers to hardware, one at a time is too slow */
1196                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1197                         failure = failure ||
1198                                   i40evf_alloc_rx_buffers_1buf(rx_ring,
1199                                                                cleaned_count);
1200                         cleaned_count = 0;
1201                 }
1202
1203                 i = rx_ring->next_to_clean;
1204                 rx_desc = I40E_RX_DESC(rx_ring, i);
1205                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1206                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1207                         I40E_RXD_QW1_STATUS_SHIFT;
1208
1209                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1210                         break;
1211
1212                 /* This memory barrier is needed to keep us from reading
1213                  * any other fields out of the rx_desc until we know the
1214                  * DD bit is set.
1215                  */
1216                 dma_rmb();
1217
1218                 rx_bi = &rx_ring->rx_bi[i];
1219                 skb = rx_bi->skb;
1220                 prefetch(skb->data);
1221
1222                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1223                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1224
1225                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1226                            I40E_RXD_QW1_ERROR_SHIFT;
1227                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1228
1229                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1230                            I40E_RXD_QW1_PTYPE_SHIFT;
1231                 rx_bi->skb = NULL;
1232                 cleaned_count++;
1233
1234                 /* Get the header and possibly the whole packet
1235                  * If this is an skb from previous receive dma will be 0
1236                  */
1237                 skb_put(skb, rx_packet_len);
1238                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1239                                  DMA_FROM_DEVICE);
1240                 rx_bi->dma = 0;
1241
1242                 I40E_RX_INCREMENT(rx_ring, i);
1243
1244                 if (unlikely(
1245                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1246                         rx_ring->rx_stats.non_eop_descs++;
1247                         continue;
1248                 }
1249
1250                 /* ERR_MASK will only have valid bits if EOP set */
1251                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1252                         dev_kfree_skb_any(skb);
1253                         continue;
1254                 }
1255
1256                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1257                 /* probably a little skewed due to removing CRC */
1258                 total_rx_bytes += skb->len;
1259                 total_rx_packets++;
1260
1261                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1262
1263                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1264
1265                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1266                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1267                          : 0;
1268                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1269
1270                 rx_desc->wb.qword1.status_error_len = 0;
1271         } while (likely(total_rx_packets < budget));
1272
1273         u64_stats_update_begin(&rx_ring->syncp);
1274         rx_ring->stats.packets += total_rx_packets;
1275         rx_ring->stats.bytes += total_rx_bytes;
1276         u64_stats_update_end(&rx_ring->syncp);
1277         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1278         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1279
1280         return failure ? budget : total_rx_packets;
1281 }
1282
1283 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1284 {
1285         u32 val;
1286
1287         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1288               /* Don't clear PBA because that can cause lost interrupts that
1289                * came in while we were cleaning/polling
1290                */
1291               (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1292               (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1293
1294         return val;
1295 }
1296
1297 /* a small macro to shorten up some long lines */
1298 #define INTREG I40E_VFINT_DYN_CTLN1
1299
1300 /**
1301  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1302  * @vsi: the VSI we care about
1303  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1304  *
1305  **/
1306 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1307                                           struct i40e_q_vector *q_vector)
1308 {
1309         struct i40e_hw *hw = &vsi->back->hw;
1310         bool rx = false, tx = false;
1311         u32 rxval, txval;
1312         int vector;
1313
1314         vector = (q_vector->v_idx + vsi->base_vector);
1315
1316         /* avoid dynamic calculation if in countdown mode OR if
1317          * all dynamic is disabled
1318          */
1319         rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1320
1321         if (q_vector->itr_countdown > 0 ||
1322             (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1323              !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1324                 goto enable_int;
1325         }
1326
1327         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1328                 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1329                 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1330         }
1331
1332         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1333                 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1334                 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1335         }
1336
1337         if (rx || tx) {
1338                 /* get the higher of the two ITR adjustments and
1339                  * use the same value for both ITR registers
1340                  * when in adaptive mode (Rx and/or Tx)
1341                  */
1342                 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1343
1344                 q_vector->tx.itr = q_vector->rx.itr = itr;
1345                 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1346                 tx = true;
1347                 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1348                 rx = true;
1349         }
1350
1351         /* only need to enable the interrupt once, but need
1352          * to possibly update both ITR values
1353          */
1354         if (rx) {
1355                 /* set the INTENA_MSK_MASK so that this first write
1356                  * won't actually enable the interrupt, instead just
1357                  * updating the ITR (it's bit 31 PF and VF)
1358                  */
1359                 rxval |= BIT(31);
1360                 /* don't check _DOWN because interrupt isn't being enabled */
1361                 wr32(hw, INTREG(vector - 1), rxval);
1362         }
1363
1364 enable_int:
1365         if (!test_bit(__I40E_DOWN, &vsi->state))
1366                 wr32(hw, INTREG(vector - 1), txval);
1367
1368         if (q_vector->itr_countdown)
1369                 q_vector->itr_countdown--;
1370         else
1371                 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1372 }
1373
1374 /**
1375  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1376  * @napi: napi struct with our devices info in it
1377  * @budget: amount of work driver is allowed to do this pass, in packets
1378  *
1379  * This function will clean all queues associated with a q_vector.
1380  *
1381  * Returns the amount of work done
1382  **/
1383 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1384 {
1385         struct i40e_q_vector *q_vector =
1386                                container_of(napi, struct i40e_q_vector, napi);
1387         struct i40e_vsi *vsi = q_vector->vsi;
1388         struct i40e_ring *ring;
1389         bool clean_complete = true;
1390         bool arm_wb = false;
1391         int budget_per_ring;
1392         int work_done = 0;
1393
1394         if (test_bit(__I40E_DOWN, &vsi->state)) {
1395                 napi_complete(napi);
1396                 return 0;
1397         }
1398
1399         /* Since the actual Tx work is minimal, we can give the Tx a larger
1400          * budget and be more aggressive about cleaning up the Tx descriptors.
1401          */
1402         i40e_for_each_ring(ring, q_vector->tx) {
1403                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1404                 arm_wb = arm_wb || ring->arm_wb;
1405                 ring->arm_wb = false;
1406         }
1407
1408         /* Handle case where we are called by netpoll with a budget of 0 */
1409         if (budget <= 0)
1410                 goto tx_only;
1411
1412         /* We attempt to distribute budget to each Rx queue fairly, but don't
1413          * allow the budget to go below 1 because that would exit polling early.
1414          */
1415         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1416
1417         i40e_for_each_ring(ring, q_vector->rx) {
1418                 int cleaned;
1419
1420                 if (ring_is_ps_enabled(ring))
1421                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1422                 else
1423                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1424
1425                 work_done += cleaned;
1426                 /* if we didn't clean as many as budgeted, we must be done */
1427                 clean_complete &= (budget_per_ring != cleaned);
1428         }
1429
1430         /* If work not completed, return budget and polling will return */
1431         if (!clean_complete) {
1432 tx_only:
1433                 if (arm_wb) {
1434                         q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1435                         i40e_enable_wb_on_itr(vsi, q_vector);
1436                 }
1437                 return budget;
1438         }
1439
1440         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1441                 q_vector->arm_wb_state = false;
1442
1443         /* Work is done so exit the polling mode and re-enable the interrupt */
1444         napi_complete_done(napi, work_done);
1445         i40e_update_enable_itr(vsi, q_vector);
1446         return 0;
1447 }
1448
1449 /**
1450  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1451  * @skb:     send buffer
1452  * @tx_ring: ring to send buffer on
1453  * @flags:   the tx flags to be set
1454  *
1455  * Checks the skb and set up correspondingly several generic transmit flags
1456  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1457  *
1458  * Returns error code indicate the frame should be dropped upon error and the
1459  * otherwise  returns 0 to indicate the flags has been set properly.
1460  **/
1461 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1462                                                struct i40e_ring *tx_ring,
1463                                                u32 *flags)
1464 {
1465         __be16 protocol = skb->protocol;
1466         u32  tx_flags = 0;
1467
1468         if (protocol == htons(ETH_P_8021Q) &&
1469             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1470                 /* When HW VLAN acceleration is turned off by the user the
1471                  * stack sets the protocol to 8021q so that the driver
1472                  * can take any steps required to support the SW only
1473                  * VLAN handling.  In our case the driver doesn't need
1474                  * to take any further steps so just set the protocol
1475                  * to the encapsulated ethertype.
1476                  */
1477                 skb->protocol = vlan_get_protocol(skb);
1478                 goto out;
1479         }
1480
1481         /* if we have a HW VLAN tag being added, default to the HW one */
1482         if (skb_vlan_tag_present(skb)) {
1483                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1484                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1485         /* else if it is a SW VLAN, check the next protocol and store the tag */
1486         } else if (protocol == htons(ETH_P_8021Q)) {
1487                 struct vlan_hdr *vhdr, _vhdr;
1488
1489                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1490                 if (!vhdr)
1491                         return -EINVAL;
1492
1493                 protocol = vhdr->h_vlan_encapsulated_proto;
1494                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1495                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1496         }
1497
1498 out:
1499         *flags = tx_flags;
1500         return 0;
1501 }
1502
1503 /**
1504  * i40e_tso - set up the tso context descriptor
1505  * @tx_ring:  ptr to the ring to send
1506  * @skb:      ptr to the skb we're sending
1507  * @hdr_len:  ptr to the size of the packet header
1508  * @cd_type_cmd_tso_mss: Quad Word 1
1509  *
1510  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1511  **/
1512 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1513                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
1514 {
1515         u32 cd_cmd, cd_tso_len, cd_mss;
1516         struct ipv6hdr *ipv6h;
1517         struct tcphdr *tcph;
1518         struct iphdr *iph;
1519         u32 l4len;
1520         int err;
1521
1522         if (skb->ip_summed != CHECKSUM_PARTIAL)
1523                 return 0;
1524
1525         if (!skb_is_gso(skb))
1526                 return 0;
1527
1528         err = skb_cow_head(skb, 0);
1529         if (err < 0)
1530                 return err;
1531
1532         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1533         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1534
1535         if (iph->version == 4) {
1536                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1537                 iph->tot_len = 0;
1538                 iph->check = 0;
1539                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1540                                                  0, IPPROTO_TCP, 0);
1541         } else if (ipv6h->version == 6) {
1542                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1543                 ipv6h->payload_len = 0;
1544                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1545                                                0, IPPROTO_TCP, 0);
1546         }
1547
1548         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1549         *hdr_len = (skb->encapsulation
1550                     ? (skb_inner_transport_header(skb) - skb->data)
1551                     : skb_transport_offset(skb)) + l4len;
1552
1553         /* find the field values */
1554         cd_cmd = I40E_TX_CTX_DESC_TSO;
1555         cd_tso_len = skb->len - *hdr_len;
1556         cd_mss = skb_shinfo(skb)->gso_size;
1557         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1558                                 ((u64)cd_tso_len <<
1559                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1560                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1561         return 1;
1562 }
1563
1564 /**
1565  * i40e_tx_enable_csum - Enable Tx checksum offloads
1566  * @skb: send buffer
1567  * @tx_flags: pointer to Tx flags currently set
1568  * @td_cmd: Tx descriptor command bits to set
1569  * @td_offset: Tx descriptor header offsets to set
1570  * @cd_tunneling: ptr to context desc bits
1571  **/
1572 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1573                                 u32 *td_cmd, u32 *td_offset,
1574                                 struct i40e_ring *tx_ring,
1575                                 u32 *cd_tunneling)
1576 {
1577         struct ipv6hdr *this_ipv6_hdr;
1578         unsigned int this_tcp_hdrlen;
1579         struct iphdr *this_ip_hdr;
1580         u32 network_hdr_len;
1581         u8 l4_hdr = 0;
1582         struct udphdr *oudph;
1583         struct iphdr *oiph;
1584         u32 l4_tunnel = 0;
1585
1586         if (skb->encapsulation) {
1587                 switch (ip_hdr(skb)->protocol) {
1588                 case IPPROTO_UDP:
1589                         oudph = udp_hdr(skb);
1590                         oiph = ip_hdr(skb);
1591                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1592                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1593                         break;
1594                 default:
1595                         return;
1596                 }
1597                 network_hdr_len = skb_inner_network_header_len(skb);
1598                 this_ip_hdr = inner_ip_hdr(skb);
1599                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1600                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1601
1602                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1603                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1604                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1605                                 ip_hdr(skb)->check = 0;
1606                         } else {
1607                                 *cd_tunneling |=
1608                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1609                         }
1610                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1611                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1612                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1613                                 ip_hdr(skb)->check = 0;
1614                 }
1615
1616                 /* Now set the ctx descriptor fields */
1617                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1618                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1619                                    l4_tunnel                             |
1620                                    ((skb_inner_network_offset(skb) -
1621                                         skb_transport_offset(skb)) >> 1) <<
1622                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1623                 if (this_ip_hdr->version == 6) {
1624                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1625                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1626                 }
1627
1628                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1629                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
1630                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1631                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1632                                         oiph->daddr,
1633                                         (skb->len - skb_transport_offset(skb)),
1634                                         IPPROTO_UDP, 0);
1635                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1636                 }
1637         } else {
1638                 network_hdr_len = skb_network_header_len(skb);
1639                 this_ip_hdr = ip_hdr(skb);
1640                 this_ipv6_hdr = ipv6_hdr(skb);
1641                 this_tcp_hdrlen = tcp_hdrlen(skb);
1642         }
1643
1644         /* Enable IP checksum offloads */
1645         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1646                 l4_hdr = this_ip_hdr->protocol;
1647                 /* the stack computes the IP header already, the only time we
1648                  * need the hardware to recompute it is in the case of TSO.
1649                  */
1650                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1651                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1652                         this_ip_hdr->check = 0;
1653                 } else {
1654                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1655                 }
1656                 /* Now set the td_offset for IP header length */
1657                 *td_offset = (network_hdr_len >> 2) <<
1658                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1659         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1660                 l4_hdr = this_ipv6_hdr->nexthdr;
1661                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1662                 /* Now set the td_offset for IP header length */
1663                 *td_offset = (network_hdr_len >> 2) <<
1664                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1665         }
1666         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1667         *td_offset |= (skb_network_offset(skb) >> 1) <<
1668                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1669
1670         /* Enable L4 checksum offloads */
1671         switch (l4_hdr) {
1672         case IPPROTO_TCP:
1673                 /* enable checksum offloads */
1674                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1675                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1676                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1677                 break;
1678         case IPPROTO_SCTP:
1679                 /* enable SCTP checksum offload */
1680                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1681                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1682                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1683                 break;
1684         case IPPROTO_UDP:
1685                 /* enable UDP checksum offload */
1686                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1687                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1688                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1689                 break;
1690         default:
1691                 break;
1692         }
1693 }
1694
1695 /**
1696  * i40e_create_tx_ctx Build the Tx context descriptor
1697  * @tx_ring:  ring to create the descriptor on
1698  * @cd_type_cmd_tso_mss: Quad Word 1
1699  * @cd_tunneling: Quad Word 0 - bits 0-31
1700  * @cd_l2tag2: Quad Word 0 - bits 32-63
1701  **/
1702 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1703                                const u64 cd_type_cmd_tso_mss,
1704                                const u32 cd_tunneling, const u32 cd_l2tag2)
1705 {
1706         struct i40e_tx_context_desc *context_desc;
1707         int i = tx_ring->next_to_use;
1708
1709         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1710             !cd_tunneling && !cd_l2tag2)
1711                 return;
1712
1713         /* grab the next descriptor */
1714         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1715
1716         i++;
1717         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1718
1719         /* cpu_to_le32 and assign to struct fields */
1720         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1721         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1722         context_desc->rsvd = cpu_to_le16(0);
1723         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1724 }
1725
1726 /**
1727  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1728  * @skb:      send buffer
1729  * @tx_flags: collected send information
1730  *
1731  * Note: Our HW can't scatter-gather more than 8 fragments to build
1732  * a packet on the wire and so we need to figure out the cases where we
1733  * need to linearize the skb.
1734  **/
1735 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1736 {
1737         struct skb_frag_struct *frag;
1738         bool linearize = false;
1739         unsigned int size = 0;
1740         u16 num_frags;
1741         u16 gso_segs;
1742
1743         num_frags = skb_shinfo(skb)->nr_frags;
1744         gso_segs = skb_shinfo(skb)->gso_segs;
1745
1746         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1747                 u16 j = 0;
1748
1749                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1750                         goto linearize_chk_done;
1751                 /* try the simple math, if we have too many frags per segment */
1752                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1753                     I40E_MAX_BUFFER_TXD) {
1754                         linearize = true;
1755                         goto linearize_chk_done;
1756                 }
1757                 frag = &skb_shinfo(skb)->frags[0];
1758                 /* we might still have more fragments per segment */
1759                 do {
1760                         size += skb_frag_size(frag);
1761                         frag++; j++;
1762                         if ((size >= skb_shinfo(skb)->gso_size) &&
1763                             (j < I40E_MAX_BUFFER_TXD)) {
1764                                 size = (size % skb_shinfo(skb)->gso_size);
1765                                 j = (size) ? 1 : 0;
1766                         }
1767                         if (j == I40E_MAX_BUFFER_TXD) {
1768                                 linearize = true;
1769                                 break;
1770                         }
1771                         num_frags--;
1772                 } while (num_frags);
1773         } else {
1774                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1775                         linearize = true;
1776         }
1777
1778 linearize_chk_done:
1779         return linearize;
1780 }
1781
1782 /**
1783  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1784  * @tx_ring: the ring to be checked
1785  * @size:    the size buffer we want to assure is available
1786  *
1787  * Returns -EBUSY if a stop is needed, else 0
1788  **/
1789 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1790 {
1791         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1792         /* Memory barrier before checking head and tail */
1793         smp_mb();
1794
1795         /* Check again in a case another CPU has just made room available. */
1796         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1797                 return -EBUSY;
1798
1799         /* A reprieve! - use start_queue because it doesn't call schedule */
1800         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1801         ++tx_ring->tx_stats.restart_queue;
1802         return 0;
1803 }
1804
1805 /**
1806  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1807  * @tx_ring: the ring to be checked
1808  * @size:    the size buffer we want to assure is available
1809  *
1810  * Returns 0 if stop is not needed
1811  **/
1812 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1813 {
1814         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1815                 return 0;
1816         return __i40evf_maybe_stop_tx(tx_ring, size);
1817 }
1818
1819 /**
1820  * i40evf_tx_map - Build the Tx descriptor
1821  * @tx_ring:  ring to send buffer on
1822  * @skb:      send buffer
1823  * @first:    first buffer info buffer to use
1824  * @tx_flags: collected send information
1825  * @hdr_len:  size of the packet header
1826  * @td_cmd:   the command field in the descriptor
1827  * @td_offset: offset for checksum or crc
1828  **/
1829 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1830                                  struct i40e_tx_buffer *first, u32 tx_flags,
1831                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1832 {
1833         unsigned int data_len = skb->data_len;
1834         unsigned int size = skb_headlen(skb);
1835         struct skb_frag_struct *frag;
1836         struct i40e_tx_buffer *tx_bi;
1837         struct i40e_tx_desc *tx_desc;
1838         u16 i = tx_ring->next_to_use;
1839         u32 td_tag = 0;
1840         dma_addr_t dma;
1841         u16 gso_segs;
1842         u16 desc_count = 0;
1843         bool tail_bump = true;
1844         bool do_rs = false;
1845
1846         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1847                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1848                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1849                          I40E_TX_FLAGS_VLAN_SHIFT;
1850         }
1851
1852         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1853                 gso_segs = skb_shinfo(skb)->gso_segs;
1854         else
1855                 gso_segs = 1;
1856
1857         /* multiply data chunks by size of headers */
1858         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1859         first->gso_segs = gso_segs;
1860         first->skb = skb;
1861         first->tx_flags = tx_flags;
1862
1863         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1864
1865         tx_desc = I40E_TX_DESC(tx_ring, i);
1866         tx_bi = first;
1867
1868         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1869                 if (dma_mapping_error(tx_ring->dev, dma))
1870                         goto dma_error;
1871
1872                 /* record length, and DMA address */
1873                 dma_unmap_len_set(tx_bi, len, size);
1874                 dma_unmap_addr_set(tx_bi, dma, dma);
1875
1876                 tx_desc->buffer_addr = cpu_to_le64(dma);
1877
1878                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1879                         tx_desc->cmd_type_offset_bsz =
1880                                 build_ctob(td_cmd, td_offset,
1881                                            I40E_MAX_DATA_PER_TXD, td_tag);
1882
1883                         tx_desc++;
1884                         i++;
1885                         desc_count++;
1886
1887                         if (i == tx_ring->count) {
1888                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1889                                 i = 0;
1890                         }
1891
1892                         dma += I40E_MAX_DATA_PER_TXD;
1893                         size -= I40E_MAX_DATA_PER_TXD;
1894
1895                         tx_desc->buffer_addr = cpu_to_le64(dma);
1896                 }
1897
1898                 if (likely(!data_len))
1899                         break;
1900
1901                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1902                                                           size, td_tag);
1903
1904                 tx_desc++;
1905                 i++;
1906                 desc_count++;
1907
1908                 if (i == tx_ring->count) {
1909                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1910                         i = 0;
1911                 }
1912
1913                 size = skb_frag_size(frag);
1914                 data_len -= size;
1915
1916                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1917                                        DMA_TO_DEVICE);
1918
1919                 tx_bi = &tx_ring->tx_bi[i];
1920         }
1921
1922         /* set next_to_watch value indicating a packet is present */
1923         first->next_to_watch = tx_desc;
1924
1925         i++;
1926         if (i == tx_ring->count)
1927                 i = 0;
1928
1929         tx_ring->next_to_use = i;
1930
1931         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1932                                                  tx_ring->queue_index),
1933                                                  first->bytecount);
1934         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1935
1936         /* Algorithm to optimize tail and RS bit setting:
1937          * if xmit_more is supported
1938          *      if xmit_more is true
1939          *              do not update tail and do not mark RS bit.
1940          *      if xmit_more is false and last xmit_more was false
1941          *              if every packet spanned less than 4 desc
1942          *                      then set RS bit on 4th packet and update tail
1943          *                      on every packet
1944          *              else
1945          *                      update tail and set RS bit on every packet.
1946          *      if xmit_more is false and last_xmit_more was true
1947          *              update tail and set RS bit.
1948          *
1949          * Optimization: wmb to be issued only in case of tail update.
1950          * Also optimize the Descriptor WB path for RS bit with the same
1951          * algorithm.
1952          *
1953          * Note: If there are less than 4 packets
1954          * pending and interrupts were disabled the service task will
1955          * trigger a force WB.
1956          */
1957         if (skb->xmit_more  &&
1958             !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1959                                                     tx_ring->queue_index))) {
1960                 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1961                 tail_bump = false;
1962         } else if (!skb->xmit_more &&
1963                    !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1964                                                        tx_ring->queue_index)) &&
1965                    (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
1966                    (tx_ring->packet_stride < WB_STRIDE) &&
1967                    (desc_count < WB_STRIDE)) {
1968                 tx_ring->packet_stride++;
1969         } else {
1970                 tx_ring->packet_stride = 0;
1971                 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1972                 do_rs = true;
1973         }
1974         if (do_rs)
1975                 tx_ring->packet_stride = 0;
1976
1977         tx_desc->cmd_type_offset_bsz =
1978                         build_ctob(td_cmd, td_offset, size, td_tag) |
1979                         cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
1980                                                   I40E_TX_DESC_CMD_EOP) <<
1981                                                   I40E_TXD_QW1_CMD_SHIFT);
1982
1983         /* notify HW of packet */
1984         if (!tail_bump)
1985                 prefetchw(tx_desc + 1);
1986
1987         if (tail_bump) {
1988                 /* Force memory writes to complete before letting h/w
1989                  * know there are new descriptors to fetch.  (Only
1990                  * applicable for weak-ordered memory model archs,
1991                  * such as IA-64).
1992                  */
1993                 wmb();
1994                 writel(i, tx_ring->tail);
1995         }
1996
1997         return;
1998
1999 dma_error:
2000         dev_info(tx_ring->dev, "TX DMA map failed\n");
2001
2002         /* clear dma mappings for failed tx_bi map */
2003         for (;;) {
2004                 tx_bi = &tx_ring->tx_bi[i];
2005                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2006                 if (tx_bi == first)
2007                         break;
2008                 if (i == 0)
2009                         i = tx_ring->count;
2010                 i--;
2011         }
2012
2013         tx_ring->next_to_use = i;
2014 }
2015
2016 /**
2017  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
2018  * @skb:     send buffer
2019  * @tx_ring: ring to send buffer on
2020  *
2021  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
2022  * there is not enough descriptors available in this ring since we need at least
2023  * one descriptor.
2024  **/
2025 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
2026                                                struct i40e_ring *tx_ring)
2027 {
2028         unsigned int f;
2029         int count = 0;
2030
2031         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2032          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2033          *       + 4 desc gap to avoid the cache line where head is,
2034          *       + 1 desc for context descriptor,
2035          * otherwise try next time
2036          */
2037         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
2038                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
2039
2040         count += TXD_USE_COUNT(skb_headlen(skb));
2041         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2042                 tx_ring->tx_stats.tx_busy++;
2043                 return 0;
2044         }
2045         return count;
2046 }
2047
2048 /**
2049  * i40e_xmit_frame_ring - Sends buffer on Tx ring
2050  * @skb:     send buffer
2051  * @tx_ring: ring to send buffer on
2052  *
2053  * Returns NETDEV_TX_OK if sent, else an error code
2054  **/
2055 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2056                                         struct i40e_ring *tx_ring)
2057 {
2058         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2059         u32 cd_tunneling = 0, cd_l2tag2 = 0;
2060         struct i40e_tx_buffer *first;
2061         u32 td_offset = 0;
2062         u32 tx_flags = 0;
2063         __be16 protocol;
2064         u32 td_cmd = 0;
2065         u8 hdr_len = 0;
2066         int tso;
2067
2068         /* prefetch the data, we'll need it later */
2069         prefetch(skb->data);
2070
2071         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
2072                 return NETDEV_TX_BUSY;
2073
2074         /* prepare the xmit flags */
2075         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2076                 goto out_drop;
2077
2078         /* obtain protocol of skb */
2079         protocol = vlan_get_protocol(skb);
2080
2081         /* record the location of the first descriptor for this packet */
2082         first = &tx_ring->tx_bi[tx_ring->next_to_use];
2083
2084         /* setup IPv4/IPv6 offloads */
2085         if (protocol == htons(ETH_P_IP))
2086                 tx_flags |= I40E_TX_FLAGS_IPV4;
2087         else if (protocol == htons(ETH_P_IPV6))
2088                 tx_flags |= I40E_TX_FLAGS_IPV6;
2089
2090         tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss);
2091
2092         if (tso < 0)
2093                 goto out_drop;
2094         else if (tso)
2095                 tx_flags |= I40E_TX_FLAGS_TSO;
2096
2097         if (i40e_chk_linearize(skb, tx_flags)) {
2098                 if (skb_linearize(skb))
2099                         goto out_drop;
2100                 tx_ring->tx_stats.tx_linearize++;
2101         }
2102         skb_tx_timestamp(skb);
2103
2104         /* always enable CRC insertion offload */
2105         td_cmd |= I40E_TX_DESC_CMD_ICRC;
2106
2107         /* Always offload the checksum, since it's in the data descriptor */
2108         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2109                 tx_flags |= I40E_TX_FLAGS_CSUM;
2110
2111                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2112                                     tx_ring, &cd_tunneling);
2113         }
2114
2115         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2116                            cd_tunneling, cd_l2tag2);
2117
2118         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2119                       td_cmd, td_offset);
2120
2121         return NETDEV_TX_OK;
2122
2123 out_drop:
2124         dev_kfree_skb_any(skb);
2125         return NETDEV_TX_OK;
2126 }
2127
2128 /**
2129  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2130  * @skb:    send buffer
2131  * @netdev: network interface device structure
2132  *
2133  * Returns NETDEV_TX_OK if sent, else an error code
2134  **/
2135 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2136 {
2137         struct i40evf_adapter *adapter = netdev_priv(netdev);
2138         struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2139
2140         /* hardware can't handle really short frames, hardware padding works
2141          * beyond this point
2142          */
2143         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2144                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2145                         return NETDEV_TX_OK;
2146                 skb->len = I40E_MIN_TX_LEN;
2147                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2148         }
2149
2150         return i40e_xmit_frame_ring(skb, tx_ring);
2151 }