drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2016 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 dev_kfree_skb_any(tx_buffer->skb);
  55                 if (dma_unmap_len(tx_buffer, len))
  56                         dma_unmap_single(ring->dev,
  57                                          dma_unmap_addr(tx_buffer, dma),
  58                                          dma_unmap_len(tx_buffer, len),
  59                                          DMA_TO_DEVICE);
  60         } else if (dma_unmap_len(tx_buffer, len)) {
  61                 dma_unmap_page(ring->dev,
  62                                dma_unmap_addr(tx_buffer, dma),
  63                                dma_unmap_len(tx_buffer, len),
  64                                DMA_TO_DEVICE);
  65         }
  66
  67         if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  68                 kfree(tx_buffer->raw_buf);
  69
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40evf_get_tx_pending - how many Tx descriptors not processed
 131  * @tx_ring: the ring of descriptors
 132  *
 133  * Since there is no access to the ring head register
 134  * in XL710, we need to use our local copies
 135  **/
 136 u32 i40evf_get_tx_pending(struct i40e_ring *ring)
 137 {
 138         u32 head, tail;
 139
 140         head = i40e_get_head(ring);
 141         tail = readl(ring->tail);
 142
 143         if (head != tail)
 144                 return (head < tail) ?
 145                         tail - head : (tail + ring->count - head);
 146
 147         return 0;
 148 }
 149
 150 #define WB_STRIDE 0x3
 151
 152 /**
 153  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 154  * @tx_ring:  tx ring to clean
 155  * @budget:   how many cleans we're allowed
 156  *
 157  * Returns true if there's any budget left (e.g. the clean is finished)
 158  **/
 159 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 160 {
 161         u16 i = tx_ring->next_to_clean;
 162         struct i40e_tx_buffer *tx_buf;
 163         struct i40e_tx_desc *tx_head;
 164         struct i40e_tx_desc *tx_desc;
 165         unsigned int total_packets = 0;
 166         unsigned int total_bytes = 0;
 167
 168         tx_buf = &tx_ring->tx_bi[i];
 169         tx_desc = I40E_TX_DESC(tx_ring, i);
 170         i -= tx_ring->count;
 171
 172         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 173
 174         do {
 175                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 176
 177                 /* if next_to_watch is not set then there is no work pending */
 178                 if (!eop_desc)
 179                         break;
 180
 181                 /* prevent any other reads prior to eop_desc */
 182                 read_barrier_depends();
 183
 184                 /* we have caught up to head, no work left to do */
 185                 if (tx_head == tx_desc)
 186                         break;
 187
 188                 /* clear next_to_watch to prevent false hangs */
 189                 tx_buf->next_to_watch = NULL;
 190
 191                 /* update the statistics for this packet */
 192                 total_bytes += tx_buf->bytecount;
 193                 total_packets += tx_buf->gso_segs;
 194
 195                 /* free the skb */
 196                 dev_kfree_skb_any(tx_buf->skb);
 197
 198                 /* unmap skb header data */
 199                 dma_unmap_single(tx_ring->dev,
 200                                  dma_unmap_addr(tx_buf, dma),
 201                                  dma_unmap_len(tx_buf, len),
 202                                  DMA_TO_DEVICE);
 203
 204                 /* clear tx_buffer data */
 205                 tx_buf->skb = NULL;
 206                 dma_unmap_len_set(tx_buf, len, 0);
 207
 208                 /* unmap remaining buffers */
 209                 while (tx_desc != eop_desc) {
 210
 211                         tx_buf++;
 212                         tx_desc++;
 213                         i++;
 214                         if (unlikely(!i)) {
 215                                 i -= tx_ring->count;
 216                                 tx_buf = tx_ring->tx_bi;
 217                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 218                         }
 219
 220                         /* unmap any remaining paged data */
 221                         if (dma_unmap_len(tx_buf, len)) {
 222                                 dma_unmap_page(tx_ring->dev,
 223                                                dma_unmap_addr(tx_buf, dma),
 224                                                dma_unmap_len(tx_buf, len),
 225                                                DMA_TO_DEVICE);
 226                                 dma_unmap_len_set(tx_buf, len, 0);
 227                         }
 228                 }
 229
 230                 /* move us one more past the eop_desc for start of next pkt */
 231                 tx_buf++;
 232                 tx_desc++;
 233                 i++;
 234                 if (unlikely(!i)) {
 235                         i -= tx_ring->count;
 236                         tx_buf = tx_ring->tx_bi;
 237                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 238                 }
 239
 240                 prefetch(tx_desc);
 241
 242                 /* update budget accounting */
 243                 budget--;
 244         } while (likely(budget));
 245
 246         i += tx_ring->count;
 247         tx_ring->next_to_clean = i;
 248         u64_stats_update_begin(&tx_ring->syncp);
 249         tx_ring->stats.bytes += total_bytes;
 250         tx_ring->stats.packets += total_packets;
 251         u64_stats_update_end(&tx_ring->syncp);
 252         tx_ring->q_vector->tx.total_bytes += total_bytes;
 253         tx_ring->q_vector->tx.total_packets += total_packets;
 254
 255         if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 256                 unsigned int j = 0;
 257                 /* check to see if there are < 4 descriptors
 258                  * waiting to be written back, then kick the hardware to force
 259                  * them to be written back in case we stay in NAPI.
 260                  * In this mode on X722 we do not enable Interrupt.
 261                  */
 262                 j = i40evf_get_tx_pending(tx_ring);
 263
 264                 if (budget &&
 265                     ((j / (WB_STRIDE + 1)) == 0) && (j > 0) &&
 266                     !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 267                     (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 268                         tx_ring->arm_wb = true;
 269         }
 270
 271         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 272                                                       tx_ring->queue_index),
 273                                   total_packets, total_bytes);
 274
 275 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 276         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 277                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 278                 /* Make sure that anybody stopping the queue after this
 279                  * sees the new next_to_clean.
 280                  */
 281                 smp_mb();
 282                 if (__netif_subqueue_stopped(tx_ring->netdev,
 283                                              tx_ring->queue_index) &&
 284                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 285                         netif_wake_subqueue(tx_ring->netdev,
 286                                             tx_ring->queue_index);
 287                         ++tx_ring->tx_stats.restart_queue;
 288                 }
 289         }
 290
 291         return !!budget;
 292 }
 293
 294 /**
 295  * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
 296  * @vsi: the VSI we care about
 297  * @q_vector: the vector on which to enable writeback
 298  *
 299  **/
 300 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
 301                                   struct i40e_q_vector *q_vector)
 302 {
 303         u16 flags = q_vector->tx.ring[0].flags;
 304         u32 val;
 305
 306         if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
 307                 return;
 308
 309         if (q_vector->arm_wb_state)
 310                 return;
 311
 312         val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
 313               I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
 314
 315         wr32(&vsi->back->hw,
 316              I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 317                                   vsi->base_vector - 1), val);
 318         q_vector->arm_wb_state = true;
 319 }
 320
 321 /**
 322  * i40evf_force_wb - Issue SW Interrupt so HW does a wb
 323  * @vsi: the VSI we care about
 324  * @q_vector: the vector  on which to force writeback
 325  *
 326  **/
 327 void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 328 {
 329         u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 330                   I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 331                   I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 332                   I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
 333                   /* allow 00 to be written to the index */;
 334
 335         wr32(&vsi->back->hw,
 336              I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
 337              val);
 338 }
 339
 340 /**
 341  * i40e_set_new_dynamic_itr - Find new ITR level
 342  * @rc: structure containing ring performance data
 343  *
 344  * Returns true if ITR changed, false if not
 345  *
 346  * Stores a new ITR value based on packets and byte counts during
 347  * the last interrupt.  The advantage of per interrupt computation
 348  * is faster updates and more accurate ITR for the current traffic
 349  * pattern.  Constants in this function were computed based on
 350  * theoretical maximum wire speed and thresholds were set based on
 351  * testing data as well as attempting to minimize response time
 352  * while increasing bulk throughput.
 353  **/
 354 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 355 {
 356         enum i40e_latency_range new_latency_range = rc->latency_range;
 357         struct i40e_q_vector *qv = rc->ring->q_vector;
 358         u32 new_itr = rc->itr;
 359         int bytes_per_int;
 360         int usecs;
 361
 362         if (rc->total_packets == 0 || !rc->itr)
 363                 return false;
 364
 365         /* simple throttlerate management
 366          *   0-10MB/s   lowest (50000 ints/s)
 367          *  10-20MB/s   low    (20000 ints/s)
 368          *  20-1249MB/s bulk   (18000 ints/s)
 369          *  > 40000 Rx packets per second (8000 ints/s)
 370          *
 371          * The math works out because the divisor is in 10^(-6) which
 372          * turns the bytes/us input value into MB/s values, but
 373          * make sure to use usecs, as the register values written
 374          * are in 2 usec increments in the ITR registers, and make sure
 375          * to use the smoothed values that the countdown timer gives us.
 376          */
 377         usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
 378         bytes_per_int = rc->total_bytes / usecs;
 379
 380         switch (new_latency_range) {
 381         case I40E_LOWEST_LATENCY:
 382                 if (bytes_per_int > 10)
 383                         new_latency_range = I40E_LOW_LATENCY;
 384                 break;
 385         case I40E_LOW_LATENCY:
 386                 if (bytes_per_int > 20)
 387                         new_latency_range = I40E_BULK_LATENCY;
 388                 else if (bytes_per_int <= 10)
 389                         new_latency_range = I40E_LOWEST_LATENCY;
 390                 break;
 391         case I40E_BULK_LATENCY:
 392         case I40E_ULTRA_LATENCY:
 393         default:
 394                 if (bytes_per_int <= 20)
 395                         new_latency_range = I40E_LOW_LATENCY;
 396                 break;
 397         }
 398
 399         /* this is to adjust RX more aggressively when streaming small
 400          * packets.  The value of 40000 was picked as it is just beyond
 401          * what the hardware can receive per second if in low latency
 402          * mode.
 403          */
 404 #define RX_ULTRA_PACKET_RATE 40000
 405
 406         if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
 407             (&qv->rx == rc))
 408                 new_latency_range = I40E_ULTRA_LATENCY;
 409
 410         rc->latency_range = new_latency_range;
 411
 412         switch (new_latency_range) {
 413         case I40E_LOWEST_LATENCY:
 414                 new_itr = I40E_ITR_50K;
 415                 break;
 416         case I40E_LOW_LATENCY:
 417                 new_itr = I40E_ITR_20K;
 418                 break;
 419         case I40E_BULK_LATENCY:
 420                 new_itr = I40E_ITR_18K;
 421                 break;
 422         case I40E_ULTRA_LATENCY:
 423                 new_itr = I40E_ITR_8K;
 424                 break;
 425         default:
 426                 break;
 427         }
 428
 429         rc->total_bytes = 0;
 430         rc->total_packets = 0;
 431
 432         if (new_itr != rc->itr) {
 433                 rc->itr = new_itr;
 434                 return true;
 435         }
 436
 437         return false;
 438 }
 439
 440 /**
 441  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 442  * @tx_ring: the tx ring to set up
 443  *
 444  * Return 0 on success, negative on error
 445  **/
 446 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 447 {
 448         struct device *dev = tx_ring->dev;
 449         int bi_size;
 450
 451         if (!dev)
 452                 return -ENOMEM;
 453
 454         /* warn if we are about to overwrite the pointer */
 455         WARN_ON(tx_ring->tx_bi);
 456         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 457         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 458         if (!tx_ring->tx_bi)
 459                 goto err;
 460
 461         /* round up to nearest 4K */
 462         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 463         /* add u32 for head writeback, align after this takes care of
 464          * guaranteeing this is at least one cache line in size
 465          */
 466         tx_ring->size += sizeof(u32);
 467         tx_ring->size = ALIGN(tx_ring->size, 4096);
 468         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 469                                            &tx_ring->dma, GFP_KERNEL);
 470         if (!tx_ring->desc) {
 471                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 472                          tx_ring->size);
 473                 goto err;
 474         }
 475
 476         tx_ring->next_to_use = 0;
 477         tx_ring->next_to_clean = 0;
 478         return 0;
 479
 480 err:
 481         kfree(tx_ring->tx_bi);
 482         tx_ring->tx_bi = NULL;
 483         return -ENOMEM;
 484 }
 485
 486 /**
 487  * i40evf_clean_rx_ring - Free Rx buffers
 488  * @rx_ring: ring to be cleaned
 489  **/
 490 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 491 {
 492         struct device *dev = rx_ring->dev;
 493         struct i40e_rx_buffer *rx_bi;
 494         unsigned long bi_size;
 495         u16 i;
 496
 497         /* ring already cleared, nothing to do */
 498         if (!rx_ring->rx_bi)
 499                 return;
 500
 501         if (ring_is_ps_enabled(rx_ring)) {
 502                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 503
 504                 rx_bi = &rx_ring->rx_bi[0];
 505                 if (rx_bi->hdr_buf) {
 506                         dma_free_coherent(dev,
 507                                           bufsz,
 508                                           rx_bi->hdr_buf,
 509                                           rx_bi->dma);
 510                         for (i = 0; i < rx_ring->count; i++) {
 511                                 rx_bi = &rx_ring->rx_bi[i];
 512                                 rx_bi->dma = 0;
 513                                 rx_bi->hdr_buf = NULL;
 514                         }
 515                 }
 516         }
 517         /* Free all the Rx ring sk_buffs */
 518         for (i = 0; i < rx_ring->count; i++) {
 519                 rx_bi = &rx_ring->rx_bi[i];
 520                 if (rx_bi->dma) {
 521                         dma_unmap_single(dev,
 522                                          rx_bi->dma,
 523                                          rx_ring->rx_buf_len,
 524                                          DMA_FROM_DEVICE);
 525                         rx_bi->dma = 0;
 526                 }
 527                 if (rx_bi->skb) {
 528                         dev_kfree_skb(rx_bi->skb);
 529                         rx_bi->skb = NULL;
 530                 }
 531                 if (rx_bi->page) {
 532                         if (rx_bi->page_dma) {
 533                                 dma_unmap_page(dev,
 534                                                rx_bi->page_dma,
 535                                                PAGE_SIZE,
 536                                                DMA_FROM_DEVICE);
 537                                 rx_bi->page_dma = 0;
 538                         }
 539                         __free_page(rx_bi->page);
 540                         rx_bi->page = NULL;
 541                         rx_bi->page_offset = 0;
 542                 }
 543         }
 544
 545         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 546         memset(rx_ring->rx_bi, 0, bi_size);
 547
 548         /* Zero out the descriptor ring */
 549         memset(rx_ring->desc, 0, rx_ring->size);
 550
 551         rx_ring->next_to_clean = 0;
 552         rx_ring->next_to_use = 0;
 553 }
 554
 555 /**
 556  * i40evf_free_rx_resources - Free Rx resources
 557  * @rx_ring: ring to clean the resources from
 558  *
 559  * Free all receive software resources
 560  **/
 561 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 562 {
 563         i40evf_clean_rx_ring(rx_ring);
 564         kfree(rx_ring->rx_bi);
 565         rx_ring->rx_bi = NULL;
 566
 567         if (rx_ring->desc) {
 568                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 569                                   rx_ring->desc, rx_ring->dma);
 570                 rx_ring->desc = NULL;
 571         }
 572 }
 573
 574 /**
 575  * i40evf_alloc_rx_headers - allocate rx header buffers
 576  * @rx_ring: ring to alloc buffers
 577  *
 578  * Allocate rx header buffers for the entire ring. As these are static,
 579  * this is only called when setting up a new ring.
 580  **/
 581 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 582 {
 583         struct device *dev = rx_ring->dev;
 584         struct i40e_rx_buffer *rx_bi;
 585         dma_addr_t dma;
 586         void *buffer;
 587         int buf_size;
 588         int i;
 589
 590         if (rx_ring->rx_bi[0].hdr_buf)
 591                 return;
 592         /* Make sure the buffers don't cross cache line boundaries. */
 593         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 594         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 595                                     &dma, GFP_KERNEL);
 596         if (!buffer)
 597                 return;
 598         for (i = 0; i < rx_ring->count; i++) {
 599                 rx_bi = &rx_ring->rx_bi[i];
 600                 rx_bi->dma = dma + (i * buf_size);
 601                 rx_bi->hdr_buf = buffer + (i * buf_size);
 602         }
 603 }
 604
 605 /**
 606  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 607  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 608  *
 609  * Returns 0 on success, negative on failure
 610  **/
 611 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 612 {
 613         struct device *dev = rx_ring->dev;
 614         int bi_size;
 615
 616         /* warn if we are about to overwrite the pointer */
 617         WARN_ON(rx_ring->rx_bi);
 618         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 619         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 620         if (!rx_ring->rx_bi)
 621                 goto err;
 622
 623         u64_stats_init(&rx_ring->syncp);
 624
 625         /* Round up to nearest 4K */
 626         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 627                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 628                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 629         rx_ring->size = ALIGN(rx_ring->size, 4096);
 630         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 631                                            &rx_ring->dma, GFP_KERNEL);
 632
 633         if (!rx_ring->desc) {
 634                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 635                          rx_ring->size);
 636                 goto err;
 637         }
 638
 639         rx_ring->next_to_clean = 0;
 640         rx_ring->next_to_use = 0;
 641
 642         return 0;
 643 err:
 644         kfree(rx_ring->rx_bi);
 645         rx_ring->rx_bi = NULL;
 646         return -ENOMEM;
 647 }
 648
 649 /**
 650  * i40e_release_rx_desc - Store the new tail and head values
 651  * @rx_ring: ring to bump
 652  * @val: new head index
 653  **/
 654 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 655 {
 656         rx_ring->next_to_use = val;
 657         /* Force memory writes to complete before letting h/w
 658          * know there are new descriptors to fetch.  (Only
 659          * applicable for weak-ordered memory model archs,
 660          * such as IA-64).
 661          */
 662         wmb();
 663         writel(val, rx_ring->tail);
 664 }
 665
 666 /**
 667  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 668  * @rx_ring: ring to place buffers on
 669  * @cleaned_count: number of buffers to replace
 670  *
 671  * Returns true if any errors on allocation
 672  **/
 673 bool i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 674 {
 675         u16 i = rx_ring->next_to_use;
 676         union i40e_rx_desc *rx_desc;
 677         struct i40e_rx_buffer *bi;
 678         const int current_node = numa_node_id();
 679
 680         /* do nothing if no valid netdev defined */
 681         if (!rx_ring->netdev || !cleaned_count)
 682                 return false;
 683
 684         while (cleaned_count--) {
 685                 rx_desc = I40E_RX_DESC(rx_ring, i);
 686                 bi = &rx_ring->rx_bi[i];
 687
 688                 if (bi->skb) /* desc is in use */
 689                         goto no_buffers;
 690
 691         /* If we've been moved to a different NUMA node, release the
 692          * page so we can get a new one on the current node.
 693          */
 694                 if (bi->page &&  page_to_nid(bi->page) != current_node) {
 695                         dma_unmap_page(rx_ring->dev,
 696                                        bi->page_dma,
 697                                        PAGE_SIZE,
 698                                        DMA_FROM_DEVICE);
 699                         __free_page(bi->page);
 700                         bi->page = NULL;
 701                         bi->page_dma = 0;
 702                         rx_ring->rx_stats.realloc_count++;
 703                 } else if (bi->page) {
 704                         rx_ring->rx_stats.page_reuse_count++;
 705                 }
 706
 707                 if (!bi->page) {
 708                         bi->page = alloc_page(GFP_ATOMIC);
 709                         if (!bi->page) {
 710                                 rx_ring->rx_stats.alloc_page_failed++;
 711                                 goto no_buffers;
 712                         }
 713                         bi->page_dma = dma_map_page(rx_ring->dev,
 714                                                     bi->page,
 715                                                     0,
 716                                                     PAGE_SIZE,
 717                                                     DMA_FROM_DEVICE);
 718                         if (dma_mapping_error(rx_ring->dev, bi->page_dma)) {
 719                                 rx_ring->rx_stats.alloc_page_failed++;
 720                                 __free_page(bi->page);
 721                                 bi->page = NULL;
 722                                 bi->page_dma = 0;
 723                                 bi->page_offset = 0;
 724                                 goto no_buffers;
 725                         }
 726                         bi->page_offset = 0;
 727                 }
 728
 729                 /* Refresh the desc even if buffer_addrs didn't change
 730                  * because each write-back erases this info.
 731                  */
 732                 rx_desc->read.pkt_addr =
 733                                 cpu_to_le64(bi->page_dma + bi->page_offset);
 734                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 735                 i++;
 736                 if (i == rx_ring->count)
 737                         i = 0;
 738         }
 739
 740         if (rx_ring->next_to_use != i)
 741                 i40e_release_rx_desc(rx_ring, i);
 742
 743         return false;
 744
 745 no_buffers:
 746         if (rx_ring->next_to_use != i)
 747                 i40e_release_rx_desc(rx_ring, i);
 748
 749         /* make sure to come back via polling to try again after
 750          * allocation failure
 751          */
 752         return true;
 753 }
 754
 755 /**
 756  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 757  * @rx_ring: ring to place buffers on
 758  * @cleaned_count: number of buffers to replace
 759  *
 760  * Returns true if any errors on allocation
 761  **/
 762 bool i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 763 {
 764         u16 i = rx_ring->next_to_use;
 765         union i40e_rx_desc *rx_desc;
 766         struct i40e_rx_buffer *bi;
 767         struct sk_buff *skb;
 768
 769         /* do nothing if no valid netdev defined */
 770         if (!rx_ring->netdev || !cleaned_count)
 771                 return false;
 772
 773         while (cleaned_count--) {
 774                 rx_desc = I40E_RX_DESC(rx_ring, i);
 775                 bi = &rx_ring->rx_bi[i];
 776                 skb = bi->skb;
 777
 778                 if (!skb) {
 779                         skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
 780                                                           rx_ring->rx_buf_len,
 781                                                           GFP_ATOMIC |
 782                                                           __GFP_NOWARN);
 783                         if (!skb) {
 784                                 rx_ring->rx_stats.alloc_buff_failed++;
 785                                 goto no_buffers;
 786                         }
 787                         /* initialize queue mapping */
 788                         skb_record_rx_queue(skb, rx_ring->queue_index);
 789                         bi->skb = skb;
 790                 }
 791
 792                 if (!bi->dma) {
 793                         bi->dma = dma_map_single(rx_ring->dev,
 794                                                  skb->data,
 795                                                  rx_ring->rx_buf_len,
 796                                                  DMA_FROM_DEVICE);
 797                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 798                                 rx_ring->rx_stats.alloc_buff_failed++;
 799                                 bi->dma = 0;
 800                                 dev_kfree_skb(bi->skb);
 801                                 bi->skb = NULL;
 802                                 goto no_buffers;
 803                         }
 804                 }
 805
 806                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 807                 rx_desc->read.hdr_addr = 0;
 808                 i++;
 809                 if (i == rx_ring->count)
 810                         i = 0;
 811         }
 812
 813         if (rx_ring->next_to_use != i)
 814                 i40e_release_rx_desc(rx_ring, i);
 815
 816         return false;
 817
 818 no_buffers:
 819         if (rx_ring->next_to_use != i)
 820                 i40e_release_rx_desc(rx_ring, i);
 821
 822         /* make sure to come back via polling to try again after
 823          * allocation failure
 824          */
 825         return true;
 826 }
 827
 828 /**
 829  * i40e_receive_skb - Send a completed packet up the stack
 830  * @rx_ring:  rx ring in play
 831  * @skb: packet to send up
 832  * @vlan_tag: vlan tag for packet
 833  **/
 834 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 835                              struct sk_buff *skb, u16 vlan_tag)
 836 {
 837         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 838
 839         if (vlan_tag & VLAN_VID_MASK)
 840                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 841
 842         napi_gro_receive(&q_vector->napi, skb);
 843 }
 844
 845 /**
 846  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 847  * @vsi: the VSI we care about
 848  * @skb: skb currently being received and modified
 849  * @rx_status: status value of last descriptor in packet
 850  * @rx_error: error value of last descriptor in packet
 851  * @rx_ptype: ptype value of last descriptor in packet
 852  **/
 853 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 854                                     struct sk_buff *skb,
 855                                     u32 rx_status,
 856                                     u32 rx_error,
 857                                     u16 rx_ptype)
 858 {
 859         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 860         bool ipv4 = false, ipv6 = false;
 861         bool ipv4_tunnel, ipv6_tunnel;
 862         __wsum rx_udp_csum;
 863         struct iphdr *iph;
 864         __sum16 csum;
 865
 866         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 867                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 868         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 869                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 870
 871         skb->ip_summed = CHECKSUM_NONE;
 872
 873         /* Rx csum enabled and ip headers found? */
 874         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 875                 return;
 876
 877         /* did the hardware decode the packet and checksum? */
 878         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 879                 return;
 880
 881         /* both known and outer_ip must be set for the below code to work */
 882         if (!(decoded.known && decoded.outer_ip))
 883                 return;
 884
 885         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 886             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 887                 ipv4 = true;
 888         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 889                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 890                 ipv6 = true;
 891
 892         if (ipv4 &&
 893             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
 894                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 895                 goto checksum_fail;
 896
 897         /* likely incorrect csum if alternate IP extension headers found */
 898         if (ipv6 &&
 899             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 900                 /* don't increment checksum err here, non-fatal err */
 901                 return;
 902
 903         /* there was some L4 error, count error and punt packet to the stack */
 904         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
 905                 goto checksum_fail;
 906
 907         /* handle packets that were not able to be checksummed due
 908          * to arrival speed, in this case the stack can compute
 909          * the csum.
 910          */
 911         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
 912                 return;
 913
 914         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 915          * it in the driver, hardware does not do it for us.
 916          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 917          * so the total length of IPv4 header is IHL*4 bytes
 918          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 919          */
 920         if (ipv4_tunnel) {
 921                 skb->transport_header = skb->mac_header +
 922                                         sizeof(struct ethhdr) +
 923                                         (ip_hdr(skb)->ihl * 4);
 924
 925                 /* Add 4 bytes for VLAN tagged packets */
 926                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 927                                           skb->protocol == htons(ETH_P_8021AD))
 928                                           ? VLAN_HLEN : 0;
 929
 930                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
 931                     (udp_hdr(skb)->check != 0)) {
 932                         rx_udp_csum = udp_csum(skb);
 933                         iph = ip_hdr(skb);
 934                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
 935                                                  (skb->len -
 936                                                   skb_transport_offset(skb)),
 937                                                  IPPROTO_UDP, rx_udp_csum);
 938
 939                         if (udp_hdr(skb)->check != csum)
 940                                 goto checksum_fail;
 941
 942                 } /* else its GRE and so no outer UDP header */
 943         }
 944
 945         skb->ip_summed = CHECKSUM_UNNECESSARY;
 946         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 947
 948         return;
 949
 950 checksum_fail:
 951         vsi->back->hw_csum_rx_error++;
 952 }
 953
 954 /**
 955  * i40e_ptype_to_htype - get a hash type
 956  * @ptype: the ptype value from the descriptor
 957  *
 958  * Returns a hash type to be used by skb_set_hash
 959  **/
 960 static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
 961 {
 962         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 963
 964         if (!decoded.known)
 965                 return PKT_HASH_TYPE_NONE;
 966
 967         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 968             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 969                 return PKT_HASH_TYPE_L4;
 970         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 971                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 972                 return PKT_HASH_TYPE_L3;
 973         else
 974                 return PKT_HASH_TYPE_L2;
 975 }
 976
 977 /**
 978  * i40e_rx_hash - set the hash value in the skb
 979  * @ring: descriptor ring
 980  * @rx_desc: specific descriptor
 981  **/
 982 static inline void i40e_rx_hash(struct i40e_ring *ring,
 983                                 union i40e_rx_desc *rx_desc,
 984                                 struct sk_buff *skb,
 985                                 u8 rx_ptype)
 986 {
 987         u32 hash;
 988         const __le64 rss_mask  =
 989                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 990                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 991
 992         if (ring->netdev->features & NETIF_F_RXHASH)
 993                 return;
 994
 995         if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
 996                 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 997                 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
 998         }
 999 }
1000
1001 /**
1002  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
1003  * @rx_ring:  rx ring to clean
1004  * @budget:   how many cleans we're allowed
1005  *
1006  * Returns true if there's any budget left (e.g. the clean is finished)
1007  **/
1008 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, const int budget)
1009 {
1010         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1011         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1012         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1013         struct i40e_vsi *vsi = rx_ring->vsi;
1014         u16 i = rx_ring->next_to_clean;
1015         union i40e_rx_desc *rx_desc;
1016         u32 rx_error, rx_status;
1017         bool failure = false;
1018         u8 rx_ptype;
1019         u64 qword;
1020         u32 copysize;
1021
1022         do {
1023                 struct i40e_rx_buffer *rx_bi;
1024                 struct sk_buff *skb;
1025                 u16 vlan_tag;
1026                 /* return some buffers to hardware, one at a time is too slow */
1027                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1028                         failure = failure ||
1029                                   i40evf_alloc_rx_buffers_ps(rx_ring,
1030                                                              cleaned_count);
1031                         cleaned_count = 0;
1032                 }
1033
1034                 i = rx_ring->next_to_clean;
1035                 rx_desc = I40E_RX_DESC(rx_ring, i);
1036                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1037                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1038                         I40E_RXD_QW1_STATUS_SHIFT;
1039
1040                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1041                         break;
1042
1043                 /* This memory barrier is needed to keep us from reading
1044                  * any other fields out of the rx_desc until we know the
1045                  * DD bit is set.
1046                  */
1047                 dma_rmb();
1048                 /* sync header buffer for reading */
1049                 dma_sync_single_range_for_cpu(rx_ring->dev,
1050                                               rx_ring->rx_bi[0].dma,
1051                                               i * rx_ring->rx_hdr_len,
1052                                               rx_ring->rx_hdr_len,
1053                                               DMA_FROM_DEVICE);
1054                 rx_bi = &rx_ring->rx_bi[i];
1055                 skb = rx_bi->skb;
1056                 if (likely(!skb)) {
1057                         skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
1058                                                           rx_ring->rx_hdr_len,
1059                                                           GFP_ATOMIC |
1060                                                           __GFP_NOWARN);
1061                         if (!skb) {
1062                                 rx_ring->rx_stats.alloc_buff_failed++;
1063                                 failure = true;
1064                                 break;
1065                         }
1066
1067                         /* initialize queue mapping */
1068                         skb_record_rx_queue(skb, rx_ring->queue_index);
1069                         /* we are reusing so sync this buffer for CPU use */
1070                         dma_sync_single_range_for_cpu(rx_ring->dev,
1071                                                       rx_ring->rx_bi[0].dma,
1072                                                       i * rx_ring->rx_hdr_len,
1073                                                       rx_ring->rx_hdr_len,
1074                                                       DMA_FROM_DEVICE);
1075                 }
1076                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1077                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1078                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1079                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1080                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1081                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1082
1083                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1084                            I40E_RXD_QW1_ERROR_SHIFT;
1085                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1086                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1087
1088                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1089                            I40E_RXD_QW1_PTYPE_SHIFT;
1090                 /* sync half-page for reading */
1091                 dma_sync_single_range_for_cpu(rx_ring->dev,
1092                                               rx_bi->page_dma,
1093                                               rx_bi->page_offset,
1094                                               PAGE_SIZE / 2,
1095                                               DMA_FROM_DEVICE);
1096                 prefetch(page_address(rx_bi->page) + rx_bi->page_offset);
1097                 rx_bi->skb = NULL;
1098                 cleaned_count++;
1099                 copysize = 0;
1100                 if (rx_hbo || rx_sph) {
1101                         int len;
1102
1103                         if (rx_hbo)
1104                                 len = I40E_RX_HDR_SIZE;
1105                         else
1106                                 len = rx_header_len;
1107                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1108                 } else if (skb->len == 0) {
1109                         int len;
1110                         unsigned char *va = page_address(rx_bi->page) +
1111                                             rx_bi->page_offset;
1112
1113                         len = min(rx_packet_len, rx_ring->rx_hdr_len);
1114                         memcpy(__skb_put(skb, len), va, len);
1115                         copysize = len;
1116                         rx_packet_len -= len;
1117                 }
1118                 /* Get the rest of the data if this was a header split */
1119                 if (rx_packet_len) {
1120                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1121                                         rx_bi->page,
1122                                         rx_bi->page_offset + copysize,
1123                                         rx_packet_len, I40E_RXBUFFER_2048);
1124
1125                         get_page(rx_bi->page);
1126                         /* switch to the other half-page here; the allocation
1127                          * code programs the right addr into HW. If we haven't
1128                          * used this half-page, the address won't be changed,
1129                          * and HW can just use it next time through.
1130                          */
1131                         rx_bi->page_offset ^= PAGE_SIZE / 2;
1132                         /* If the page count is more than 2, then both halves
1133                          * of the page are used and we need to free it. Do it
1134                          * here instead of in the alloc code. Otherwise one
1135                          * of the half-pages might be released between now and
1136                          * then, and we wouldn't know which one to use.
1137                          */
1138                         if (page_count(rx_bi->page) > 2) {
1139                                 dma_unmap_page(rx_ring->dev,
1140                                                rx_bi->page_dma,
1141                                                PAGE_SIZE,
1142                                                DMA_FROM_DEVICE);
1143                                 __free_page(rx_bi->page);
1144                                 rx_bi->page = NULL;
1145                                 rx_bi->page_dma = 0;
1146                                 rx_ring->rx_stats.realloc_count++;
1147                         }
1148
1149                 }
1150                 I40E_RX_INCREMENT(rx_ring, i);
1151
1152                 if (unlikely(
1153                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1154                         struct i40e_rx_buffer *next_buffer;
1155
1156                         next_buffer = &rx_ring->rx_bi[i];
1157                         next_buffer->skb = skb;
1158                         rx_ring->rx_stats.non_eop_descs++;
1159                         continue;
1160                 }
1161
1162                 /* ERR_MASK will only have valid bits if EOP set */
1163                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1164                         dev_kfree_skb_any(skb);
1165                         continue;
1166                 }
1167
1168                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1169
1170                 /* probably a little skewed due to removing CRC */
1171                 total_rx_bytes += skb->len;
1172                 total_rx_packets++;
1173
1174                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1175
1176                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1177
1178                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1179                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1180                          : 0;
1181 #ifdef I40E_FCOE
1182                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1183                         dev_kfree_skb_any(skb);
1184                         continue;
1185                 }
1186 #endif
1187                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1188
1189                 rx_desc->wb.qword1.status_error_len = 0;
1190
1191         } while (likely(total_rx_packets < budget));
1192
1193         u64_stats_update_begin(&rx_ring->syncp);
1194         rx_ring->stats.packets += total_rx_packets;
1195         rx_ring->stats.bytes += total_rx_bytes;
1196         u64_stats_update_end(&rx_ring->syncp);
1197         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1198         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1199
1200         return failure ? budget : total_rx_packets;
1201 }
1202
1203 /**
1204  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1205  * @rx_ring:  rx ring to clean
1206  * @budget:   how many cleans we're allowed
1207  *
1208  * Returns number of packets cleaned
1209  **/
1210 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1211 {
1212         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1213         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1214         struct i40e_vsi *vsi = rx_ring->vsi;
1215         union i40e_rx_desc *rx_desc;
1216         u32 rx_error, rx_status;
1217         u16 rx_packet_len;
1218         bool failure = false;
1219         u8 rx_ptype;
1220         u64 qword;
1221         u16 i;
1222
1223         do {
1224                 struct i40e_rx_buffer *rx_bi;
1225                 struct sk_buff *skb;
1226                 u16 vlan_tag;
1227                 /* return some buffers to hardware, one at a time is too slow */
1228                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1229                         failure = failure ||
1230                                   i40evf_alloc_rx_buffers_1buf(rx_ring,
1231                                                                cleaned_count);
1232                         cleaned_count = 0;
1233                 }
1234
1235                 i = rx_ring->next_to_clean;
1236                 rx_desc = I40E_RX_DESC(rx_ring, i);
1237                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1238                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1239                         I40E_RXD_QW1_STATUS_SHIFT;
1240
1241                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1242                         break;
1243
1244                 /* This memory barrier is needed to keep us from reading
1245                  * any other fields out of the rx_desc until we know the
1246                  * DD bit is set.
1247                  */
1248                 dma_rmb();
1249
1250                 rx_bi = &rx_ring->rx_bi[i];
1251                 skb = rx_bi->skb;
1252                 prefetch(skb->data);
1253
1254                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1255                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1256
1257                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1258                            I40E_RXD_QW1_ERROR_SHIFT;
1259                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1260
1261                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1262                            I40E_RXD_QW1_PTYPE_SHIFT;
1263                 rx_bi->skb = NULL;
1264                 cleaned_count++;
1265
1266                 /* Get the header and possibly the whole packet
1267                  * If this is an skb from previous receive dma will be 0
1268                  */
1269                 skb_put(skb, rx_packet_len);
1270                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1271                                  DMA_FROM_DEVICE);
1272                 rx_bi->dma = 0;
1273
1274                 I40E_RX_INCREMENT(rx_ring, i);
1275
1276                 if (unlikely(
1277                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1278                         rx_ring->rx_stats.non_eop_descs++;
1279                         continue;
1280                 }
1281
1282                 /* ERR_MASK will only have valid bits if EOP set */
1283                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1284                         dev_kfree_skb_any(skb);
1285                         continue;
1286                 }
1287
1288                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1289                 /* probably a little skewed due to removing CRC */
1290                 total_rx_bytes += skb->len;
1291                 total_rx_packets++;
1292
1293                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1294
1295                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1296
1297                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1298                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1299                          : 0;
1300                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1301
1302                 rx_desc->wb.qword1.status_error_len = 0;
1303         } while (likely(total_rx_packets < budget));
1304
1305         u64_stats_update_begin(&rx_ring->syncp);
1306         rx_ring->stats.packets += total_rx_packets;
1307         rx_ring->stats.bytes += total_rx_bytes;
1308         u64_stats_update_end(&rx_ring->syncp);
1309         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1310         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1311
1312         return failure ? budget : total_rx_packets;
1313 }
1314
1315 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1316 {
1317         u32 val;
1318
1319         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1320               /* Don't clear PBA because that can cause lost interrupts that
1321                * came in while we were cleaning/polling
1322                */
1323               (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1324               (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1325
1326         return val;
1327 }
1328
1329 /* a small macro to shorten up some long lines */
1330 #define INTREG I40E_VFINT_DYN_CTLN1
1331
1332 /**
1333  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1334  * @vsi: the VSI we care about
1335  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1336  *
1337  **/
1338 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1339                                           struct i40e_q_vector *q_vector)
1340 {
1341         struct i40e_hw *hw = &vsi->back->hw;
1342         bool rx = false, tx = false;
1343         u32 rxval, txval;
1344         int vector;
1345
1346         vector = (q_vector->v_idx + vsi->base_vector);
1347
1348         /* avoid dynamic calculation if in countdown mode OR if
1349          * all dynamic is disabled
1350          */
1351         rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1352
1353         if (q_vector->itr_countdown > 0 ||
1354             (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1355              !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1356                 goto enable_int;
1357         }
1358
1359         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1360                 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1361                 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1362         }
1363
1364         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1365                 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1366                 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1367         }
1368
1369         if (rx || tx) {
1370                 /* get the higher of the two ITR adjustments and
1371                  * use the same value for both ITR registers
1372                  * when in adaptive mode (Rx and/or Tx)
1373                  */
1374                 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1375
1376                 q_vector->tx.itr = q_vector->rx.itr = itr;
1377                 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1378                 tx = true;
1379                 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1380                 rx = true;
1381         }
1382
1383         /* only need to enable the interrupt once, but need
1384          * to possibly update both ITR values
1385          */
1386         if (rx) {
1387                 /* set the INTENA_MSK_MASK so that this first write
1388                  * won't actually enable the interrupt, instead just
1389                  * updating the ITR (it's bit 31 PF and VF)
1390                  */
1391                 rxval |= BIT(31);
1392                 /* don't check _DOWN because interrupt isn't being enabled */
1393                 wr32(hw, INTREG(vector - 1), rxval);
1394         }
1395
1396 enable_int:
1397         if (!test_bit(__I40E_DOWN, &vsi->state))
1398                 wr32(hw, INTREG(vector - 1), txval);
1399
1400         if (q_vector->itr_countdown)
1401                 q_vector->itr_countdown--;
1402         else
1403                 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1404 }
1405
1406 /**
1407  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1408  * @napi: napi struct with our devices info in it
1409  * @budget: amount of work driver is allowed to do this pass, in packets
1410  *
1411  * This function will clean all queues associated with a q_vector.
1412  *
1413  * Returns the amount of work done
1414  **/
1415 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1416 {
1417         struct i40e_q_vector *q_vector =
1418                                container_of(napi, struct i40e_q_vector, napi);
1419         struct i40e_vsi *vsi = q_vector->vsi;
1420         struct i40e_ring *ring;
1421         bool clean_complete = true;
1422         bool arm_wb = false;
1423         int budget_per_ring;
1424         int work_done = 0;
1425
1426         if (test_bit(__I40E_DOWN, &vsi->state)) {
1427                 napi_complete(napi);
1428                 return 0;
1429         }
1430
1431         /* Since the actual Tx work is minimal, we can give the Tx a larger
1432          * budget and be more aggressive about cleaning up the Tx descriptors.
1433          */
1434         i40e_for_each_ring(ring, q_vector->tx) {
1435                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1436                 arm_wb = arm_wb || ring->arm_wb;
1437                 ring->arm_wb = false;
1438         }
1439
1440         /* Handle case where we are called by netpoll with a budget of 0 */
1441         if (budget <= 0)
1442                 goto tx_only;
1443
1444         /* We attempt to distribute budget to each Rx queue fairly, but don't
1445          * allow the budget to go below 1 because that would exit polling early.
1446          */
1447         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1448
1449         i40e_for_each_ring(ring, q_vector->rx) {
1450                 int cleaned;
1451
1452                 if (ring_is_ps_enabled(ring))
1453                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1454                 else
1455                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1456
1457                 work_done += cleaned;
1458                 /* if we didn't clean as many as budgeted, we must be done */
1459                 clean_complete &= (budget_per_ring != cleaned);
1460         }
1461
1462         /* If work not completed, return budget and polling will return */
1463         if (!clean_complete) {
1464 tx_only:
1465                 if (arm_wb) {
1466                         q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1467                         i40e_enable_wb_on_itr(vsi, q_vector);
1468                 }
1469                 return budget;
1470         }
1471
1472         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1473                 q_vector->arm_wb_state = false;
1474
1475         /* Work is done so exit the polling mode and re-enable the interrupt */
1476         napi_complete_done(napi, work_done);
1477         i40e_update_enable_itr(vsi, q_vector);
1478         return 0;
1479 }
1480
1481 /**
1482  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1483  * @skb:     send buffer
1484  * @tx_ring: ring to send buffer on
1485  * @flags:   the tx flags to be set
1486  *
1487  * Checks the skb and set up correspondingly several generic transmit flags
1488  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1489  *
1490  * Returns error code indicate the frame should be dropped upon error and the
1491  * otherwise  returns 0 to indicate the flags has been set properly.
1492  **/
1493 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1494                                                struct i40e_ring *tx_ring,
1495                                                u32 *flags)
1496 {
1497         __be16 protocol = skb->protocol;
1498         u32  tx_flags = 0;
1499
1500         if (protocol == htons(ETH_P_8021Q) &&
1501             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1502                 /* When HW VLAN acceleration is turned off by the user the
1503                  * stack sets the protocol to 8021q so that the driver
1504                  * can take any steps required to support the SW only
1505                  * VLAN handling.  In our case the driver doesn't need
1506                  * to take any further steps so just set the protocol
1507                  * to the encapsulated ethertype.
1508                  */
1509                 skb->protocol = vlan_get_protocol(skb);
1510                 goto out;
1511         }
1512
1513         /* if we have a HW VLAN tag being added, default to the HW one */
1514         if (skb_vlan_tag_present(skb)) {
1515                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1516                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1517         /* else if it is a SW VLAN, check the next protocol and store the tag */
1518         } else if (protocol == htons(ETH_P_8021Q)) {
1519                 struct vlan_hdr *vhdr, _vhdr;
1520
1521                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1522                 if (!vhdr)
1523                         return -EINVAL;
1524
1525                 protocol = vhdr->h_vlan_encapsulated_proto;
1526                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1527                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1528         }
1529
1530 out:
1531         *flags = tx_flags;
1532         return 0;
1533 }
1534
1535 /**
1536  * i40e_tso - set up the tso context descriptor
1537  * @tx_ring:  ptr to the ring to send
1538  * @skb:      ptr to the skb we're sending
1539  * @hdr_len:  ptr to the size of the packet header
1540  * @cd_type_cmd_tso_mss: Quad Word 1
1541  *
1542  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1543  **/
1544 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1545                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
1546 {
1547         u32 cd_cmd, cd_tso_len, cd_mss;
1548         struct ipv6hdr *ipv6h;
1549         struct tcphdr *tcph;
1550         struct iphdr *iph;
1551         u32 l4len;
1552         int err;
1553
1554         if (skb->ip_summed != CHECKSUM_PARTIAL)
1555                 return 0;
1556
1557         if (!skb_is_gso(skb))
1558                 return 0;
1559
1560         err = skb_cow_head(skb, 0);
1561         if (err < 0)
1562                 return err;
1563
1564         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1565         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1566
1567         if (iph->version == 4) {
1568                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1569                 iph->tot_len = 0;
1570                 iph->check = 0;
1571                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1572                                                  0, IPPROTO_TCP, 0);
1573         } else if (ipv6h->version == 6) {
1574                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1575                 ipv6h->payload_len = 0;
1576                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1577                                                0, IPPROTO_TCP, 0);
1578         }
1579
1580         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1581         *hdr_len = (skb->encapsulation
1582                     ? (skb_inner_transport_header(skb) - skb->data)
1583                     : skb_transport_offset(skb)) + l4len;
1584
1585         /* find the field values */
1586         cd_cmd = I40E_TX_CTX_DESC_TSO;
1587         cd_tso_len = skb->len - *hdr_len;
1588         cd_mss = skb_shinfo(skb)->gso_size;
1589         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1590                                 ((u64)cd_tso_len <<
1591                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1592                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1593         return 1;
1594 }
1595
1596 /**
1597  * i40e_tx_enable_csum - Enable Tx checksum offloads
1598  * @skb: send buffer
1599  * @tx_flags: pointer to Tx flags currently set
1600  * @td_cmd: Tx descriptor command bits to set
1601  * @td_offset: Tx descriptor header offsets to set
1602  * @cd_tunneling: ptr to context desc bits
1603  **/
1604 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1605                                 u32 *td_cmd, u32 *td_offset,
1606                                 struct i40e_ring *tx_ring,
1607                                 u32 *cd_tunneling)
1608 {
1609         struct ipv6hdr *this_ipv6_hdr;
1610         unsigned int this_tcp_hdrlen;
1611         struct iphdr *this_ip_hdr;
1612         u32 network_hdr_len;
1613         u8 l4_hdr = 0;
1614         struct udphdr *oudph;
1615         struct iphdr *oiph;
1616         u32 l4_tunnel = 0;
1617
1618         if (skb->encapsulation) {
1619                 switch (ip_hdr(skb)->protocol) {
1620                 case IPPROTO_UDP:
1621                         oudph = udp_hdr(skb);
1622                         oiph = ip_hdr(skb);
1623                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1624                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1625                         break;
1626                 default:
1627                         return;
1628                 }
1629                 network_hdr_len = skb_inner_network_header_len(skb);
1630                 this_ip_hdr = inner_ip_hdr(skb);
1631                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1632                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1633
1634                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1635                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1636                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1637                                 ip_hdr(skb)->check = 0;
1638                         } else {
1639                                 *cd_tunneling |=
1640                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1641                         }
1642                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1643                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1644                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1645                                 ip_hdr(skb)->check = 0;
1646                 }
1647
1648                 /* Now set the ctx descriptor fields */
1649                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1650                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1651                                    l4_tunnel                             |
1652                                    ((skb_inner_network_offset(skb) -
1653                                         skb_transport_offset(skb)) >> 1) <<
1654                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1655                 if (this_ip_hdr->version == 6) {
1656                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1657                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1658                 }
1659
1660                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1661                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
1662                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1663                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1664                                         oiph->daddr,
1665                                         (skb->len - skb_transport_offset(skb)),
1666                                         IPPROTO_UDP, 0);
1667                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1668                 }
1669         } else {
1670                 network_hdr_len = skb_network_header_len(skb);
1671                 this_ip_hdr = ip_hdr(skb);
1672                 this_ipv6_hdr = ipv6_hdr(skb);
1673                 this_tcp_hdrlen = tcp_hdrlen(skb);
1674         }
1675
1676         /* Enable IP checksum offloads */
1677         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1678                 l4_hdr = this_ip_hdr->protocol;
1679                 /* the stack computes the IP header already, the only time we
1680                  * need the hardware to recompute it is in the case of TSO.
1681                  */
1682                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1683                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1684                         this_ip_hdr->check = 0;
1685                 } else {
1686                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1687                 }
1688                 /* Now set the td_offset for IP header length */
1689                 *td_offset = (network_hdr_len >> 2) <<
1690                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1691         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1692                 l4_hdr = this_ipv6_hdr->nexthdr;
1693                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1694                 /* Now set the td_offset for IP header length */
1695                 *td_offset = (network_hdr_len >> 2) <<
1696                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1697         }
1698         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1699         *td_offset |= (skb_network_offset(skb) >> 1) <<
1700                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1701
1702         /* Enable L4 checksum offloads */
1703         switch (l4_hdr) {
1704         case IPPROTO_TCP:
1705                 /* enable checksum offloads */
1706                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1707                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1708                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1709                 break;
1710         case IPPROTO_SCTP:
1711                 /* enable SCTP checksum offload */
1712                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1713                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1714                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1715                 break;
1716         case IPPROTO_UDP:
1717                 /* enable UDP checksum offload */
1718                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1719                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1720                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1721                 break;
1722         default:
1723                 break;
1724         }
1725 }
1726
1727 /**
1728  * i40e_create_tx_ctx Build the Tx context descriptor
1729  * @tx_ring:  ring to create the descriptor on
1730  * @cd_type_cmd_tso_mss: Quad Word 1
1731  * @cd_tunneling: Quad Word 0 - bits 0-31
1732  * @cd_l2tag2: Quad Word 0 - bits 32-63
1733  **/
1734 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1735                                const u64 cd_type_cmd_tso_mss,
1736                                const u32 cd_tunneling, const u32 cd_l2tag2)
1737 {
1738         struct i40e_tx_context_desc *context_desc;
1739         int i = tx_ring->next_to_use;
1740
1741         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1742             !cd_tunneling && !cd_l2tag2)
1743                 return;
1744
1745         /* grab the next descriptor */
1746         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1747
1748         i++;
1749         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1750
1751         /* cpu_to_le32 and assign to struct fields */
1752         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1753         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1754         context_desc->rsvd = cpu_to_le16(0);
1755         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1756 }
1757
1758 /**
1759  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1760  * @skb:      send buffer
1761  * @tx_flags: collected send information
1762  *
1763  * Note: Our HW can't scatter-gather more than 8 fragments to build
1764  * a packet on the wire and so we need to figure out the cases where we
1765  * need to linearize the skb.
1766  **/
1767 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1768 {
1769         struct skb_frag_struct *frag;
1770         bool linearize = false;
1771         unsigned int size = 0;
1772         u16 num_frags;
1773         u16 gso_segs;
1774
1775         num_frags = skb_shinfo(skb)->nr_frags;
1776         gso_segs = skb_shinfo(skb)->gso_segs;
1777
1778         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1779                 u16 j = 0;
1780
1781                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1782                         goto linearize_chk_done;
1783                 /* try the simple math, if we have too many frags per segment */
1784                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1785                     I40E_MAX_BUFFER_TXD) {
1786                         linearize = true;
1787                         goto linearize_chk_done;
1788                 }
1789                 frag = &skb_shinfo(skb)->frags[0];
1790                 /* we might still have more fragments per segment */
1791                 do {
1792                         size += skb_frag_size(frag);
1793                         frag++; j++;
1794                         if ((size >= skb_shinfo(skb)->gso_size) &&
1795                             (j < I40E_MAX_BUFFER_TXD)) {
1796                                 size = (size % skb_shinfo(skb)->gso_size);
1797                                 j = (size) ? 1 : 0;
1798                         }
1799                         if (j == I40E_MAX_BUFFER_TXD) {
1800                                 linearize = true;
1801                                 break;
1802                         }
1803                         num_frags--;
1804                 } while (num_frags);
1805         } else {
1806                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1807                         linearize = true;
1808         }
1809
1810 linearize_chk_done:
1811         return linearize;
1812 }
1813
1814 /**
1815  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1816  * @tx_ring: the ring to be checked
1817  * @size:    the size buffer we want to assure is available
1818  *
1819  * Returns -EBUSY if a stop is needed, else 0
1820  **/
1821 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1822 {
1823         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1824         /* Memory barrier before checking head and tail */
1825         smp_mb();
1826
1827         /* Check again in a case another CPU has just made room available. */
1828         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1829                 return -EBUSY;
1830
1831         /* A reprieve! - use start_queue because it doesn't call schedule */
1832         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1833         ++tx_ring->tx_stats.restart_queue;
1834         return 0;
1835 }
1836
1837 /**
1838  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1839  * @tx_ring: the ring to be checked
1840  * @size:    the size buffer we want to assure is available
1841  *
1842  * Returns 0 if stop is not needed
1843  **/
1844 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1845 {
1846         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1847                 return 0;
1848         return __i40evf_maybe_stop_tx(tx_ring, size);
1849 }
1850
1851 /**
1852  * i40evf_tx_map - Build the Tx descriptor
1853  * @tx_ring:  ring to send buffer on
1854  * @skb:      send buffer
1855  * @first:    first buffer info buffer to use
1856  * @tx_flags: collected send information
1857  * @hdr_len:  size of the packet header
1858  * @td_cmd:   the command field in the descriptor
1859  * @td_offset: offset for checksum or crc
1860  **/
1861 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1862                                  struct i40e_tx_buffer *first, u32 tx_flags,
1863                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1864 {
1865         unsigned int data_len = skb->data_len;
1866         unsigned int size = skb_headlen(skb);
1867         struct skb_frag_struct *frag;
1868         struct i40e_tx_buffer *tx_bi;
1869         struct i40e_tx_desc *tx_desc;
1870         u16 i = tx_ring->next_to_use;
1871         u32 td_tag = 0;
1872         dma_addr_t dma;
1873         u16 gso_segs;
1874         u16 desc_count = 0;
1875         bool tail_bump = true;
1876         bool do_rs = false;
1877
1878         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1879                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1880                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1881                          I40E_TX_FLAGS_VLAN_SHIFT;
1882         }
1883
1884         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1885                 gso_segs = skb_shinfo(skb)->gso_segs;
1886         else
1887                 gso_segs = 1;
1888
1889         /* multiply data chunks by size of headers */
1890         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1891         first->gso_segs = gso_segs;
1892         first->skb = skb;
1893         first->tx_flags = tx_flags;
1894
1895         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1896
1897         tx_desc = I40E_TX_DESC(tx_ring, i);
1898         tx_bi = first;
1899
1900         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1901                 if (dma_mapping_error(tx_ring->dev, dma))
1902                         goto dma_error;
1903
1904                 /* record length, and DMA address */
1905                 dma_unmap_len_set(tx_bi, len, size);
1906                 dma_unmap_addr_set(tx_bi, dma, dma);
1907
1908                 tx_desc->buffer_addr = cpu_to_le64(dma);
1909
1910                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1911                         tx_desc->cmd_type_offset_bsz =
1912                                 build_ctob(td_cmd, td_offset,
1913                                            I40E_MAX_DATA_PER_TXD, td_tag);
1914
1915                         tx_desc++;
1916                         i++;
1917                         desc_count++;
1918
1919                         if (i == tx_ring->count) {
1920                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1921                                 i = 0;
1922                         }
1923
1924                         dma += I40E_MAX_DATA_PER_TXD;
1925                         size -= I40E_MAX_DATA_PER_TXD;
1926
1927                         tx_desc->buffer_addr = cpu_to_le64(dma);
1928                 }
1929
1930                 if (likely(!data_len))
1931                         break;
1932
1933                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1934                                                           size, td_tag);
1935
1936                 tx_desc++;
1937                 i++;
1938                 desc_count++;
1939
1940                 if (i == tx_ring->count) {
1941                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1942                         i = 0;
1943                 }
1944
1945                 size = skb_frag_size(frag);
1946                 data_len -= size;
1947
1948                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1949                                        DMA_TO_DEVICE);
1950
1951                 tx_bi = &tx_ring->tx_bi[i];
1952         }
1953
1954         /* set next_to_watch value indicating a packet is present */
1955         first->next_to_watch = tx_desc;
1956
1957         i++;
1958         if (i == tx_ring->count)
1959                 i = 0;
1960
1961         tx_ring->next_to_use = i;
1962
1963         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1964                                                  tx_ring->queue_index),
1965                                                  first->bytecount);
1966         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1967
1968         /* Algorithm to optimize tail and RS bit setting:
1969          * if xmit_more is supported
1970          *      if xmit_more is true
1971          *              do not update tail and do not mark RS bit.
1972          *      if xmit_more is false and last xmit_more was false
1973          *              if every packet spanned less than 4 desc
1974          *                      then set RS bit on 4th packet and update tail
1975          *                      on every packet
1976          *              else
1977          *                      update tail and set RS bit on every packet.
1978          *      if xmit_more is false and last_xmit_more was true
1979          *              update tail and set RS bit.
1980          *
1981          * Optimization: wmb to be issued only in case of tail update.
1982          * Also optimize the Descriptor WB path for RS bit with the same
1983          * algorithm.
1984          *
1985          * Note: If there are less than 4 packets
1986          * pending and interrupts were disabled the service task will
1987          * trigger a force WB.
1988          */
1989         if (skb->xmit_more  &&
1990             !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1991                                                     tx_ring->queue_index))) {
1992                 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1993                 tail_bump = false;
1994         } else if (!skb->xmit_more &&
1995                    !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1996                                                        tx_ring->queue_index)) &&
1997                    (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
1998                    (tx_ring->packet_stride < WB_STRIDE) &&
1999                    (desc_count < WB_STRIDE)) {
2000                 tx_ring->packet_stride++;
2001         } else {
2002                 tx_ring->packet_stride = 0;
2003                 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2004                 do_rs = true;
2005         }
2006         if (do_rs)
2007                 tx_ring->packet_stride = 0;
2008
2009         tx_desc->cmd_type_offset_bsz =
2010                         build_ctob(td_cmd, td_offset, size, td_tag) |
2011                         cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
2012                                                   I40E_TX_DESC_CMD_EOP) <<
2013                                                   I40E_TXD_QW1_CMD_SHIFT);
2014
2015         /* notify HW of packet */
2016         if (!tail_bump)
2017                 prefetchw(tx_desc + 1);
2018
2019         if (tail_bump) {
2020                 /* Force memory writes to complete before letting h/w
2021                  * know there are new descriptors to fetch.  (Only
2022                  * applicable for weak-ordered memory model archs,
2023                  * such as IA-64).
2024                  */
2025                 wmb();
2026                 writel(i, tx_ring->tail);
2027         }
2028
2029         return;
2030
2031 dma_error:
2032         dev_info(tx_ring->dev, "TX DMA map failed\n");
2033
2034         /* clear dma mappings for failed tx_bi map */
2035         for (;;) {
2036                 tx_bi = &tx_ring->tx_bi[i];
2037                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2038                 if (tx_bi == first)
2039                         break;
2040                 if (i == 0)
2041                         i = tx_ring->count;
2042                 i--;
2043         }
2044
2045         tx_ring->next_to_use = i;
2046 }
2047
2048 /**
2049  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
2050  * @skb:     send buffer
2051  * @tx_ring: ring to send buffer on
2052  *
2053  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
2054  * there is not enough descriptors available in this ring since we need at least
2055  * one descriptor.
2056  **/
2057 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
2058                                                struct i40e_ring *tx_ring)
2059 {
2060         unsigned int f;
2061         int count = 0;
2062
2063         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2064          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2065          *       + 4 desc gap to avoid the cache line where head is,
2066          *       + 1 desc for context descriptor,
2067          * otherwise try next time
2068          */
2069         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
2070                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
2071
2072         count += TXD_USE_COUNT(skb_headlen(skb));
2073         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2074                 tx_ring->tx_stats.tx_busy++;
2075                 return 0;
2076         }
2077         return count;
2078 }
2079
2080 /**
2081  * i40e_xmit_frame_ring - Sends buffer on Tx ring
2082  * @skb:     send buffer
2083  * @tx_ring: ring to send buffer on
2084  *
2085  * Returns NETDEV_TX_OK if sent, else an error code
2086  **/
2087 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2088                                         struct i40e_ring *tx_ring)
2089 {
2090         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2091         u32 cd_tunneling = 0, cd_l2tag2 = 0;
2092         struct i40e_tx_buffer *first;
2093         u32 td_offset = 0;
2094         u32 tx_flags = 0;
2095         __be16 protocol;
2096         u32 td_cmd = 0;
2097         u8 hdr_len = 0;
2098         int tso;
2099
2100         /* prefetch the data, we'll need it later */
2101         prefetch(skb->data);
2102
2103         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
2104                 return NETDEV_TX_BUSY;
2105
2106         /* prepare the xmit flags */
2107         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2108                 goto out_drop;
2109
2110         /* obtain protocol of skb */
2111         protocol = vlan_get_protocol(skb);
2112
2113         /* record the location of the first descriptor for this packet */
2114         first = &tx_ring->tx_bi[tx_ring->next_to_use];
2115
2116         /* setup IPv4/IPv6 offloads */
2117         if (protocol == htons(ETH_P_IP))
2118                 tx_flags |= I40E_TX_FLAGS_IPV4;
2119         else if (protocol == htons(ETH_P_IPV6))
2120                 tx_flags |= I40E_TX_FLAGS_IPV6;
2121
2122         tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss);
2123
2124         if (tso < 0)
2125                 goto out_drop;
2126         else if (tso)
2127                 tx_flags |= I40E_TX_FLAGS_TSO;
2128
2129         if (i40e_chk_linearize(skb, tx_flags)) {
2130                 if (skb_linearize(skb))
2131                         goto out_drop;
2132                 tx_ring->tx_stats.tx_linearize++;
2133         }
2134         skb_tx_timestamp(skb);
2135
2136         /* always enable CRC insertion offload */
2137         td_cmd |= I40E_TX_DESC_CMD_ICRC;
2138
2139         /* Always offload the checksum, since it's in the data descriptor */
2140         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2141                 tx_flags |= I40E_TX_FLAGS_CSUM;
2142
2143                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2144                                     tx_ring, &cd_tunneling);
2145         }
2146
2147         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2148                            cd_tunneling, cd_l2tag2);
2149
2150         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2151                       td_cmd, td_offset);
2152
2153         return NETDEV_TX_OK;
2154
2155 out_drop:
2156         dev_kfree_skb_any(skb);
2157         return NETDEV_TX_OK;
2158 }
2159
2160 /**
2161  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2162  * @skb:    send buffer
2163  * @netdev: network interface device structure
2164  *
2165  * Returns NETDEV_TX_OK if sent, else an error code
2166  **/
2167 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2168 {
2169         struct i40evf_adapter *adapter = netdev_priv(netdev);
2170         struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2171
2172         /* hardware can't handle really short frames, hardware padding works
2173          * beyond this point
2174          */
2175         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2176                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2177                         return NETDEV_TX_OK;
2178                 skb->len = I40E_MIN_TX_LEN;
2179                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2180         }
2181
2182         return i40e_xmit_frame_ring(skb, tx_ring);
2183 }