]> git.karo-electronics.de Git - karo-tx-linux.git/blob - drivers/net/ethernet/intel/i40evf/i40e_txrx.c
usb: chipidea: udc: remove unused value assignment
[karo-tx-linux.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c
1 /*******************************************************************************
2  *
3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4  * Copyright(c) 2013 - 2014 Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  * The full GNU General Public License is included in this distribution in
19  * the file called "COPYING".
20  *
21  * Contact Information:
22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  ******************************************************************************/
26
27 #include <linux/prefetch.h>
28 #include <net/busy_poll.h>
29
30 #include "i40evf.h"
31 #include "i40e_prototype.h"
32
33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
34                                 u32 td_tag)
35 {
36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
41 }
42
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
44
45 /**
46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47  * @ring:      the ring that owns the buffer
48  * @tx_buffer: the buffer to free
49  **/
50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
51                                             struct i40e_tx_buffer *tx_buffer)
52 {
53         if (tx_buffer->skb) {
54                 dev_kfree_skb_any(tx_buffer->skb);
55                 if (dma_unmap_len(tx_buffer, len))
56                         dma_unmap_single(ring->dev,
57                                          dma_unmap_addr(tx_buffer, dma),
58                                          dma_unmap_len(tx_buffer, len),
59                                          DMA_TO_DEVICE);
60         } else if (dma_unmap_len(tx_buffer, len)) {
61                 dma_unmap_page(ring->dev,
62                                dma_unmap_addr(tx_buffer, dma),
63                                dma_unmap_len(tx_buffer, len),
64                                DMA_TO_DEVICE);
65         }
66
67         if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
68                 kfree(tx_buffer->raw_buf);
69
70         tx_buffer->next_to_watch = NULL;
71         tx_buffer->skb = NULL;
72         dma_unmap_len_set(tx_buffer, len, 0);
73         /* tx_buffer must be completely set up in the transmit path */
74 }
75
76 /**
77  * i40evf_clean_tx_ring - Free any empty Tx buffers
78  * @tx_ring: ring to be cleaned
79  **/
80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
81 {
82         unsigned long bi_size;
83         u16 i;
84
85         /* ring already cleared, nothing to do */
86         if (!tx_ring->tx_bi)
87                 return;
88
89         /* Free all the Tx ring sk_buffs */
90         for (i = 0; i < tx_ring->count; i++)
91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
92
93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
94         memset(tx_ring->tx_bi, 0, bi_size);
95
96         /* Zero out the descriptor ring */
97         memset(tx_ring->desc, 0, tx_ring->size);
98
99         tx_ring->next_to_use = 0;
100         tx_ring->next_to_clean = 0;
101
102         if (!tx_ring->netdev)
103                 return;
104
105         /* cleanup Tx queue statistics */
106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
107                                                   tx_ring->queue_index));
108 }
109
110 /**
111  * i40evf_free_tx_resources - Free Tx resources per queue
112  * @tx_ring: Tx descriptor ring for a specific queue
113  *
114  * Free all transmit software resources
115  **/
116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
117 {
118         i40evf_clean_tx_ring(tx_ring);
119         kfree(tx_ring->tx_bi);
120         tx_ring->tx_bi = NULL;
121
122         if (tx_ring->desc) {
123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
124                                   tx_ring->desc, tx_ring->dma);
125                 tx_ring->desc = NULL;
126         }
127 }
128
129 /**
130  * i40evf_get_tx_pending - how many Tx descriptors not processed
131  * @tx_ring: the ring of descriptors
132  *
133  * Since there is no access to the ring head register
134  * in XL710, we need to use our local copies
135  **/
136 u32 i40evf_get_tx_pending(struct i40e_ring *ring)
137 {
138         u32 head, tail;
139
140         head = i40e_get_head(ring);
141         tail = readl(ring->tail);
142
143         if (head != tail)
144                 return (head < tail) ?
145                         tail - head : (tail + ring->count - head);
146
147         return 0;
148 }
149
150 #define WB_STRIDE 0x3
151
152 /**
153  * i40e_clean_tx_irq - Reclaim resources after transmit completes
154  * @tx_ring:  tx ring to clean
155  * @budget:   how many cleans we're allowed
156  *
157  * Returns true if there's any budget left (e.g. the clean is finished)
158  **/
159 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
160 {
161         u16 i = tx_ring->next_to_clean;
162         struct i40e_tx_buffer *tx_buf;
163         struct i40e_tx_desc *tx_head;
164         struct i40e_tx_desc *tx_desc;
165         unsigned int total_packets = 0;
166         unsigned int total_bytes = 0;
167
168         tx_buf = &tx_ring->tx_bi[i];
169         tx_desc = I40E_TX_DESC(tx_ring, i);
170         i -= tx_ring->count;
171
172         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
173
174         do {
175                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
176
177                 /* if next_to_watch is not set then there is no work pending */
178                 if (!eop_desc)
179                         break;
180
181                 /* prevent any other reads prior to eop_desc */
182                 read_barrier_depends();
183
184                 /* we have caught up to head, no work left to do */
185                 if (tx_head == tx_desc)
186                         break;
187
188                 /* clear next_to_watch to prevent false hangs */
189                 tx_buf->next_to_watch = NULL;
190
191                 /* update the statistics for this packet */
192                 total_bytes += tx_buf->bytecount;
193                 total_packets += tx_buf->gso_segs;
194
195                 /* free the skb */
196                 dev_kfree_skb_any(tx_buf->skb);
197
198                 /* unmap skb header data */
199                 dma_unmap_single(tx_ring->dev,
200                                  dma_unmap_addr(tx_buf, dma),
201                                  dma_unmap_len(tx_buf, len),
202                                  DMA_TO_DEVICE);
203
204                 /* clear tx_buffer data */
205                 tx_buf->skb = NULL;
206                 dma_unmap_len_set(tx_buf, len, 0);
207
208                 /* unmap remaining buffers */
209                 while (tx_desc != eop_desc) {
210
211                         tx_buf++;
212                         tx_desc++;
213                         i++;
214                         if (unlikely(!i)) {
215                                 i -= tx_ring->count;
216                                 tx_buf = tx_ring->tx_bi;
217                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
218                         }
219
220                         /* unmap any remaining paged data */
221                         if (dma_unmap_len(tx_buf, len)) {
222                                 dma_unmap_page(tx_ring->dev,
223                                                dma_unmap_addr(tx_buf, dma),
224                                                dma_unmap_len(tx_buf, len),
225                                                DMA_TO_DEVICE);
226                                 dma_unmap_len_set(tx_buf, len, 0);
227                         }
228                 }
229
230                 /* move us one more past the eop_desc for start of next pkt */
231                 tx_buf++;
232                 tx_desc++;
233                 i++;
234                 if (unlikely(!i)) {
235                         i -= tx_ring->count;
236                         tx_buf = tx_ring->tx_bi;
237                         tx_desc = I40E_TX_DESC(tx_ring, 0);
238                 }
239
240                 prefetch(tx_desc);
241
242                 /* update budget accounting */
243                 budget--;
244         } while (likely(budget));
245
246         i += tx_ring->count;
247         tx_ring->next_to_clean = i;
248         u64_stats_update_begin(&tx_ring->syncp);
249         tx_ring->stats.bytes += total_bytes;
250         tx_ring->stats.packets += total_packets;
251         u64_stats_update_end(&tx_ring->syncp);
252         tx_ring->q_vector->tx.total_bytes += total_bytes;
253         tx_ring->q_vector->tx.total_packets += total_packets;
254
255         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
256                                                       tx_ring->queue_index),
257                                   total_packets, total_bytes);
258
259 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
260         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
261                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
262                 /* Make sure that anybody stopping the queue after this
263                  * sees the new next_to_clean.
264                  */
265                 smp_mb();
266                 if (__netif_subqueue_stopped(tx_ring->netdev,
267                                              tx_ring->queue_index) &&
268                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
269                         netif_wake_subqueue(tx_ring->netdev,
270                                             tx_ring->queue_index);
271                         ++tx_ring->tx_stats.restart_queue;
272                 }
273         }
274
275         return !!budget;
276 }
277
278 /**
279  * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
280  * @vsi: the VSI we care about
281  * @q_vector: the vector  on which to force writeback
282  *
283  **/
284 static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
285 {
286         u16 flags = q_vector->tx.ring[0].flags;
287
288         if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
289                 u32 val;
290
291                 if (q_vector->arm_wb_state)
292                         return;
293
294                 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK;
295
296                 wr32(&vsi->back->hw,
297                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
298                                           vsi->base_vector - 1),
299                      val);
300                 q_vector->arm_wb_state = true;
301         } else {
302                 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
303                           I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
304                           I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
305                           I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
306                           /* allow 00 to be written to the index */
307
308                 wr32(&vsi->back->hw,
309                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
310                                           vsi->base_vector - 1), val);
311         }
312 }
313
314 /**
315  * i40e_set_new_dynamic_itr - Find new ITR level
316  * @rc: structure containing ring performance data
317  *
318  * Returns true if ITR changed, false if not
319  *
320  * Stores a new ITR value based on packets and byte counts during
321  * the last interrupt.  The advantage of per interrupt computation
322  * is faster updates and more accurate ITR for the current traffic
323  * pattern.  Constants in this function were computed based on
324  * theoretical maximum wire speed and thresholds were set based on
325  * testing data as well as attempting to minimize response time
326  * while increasing bulk throughput.
327  **/
328 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
329 {
330         enum i40e_latency_range new_latency_range = rc->latency_range;
331         struct i40e_q_vector *qv = rc->ring->q_vector;
332         u32 new_itr = rc->itr;
333         int bytes_per_int;
334         int usecs;
335
336         if (rc->total_packets == 0 || !rc->itr)
337                 return false;
338
339         /* simple throttlerate management
340          *   0-10MB/s   lowest (50000 ints/s)
341          *  10-20MB/s   low    (20000 ints/s)
342          *  20-1249MB/s bulk   (18000 ints/s)
343          *  > 40000 Rx packets per second (8000 ints/s)
344          *
345          * The math works out because the divisor is in 10^(-6) which
346          * turns the bytes/us input value into MB/s values, but
347          * make sure to use usecs, as the register values written
348          * are in 2 usec increments in the ITR registers, and make sure
349          * to use the smoothed values that the countdown timer gives us.
350          */
351         usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
352         bytes_per_int = rc->total_bytes / usecs;
353
354         switch (new_latency_range) {
355         case I40E_LOWEST_LATENCY:
356                 if (bytes_per_int > 10)
357                         new_latency_range = I40E_LOW_LATENCY;
358                 break;
359         case I40E_LOW_LATENCY:
360                 if (bytes_per_int > 20)
361                         new_latency_range = I40E_BULK_LATENCY;
362                 else if (bytes_per_int <= 10)
363                         new_latency_range = I40E_LOWEST_LATENCY;
364                 break;
365         case I40E_BULK_LATENCY:
366         case I40E_ULTRA_LATENCY:
367         default:
368                 if (bytes_per_int <= 20)
369                         new_latency_range = I40E_LOW_LATENCY;
370                 break;
371         }
372
373         /* this is to adjust RX more aggressively when streaming small
374          * packets.  The value of 40000 was picked as it is just beyond
375          * what the hardware can receive per second if in low latency
376          * mode.
377          */
378 #define RX_ULTRA_PACKET_RATE 40000
379
380         if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
381             (&qv->rx == rc))
382                 new_latency_range = I40E_ULTRA_LATENCY;
383
384         rc->latency_range = new_latency_range;
385
386         switch (new_latency_range) {
387         case I40E_LOWEST_LATENCY:
388                 new_itr = I40E_ITR_50K;
389                 break;
390         case I40E_LOW_LATENCY:
391                 new_itr = I40E_ITR_20K;
392                 break;
393         case I40E_BULK_LATENCY:
394                 new_itr = I40E_ITR_18K;
395                 break;
396         case I40E_ULTRA_LATENCY:
397                 new_itr = I40E_ITR_8K;
398                 break;
399         default:
400                 break;
401         }
402
403         rc->total_bytes = 0;
404         rc->total_packets = 0;
405
406         if (new_itr != rc->itr) {
407                 rc->itr = new_itr;
408                 return true;
409         }
410
411         return false;
412 }
413
414 /**
415  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
416  * @tx_ring: the tx ring to set up
417  *
418  * Return 0 on success, negative on error
419  **/
420 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
421 {
422         struct device *dev = tx_ring->dev;
423         int bi_size;
424
425         if (!dev)
426                 return -ENOMEM;
427
428         /* warn if we are about to overwrite the pointer */
429         WARN_ON(tx_ring->tx_bi);
430         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
431         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
432         if (!tx_ring->tx_bi)
433                 goto err;
434
435         /* round up to nearest 4K */
436         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
437         /* add u32 for head writeback, align after this takes care of
438          * guaranteeing this is at least one cache line in size
439          */
440         tx_ring->size += sizeof(u32);
441         tx_ring->size = ALIGN(tx_ring->size, 4096);
442         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
443                                            &tx_ring->dma, GFP_KERNEL);
444         if (!tx_ring->desc) {
445                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
446                          tx_ring->size);
447                 goto err;
448         }
449
450         tx_ring->next_to_use = 0;
451         tx_ring->next_to_clean = 0;
452         return 0;
453
454 err:
455         kfree(tx_ring->tx_bi);
456         tx_ring->tx_bi = NULL;
457         return -ENOMEM;
458 }
459
460 /**
461  * i40evf_clean_rx_ring - Free Rx buffers
462  * @rx_ring: ring to be cleaned
463  **/
464 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
465 {
466         struct device *dev = rx_ring->dev;
467         struct i40e_rx_buffer *rx_bi;
468         unsigned long bi_size;
469         u16 i;
470
471         /* ring already cleared, nothing to do */
472         if (!rx_ring->rx_bi)
473                 return;
474
475         if (ring_is_ps_enabled(rx_ring)) {
476                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
477
478                 rx_bi = &rx_ring->rx_bi[0];
479                 if (rx_bi->hdr_buf) {
480                         dma_free_coherent(dev,
481                                           bufsz,
482                                           rx_bi->hdr_buf,
483                                           rx_bi->dma);
484                         for (i = 0; i < rx_ring->count; i++) {
485                                 rx_bi = &rx_ring->rx_bi[i];
486                                 rx_bi->dma = 0;
487                                 rx_bi->hdr_buf = NULL;
488                         }
489                 }
490         }
491         /* Free all the Rx ring sk_buffs */
492         for (i = 0; i < rx_ring->count; i++) {
493                 rx_bi = &rx_ring->rx_bi[i];
494                 if (rx_bi->dma) {
495                         dma_unmap_single(dev,
496                                          rx_bi->dma,
497                                          rx_ring->rx_buf_len,
498                                          DMA_FROM_DEVICE);
499                         rx_bi->dma = 0;
500                 }
501                 if (rx_bi->skb) {
502                         dev_kfree_skb(rx_bi->skb);
503                         rx_bi->skb = NULL;
504                 }
505                 if (rx_bi->page) {
506                         if (rx_bi->page_dma) {
507                                 dma_unmap_page(dev,
508                                                rx_bi->page_dma,
509                                                PAGE_SIZE / 2,
510                                                DMA_FROM_DEVICE);
511                                 rx_bi->page_dma = 0;
512                         }
513                         __free_page(rx_bi->page);
514                         rx_bi->page = NULL;
515                         rx_bi->page_offset = 0;
516                 }
517         }
518
519         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
520         memset(rx_ring->rx_bi, 0, bi_size);
521
522         /* Zero out the descriptor ring */
523         memset(rx_ring->desc, 0, rx_ring->size);
524
525         rx_ring->next_to_clean = 0;
526         rx_ring->next_to_use = 0;
527 }
528
529 /**
530  * i40evf_free_rx_resources - Free Rx resources
531  * @rx_ring: ring to clean the resources from
532  *
533  * Free all receive software resources
534  **/
535 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
536 {
537         i40evf_clean_rx_ring(rx_ring);
538         kfree(rx_ring->rx_bi);
539         rx_ring->rx_bi = NULL;
540
541         if (rx_ring->desc) {
542                 dma_free_coherent(rx_ring->dev, rx_ring->size,
543                                   rx_ring->desc, rx_ring->dma);
544                 rx_ring->desc = NULL;
545         }
546 }
547
548 /**
549  * i40evf_alloc_rx_headers - allocate rx header buffers
550  * @rx_ring: ring to alloc buffers
551  *
552  * Allocate rx header buffers for the entire ring. As these are static,
553  * this is only called when setting up a new ring.
554  **/
555 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
556 {
557         struct device *dev = rx_ring->dev;
558         struct i40e_rx_buffer *rx_bi;
559         dma_addr_t dma;
560         void *buffer;
561         int buf_size;
562         int i;
563
564         if (rx_ring->rx_bi[0].hdr_buf)
565                 return;
566         /* Make sure the buffers don't cross cache line boundaries. */
567         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
568         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
569                                     &dma, GFP_KERNEL);
570         if (!buffer)
571                 return;
572         for (i = 0; i < rx_ring->count; i++) {
573                 rx_bi = &rx_ring->rx_bi[i];
574                 rx_bi->dma = dma + (i * buf_size);
575                 rx_bi->hdr_buf = buffer + (i * buf_size);
576         }
577 }
578
579 /**
580  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
581  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
582  *
583  * Returns 0 on success, negative on failure
584  **/
585 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
586 {
587         struct device *dev = rx_ring->dev;
588         int bi_size;
589
590         /* warn if we are about to overwrite the pointer */
591         WARN_ON(rx_ring->rx_bi);
592         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
593         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
594         if (!rx_ring->rx_bi)
595                 goto err;
596
597         u64_stats_init(&rx_ring->syncp);
598
599         /* Round up to nearest 4K */
600         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
601                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
602                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
603         rx_ring->size = ALIGN(rx_ring->size, 4096);
604         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
605                                            &rx_ring->dma, GFP_KERNEL);
606
607         if (!rx_ring->desc) {
608                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
609                          rx_ring->size);
610                 goto err;
611         }
612
613         rx_ring->next_to_clean = 0;
614         rx_ring->next_to_use = 0;
615
616         return 0;
617 err:
618         kfree(rx_ring->rx_bi);
619         rx_ring->rx_bi = NULL;
620         return -ENOMEM;
621 }
622
623 /**
624  * i40e_release_rx_desc - Store the new tail and head values
625  * @rx_ring: ring to bump
626  * @val: new head index
627  **/
628 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
629 {
630         rx_ring->next_to_use = val;
631         /* Force memory writes to complete before letting h/w
632          * know there are new descriptors to fetch.  (Only
633          * applicable for weak-ordered memory model archs,
634          * such as IA-64).
635          */
636         wmb();
637         writel(val, rx_ring->tail);
638 }
639
640 /**
641  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
642  * @rx_ring: ring to place buffers on
643  * @cleaned_count: number of buffers to replace
644  **/
645 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
646 {
647         u16 i = rx_ring->next_to_use;
648         union i40e_rx_desc *rx_desc;
649         struct i40e_rx_buffer *bi;
650
651         /* do nothing if no valid netdev defined */
652         if (!rx_ring->netdev || !cleaned_count)
653                 return;
654
655         while (cleaned_count--) {
656                 rx_desc = I40E_RX_DESC(rx_ring, i);
657                 bi = &rx_ring->rx_bi[i];
658
659                 if (bi->skb) /* desc is in use */
660                         goto no_buffers;
661                 if (!bi->page) {
662                         bi->page = alloc_page(GFP_ATOMIC);
663                         if (!bi->page) {
664                                 rx_ring->rx_stats.alloc_page_failed++;
665                                 goto no_buffers;
666                         }
667                 }
668
669                 if (!bi->page_dma) {
670                         /* use a half page if we're re-using */
671                         bi->page_offset ^= PAGE_SIZE / 2;
672                         bi->page_dma = dma_map_page(rx_ring->dev,
673                                                     bi->page,
674                                                     bi->page_offset,
675                                                     PAGE_SIZE / 2,
676                                                     DMA_FROM_DEVICE);
677                         if (dma_mapping_error(rx_ring->dev,
678                                               bi->page_dma)) {
679                                 rx_ring->rx_stats.alloc_page_failed++;
680                                 bi->page_dma = 0;
681                                 goto no_buffers;
682                         }
683                 }
684
685                 dma_sync_single_range_for_device(rx_ring->dev,
686                                                  bi->dma,
687                                                  0,
688                                                  rx_ring->rx_hdr_len,
689                                                  DMA_FROM_DEVICE);
690                 /* Refresh the desc even if buffer_addrs didn't change
691                  * because each write-back erases this info.
692                  */
693                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
694                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
695                 i++;
696                 if (i == rx_ring->count)
697                         i = 0;
698         }
699
700 no_buffers:
701         if (rx_ring->next_to_use != i)
702                 i40e_release_rx_desc(rx_ring, i);
703 }
704
705 /**
706  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
707  * @rx_ring: ring to place buffers on
708  * @cleaned_count: number of buffers to replace
709  **/
710 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
711 {
712         u16 i = rx_ring->next_to_use;
713         union i40e_rx_desc *rx_desc;
714         struct i40e_rx_buffer *bi;
715         struct sk_buff *skb;
716
717         /* do nothing if no valid netdev defined */
718         if (!rx_ring->netdev || !cleaned_count)
719                 return;
720
721         while (cleaned_count--) {
722                 rx_desc = I40E_RX_DESC(rx_ring, i);
723                 bi = &rx_ring->rx_bi[i];
724                 skb = bi->skb;
725
726                 if (!skb) {
727                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
728                                                         rx_ring->rx_buf_len);
729                         if (!skb) {
730                                 rx_ring->rx_stats.alloc_buff_failed++;
731                                 goto no_buffers;
732                         }
733                         /* initialize queue mapping */
734                         skb_record_rx_queue(skb, rx_ring->queue_index);
735                         bi->skb = skb;
736                 }
737
738                 if (!bi->dma) {
739                         bi->dma = dma_map_single(rx_ring->dev,
740                                                  skb->data,
741                                                  rx_ring->rx_buf_len,
742                                                  DMA_FROM_DEVICE);
743                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
744                                 rx_ring->rx_stats.alloc_buff_failed++;
745                                 bi->dma = 0;
746                                 goto no_buffers;
747                         }
748                 }
749
750                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
751                 rx_desc->read.hdr_addr = 0;
752                 i++;
753                 if (i == rx_ring->count)
754                         i = 0;
755         }
756
757 no_buffers:
758         if (rx_ring->next_to_use != i)
759                 i40e_release_rx_desc(rx_ring, i);
760 }
761
762 /**
763  * i40e_receive_skb - Send a completed packet up the stack
764  * @rx_ring:  rx ring in play
765  * @skb: packet to send up
766  * @vlan_tag: vlan tag for packet
767  **/
768 static void i40e_receive_skb(struct i40e_ring *rx_ring,
769                              struct sk_buff *skb, u16 vlan_tag)
770 {
771         struct i40e_q_vector *q_vector = rx_ring->q_vector;
772
773         if (vlan_tag & VLAN_VID_MASK)
774                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
775
776         napi_gro_receive(&q_vector->napi, skb);
777 }
778
779 /**
780  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
781  * @vsi: the VSI we care about
782  * @skb: skb currently being received and modified
783  * @rx_status: status value of last descriptor in packet
784  * @rx_error: error value of last descriptor in packet
785  * @rx_ptype: ptype value of last descriptor in packet
786  **/
787 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
788                                     struct sk_buff *skb,
789                                     u32 rx_status,
790                                     u32 rx_error,
791                                     u16 rx_ptype)
792 {
793         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
794         bool ipv4 = false, ipv6 = false;
795         bool ipv4_tunnel, ipv6_tunnel;
796         __wsum rx_udp_csum;
797         struct iphdr *iph;
798         __sum16 csum;
799
800         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
801                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
802         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
803                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
804
805         skb->ip_summed = CHECKSUM_NONE;
806
807         /* Rx csum enabled and ip headers found? */
808         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
809                 return;
810
811         /* did the hardware decode the packet and checksum? */
812         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
813                 return;
814
815         /* both known and outer_ip must be set for the below code to work */
816         if (!(decoded.known && decoded.outer_ip))
817                 return;
818
819         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
820             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
821                 ipv4 = true;
822         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
823                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
824                 ipv6 = true;
825
826         if (ipv4 &&
827             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
828                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
829                 goto checksum_fail;
830
831         /* likely incorrect csum if alternate IP extension headers found */
832         if (ipv6 &&
833             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
834                 /* don't increment checksum err here, non-fatal err */
835                 return;
836
837         /* there was some L4 error, count error and punt packet to the stack */
838         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
839                 goto checksum_fail;
840
841         /* handle packets that were not able to be checksummed due
842          * to arrival speed, in this case the stack can compute
843          * the csum.
844          */
845         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
846                 return;
847
848         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
849          * it in the driver, hardware does not do it for us.
850          * Since L3L4P bit was set we assume a valid IHL value (>=5)
851          * so the total length of IPv4 header is IHL*4 bytes
852          * The UDP_0 bit *may* bet set if the *inner* header is UDP
853          */
854         if (ipv4_tunnel) {
855                 skb->transport_header = skb->mac_header +
856                                         sizeof(struct ethhdr) +
857                                         (ip_hdr(skb)->ihl * 4);
858
859                 /* Add 4 bytes for VLAN tagged packets */
860                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
861                                           skb->protocol == htons(ETH_P_8021AD))
862                                           ? VLAN_HLEN : 0;
863
864                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
865                     (udp_hdr(skb)->check != 0)) {
866                         rx_udp_csum = udp_csum(skb);
867                         iph = ip_hdr(skb);
868                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
869                                                  (skb->len -
870                                                   skb_transport_offset(skb)),
871                                                  IPPROTO_UDP, rx_udp_csum);
872
873                         if (udp_hdr(skb)->check != csum)
874                                 goto checksum_fail;
875
876                 } /* else its GRE and so no outer UDP header */
877         }
878
879         skb->ip_summed = CHECKSUM_UNNECESSARY;
880         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
881
882         return;
883
884 checksum_fail:
885         vsi->back->hw_csum_rx_error++;
886 }
887
888 /**
889  * i40e_ptype_to_htype - get a hash type
890  * @ptype: the ptype value from the descriptor
891  *
892  * Returns a hash type to be used by skb_set_hash
893  **/
894 static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
895 {
896         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
897
898         if (!decoded.known)
899                 return PKT_HASH_TYPE_NONE;
900
901         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
902             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
903                 return PKT_HASH_TYPE_L4;
904         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
905                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
906                 return PKT_HASH_TYPE_L3;
907         else
908                 return PKT_HASH_TYPE_L2;
909 }
910
911 /**
912  * i40e_rx_hash - set the hash value in the skb
913  * @ring: descriptor ring
914  * @rx_desc: specific descriptor
915  **/
916 static inline void i40e_rx_hash(struct i40e_ring *ring,
917                                 union i40e_rx_desc *rx_desc,
918                                 struct sk_buff *skb,
919                                 u8 rx_ptype)
920 {
921         u32 hash;
922         const __le64 rss_mask  =
923                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
924                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
925
926         if (ring->netdev->features & NETIF_F_RXHASH)
927                 return;
928
929         if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
930                 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
931                 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
932         }
933 }
934
935 /**
936  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
937  * @rx_ring:  rx ring to clean
938  * @budget:   how many cleans we're allowed
939  *
940  * Returns true if there's any budget left (e.g. the clean is finished)
941  **/
942 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
943 {
944         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
945         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
946         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
947         const int current_node = numa_mem_id();
948         struct i40e_vsi *vsi = rx_ring->vsi;
949         u16 i = rx_ring->next_to_clean;
950         union i40e_rx_desc *rx_desc;
951         u32 rx_error, rx_status;
952         u8 rx_ptype;
953         u64 qword;
954
955         do {
956                 struct i40e_rx_buffer *rx_bi;
957                 struct sk_buff *skb;
958                 u16 vlan_tag;
959                 /* return some buffers to hardware, one at a time is too slow */
960                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
961                         i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
962                         cleaned_count = 0;
963                 }
964
965                 i = rx_ring->next_to_clean;
966                 rx_desc = I40E_RX_DESC(rx_ring, i);
967                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
968                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
969                         I40E_RXD_QW1_STATUS_SHIFT;
970
971                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
972                         break;
973
974                 /* This memory barrier is needed to keep us from reading
975                  * any other fields out of the rx_desc until we know the
976                  * DD bit is set.
977                  */
978                 dma_rmb();
979                 rx_bi = &rx_ring->rx_bi[i];
980                 skb = rx_bi->skb;
981                 if (likely(!skb)) {
982                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
983                                                         rx_ring->rx_hdr_len);
984                         if (!skb) {
985                                 rx_ring->rx_stats.alloc_buff_failed++;
986                                 break;
987                         }
988
989                         /* initialize queue mapping */
990                         skb_record_rx_queue(skb, rx_ring->queue_index);
991                         /* we are reusing so sync this buffer for CPU use */
992                         dma_sync_single_range_for_cpu(rx_ring->dev,
993                                                       rx_bi->dma,
994                                                       0,
995                                                       rx_ring->rx_hdr_len,
996                                                       DMA_FROM_DEVICE);
997                 }
998                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
999                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1000                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1001                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1002                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1003                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1004
1005                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1006                            I40E_RXD_QW1_ERROR_SHIFT;
1007                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1008                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1009
1010                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1011                            I40E_RXD_QW1_PTYPE_SHIFT;
1012                 prefetch(rx_bi->page);
1013                 rx_bi->skb = NULL;
1014                 cleaned_count++;
1015                 if (rx_hbo || rx_sph) {
1016                         int len;
1017
1018                         if (rx_hbo)
1019                                 len = I40E_RX_HDR_SIZE;
1020                         else
1021                                 len = rx_header_len;
1022                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1023                 } else if (skb->len == 0) {
1024                         int len;
1025
1026                         len = (rx_packet_len > skb_headlen(skb) ?
1027                                 skb_headlen(skb) : rx_packet_len);
1028                         memcpy(__skb_put(skb, len),
1029                                rx_bi->page + rx_bi->page_offset,
1030                                len);
1031                         rx_bi->page_offset += len;
1032                         rx_packet_len -= len;
1033                 }
1034
1035                 /* Get the rest of the data if this was a header split */
1036                 if (rx_packet_len) {
1037                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1038                                            rx_bi->page,
1039                                            rx_bi->page_offset,
1040                                            rx_packet_len);
1041
1042                         skb->len += rx_packet_len;
1043                         skb->data_len += rx_packet_len;
1044                         skb->truesize += rx_packet_len;
1045
1046                         if ((page_count(rx_bi->page) == 1) &&
1047                             (page_to_nid(rx_bi->page) == current_node))
1048                                 get_page(rx_bi->page);
1049                         else
1050                                 rx_bi->page = NULL;
1051
1052                         dma_unmap_page(rx_ring->dev,
1053                                        rx_bi->page_dma,
1054                                        PAGE_SIZE / 2,
1055                                        DMA_FROM_DEVICE);
1056                         rx_bi->page_dma = 0;
1057                 }
1058                 I40E_RX_INCREMENT(rx_ring, i);
1059
1060                 if (unlikely(
1061                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1062                         struct i40e_rx_buffer *next_buffer;
1063
1064                         next_buffer = &rx_ring->rx_bi[i];
1065                         next_buffer->skb = skb;
1066                         rx_ring->rx_stats.non_eop_descs++;
1067                         continue;
1068                 }
1069
1070                 /* ERR_MASK will only have valid bits if EOP set */
1071                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1072                         dev_kfree_skb_any(skb);
1073                         continue;
1074                 }
1075
1076                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1077
1078                 /* probably a little skewed due to removing CRC */
1079                 total_rx_bytes += skb->len;
1080                 total_rx_packets++;
1081
1082                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1083
1084                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1085
1086                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1087                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1088                          : 0;
1089 #ifdef I40E_FCOE
1090                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1091                         dev_kfree_skb_any(skb);
1092                         continue;
1093                 }
1094 #endif
1095                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1096
1097                 rx_desc->wb.qword1.status_error_len = 0;
1098
1099         } while (likely(total_rx_packets < budget));
1100
1101         u64_stats_update_begin(&rx_ring->syncp);
1102         rx_ring->stats.packets += total_rx_packets;
1103         rx_ring->stats.bytes += total_rx_bytes;
1104         u64_stats_update_end(&rx_ring->syncp);
1105         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1106         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1107
1108         return total_rx_packets;
1109 }
1110
1111 /**
1112  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1113  * @rx_ring:  rx ring to clean
1114  * @budget:   how many cleans we're allowed
1115  *
1116  * Returns number of packets cleaned
1117  **/
1118 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1119 {
1120         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1121         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1122         struct i40e_vsi *vsi = rx_ring->vsi;
1123         union i40e_rx_desc *rx_desc;
1124         u32 rx_error, rx_status;
1125         u16 rx_packet_len;
1126         u8 rx_ptype;
1127         u64 qword;
1128         u16 i;
1129
1130         do {
1131                 struct i40e_rx_buffer *rx_bi;
1132                 struct sk_buff *skb;
1133                 u16 vlan_tag;
1134                 /* return some buffers to hardware, one at a time is too slow */
1135                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1136                         i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1137                         cleaned_count = 0;
1138                 }
1139
1140                 i = rx_ring->next_to_clean;
1141                 rx_desc = I40E_RX_DESC(rx_ring, i);
1142                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1143                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1144                         I40E_RXD_QW1_STATUS_SHIFT;
1145
1146                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1147                         break;
1148
1149                 /* This memory barrier is needed to keep us from reading
1150                  * any other fields out of the rx_desc until we know the
1151                  * DD bit is set.
1152                  */
1153                 dma_rmb();
1154
1155                 rx_bi = &rx_ring->rx_bi[i];
1156                 skb = rx_bi->skb;
1157                 prefetch(skb->data);
1158
1159                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1160                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1161
1162                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1163                            I40E_RXD_QW1_ERROR_SHIFT;
1164                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1165
1166                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1167                            I40E_RXD_QW1_PTYPE_SHIFT;
1168                 rx_bi->skb = NULL;
1169                 cleaned_count++;
1170
1171                 /* Get the header and possibly the whole packet
1172                  * If this is an skb from previous receive dma will be 0
1173                  */
1174                 skb_put(skb, rx_packet_len);
1175                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1176                                  DMA_FROM_DEVICE);
1177                 rx_bi->dma = 0;
1178
1179                 I40E_RX_INCREMENT(rx_ring, i);
1180
1181                 if (unlikely(
1182                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1183                         rx_ring->rx_stats.non_eop_descs++;
1184                         continue;
1185                 }
1186
1187                 /* ERR_MASK will only have valid bits if EOP set */
1188                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1189                         dev_kfree_skb_any(skb);
1190                         continue;
1191                 }
1192
1193                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1194                 /* probably a little skewed due to removing CRC */
1195                 total_rx_bytes += skb->len;
1196                 total_rx_packets++;
1197
1198                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1199
1200                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1201
1202                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1203                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1204                          : 0;
1205                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1206
1207                 rx_desc->wb.qword1.status_error_len = 0;
1208         } while (likely(total_rx_packets < budget));
1209
1210         u64_stats_update_begin(&rx_ring->syncp);
1211         rx_ring->stats.packets += total_rx_packets;
1212         rx_ring->stats.bytes += total_rx_bytes;
1213         u64_stats_update_end(&rx_ring->syncp);
1214         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1215         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1216
1217         return total_rx_packets;
1218 }
1219
1220 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1221 {
1222         u32 val;
1223
1224         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1225               I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1226               (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1227               (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1228
1229         return val;
1230 }
1231
1232 /* a small macro to shorten up some long lines */
1233 #define INTREG I40E_VFINT_DYN_CTLN1
1234
1235 /**
1236  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1237  * @vsi: the VSI we care about
1238  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1239  *
1240  **/
1241 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1242                                           struct i40e_q_vector *q_vector)
1243 {
1244         struct i40e_hw *hw = &vsi->back->hw;
1245         bool rx = false, tx = false;
1246         u32 rxval, txval;
1247         int vector;
1248
1249         vector = (q_vector->v_idx + vsi->base_vector);
1250
1251         /* avoid dynamic calculation if in countdown mode OR if
1252          * all dynamic is disabled
1253          */
1254         rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1255
1256         if (q_vector->itr_countdown > 0 ||
1257             (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1258              !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1259                 goto enable_int;
1260         }
1261
1262         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1263                 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1264                 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1265         }
1266
1267         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1268                 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1269                 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1270         }
1271
1272         if (rx || tx) {
1273                 /* get the higher of the two ITR adjustments and
1274                  * use the same value for both ITR registers
1275                  * when in adaptive mode (Rx and/or Tx)
1276                  */
1277                 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1278
1279                 q_vector->tx.itr = q_vector->rx.itr = itr;
1280                 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1281                 tx = true;
1282                 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1283                 rx = true;
1284         }
1285
1286         /* only need to enable the interrupt once, but need
1287          * to possibly update both ITR values
1288          */
1289         if (rx) {
1290                 /* set the INTENA_MSK_MASK so that this first write
1291                  * won't actually enable the interrupt, instead just
1292                  * updating the ITR (it's bit 31 PF and VF)
1293                  */
1294                 rxval |= BIT(31);
1295                 /* don't check _DOWN because interrupt isn't being enabled */
1296                 wr32(hw, INTREG(vector - 1), rxval);
1297         }
1298
1299 enable_int:
1300         if (!test_bit(__I40E_DOWN, &vsi->state))
1301                 wr32(hw, INTREG(vector - 1), txval);
1302
1303         if (q_vector->itr_countdown)
1304                 q_vector->itr_countdown--;
1305         else
1306                 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1307 }
1308
1309 /**
1310  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1311  * @napi: napi struct with our devices info in it
1312  * @budget: amount of work driver is allowed to do this pass, in packets
1313  *
1314  * This function will clean all queues associated with a q_vector.
1315  *
1316  * Returns the amount of work done
1317  **/
1318 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1319 {
1320         struct i40e_q_vector *q_vector =
1321                                container_of(napi, struct i40e_q_vector, napi);
1322         struct i40e_vsi *vsi = q_vector->vsi;
1323         struct i40e_ring *ring;
1324         bool clean_complete = true;
1325         bool arm_wb = false;
1326         int budget_per_ring;
1327         int work_done = 0;
1328
1329         if (test_bit(__I40E_DOWN, &vsi->state)) {
1330                 napi_complete(napi);
1331                 return 0;
1332         }
1333
1334         /* Since the actual Tx work is minimal, we can give the Tx a larger
1335          * budget and be more aggressive about cleaning up the Tx descriptors.
1336          */
1337         i40e_for_each_ring(ring, q_vector->tx) {
1338                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1339                 arm_wb = arm_wb || ring->arm_wb;
1340                 ring->arm_wb = false;
1341         }
1342
1343         /* Handle case where we are called by netpoll with a budget of 0 */
1344         if (budget <= 0)
1345                 goto tx_only;
1346
1347         /* We attempt to distribute budget to each Rx queue fairly, but don't
1348          * allow the budget to go below 1 because that would exit polling early.
1349          */
1350         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1351
1352         i40e_for_each_ring(ring, q_vector->rx) {
1353                 int cleaned;
1354
1355                 if (ring_is_ps_enabled(ring))
1356                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1357                 else
1358                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1359
1360                 work_done += cleaned;
1361                 /* if we didn't clean as many as budgeted, we must be done */
1362                 clean_complete &= (budget_per_ring != cleaned);
1363         }
1364
1365         /* If work not completed, return budget and polling will return */
1366         if (!clean_complete) {
1367 tx_only:
1368                 if (arm_wb) {
1369                         q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1370                         i40evf_force_wb(vsi, q_vector);
1371                 }
1372                 return budget;
1373         }
1374
1375         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1376                 q_vector->arm_wb_state = false;
1377
1378         /* Work is done so exit the polling mode and re-enable the interrupt */
1379         napi_complete_done(napi, work_done);
1380         i40e_update_enable_itr(vsi, q_vector);
1381         return 0;
1382 }
1383
1384 /**
1385  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1386  * @skb:     send buffer
1387  * @tx_ring: ring to send buffer on
1388  * @flags:   the tx flags to be set
1389  *
1390  * Checks the skb and set up correspondingly several generic transmit flags
1391  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1392  *
1393  * Returns error code indicate the frame should be dropped upon error and the
1394  * otherwise  returns 0 to indicate the flags has been set properly.
1395  **/
1396 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1397                                                struct i40e_ring *tx_ring,
1398                                                u32 *flags)
1399 {
1400         __be16 protocol = skb->protocol;
1401         u32  tx_flags = 0;
1402
1403         if (protocol == htons(ETH_P_8021Q) &&
1404             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1405                 /* When HW VLAN acceleration is turned off by the user the
1406                  * stack sets the protocol to 8021q so that the driver
1407                  * can take any steps required to support the SW only
1408                  * VLAN handling.  In our case the driver doesn't need
1409                  * to take any further steps so just set the protocol
1410                  * to the encapsulated ethertype.
1411                  */
1412                 skb->protocol = vlan_get_protocol(skb);
1413                 goto out;
1414         }
1415
1416         /* if we have a HW VLAN tag being added, default to the HW one */
1417         if (skb_vlan_tag_present(skb)) {
1418                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1419                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1420         /* else if it is a SW VLAN, check the next protocol and store the tag */
1421         } else if (protocol == htons(ETH_P_8021Q)) {
1422                 struct vlan_hdr *vhdr, _vhdr;
1423
1424                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1425                 if (!vhdr)
1426                         return -EINVAL;
1427
1428                 protocol = vhdr->h_vlan_encapsulated_proto;
1429                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1430                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1431         }
1432
1433 out:
1434         *flags = tx_flags;
1435         return 0;
1436 }
1437
1438 /**
1439  * i40e_tso - set up the tso context descriptor
1440  * @tx_ring:  ptr to the ring to send
1441  * @skb:      ptr to the skb we're sending
1442  * @hdr_len:  ptr to the size of the packet header
1443  * @cd_type_cmd_tso_mss: Quad Word 1
1444  *
1445  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1446  **/
1447 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1448                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
1449 {
1450         u32 cd_cmd, cd_tso_len, cd_mss;
1451         struct ipv6hdr *ipv6h;
1452         struct tcphdr *tcph;
1453         struct iphdr *iph;
1454         u32 l4len;
1455         int err;
1456
1457         if (!skb_is_gso(skb))
1458                 return 0;
1459
1460         err = skb_cow_head(skb, 0);
1461         if (err < 0)
1462                 return err;
1463
1464         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1465         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1466
1467         if (iph->version == 4) {
1468                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1469                 iph->tot_len = 0;
1470                 iph->check = 0;
1471                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1472                                                  0, IPPROTO_TCP, 0);
1473         } else if (ipv6h->version == 6) {
1474                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1475                 ipv6h->payload_len = 0;
1476                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1477                                                0, IPPROTO_TCP, 0);
1478         }
1479
1480         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1481         *hdr_len = (skb->encapsulation
1482                     ? (skb_inner_transport_header(skb) - skb->data)
1483                     : skb_transport_offset(skb)) + l4len;
1484
1485         /* find the field values */
1486         cd_cmd = I40E_TX_CTX_DESC_TSO;
1487         cd_tso_len = skb->len - *hdr_len;
1488         cd_mss = skb_shinfo(skb)->gso_size;
1489         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1490                                 ((u64)cd_tso_len <<
1491                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1492                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1493         return 1;
1494 }
1495
1496 /**
1497  * i40e_tx_enable_csum - Enable Tx checksum offloads
1498  * @skb: send buffer
1499  * @tx_flags: pointer to Tx flags currently set
1500  * @td_cmd: Tx descriptor command bits to set
1501  * @td_offset: Tx descriptor header offsets to set
1502  * @cd_tunneling: ptr to context desc bits
1503  **/
1504 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1505                                 u32 *td_cmd, u32 *td_offset,
1506                                 struct i40e_ring *tx_ring,
1507                                 u32 *cd_tunneling)
1508 {
1509         struct ipv6hdr *this_ipv6_hdr;
1510         unsigned int this_tcp_hdrlen;
1511         struct iphdr *this_ip_hdr;
1512         u32 network_hdr_len;
1513         u8 l4_hdr = 0;
1514         struct udphdr *oudph;
1515         struct iphdr *oiph;
1516         u32 l4_tunnel = 0;
1517
1518         if (skb->encapsulation) {
1519                 switch (ip_hdr(skb)->protocol) {
1520                 case IPPROTO_UDP:
1521                         oudph = udp_hdr(skb);
1522                         oiph = ip_hdr(skb);
1523                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1524                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1525                         break;
1526                 default:
1527                         return;
1528                 }
1529                 network_hdr_len = skb_inner_network_header_len(skb);
1530                 this_ip_hdr = inner_ip_hdr(skb);
1531                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1532                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1533
1534                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1535                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1536                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1537                                 ip_hdr(skb)->check = 0;
1538                         } else {
1539                                 *cd_tunneling |=
1540                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1541                         }
1542                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1543                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1544                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1545                                 ip_hdr(skb)->check = 0;
1546                 }
1547
1548                 /* Now set the ctx descriptor fields */
1549                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1550                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1551                                    l4_tunnel                             |
1552                                    ((skb_inner_network_offset(skb) -
1553                                         skb_transport_offset(skb)) >> 1) <<
1554                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1555                 if (this_ip_hdr->version == 6) {
1556                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1557                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1558                 }
1559
1560                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1561                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
1562                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1563                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1564                                         oiph->daddr,
1565                                         (skb->len - skb_transport_offset(skb)),
1566                                         IPPROTO_UDP, 0);
1567                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1568                 }
1569         } else {
1570                 network_hdr_len = skb_network_header_len(skb);
1571                 this_ip_hdr = ip_hdr(skb);
1572                 this_ipv6_hdr = ipv6_hdr(skb);
1573                 this_tcp_hdrlen = tcp_hdrlen(skb);
1574         }
1575
1576         /* Enable IP checksum offloads */
1577         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1578                 l4_hdr = this_ip_hdr->protocol;
1579                 /* the stack computes the IP header already, the only time we
1580                  * need the hardware to recompute it is in the case of TSO.
1581                  */
1582                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1583                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1584                         this_ip_hdr->check = 0;
1585                 } else {
1586                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1587                 }
1588                 /* Now set the td_offset for IP header length */
1589                 *td_offset = (network_hdr_len >> 2) <<
1590                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1591         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1592                 l4_hdr = this_ipv6_hdr->nexthdr;
1593                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1594                 /* Now set the td_offset for IP header length */
1595                 *td_offset = (network_hdr_len >> 2) <<
1596                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1597         }
1598         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1599         *td_offset |= (skb_network_offset(skb) >> 1) <<
1600                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1601
1602         /* Enable L4 checksum offloads */
1603         switch (l4_hdr) {
1604         case IPPROTO_TCP:
1605                 /* enable checksum offloads */
1606                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1607                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1608                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1609                 break;
1610         case IPPROTO_SCTP:
1611                 /* enable SCTP checksum offload */
1612                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1613                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1614                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1615                 break;
1616         case IPPROTO_UDP:
1617                 /* enable UDP checksum offload */
1618                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1619                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1620                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1621                 break;
1622         default:
1623                 break;
1624         }
1625 }
1626
1627 /**
1628  * i40e_create_tx_ctx Build the Tx context descriptor
1629  * @tx_ring:  ring to create the descriptor on
1630  * @cd_type_cmd_tso_mss: Quad Word 1
1631  * @cd_tunneling: Quad Word 0 - bits 0-31
1632  * @cd_l2tag2: Quad Word 0 - bits 32-63
1633  **/
1634 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1635                                const u64 cd_type_cmd_tso_mss,
1636                                const u32 cd_tunneling, const u32 cd_l2tag2)
1637 {
1638         struct i40e_tx_context_desc *context_desc;
1639         int i = tx_ring->next_to_use;
1640
1641         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1642             !cd_tunneling && !cd_l2tag2)
1643                 return;
1644
1645         /* grab the next descriptor */
1646         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1647
1648         i++;
1649         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1650
1651         /* cpu_to_le32 and assign to struct fields */
1652         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1653         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1654         context_desc->rsvd = cpu_to_le16(0);
1655         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1656 }
1657
1658 /**
1659  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1660  * @skb:      send buffer
1661  * @tx_flags: collected send information
1662  *
1663  * Note: Our HW can't scatter-gather more than 8 fragments to build
1664  * a packet on the wire and so we need to figure out the cases where we
1665  * need to linearize the skb.
1666  **/
1667 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1668 {
1669         struct skb_frag_struct *frag;
1670         bool linearize = false;
1671         unsigned int size = 0;
1672         u16 num_frags;
1673         u16 gso_segs;
1674
1675         num_frags = skb_shinfo(skb)->nr_frags;
1676         gso_segs = skb_shinfo(skb)->gso_segs;
1677
1678         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1679                 u16 j = 0;
1680
1681                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1682                         goto linearize_chk_done;
1683                 /* try the simple math, if we have too many frags per segment */
1684                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1685                     I40E_MAX_BUFFER_TXD) {
1686                         linearize = true;
1687                         goto linearize_chk_done;
1688                 }
1689                 frag = &skb_shinfo(skb)->frags[0];
1690                 /* we might still have more fragments per segment */
1691                 do {
1692                         size += skb_frag_size(frag);
1693                         frag++; j++;
1694                         if ((size >= skb_shinfo(skb)->gso_size) &&
1695                             (j < I40E_MAX_BUFFER_TXD)) {
1696                                 size = (size % skb_shinfo(skb)->gso_size);
1697                                 j = (size) ? 1 : 0;
1698                         }
1699                         if (j == I40E_MAX_BUFFER_TXD) {
1700                                 linearize = true;
1701                                 break;
1702                         }
1703                         num_frags--;
1704                 } while (num_frags);
1705         } else {
1706                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1707                         linearize = true;
1708         }
1709
1710 linearize_chk_done:
1711         return linearize;
1712 }
1713
1714 /**
1715  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1716  * @tx_ring: the ring to be checked
1717  * @size:    the size buffer we want to assure is available
1718  *
1719  * Returns -EBUSY if a stop is needed, else 0
1720  **/
1721 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1722 {
1723         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1724         /* Memory barrier before checking head and tail */
1725         smp_mb();
1726
1727         /* Check again in a case another CPU has just made room available. */
1728         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1729                 return -EBUSY;
1730
1731         /* A reprieve! - use start_queue because it doesn't call schedule */
1732         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1733         ++tx_ring->tx_stats.restart_queue;
1734         return 0;
1735 }
1736
1737 /**
1738  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1739  * @tx_ring: the ring to be checked
1740  * @size:    the size buffer we want to assure is available
1741  *
1742  * Returns 0 if stop is not needed
1743  **/
1744 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1745 {
1746         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1747                 return 0;
1748         return __i40evf_maybe_stop_tx(tx_ring, size);
1749 }
1750
1751 /**
1752  * i40evf_tx_map - Build the Tx descriptor
1753  * @tx_ring:  ring to send buffer on
1754  * @skb:      send buffer
1755  * @first:    first buffer info buffer to use
1756  * @tx_flags: collected send information
1757  * @hdr_len:  size of the packet header
1758  * @td_cmd:   the command field in the descriptor
1759  * @td_offset: offset for checksum or crc
1760  **/
1761 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1762                                  struct i40e_tx_buffer *first, u32 tx_flags,
1763                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1764 {
1765         unsigned int data_len = skb->data_len;
1766         unsigned int size = skb_headlen(skb);
1767         struct skb_frag_struct *frag;
1768         struct i40e_tx_buffer *tx_bi;
1769         struct i40e_tx_desc *tx_desc;
1770         u16 i = tx_ring->next_to_use;
1771         u32 td_tag = 0;
1772         dma_addr_t dma;
1773         u16 gso_segs;
1774         u16 desc_count = 0;
1775         bool tail_bump = true;
1776         bool do_rs = false;
1777
1778         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1779                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1780                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1781                          I40E_TX_FLAGS_VLAN_SHIFT;
1782         }
1783
1784         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1785                 gso_segs = skb_shinfo(skb)->gso_segs;
1786         else
1787                 gso_segs = 1;
1788
1789         /* multiply data chunks by size of headers */
1790         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1791         first->gso_segs = gso_segs;
1792         first->skb = skb;
1793         first->tx_flags = tx_flags;
1794
1795         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1796
1797         tx_desc = I40E_TX_DESC(tx_ring, i);
1798         tx_bi = first;
1799
1800         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1801                 if (dma_mapping_error(tx_ring->dev, dma))
1802                         goto dma_error;
1803
1804                 /* record length, and DMA address */
1805                 dma_unmap_len_set(tx_bi, len, size);
1806                 dma_unmap_addr_set(tx_bi, dma, dma);
1807
1808                 tx_desc->buffer_addr = cpu_to_le64(dma);
1809
1810                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1811                         tx_desc->cmd_type_offset_bsz =
1812                                 build_ctob(td_cmd, td_offset,
1813                                            I40E_MAX_DATA_PER_TXD, td_tag);
1814
1815                         tx_desc++;
1816                         i++;
1817                         desc_count++;
1818
1819                         if (i == tx_ring->count) {
1820                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1821                                 i = 0;
1822                         }
1823
1824                         dma += I40E_MAX_DATA_PER_TXD;
1825                         size -= I40E_MAX_DATA_PER_TXD;
1826
1827                         tx_desc->buffer_addr = cpu_to_le64(dma);
1828                 }
1829
1830                 if (likely(!data_len))
1831                         break;
1832
1833                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1834                                                           size, td_tag);
1835
1836                 tx_desc++;
1837                 i++;
1838                 desc_count++;
1839
1840                 if (i == tx_ring->count) {
1841                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1842                         i = 0;
1843                 }
1844
1845                 size = skb_frag_size(frag);
1846                 data_len -= size;
1847
1848                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1849                                        DMA_TO_DEVICE);
1850
1851                 tx_bi = &tx_ring->tx_bi[i];
1852         }
1853
1854         /* set next_to_watch value indicating a packet is present */
1855         first->next_to_watch = tx_desc;
1856
1857         i++;
1858         if (i == tx_ring->count)
1859                 i = 0;
1860
1861         tx_ring->next_to_use = i;
1862
1863         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1864                                                  tx_ring->queue_index),
1865                                                  first->bytecount);
1866         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1867
1868         /* Algorithm to optimize tail and RS bit setting:
1869          * if xmit_more is supported
1870          *      if xmit_more is true
1871          *              do not update tail and do not mark RS bit.
1872          *      if xmit_more is false and last xmit_more was false
1873          *              if every packet spanned less than 4 desc
1874          *                      then set RS bit on 4th packet and update tail
1875          *                      on every packet
1876          *              else
1877          *                      update tail and set RS bit on every packet.
1878          *      if xmit_more is false and last_xmit_more was true
1879          *              update tail and set RS bit.
1880          *
1881          * Optimization: wmb to be issued only in case of tail update.
1882          * Also optimize the Descriptor WB path for RS bit with the same
1883          * algorithm.
1884          *
1885          * Note: If there are less than 4 packets
1886          * pending and interrupts were disabled the service task will
1887          * trigger a force WB.
1888          */
1889         if (skb->xmit_more  &&
1890             !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1891                                                     tx_ring->queue_index))) {
1892                 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1893                 tail_bump = false;
1894         } else if (!skb->xmit_more &&
1895                    !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1896                                                        tx_ring->queue_index)) &&
1897                    (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
1898                    (tx_ring->packet_stride < WB_STRIDE) &&
1899                    (desc_count < WB_STRIDE)) {
1900                 tx_ring->packet_stride++;
1901         } else {
1902                 tx_ring->packet_stride = 0;
1903                 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1904                 do_rs = true;
1905         }
1906         if (do_rs)
1907                 tx_ring->packet_stride = 0;
1908
1909         tx_desc->cmd_type_offset_bsz =
1910                         build_ctob(td_cmd, td_offset, size, td_tag) |
1911                         cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
1912                                                   I40E_TX_DESC_CMD_EOP) <<
1913                                                   I40E_TXD_QW1_CMD_SHIFT);
1914
1915         /* notify HW of packet */
1916         if (!tail_bump)
1917                 prefetchw(tx_desc + 1);
1918
1919         if (tail_bump) {
1920                 /* Force memory writes to complete before letting h/w
1921                  * know there are new descriptors to fetch.  (Only
1922                  * applicable for weak-ordered memory model archs,
1923                  * such as IA-64).
1924                  */
1925                 wmb();
1926                 writel(i, tx_ring->tail);
1927         }
1928
1929         return;
1930
1931 dma_error:
1932         dev_info(tx_ring->dev, "TX DMA map failed\n");
1933
1934         /* clear dma mappings for failed tx_bi map */
1935         for (;;) {
1936                 tx_bi = &tx_ring->tx_bi[i];
1937                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1938                 if (tx_bi == first)
1939                         break;
1940                 if (i == 0)
1941                         i = tx_ring->count;
1942                 i--;
1943         }
1944
1945         tx_ring->next_to_use = i;
1946 }
1947
1948 /**
1949  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1950  * @skb:     send buffer
1951  * @tx_ring: ring to send buffer on
1952  *
1953  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1954  * there is not enough descriptors available in this ring since we need at least
1955  * one descriptor.
1956  **/
1957 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1958                                                struct i40e_ring *tx_ring)
1959 {
1960         unsigned int f;
1961         int count = 0;
1962
1963         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1964          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1965          *       + 4 desc gap to avoid the cache line where head is,
1966          *       + 1 desc for context descriptor,
1967          * otherwise try next time
1968          */
1969         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1970                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1971
1972         count += TXD_USE_COUNT(skb_headlen(skb));
1973         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1974                 tx_ring->tx_stats.tx_busy++;
1975                 return 0;
1976         }
1977         return count;
1978 }
1979
1980 /**
1981  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1982  * @skb:     send buffer
1983  * @tx_ring: ring to send buffer on
1984  *
1985  * Returns NETDEV_TX_OK if sent, else an error code
1986  **/
1987 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1988                                         struct i40e_ring *tx_ring)
1989 {
1990         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1991         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1992         struct i40e_tx_buffer *first;
1993         u32 td_offset = 0;
1994         u32 tx_flags = 0;
1995         __be16 protocol;
1996         u32 td_cmd = 0;
1997         u8 hdr_len = 0;
1998         int tso;
1999
2000         /* prefetch the data, we'll need it later */
2001         prefetch(skb->data);
2002
2003         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
2004                 return NETDEV_TX_BUSY;
2005
2006         /* prepare the xmit flags */
2007         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2008                 goto out_drop;
2009
2010         /* obtain protocol of skb */
2011         protocol = vlan_get_protocol(skb);
2012
2013         /* record the location of the first descriptor for this packet */
2014         first = &tx_ring->tx_bi[tx_ring->next_to_use];
2015
2016         /* setup IPv4/IPv6 offloads */
2017         if (protocol == htons(ETH_P_IP))
2018                 tx_flags |= I40E_TX_FLAGS_IPV4;
2019         else if (protocol == htons(ETH_P_IPV6))
2020                 tx_flags |= I40E_TX_FLAGS_IPV6;
2021
2022         tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss);
2023
2024         if (tso < 0)
2025                 goto out_drop;
2026         else if (tso)
2027                 tx_flags |= I40E_TX_FLAGS_TSO;
2028
2029         if (i40e_chk_linearize(skb, tx_flags)) {
2030                 if (skb_linearize(skb))
2031                         goto out_drop;
2032                 tx_ring->tx_stats.tx_linearize++;
2033         }
2034         skb_tx_timestamp(skb);
2035
2036         /* always enable CRC insertion offload */
2037         td_cmd |= I40E_TX_DESC_CMD_ICRC;
2038
2039         /* Always offload the checksum, since it's in the data descriptor */
2040         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2041                 tx_flags |= I40E_TX_FLAGS_CSUM;
2042
2043                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2044                                     tx_ring, &cd_tunneling);
2045         }
2046
2047         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2048                            cd_tunneling, cd_l2tag2);
2049
2050         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2051                       td_cmd, td_offset);
2052
2053         return NETDEV_TX_OK;
2054
2055 out_drop:
2056         dev_kfree_skb_any(skb);
2057         return NETDEV_TX_OK;
2058 }
2059
2060 /**
2061  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2062  * @skb:    send buffer
2063  * @netdev: network interface device structure
2064  *
2065  * Returns NETDEV_TX_OK if sent, else an error code
2066  **/
2067 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2068 {
2069         struct i40evf_adapter *adapter = netdev_priv(netdev);
2070         struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2071
2072         /* hardware can't handle really short frames, hardware padding works
2073          * beyond this point
2074          */
2075         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2076                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2077                         return NETDEV_TX_OK;
2078                 skb->len = I40E_MIN_TX_LEN;
2079                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2080         }
2081
2082         return i40e_xmit_frame_ring(skb, tx_ring);
2083 }