drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  55                         kfree(tx_buffer->raw_buf);
  56                 else
  57                         dev_kfree_skb_any(tx_buffer->skb);
  58
  59                 if (dma_unmap_len(tx_buffer, len))
  60                         dma_unmap_single(ring->dev,
  61                                          dma_unmap_addr(tx_buffer, dma),
  62                                          dma_unmap_len(tx_buffer, len),
  63                                          DMA_TO_DEVICE);
  64         } else if (dma_unmap_len(tx_buffer, len)) {
  65                 dma_unmap_page(ring->dev,
  66                                dma_unmap_addr(tx_buffer, dma),
  67                                dma_unmap_len(tx_buffer, len),
  68                                DMA_TO_DEVICE);
  69         }
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40e_get_head - Retrieve head from head writeback
 131  * @tx_ring:  tx ring to fetch head of
 132  *
 133  * Returns value of Tx ring head based on value stored
 134  * in head write-back location
 135  **/
 136 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
 137 {
 138         void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
 139
 140         return le32_to_cpu(*(volatile __le32 *)head);
 141 }
 142
 143 #define WB_STRIDE 0x3
 144
 145 /**
 146  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 147  * @tx_ring:  tx ring to clean
 148  * @budget:   how many cleans we're allowed
 149  *
 150  * Returns true if there's any budget left (e.g. the clean is finished)
 151  **/
 152 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 153 {
 154         u16 i = tx_ring->next_to_clean;
 155         struct i40e_tx_buffer *tx_buf;
 156         struct i40e_tx_desc *tx_head;
 157         struct i40e_tx_desc *tx_desc;
 158         unsigned int total_packets = 0;
 159         unsigned int total_bytes = 0;
 160
 161         tx_buf = &tx_ring->tx_bi[i];
 162         tx_desc = I40E_TX_DESC(tx_ring, i);
 163         i -= tx_ring->count;
 164
 165         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 166
 167         do {
 168                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 169
 170                 /* if next_to_watch is not set then there is no work pending */
 171                 if (!eop_desc)
 172                         break;
 173
 174                 /* prevent any other reads prior to eop_desc */
 175                 read_barrier_depends();
 176
 177                 /* we have caught up to head, no work left to do */
 178                 if (tx_head == tx_desc)
 179                         break;
 180
 181                 /* clear next_to_watch to prevent false hangs */
 182                 tx_buf->next_to_watch = NULL;
 183
 184                 /* update the statistics for this packet */
 185                 total_bytes += tx_buf->bytecount;
 186                 total_packets += tx_buf->gso_segs;
 187
 188                 /* free the skb */
 189                 dev_kfree_skb_any(tx_buf->skb);
 190
 191                 /* unmap skb header data */
 192                 dma_unmap_single(tx_ring->dev,
 193                                  dma_unmap_addr(tx_buf, dma),
 194                                  dma_unmap_len(tx_buf, len),
 195                                  DMA_TO_DEVICE);
 196
 197                 /* clear tx_buffer data */
 198                 tx_buf->skb = NULL;
 199                 dma_unmap_len_set(tx_buf, len, 0);
 200
 201                 /* unmap remaining buffers */
 202                 while (tx_desc != eop_desc) {
 203
 204                         tx_buf++;
 205                         tx_desc++;
 206                         i++;
 207                         if (unlikely(!i)) {
 208                                 i -= tx_ring->count;
 209                                 tx_buf = tx_ring->tx_bi;
 210                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 211                         }
 212
 213                         /* unmap any remaining paged data */
 214                         if (dma_unmap_len(tx_buf, len)) {
 215                                 dma_unmap_page(tx_ring->dev,
 216                                                dma_unmap_addr(tx_buf, dma),
 217                                                dma_unmap_len(tx_buf, len),
 218                                                DMA_TO_DEVICE);
 219                                 dma_unmap_len_set(tx_buf, len, 0);
 220                         }
 221                 }
 222
 223                 /* move us one more past the eop_desc for start of next pkt */
 224                 tx_buf++;
 225                 tx_desc++;
 226                 i++;
 227                 if (unlikely(!i)) {
 228                         i -= tx_ring->count;
 229                         tx_buf = tx_ring->tx_bi;
 230                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 231                 }
 232
 233                 prefetch(tx_desc);
 234
 235                 /* update budget accounting */
 236                 budget--;
 237         } while (likely(budget));
 238
 239         i += tx_ring->count;
 240         tx_ring->next_to_clean = i;
 241         u64_stats_update_begin(&tx_ring->syncp);
 242         tx_ring->stats.bytes += total_bytes;
 243         tx_ring->stats.packets += total_packets;
 244         u64_stats_update_end(&tx_ring->syncp);
 245         tx_ring->q_vector->tx.total_bytes += total_bytes;
 246         tx_ring->q_vector->tx.total_packets += total_packets;
 247
 248         /* check to see if there are any non-cache aligned descriptors
 249          * waiting to be written back, and kick the hardware to force
 250          * them to be written back in case of napi polling
 251          */
 252         if (budget &&
 253             !((i & WB_STRIDE) == WB_STRIDE) &&
 254             !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 255             (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 256                 tx_ring->arm_wb = true;
 257
 258         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 259                                                       tx_ring->queue_index),
 260                                   total_packets, total_bytes);
 261
 262 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 263         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 264                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 265                 /* Make sure that anybody stopping the queue after this
 266                  * sees the new next_to_clean.
 267                  */
 268                 smp_mb();
 269                 if (__netif_subqueue_stopped(tx_ring->netdev,
 270                                              tx_ring->queue_index) &&
 271                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 272                         netif_wake_subqueue(tx_ring->netdev,
 273                                             tx_ring->queue_index);
 274                         ++tx_ring->tx_stats.restart_queue;
 275                 }
 276         }
 277
 278         return !!budget;
 279 }
 280
 281 /**
 282  * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
 283  * @vsi: the VSI we care about
 284  * @q_vector: the vector  on which to force writeback
 285  *
 286  **/
 287 static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 288 {
 289         u16 flags = q_vector->tx.ring[0].flags;
 290
 291         if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 292                 u32 val;
 293
 294                 if (q_vector->arm_wb_state)
 295                         return;
 296
 297                 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK;
 298
 299                 wr32(&vsi->back->hw,
 300                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 301                                           vsi->base_vector - 1),
 302                      val);
 303                 q_vector->arm_wb_state = true;
 304         } else {
 305                 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 306                           I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 307                           I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 308                           I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
 309                           /* allow 00 to be written to the index */
 310
 311                 wr32(&vsi->back->hw,
 312                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 313                                           vsi->base_vector - 1), val);
 314         }
 315 }
 316
 317 /**
 318  * i40e_set_new_dynamic_itr - Find new ITR level
 319  * @rc: structure containing ring performance data
 320  *
 321  * Returns true if ITR changed, false if not
 322  *
 323  * Stores a new ITR value based on packets and byte counts during
 324  * the last interrupt.  The advantage of per interrupt computation
 325  * is faster updates and more accurate ITR for the current traffic
 326  * pattern.  Constants in this function were computed based on
 327  * theoretical maximum wire speed and thresholds were set based on
 328  * testing data as well as attempting to minimize response time
 329  * while increasing bulk throughput.
 330  **/
 331 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 332 {
 333         enum i40e_latency_range new_latency_range = rc->latency_range;
 334         u32 new_itr = rc->itr;
 335         int bytes_per_int;
 336         int usecs;
 337
 338         if (rc->total_packets == 0 || !rc->itr)
 339                 return false;
 340
 341         /* simple throttlerate management
 342          *   0-10MB/s   lowest (100000 ints/s)
 343          *  10-20MB/s   low    (20000 ints/s)
 344          *  20-1249MB/s bulk   (8000 ints/s)
 345          *
 346          * The math works out because the divisor is in 10^(-6) which
 347          * turns the bytes/us input value into MB/s values, but
 348          * make sure to use usecs, as the register values written
 349          * are in 2 usec increments in the ITR registers.
 350          */
 351         usecs = (rc->itr << 1);
 352         bytes_per_int = rc->total_bytes / usecs;
 353         switch (new_latency_range) {
 354         case I40E_LOWEST_LATENCY:
 355                 if (bytes_per_int > 10)
 356                         new_latency_range = I40E_LOW_LATENCY;
 357                 break;
 358         case I40E_LOW_LATENCY:
 359                 if (bytes_per_int > 20)
 360                         new_latency_range = I40E_BULK_LATENCY;
 361                 else if (bytes_per_int <= 10)
 362                         new_latency_range = I40E_LOWEST_LATENCY;
 363                 break;
 364         case I40E_BULK_LATENCY:
 365                 if (bytes_per_int <= 20)
 366                         new_latency_range = I40E_LOW_LATENCY;
 367                 break;
 368         default:
 369                 if (bytes_per_int <= 20)
 370                         new_latency_range = I40E_LOW_LATENCY;
 371                 break;
 372         }
 373         rc->latency_range = new_latency_range;
 374
 375         switch (new_latency_range) {
 376         case I40E_LOWEST_LATENCY:
 377                 new_itr = I40E_ITR_100K;
 378                 break;
 379         case I40E_LOW_LATENCY:
 380                 new_itr = I40E_ITR_20K;
 381                 break;
 382         case I40E_BULK_LATENCY:
 383                 new_itr = I40E_ITR_8K;
 384                 break;
 385         default:
 386                 break;
 387         }
 388
 389         rc->total_bytes = 0;
 390         rc->total_packets = 0;
 391
 392         if (new_itr != rc->itr) {
 393                 rc->itr = new_itr;
 394                 return true;
 395         }
 396
 397         return false;
 398 }
 399
 400 /*
 401  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 402  * @tx_ring: the tx ring to set up
 403  *
 404  * Return 0 on success, negative on error
 405  **/
 406 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 407 {
 408         struct device *dev = tx_ring->dev;
 409         int bi_size;
 410
 411         if (!dev)
 412                 return -ENOMEM;
 413
 414         /* warn if we are about to overwrite the pointer */
 415         WARN_ON(tx_ring->tx_bi);
 416         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 417         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 418         if (!tx_ring->tx_bi)
 419                 goto err;
 420
 421         /* round up to nearest 4K */
 422         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 423         /* add u32 for head writeback, align after this takes care of
 424          * guaranteeing this is at least one cache line in size
 425          */
 426         tx_ring->size += sizeof(u32);
 427         tx_ring->size = ALIGN(tx_ring->size, 4096);
 428         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 429                                            &tx_ring->dma, GFP_KERNEL);
 430         if (!tx_ring->desc) {
 431                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 432                          tx_ring->size);
 433                 goto err;
 434         }
 435
 436         tx_ring->next_to_use = 0;
 437         tx_ring->next_to_clean = 0;
 438         return 0;
 439
 440 err:
 441         kfree(tx_ring->tx_bi);
 442         tx_ring->tx_bi = NULL;
 443         return -ENOMEM;
 444 }
 445
 446 /**
 447  * i40evf_clean_rx_ring - Free Rx buffers
 448  * @rx_ring: ring to be cleaned
 449  **/
 450 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 451 {
 452         struct device *dev = rx_ring->dev;
 453         struct i40e_rx_buffer *rx_bi;
 454         unsigned long bi_size;
 455         u16 i;
 456
 457         /* ring already cleared, nothing to do */
 458         if (!rx_ring->rx_bi)
 459                 return;
 460
 461         if (ring_is_ps_enabled(rx_ring)) {
 462                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 463
 464                 rx_bi = &rx_ring->rx_bi[0];
 465                 if (rx_bi->hdr_buf) {
 466                         dma_free_coherent(dev,
 467                                           bufsz,
 468                                           rx_bi->hdr_buf,
 469                                           rx_bi->dma);
 470                         for (i = 0; i < rx_ring->count; i++) {
 471                                 rx_bi = &rx_ring->rx_bi[i];
 472                                 rx_bi->dma = 0;
 473                                 rx_bi->hdr_buf = NULL;
 474                         }
 475                 }
 476         }
 477         /* Free all the Rx ring sk_buffs */
 478         for (i = 0; i < rx_ring->count; i++) {
 479                 rx_bi = &rx_ring->rx_bi[i];
 480                 if (rx_bi->dma) {
 481                         dma_unmap_single(dev,
 482                                          rx_bi->dma,
 483                                          rx_ring->rx_buf_len,
 484                                          DMA_FROM_DEVICE);
 485                         rx_bi->dma = 0;
 486                 }
 487                 if (rx_bi->skb) {
 488                         dev_kfree_skb(rx_bi->skb);
 489                         rx_bi->skb = NULL;
 490                 }
 491                 if (rx_bi->page) {
 492                         if (rx_bi->page_dma) {
 493                                 dma_unmap_page(dev,
 494                                                rx_bi->page_dma,
 495                                                PAGE_SIZE / 2,
 496                                                DMA_FROM_DEVICE);
 497                                 rx_bi->page_dma = 0;
 498                         }
 499                         __free_page(rx_bi->page);
 500                         rx_bi->page = NULL;
 501                         rx_bi->page_offset = 0;
 502                 }
 503         }
 504
 505         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 506         memset(rx_ring->rx_bi, 0, bi_size);
 507
 508         /* Zero out the descriptor ring */
 509         memset(rx_ring->desc, 0, rx_ring->size);
 510
 511         rx_ring->next_to_clean = 0;
 512         rx_ring->next_to_use = 0;
 513 }
 514
 515 /**
 516  * i40evf_free_rx_resources - Free Rx resources
 517  * @rx_ring: ring to clean the resources from
 518  *
 519  * Free all receive software resources
 520  **/
 521 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 522 {
 523         i40evf_clean_rx_ring(rx_ring);
 524         kfree(rx_ring->rx_bi);
 525         rx_ring->rx_bi = NULL;
 526
 527         if (rx_ring->desc) {
 528                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 529                                   rx_ring->desc, rx_ring->dma);
 530                 rx_ring->desc = NULL;
 531         }
 532 }
 533
 534 /**
 535  * i40evf_alloc_rx_headers - allocate rx header buffers
 536  * @rx_ring: ring to alloc buffers
 537  *
 538  * Allocate rx header buffers for the entire ring. As these are static,
 539  * this is only called when setting up a new ring.
 540  **/
 541 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 542 {
 543         struct device *dev = rx_ring->dev;
 544         struct i40e_rx_buffer *rx_bi;
 545         dma_addr_t dma;
 546         void *buffer;
 547         int buf_size;
 548         int i;
 549
 550         if (rx_ring->rx_bi[0].hdr_buf)
 551                 return;
 552         /* Make sure the buffers don't cross cache line boundaries. */
 553         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 554         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 555                                     &dma, GFP_KERNEL);
 556         if (!buffer)
 557                 return;
 558         for (i = 0; i < rx_ring->count; i++) {
 559                 rx_bi = &rx_ring->rx_bi[i];
 560                 rx_bi->dma = dma + (i * buf_size);
 561                 rx_bi->hdr_buf = buffer + (i * buf_size);
 562         }
 563 }
 564
 565 /**
 566  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 567  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 568  *
 569  * Returns 0 on success, negative on failure
 570  **/
 571 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 572 {
 573         struct device *dev = rx_ring->dev;
 574         int bi_size;
 575
 576         /* warn if we are about to overwrite the pointer */
 577         WARN_ON(rx_ring->rx_bi);
 578         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 579         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 580         if (!rx_ring->rx_bi)
 581                 goto err;
 582
 583         u64_stats_init(&rx_ring->syncp);
 584
 585         /* Round up to nearest 4K */
 586         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 587                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 588                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 589         rx_ring->size = ALIGN(rx_ring->size, 4096);
 590         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 591                                            &rx_ring->dma, GFP_KERNEL);
 592
 593         if (!rx_ring->desc) {
 594                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 595                          rx_ring->size);
 596                 goto err;
 597         }
 598
 599         rx_ring->next_to_clean = 0;
 600         rx_ring->next_to_use = 0;
 601
 602         return 0;
 603 err:
 604         kfree(rx_ring->rx_bi);
 605         rx_ring->rx_bi = NULL;
 606         return -ENOMEM;
 607 }
 608
 609 /**
 610  * i40e_release_rx_desc - Store the new tail and head values
 611  * @rx_ring: ring to bump
 612  * @val: new head index
 613  **/
 614 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 615 {
 616         rx_ring->next_to_use = val;
 617         /* Force memory writes to complete before letting h/w
 618          * know there are new descriptors to fetch.  (Only
 619          * applicable for weak-ordered memory model archs,
 620          * such as IA-64).
 621          */
 622         wmb();
 623         writel(val, rx_ring->tail);
 624 }
 625
 626 /**
 627  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 628  * @rx_ring: ring to place buffers on
 629  * @cleaned_count: number of buffers to replace
 630  **/
 631 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 632 {
 633         u16 i = rx_ring->next_to_use;
 634         union i40e_rx_desc *rx_desc;
 635         struct i40e_rx_buffer *bi;
 636
 637         /* do nothing if no valid netdev defined */
 638         if (!rx_ring->netdev || !cleaned_count)
 639                 return;
 640
 641         while (cleaned_count--) {
 642                 rx_desc = I40E_RX_DESC(rx_ring, i);
 643                 bi = &rx_ring->rx_bi[i];
 644
 645                 if (bi->skb) /* desc is in use */
 646                         goto no_buffers;
 647                 if (!bi->page) {
 648                         bi->page = alloc_page(GFP_ATOMIC);
 649                         if (!bi->page) {
 650                                 rx_ring->rx_stats.alloc_page_failed++;
 651                                 goto no_buffers;
 652                         }
 653                 }
 654
 655                 if (!bi->page_dma) {
 656                         /* use a half page if we're re-using */
 657                         bi->page_offset ^= PAGE_SIZE / 2;
 658                         bi->page_dma = dma_map_page(rx_ring->dev,
 659                                                     bi->page,
 660                                                     bi->page_offset,
 661                                                     PAGE_SIZE / 2,
 662                                                     DMA_FROM_DEVICE);
 663                         if (dma_mapping_error(rx_ring->dev,
 664                                               bi->page_dma)) {
 665                                 rx_ring->rx_stats.alloc_page_failed++;
 666                                 bi->page_dma = 0;
 667                                 goto no_buffers;
 668                         }
 669                 }
 670
 671                 dma_sync_single_range_for_device(rx_ring->dev,
 672                                                  bi->dma,
 673                                                  0,
 674                                                  rx_ring->rx_hdr_len,
 675                                                  DMA_FROM_DEVICE);
 676                 /* Refresh the desc even if buffer_addrs didn't change
 677                  * because each write-back erases this info.
 678                  */
 679                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 680                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 681                 i++;
 682                 if (i == rx_ring->count)
 683                         i = 0;
 684         }
 685
 686 no_buffers:
 687         if (rx_ring->next_to_use != i)
 688                 i40e_release_rx_desc(rx_ring, i);
 689 }
 690
 691 /**
 692  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 693  * @rx_ring: ring to place buffers on
 694  * @cleaned_count: number of buffers to replace
 695  **/
 696 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 697 {
 698         u16 i = rx_ring->next_to_use;
 699         union i40e_rx_desc *rx_desc;
 700         struct i40e_rx_buffer *bi;
 701         struct sk_buff *skb;
 702
 703         /* do nothing if no valid netdev defined */
 704         if (!rx_ring->netdev || !cleaned_count)
 705                 return;
 706
 707         while (cleaned_count--) {
 708                 rx_desc = I40E_RX_DESC(rx_ring, i);
 709                 bi = &rx_ring->rx_bi[i];
 710                 skb = bi->skb;
 711
 712                 if (!skb) {
 713                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 714                                                         rx_ring->rx_buf_len);
 715                         if (!skb) {
 716                                 rx_ring->rx_stats.alloc_buff_failed++;
 717                                 goto no_buffers;
 718                         }
 719                         /* initialize queue mapping */
 720                         skb_record_rx_queue(skb, rx_ring->queue_index);
 721                         bi->skb = skb;
 722                 }
 723
 724                 if (!bi->dma) {
 725                         bi->dma = dma_map_single(rx_ring->dev,
 726                                                  skb->data,
 727                                                  rx_ring->rx_buf_len,
 728                                                  DMA_FROM_DEVICE);
 729                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 730                                 rx_ring->rx_stats.alloc_buff_failed++;
 731                                 bi->dma = 0;
 732                                 goto no_buffers;
 733                         }
 734                 }
 735
 736                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 737                 rx_desc->read.hdr_addr = 0;
 738                 i++;
 739                 if (i == rx_ring->count)
 740                         i = 0;
 741         }
 742
 743 no_buffers:
 744         if (rx_ring->next_to_use != i)
 745                 i40e_release_rx_desc(rx_ring, i);
 746 }
 747
 748 /**
 749  * i40e_receive_skb - Send a completed packet up the stack
 750  * @rx_ring:  rx ring in play
 751  * @skb: packet to send up
 752  * @vlan_tag: vlan tag for packet
 753  **/
 754 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 755                              struct sk_buff *skb, u16 vlan_tag)
 756 {
 757         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 758
 759         if (vlan_tag & VLAN_VID_MASK)
 760                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 761
 762         napi_gro_receive(&q_vector->napi, skb);
 763 }
 764
 765 /**
 766  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 767  * @vsi: the VSI we care about
 768  * @skb: skb currently being received and modified
 769  * @rx_status: status value of last descriptor in packet
 770  * @rx_error: error value of last descriptor in packet
 771  * @rx_ptype: ptype value of last descriptor in packet
 772  **/
 773 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 774                                     struct sk_buff *skb,
 775                                     u32 rx_status,
 776                                     u32 rx_error,
 777                                     u16 rx_ptype)
 778 {
 779         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 780         bool ipv4 = false, ipv6 = false;
 781         bool ipv4_tunnel, ipv6_tunnel;
 782         __wsum rx_udp_csum;
 783         struct iphdr *iph;
 784         __sum16 csum;
 785
 786         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 787                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 788         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 789                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 790
 791         skb->ip_summed = CHECKSUM_NONE;
 792
 793         /* Rx csum enabled and ip headers found? */
 794         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 795                 return;
 796
 797         /* did the hardware decode the packet and checksum? */
 798         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 799                 return;
 800
 801         /* both known and outer_ip must be set for the below code to work */
 802         if (!(decoded.known && decoded.outer_ip))
 803                 return;
 804
 805         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 806             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 807                 ipv4 = true;
 808         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 809                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 810                 ipv6 = true;
 811
 812         if (ipv4 &&
 813             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
 814                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 815                 goto checksum_fail;
 816
 817         /* likely incorrect csum if alternate IP extension headers found */
 818         if (ipv6 &&
 819             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 820                 /* don't increment checksum err here, non-fatal err */
 821                 return;
 822
 823         /* there was some L4 error, count error and punt packet to the stack */
 824         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
 825                 goto checksum_fail;
 826
 827         /* handle packets that were not able to be checksummed due
 828          * to arrival speed, in this case the stack can compute
 829          * the csum.
 830          */
 831         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
 832                 return;
 833
 834         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 835          * it in the driver, hardware does not do it for us.
 836          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 837          * so the total length of IPv4 header is IHL*4 bytes
 838          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 839          */
 840         if (ipv4_tunnel) {
 841                 skb->transport_header = skb->mac_header +
 842                                         sizeof(struct ethhdr) +
 843                                         (ip_hdr(skb)->ihl * 4);
 844
 845                 /* Add 4 bytes for VLAN tagged packets */
 846                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 847                                           skb->protocol == htons(ETH_P_8021AD))
 848                                           ? VLAN_HLEN : 0;
 849
 850                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
 851                     (udp_hdr(skb)->check != 0)) {
 852                         rx_udp_csum = udp_csum(skb);
 853                         iph = ip_hdr(skb);
 854                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
 855                                                  (skb->len -
 856                                                   skb_transport_offset(skb)),
 857                                                  IPPROTO_UDP, rx_udp_csum);
 858
 859                         if (udp_hdr(skb)->check != csum)
 860                                 goto checksum_fail;
 861
 862                 } /* else its GRE and so no outer UDP header */
 863         }
 864
 865         skb->ip_summed = CHECKSUM_UNNECESSARY;
 866         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 867
 868         return;
 869
 870 checksum_fail:
 871         vsi->back->hw_csum_rx_error++;
 872 }
 873
 874 /**
 875  * i40e_rx_hash - returns the hash value from the Rx descriptor
 876  * @ring: descriptor ring
 877  * @rx_desc: specific descriptor
 878  **/
 879 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
 880                                union i40e_rx_desc *rx_desc)
 881 {
 882         const __le64 rss_mask =
 883                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 884                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 885
 886         if ((ring->netdev->features & NETIF_F_RXHASH) &&
 887             (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
 888                 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 889         else
 890                 return 0;
 891 }
 892
 893 /**
 894  * i40e_ptype_to_hash - get a hash type
 895  * @ptype: the ptype value from the descriptor
 896  *
 897  * Returns a hash type to be used by skb_set_hash
 898  **/
 899 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
 900 {
 901         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 902
 903         if (!decoded.known)
 904                 return PKT_HASH_TYPE_NONE;
 905
 906         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 907             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 908                 return PKT_HASH_TYPE_L4;
 909         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 910                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 911                 return PKT_HASH_TYPE_L3;
 912         else
 913                 return PKT_HASH_TYPE_L2;
 914 }
 915
 916 /**
 917  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
 918  * @rx_ring:  rx ring to clean
 919  * @budget:   how many cleans we're allowed
 920  *
 921  * Returns true if there's any budget left (e.g. the clean is finished)
 922  **/
 923 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
 924 {
 925         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 926         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 927         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
 928         const int current_node = numa_mem_id();
 929         struct i40e_vsi *vsi = rx_ring->vsi;
 930         u16 i = rx_ring->next_to_clean;
 931         union i40e_rx_desc *rx_desc;
 932         u32 rx_error, rx_status;
 933         u8 rx_ptype;
 934         u64 qword;
 935
 936         do {
 937                 struct i40e_rx_buffer *rx_bi;
 938                 struct sk_buff *skb;
 939                 u16 vlan_tag;
 940                 /* return some buffers to hardware, one at a time is too slow */
 941                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
 942                         i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
 943                         cleaned_count = 0;
 944                 }
 945
 946                 i = rx_ring->next_to_clean;
 947                 rx_desc = I40E_RX_DESC(rx_ring, i);
 948                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 949                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
 950                         I40E_RXD_QW1_STATUS_SHIFT;
 951
 952                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
 953                         break;
 954
 955                 /* This memory barrier is needed to keep us from reading
 956                  * any other fields out of the rx_desc until we know the
 957                  * DD bit is set.
 958                  */
 959                 dma_rmb();
 960                 rx_bi = &rx_ring->rx_bi[i];
 961                 skb = rx_bi->skb;
 962                 if (likely(!skb)) {
 963                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 964                                                         rx_ring->rx_hdr_len);
 965                         if (!skb) {
 966                                 rx_ring->rx_stats.alloc_buff_failed++;
 967                                 break;
 968                         }
 969
 970                         /* initialize queue mapping */
 971                         skb_record_rx_queue(skb, rx_ring->queue_index);
 972                         /* we are reusing so sync this buffer for CPU use */
 973                         dma_sync_single_range_for_cpu(rx_ring->dev,
 974                                                       rx_bi->dma,
 975                                                       0,
 976                                                       rx_ring->rx_hdr_len,
 977                                                       DMA_FROM_DEVICE);
 978                 }
 979                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 980                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 981                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
 982                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
 983                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
 984                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
 985
 986                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
 987                            I40E_RXD_QW1_ERROR_SHIFT;
 988                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
 989                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
 990
 991                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
 992                            I40E_RXD_QW1_PTYPE_SHIFT;
 993                 prefetch(rx_bi->page);
 994                 rx_bi->skb = NULL;
 995                 cleaned_count++;
 996                 if (rx_hbo || rx_sph) {
 997                         int len;
 998
 999                         if (rx_hbo)
1000                                 len = I40E_RX_HDR_SIZE;
1001                         else
1002                                 len = rx_header_len;
1003                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1004                 } else if (skb->len == 0) {
1005                         int len;
1006
1007                         len = (rx_packet_len > skb_headlen(skb) ?
1008                                 skb_headlen(skb) : rx_packet_len);
1009                         memcpy(__skb_put(skb, len),
1010                                rx_bi->page + rx_bi->page_offset,
1011                                len);
1012                         rx_bi->page_offset += len;
1013                         rx_packet_len -= len;
1014                 }
1015
1016                 /* Get the rest of the data if this was a header split */
1017                 if (rx_packet_len) {
1018                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1019                                            rx_bi->page,
1020                                            rx_bi->page_offset,
1021                                            rx_packet_len);
1022
1023                         skb->len += rx_packet_len;
1024                         skb->data_len += rx_packet_len;
1025                         skb->truesize += rx_packet_len;
1026
1027                         if ((page_count(rx_bi->page) == 1) &&
1028                             (page_to_nid(rx_bi->page) == current_node))
1029                                 get_page(rx_bi->page);
1030                         else
1031                                 rx_bi->page = NULL;
1032
1033                         dma_unmap_page(rx_ring->dev,
1034                                        rx_bi->page_dma,
1035                                        PAGE_SIZE / 2,
1036                                        DMA_FROM_DEVICE);
1037                         rx_bi->page_dma = 0;
1038                 }
1039                 I40E_RX_INCREMENT(rx_ring, i);
1040
1041                 if (unlikely(
1042                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1043                         struct i40e_rx_buffer *next_buffer;
1044
1045                         next_buffer = &rx_ring->rx_bi[i];
1046                         next_buffer->skb = skb;
1047                         rx_ring->rx_stats.non_eop_descs++;
1048                         continue;
1049                 }
1050
1051                 /* ERR_MASK will only have valid bits if EOP set */
1052                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1053                         dev_kfree_skb_any(skb);
1054                         continue;
1055                 }
1056
1057                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1058                              i40e_ptype_to_hash(rx_ptype));
1059                 /* probably a little skewed due to removing CRC */
1060                 total_rx_bytes += skb->len;
1061                 total_rx_packets++;
1062
1063                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1064
1065                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1066
1067                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1068                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1069                          : 0;
1070 #ifdef I40E_FCOE
1071                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1072                         dev_kfree_skb_any(skb);
1073                         continue;
1074                 }
1075 #endif
1076                 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1077                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1078
1079                 rx_desc->wb.qword1.status_error_len = 0;
1080
1081         } while (likely(total_rx_packets < budget));
1082
1083         u64_stats_update_begin(&rx_ring->syncp);
1084         rx_ring->stats.packets += total_rx_packets;
1085         rx_ring->stats.bytes += total_rx_bytes;
1086         u64_stats_update_end(&rx_ring->syncp);
1087         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1088         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1089
1090         return total_rx_packets;
1091 }
1092
1093 /**
1094  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1095  * @rx_ring:  rx ring to clean
1096  * @budget:   how many cleans we're allowed
1097  *
1098  * Returns number of packets cleaned
1099  **/
1100 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1101 {
1102         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1103         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1104         struct i40e_vsi *vsi = rx_ring->vsi;
1105         union i40e_rx_desc *rx_desc;
1106         u32 rx_error, rx_status;
1107         u16 rx_packet_len;
1108         u8 rx_ptype;
1109         u64 qword;
1110         u16 i;
1111
1112         do {
1113                 struct i40e_rx_buffer *rx_bi;
1114                 struct sk_buff *skb;
1115                 u16 vlan_tag;
1116                 /* return some buffers to hardware, one at a time is too slow */
1117                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1118                         i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1119                         cleaned_count = 0;
1120                 }
1121
1122                 i = rx_ring->next_to_clean;
1123                 rx_desc = I40E_RX_DESC(rx_ring, i);
1124                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1125                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1126                         I40E_RXD_QW1_STATUS_SHIFT;
1127
1128                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1129                         break;
1130
1131                 /* This memory barrier is needed to keep us from reading
1132                  * any other fields out of the rx_desc until we know the
1133                  * DD bit is set.
1134                  */
1135                 dma_rmb();
1136
1137                 rx_bi = &rx_ring->rx_bi[i];
1138                 skb = rx_bi->skb;
1139                 prefetch(skb->data);
1140
1141                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1142                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1143
1144                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1145                            I40E_RXD_QW1_ERROR_SHIFT;
1146                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1147
1148                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1149                            I40E_RXD_QW1_PTYPE_SHIFT;
1150                 rx_bi->skb = NULL;
1151                 cleaned_count++;
1152
1153                 /* Get the header and possibly the whole packet
1154                  * If this is an skb from previous receive dma will be 0
1155                  */
1156                 skb_put(skb, rx_packet_len);
1157                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1158                                  DMA_FROM_DEVICE);
1159                 rx_bi->dma = 0;
1160
1161                 I40E_RX_INCREMENT(rx_ring, i);
1162
1163                 if (unlikely(
1164                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1165                         rx_ring->rx_stats.non_eop_descs++;
1166                         continue;
1167                 }
1168
1169                 /* ERR_MASK will only have valid bits if EOP set */
1170                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1171                         dev_kfree_skb_any(skb);
1172                         continue;
1173                 }
1174
1175                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1176                              i40e_ptype_to_hash(rx_ptype));
1177                 /* probably a little skewed due to removing CRC */
1178                 total_rx_bytes += skb->len;
1179                 total_rx_packets++;
1180
1181                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1182
1183                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1184
1185                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1186                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1187                          : 0;
1188                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1189
1190                 rx_desc->wb.qword1.status_error_len = 0;
1191         } while (likely(total_rx_packets < budget));
1192
1193         u64_stats_update_begin(&rx_ring->syncp);
1194         rx_ring->stats.packets += total_rx_packets;
1195         rx_ring->stats.bytes += total_rx_bytes;
1196         u64_stats_update_end(&rx_ring->syncp);
1197         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1198         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1199
1200         return total_rx_packets;
1201 }
1202
1203 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1204 {
1205         u32 val;
1206
1207         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1208               I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1209               (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1210               (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1211
1212         return val;
1213 }
1214
1215 /* a small macro to shorten up some long lines */
1216 #define INTREG I40E_VFINT_DYN_CTLN1
1217
1218 /**
1219  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1220  * @vsi: the VSI we care about
1221  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1222  *
1223  **/
1224 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1225                                           struct i40e_q_vector *q_vector)
1226 {
1227         struct i40e_hw *hw = &vsi->back->hw;
1228         bool rx = false, tx = false;
1229         u32 rxval, txval;
1230         int vector;
1231
1232         vector = (q_vector->v_idx + vsi->base_vector);
1233         rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1234
1235         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1236                 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1237                 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1238         }
1239         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1240                 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1241                 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1242         }
1243         if (rx || tx) {
1244                 /* get the higher of the two ITR adjustments and
1245                  * use the same value for both ITR registers
1246                  * when in adaptive mode (Rx and/or Tx)
1247                  */
1248                 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1249
1250                 q_vector->tx.itr = q_vector->rx.itr = itr;
1251                 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1252                 tx = true;
1253                 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1254                 rx = true;
1255         }
1256
1257         /* only need to enable the interrupt once, but need
1258          * to possibly update both ITR values
1259          */
1260         if (rx) {
1261                 /* set the INTENA_MSK_MASK so that this first write
1262                  * won't actually enable the interrupt, instead just
1263                  * updating the ITR (it's bit 31 PF and VF)
1264                  */
1265                 rxval |= BIT(31);
1266                 /* don't check _DOWN because interrupt isn't being enabled */
1267                 wr32(hw, INTREG(vector - 1), rxval);
1268         }
1269
1270         if (!test_bit(__I40E_DOWN, &vsi->state))
1271                 wr32(hw, INTREG(vector - 1), txval);
1272 }
1273
1274 /**
1275  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1276  * @napi: napi struct with our devices info in it
1277  * @budget: amount of work driver is allowed to do this pass, in packets
1278  *
1279  * This function will clean all queues associated with a q_vector.
1280  *
1281  * Returns the amount of work done
1282  **/
1283 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1284 {
1285         struct i40e_q_vector *q_vector =
1286                                container_of(napi, struct i40e_q_vector, napi);
1287         struct i40e_vsi *vsi = q_vector->vsi;
1288         struct i40e_ring *ring;
1289         bool clean_complete = true;
1290         bool arm_wb = false;
1291         int budget_per_ring;
1292         int work_done = 0;
1293
1294         if (test_bit(__I40E_DOWN, &vsi->state)) {
1295                 napi_complete(napi);
1296                 return 0;
1297         }
1298
1299         /* Since the actual Tx work is minimal, we can give the Tx a larger
1300          * budget and be more aggressive about cleaning up the Tx descriptors.
1301          */
1302         i40e_for_each_ring(ring, q_vector->tx) {
1303                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1304                 arm_wb |= ring->arm_wb;
1305                 ring->arm_wb = false;
1306         }
1307
1308         /* Handle case where we are called by netpoll with a budget of 0 */
1309         if (budget <= 0)
1310                 goto tx_only;
1311
1312         /* We attempt to distribute budget to each Rx queue fairly, but don't
1313          * allow the budget to go below 1 because that would exit polling early.
1314          */
1315         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1316
1317         i40e_for_each_ring(ring, q_vector->rx) {
1318                 int cleaned;
1319
1320                 if (ring_is_ps_enabled(ring))
1321                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1322                 else
1323                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1324
1325                 work_done += cleaned;
1326                 /* if we didn't clean as many as budgeted, we must be done */
1327                 clean_complete &= (budget_per_ring != cleaned);
1328         }
1329
1330         /* If work not completed, return budget and polling will return */
1331         if (!clean_complete) {
1332 tx_only:
1333                 if (arm_wb)
1334                         i40evf_force_wb(vsi, q_vector);
1335                 return budget;
1336         }
1337
1338         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1339                 q_vector->arm_wb_state = false;
1340
1341         /* Work is done so exit the polling mode and re-enable the interrupt */
1342         napi_complete_done(napi, work_done);
1343         i40e_update_enable_itr(vsi, q_vector);
1344         return 0;
1345 }
1346
1347 /**
1348  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1349  * @skb:     send buffer
1350  * @tx_ring: ring to send buffer on
1351  * @flags:   the tx flags to be set
1352  *
1353  * Checks the skb and set up correspondingly several generic transmit flags
1354  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1355  *
1356  * Returns error code indicate the frame should be dropped upon error and the
1357  * otherwise  returns 0 to indicate the flags has been set properly.
1358  **/
1359 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1360                                                struct i40e_ring *tx_ring,
1361                                                u32 *flags)
1362 {
1363         __be16 protocol = skb->protocol;
1364         u32  tx_flags = 0;
1365
1366         if (protocol == htons(ETH_P_8021Q) &&
1367             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1368                 /* When HW VLAN acceleration is turned off by the user the
1369                  * stack sets the protocol to 8021q so that the driver
1370                  * can take any steps required to support the SW only
1371                  * VLAN handling.  In our case the driver doesn't need
1372                  * to take any further steps so just set the protocol
1373                  * to the encapsulated ethertype.
1374                  */
1375                 skb->protocol = vlan_get_protocol(skb);
1376                 goto out;
1377         }
1378
1379         /* if we have a HW VLAN tag being added, default to the HW one */
1380         if (skb_vlan_tag_present(skb)) {
1381                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1382                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1383         /* else if it is a SW VLAN, check the next protocol and store the tag */
1384         } else if (protocol == htons(ETH_P_8021Q)) {
1385                 struct vlan_hdr *vhdr, _vhdr;
1386
1387                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1388                 if (!vhdr)
1389                         return -EINVAL;
1390
1391                 protocol = vhdr->h_vlan_encapsulated_proto;
1392                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1393                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1394         }
1395
1396 out:
1397         *flags = tx_flags;
1398         return 0;
1399 }
1400
1401 /**
1402  * i40e_tso - set up the tso context descriptor
1403  * @tx_ring:  ptr to the ring to send
1404  * @skb:      ptr to the skb we're sending
1405  * @hdr_len:  ptr to the size of the packet header
1406  * @cd_tunneling: ptr to context descriptor bits
1407  *
1408  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1409  **/
1410 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1411                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
1412                     u32 *cd_tunneling)
1413 {
1414         u32 cd_cmd, cd_tso_len, cd_mss;
1415         struct ipv6hdr *ipv6h;
1416         struct tcphdr *tcph;
1417         struct iphdr *iph;
1418         u32 l4len;
1419         int err;
1420
1421         if (!skb_is_gso(skb))
1422                 return 0;
1423
1424         err = skb_cow_head(skb, 0);
1425         if (err < 0)
1426                 return err;
1427
1428         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1429         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1430
1431         if (iph->version == 4) {
1432                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1433                 iph->tot_len = 0;
1434                 iph->check = 0;
1435                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1436                                                  0, IPPROTO_TCP, 0);
1437         } else if (ipv6h->version == 6) {
1438                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1439                 ipv6h->payload_len = 0;
1440                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1441                                                0, IPPROTO_TCP, 0);
1442         }
1443
1444         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1445         *hdr_len = (skb->encapsulation
1446                     ? (skb_inner_transport_header(skb) - skb->data)
1447                     : skb_transport_offset(skb)) + l4len;
1448
1449         /* find the field values */
1450         cd_cmd = I40E_TX_CTX_DESC_TSO;
1451         cd_tso_len = skb->len - *hdr_len;
1452         cd_mss = skb_shinfo(skb)->gso_size;
1453         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1454                                 ((u64)cd_tso_len <<
1455                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1456                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1457         return 1;
1458 }
1459
1460 /**
1461  * i40e_tx_enable_csum - Enable Tx checksum offloads
1462  * @skb: send buffer
1463  * @tx_flags: pointer to Tx flags currently set
1464  * @td_cmd: Tx descriptor command bits to set
1465  * @td_offset: Tx descriptor header offsets to set
1466  * @cd_tunneling: ptr to context desc bits
1467  **/
1468 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1469                                 u32 *td_cmd, u32 *td_offset,
1470                                 struct i40e_ring *tx_ring,
1471                                 u32 *cd_tunneling)
1472 {
1473         struct ipv6hdr *this_ipv6_hdr;
1474         unsigned int this_tcp_hdrlen;
1475         struct iphdr *this_ip_hdr;
1476         u32 network_hdr_len;
1477         u8 l4_hdr = 0;
1478         struct udphdr *oudph;
1479         struct iphdr *oiph;
1480         u32 l4_tunnel = 0;
1481
1482         if (skb->encapsulation) {
1483                 switch (ip_hdr(skb)->protocol) {
1484                 case IPPROTO_UDP:
1485                         oudph = udp_hdr(skb);
1486                         oiph = ip_hdr(skb);
1487                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1488                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1489                         break;
1490                 default:
1491                         return;
1492                 }
1493                 network_hdr_len = skb_inner_network_header_len(skb);
1494                 this_ip_hdr = inner_ip_hdr(skb);
1495                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1496                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1497
1498                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1499                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1500                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1501                                 ip_hdr(skb)->check = 0;
1502                         } else {
1503                                 *cd_tunneling |=
1504                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1505                         }
1506                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1507                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1508                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1509                                 ip_hdr(skb)->check = 0;
1510                 }
1511
1512                 /* Now set the ctx descriptor fields */
1513                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1514                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1515                                    l4_tunnel                             |
1516                                    ((skb_inner_network_offset(skb) -
1517                                         skb_transport_offset(skb)) >> 1) <<
1518                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1519                 if (this_ip_hdr->version == 6) {
1520                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1521                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1522                 }
1523
1524
1525                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1526                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
1527                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1528                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1529                                         oiph->daddr,
1530                                         (skb->len - skb_transport_offset(skb)),
1531                                         IPPROTO_UDP, 0);
1532                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1533                 }
1534         } else {
1535                 network_hdr_len = skb_network_header_len(skb);
1536                 this_ip_hdr = ip_hdr(skb);
1537                 this_ipv6_hdr = ipv6_hdr(skb);
1538                 this_tcp_hdrlen = tcp_hdrlen(skb);
1539         }
1540
1541         /* Enable IP checksum offloads */
1542         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1543                 l4_hdr = this_ip_hdr->protocol;
1544                 /* the stack computes the IP header already, the only time we
1545                  * need the hardware to recompute it is in the case of TSO.
1546                  */
1547                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1548                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1549                         this_ip_hdr->check = 0;
1550                 } else {
1551                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1552                 }
1553                 /* Now set the td_offset for IP header length */
1554                 *td_offset = (network_hdr_len >> 2) <<
1555                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1556         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1557                 l4_hdr = this_ipv6_hdr->nexthdr;
1558                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1559                 /* Now set the td_offset for IP header length */
1560                 *td_offset = (network_hdr_len >> 2) <<
1561                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1562         }
1563         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1564         *td_offset |= (skb_network_offset(skb) >> 1) <<
1565                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1566
1567         /* Enable L4 checksum offloads */
1568         switch (l4_hdr) {
1569         case IPPROTO_TCP:
1570                 /* enable checksum offloads */
1571                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1572                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1573                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1574                 break;
1575         case IPPROTO_SCTP:
1576                 /* enable SCTP checksum offload */
1577                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1578                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1579                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1580                 break;
1581         case IPPROTO_UDP:
1582                 /* enable UDP checksum offload */
1583                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1584                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1585                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1586                 break;
1587         default:
1588                 break;
1589         }
1590 }
1591
1592 /**
1593  * i40e_create_tx_ctx Build the Tx context descriptor
1594  * @tx_ring:  ring to create the descriptor on
1595  * @cd_type_cmd_tso_mss: Quad Word 1
1596  * @cd_tunneling: Quad Word 0 - bits 0-31
1597  * @cd_l2tag2: Quad Word 0 - bits 32-63
1598  **/
1599 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1600                                const u64 cd_type_cmd_tso_mss,
1601                                const u32 cd_tunneling, const u32 cd_l2tag2)
1602 {
1603         struct i40e_tx_context_desc *context_desc;
1604         int i = tx_ring->next_to_use;
1605
1606         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1607             !cd_tunneling && !cd_l2tag2)
1608                 return;
1609
1610         /* grab the next descriptor */
1611         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1612
1613         i++;
1614         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1615
1616         /* cpu_to_le32 and assign to struct fields */
1617         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1618         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1619         context_desc->rsvd = cpu_to_le16(0);
1620         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1621 }
1622
1623  /**
1624  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1625  * @skb:      send buffer
1626  * @tx_flags: collected send information
1627  *
1628  * Note: Our HW can't scatter-gather more than 8 fragments to build
1629  * a packet on the wire and so we need to figure out the cases where we
1630  * need to linearize the skb.
1631  **/
1632 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1633 {
1634         struct skb_frag_struct *frag;
1635         bool linearize = false;
1636         unsigned int size = 0;
1637         u16 num_frags;
1638         u16 gso_segs;
1639
1640         num_frags = skb_shinfo(skb)->nr_frags;
1641         gso_segs = skb_shinfo(skb)->gso_segs;
1642
1643         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1644                 u16 j = 0;
1645
1646                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1647                         goto linearize_chk_done;
1648                 /* try the simple math, if we have too many frags per segment */
1649                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1650                     I40E_MAX_BUFFER_TXD) {
1651                         linearize = true;
1652                         goto linearize_chk_done;
1653                 }
1654                 frag = &skb_shinfo(skb)->frags[0];
1655                 /* we might still have more fragments per segment */
1656                 do {
1657                         size += skb_frag_size(frag);
1658                         frag++; j++;
1659                         if ((size >= skb_shinfo(skb)->gso_size) &&
1660                             (j < I40E_MAX_BUFFER_TXD)) {
1661                                 size = (size % skb_shinfo(skb)->gso_size);
1662                                 j = (size) ? 1 : 0;
1663                         }
1664                         if (j == I40E_MAX_BUFFER_TXD) {
1665                                 linearize = true;
1666                                 break;
1667                         }
1668                         num_frags--;
1669                 } while (num_frags);
1670         } else {
1671                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1672                         linearize = true;
1673         }
1674
1675 linearize_chk_done:
1676         return linearize;
1677 }
1678
1679 /**
1680  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1681  * @tx_ring: the ring to be checked
1682  * @size:    the size buffer we want to assure is available
1683  *
1684  * Returns -EBUSY if a stop is needed, else 0
1685  **/
1686 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1687 {
1688         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1689         /* Memory barrier before checking head and tail */
1690         smp_mb();
1691
1692         /* Check again in a case another CPU has just made room available. */
1693         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1694                 return -EBUSY;
1695
1696         /* A reprieve! - use start_queue because it doesn't call schedule */
1697         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1698         ++tx_ring->tx_stats.restart_queue;
1699         return 0;
1700 }
1701
1702 /**
1703  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1704  * @tx_ring: the ring to be checked
1705  * @size:    the size buffer we want to assure is available
1706  *
1707  * Returns 0 if stop is not needed
1708  **/
1709 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1710 {
1711         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1712                 return 0;
1713         return __i40evf_maybe_stop_tx(tx_ring, size);
1714 }
1715
1716 /**
1717  * i40evf_tx_map - Build the Tx descriptor
1718  * @tx_ring:  ring to send buffer on
1719  * @skb:      send buffer
1720  * @first:    first buffer info buffer to use
1721  * @tx_flags: collected send information
1722  * @hdr_len:  size of the packet header
1723  * @td_cmd:   the command field in the descriptor
1724  * @td_offset: offset for checksum or crc
1725  **/
1726 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1727                                  struct i40e_tx_buffer *first, u32 tx_flags,
1728                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1729 {
1730         unsigned int data_len = skb->data_len;
1731         unsigned int size = skb_headlen(skb);
1732         struct skb_frag_struct *frag;
1733         struct i40e_tx_buffer *tx_bi;
1734         struct i40e_tx_desc *tx_desc;
1735         u16 i = tx_ring->next_to_use;
1736         u32 td_tag = 0;
1737         dma_addr_t dma;
1738         u16 gso_segs;
1739
1740         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1741                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1742                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1743                          I40E_TX_FLAGS_VLAN_SHIFT;
1744         }
1745
1746         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1747                 gso_segs = skb_shinfo(skb)->gso_segs;
1748         else
1749                 gso_segs = 1;
1750
1751         /* multiply data chunks by size of headers */
1752         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1753         first->gso_segs = gso_segs;
1754         first->skb = skb;
1755         first->tx_flags = tx_flags;
1756
1757         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1758
1759         tx_desc = I40E_TX_DESC(tx_ring, i);
1760         tx_bi = first;
1761
1762         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1763                 if (dma_mapping_error(tx_ring->dev, dma))
1764                         goto dma_error;
1765
1766                 /* record length, and DMA address */
1767                 dma_unmap_len_set(tx_bi, len, size);
1768                 dma_unmap_addr_set(tx_bi, dma, dma);
1769
1770                 tx_desc->buffer_addr = cpu_to_le64(dma);
1771
1772                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1773                         tx_desc->cmd_type_offset_bsz =
1774                                 build_ctob(td_cmd, td_offset,
1775                                            I40E_MAX_DATA_PER_TXD, td_tag);
1776
1777                         tx_desc++;
1778                         i++;
1779                         if (i == tx_ring->count) {
1780                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1781                                 i = 0;
1782                         }
1783
1784                         dma += I40E_MAX_DATA_PER_TXD;
1785                         size -= I40E_MAX_DATA_PER_TXD;
1786
1787                         tx_desc->buffer_addr = cpu_to_le64(dma);
1788                 }
1789
1790                 if (likely(!data_len))
1791                         break;
1792
1793                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1794                                                           size, td_tag);
1795
1796                 tx_desc++;
1797                 i++;
1798                 if (i == tx_ring->count) {
1799                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1800                         i = 0;
1801                 }
1802
1803                 size = skb_frag_size(frag);
1804                 data_len -= size;
1805
1806                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1807                                        DMA_TO_DEVICE);
1808
1809                 tx_bi = &tx_ring->tx_bi[i];
1810         }
1811
1812         /* Place RS bit on last descriptor of any packet that spans across the
1813          * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1814          */
1815 #define WB_STRIDE 0x3
1816         if (((i & WB_STRIDE) != WB_STRIDE) &&
1817             (first <= &tx_ring->tx_bi[i]) &&
1818             (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1819                 tx_desc->cmd_type_offset_bsz =
1820                         build_ctob(td_cmd, td_offset, size, td_tag) |
1821                         cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1822                                          I40E_TXD_QW1_CMD_SHIFT);
1823         } else {
1824                 tx_desc->cmd_type_offset_bsz =
1825                         build_ctob(td_cmd, td_offset, size, td_tag) |
1826                         cpu_to_le64((u64)I40E_TXD_CMD <<
1827                                          I40E_TXD_QW1_CMD_SHIFT);
1828         }
1829
1830         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1831                                                  tx_ring->queue_index),
1832                              first->bytecount);
1833
1834         /* Force memory writes to complete before letting h/w
1835          * know there are new descriptors to fetch.  (Only
1836          * applicable for weak-ordered memory model archs,
1837          * such as IA-64).
1838          */
1839         wmb();
1840
1841         /* set next_to_watch value indicating a packet is present */
1842         first->next_to_watch = tx_desc;
1843
1844         i++;
1845         if (i == tx_ring->count)
1846                 i = 0;
1847
1848         tx_ring->next_to_use = i;
1849
1850         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1851         /* notify HW of packet */
1852         if (!skb->xmit_more ||
1853             netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1854                                                    tx_ring->queue_index)))
1855                 writel(i, tx_ring->tail);
1856         else
1857                 prefetchw(tx_desc + 1);
1858
1859         return;
1860
1861 dma_error:
1862         dev_info(tx_ring->dev, "TX DMA map failed\n");
1863
1864         /* clear dma mappings for failed tx_bi map */
1865         for (;;) {
1866                 tx_bi = &tx_ring->tx_bi[i];
1867                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1868                 if (tx_bi == first)
1869                         break;
1870                 if (i == 0)
1871                         i = tx_ring->count;
1872                 i--;
1873         }
1874
1875         tx_ring->next_to_use = i;
1876 }
1877
1878 /**
1879  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1880  * @skb:     send buffer
1881  * @tx_ring: ring to send buffer on
1882  *
1883  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1884  * there is not enough descriptors available in this ring since we need at least
1885  * one descriptor.
1886  **/
1887 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1888                                                struct i40e_ring *tx_ring)
1889 {
1890         unsigned int f;
1891         int count = 0;
1892
1893         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1894          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1895          *       + 4 desc gap to avoid the cache line where head is,
1896          *       + 1 desc for context descriptor,
1897          * otherwise try next time
1898          */
1899         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1900                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1901
1902         count += TXD_USE_COUNT(skb_headlen(skb));
1903         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1904                 tx_ring->tx_stats.tx_busy++;
1905                 return 0;
1906         }
1907         return count;
1908 }
1909
1910 /**
1911  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1912  * @skb:     send buffer
1913  * @tx_ring: ring to send buffer on
1914  *
1915  * Returns NETDEV_TX_OK if sent, else an error code
1916  **/
1917 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1918                                         struct i40e_ring *tx_ring)
1919 {
1920         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1921         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1922         struct i40e_tx_buffer *first;
1923         u32 td_offset = 0;
1924         u32 tx_flags = 0;
1925         __be16 protocol;
1926         u32 td_cmd = 0;
1927         u8 hdr_len = 0;
1928         int tso;
1929
1930         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
1931                 return NETDEV_TX_BUSY;
1932
1933         /* prepare the xmit flags */
1934         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1935                 goto out_drop;
1936
1937         /* obtain protocol of skb */
1938         protocol = vlan_get_protocol(skb);
1939
1940         /* record the location of the first descriptor for this packet */
1941         first = &tx_ring->tx_bi[tx_ring->next_to_use];
1942
1943         /* setup IPv4/IPv6 offloads */
1944         if (protocol == htons(ETH_P_IP))
1945                 tx_flags |= I40E_TX_FLAGS_IPV4;
1946         else if (protocol == htons(ETH_P_IPV6))
1947                 tx_flags |= I40E_TX_FLAGS_IPV6;
1948
1949         tso = i40e_tso(tx_ring, skb, &hdr_len,
1950                        &cd_type_cmd_tso_mss, &cd_tunneling);
1951
1952         if (tso < 0)
1953                 goto out_drop;
1954         else if (tso)
1955                 tx_flags |= I40E_TX_FLAGS_TSO;
1956
1957         if (i40e_chk_linearize(skb, tx_flags)) {
1958                 if (skb_linearize(skb))
1959                         goto out_drop;
1960                 tx_ring->tx_stats.tx_linearize++;
1961         }
1962         skb_tx_timestamp(skb);
1963
1964         /* always enable CRC insertion offload */
1965         td_cmd |= I40E_TX_DESC_CMD_ICRC;
1966
1967         /* Always offload the checksum, since it's in the data descriptor */
1968         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1969                 tx_flags |= I40E_TX_FLAGS_CSUM;
1970
1971                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
1972                                     tx_ring, &cd_tunneling);
1973         }
1974
1975         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1976                            cd_tunneling, cd_l2tag2);
1977
1978         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1979                       td_cmd, td_offset);
1980
1981         return NETDEV_TX_OK;
1982
1983 out_drop:
1984         dev_kfree_skb_any(skb);
1985         return NETDEV_TX_OK;
1986 }
1987
1988 /**
1989  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1990  * @skb:    send buffer
1991  * @netdev: network interface device structure
1992  *
1993  * Returns NETDEV_TX_OK if sent, else an error code
1994  **/
1995 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1996 {
1997         struct i40evf_adapter *adapter = netdev_priv(netdev);
1998         struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1999
2000         /* hardware can't handle really short frames, hardware padding works
2001          * beyond this point
2002          */
2003         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2004                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2005                         return NETDEV_TX_OK;
2006                 skb->len = I40E_MIN_TX_LEN;
2007                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2008         }
2009
2010         return i40e_xmit_frame_ring(skb, tx_ring);
2011 }