drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 dev_kfree_skb_any(tx_buffer->skb);
  55                 if (dma_unmap_len(tx_buffer, len))
  56                         dma_unmap_single(ring->dev,
  57                                          dma_unmap_addr(tx_buffer, dma),
  58                                          dma_unmap_len(tx_buffer, len),
  59                                          DMA_TO_DEVICE);
  60         } else if (dma_unmap_len(tx_buffer, len)) {
  61                 dma_unmap_page(ring->dev,
  62                                dma_unmap_addr(tx_buffer, dma),
  63                                dma_unmap_len(tx_buffer, len),
  64                                DMA_TO_DEVICE);
  65         }
  66
  67         if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  68                 kfree(tx_buffer->raw_buf);
  69
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40evf_get_tx_pending - how many Tx descriptors not processed
 131  * @tx_ring: the ring of descriptors
 132  *
 133  * Since there is no access to the ring head register
 134  * in XL710, we need to use our local copies
 135  **/
 136 u32 i40evf_get_tx_pending(struct i40e_ring *ring)
 137 {
 138         u32 head, tail;
 139
 140         head = i40e_get_head(ring);
 141         tail = readl(ring->tail);
 142
 143         if (head != tail)
 144                 return (head < tail) ?
 145                         tail - head : (tail + ring->count - head);
 146
 147         return 0;
 148 }
 149
 150 #define WB_STRIDE 0x3
 151
 152 /**
 153  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 154  * @tx_ring:  tx ring to clean
 155  * @budget:   how many cleans we're allowed
 156  *
 157  * Returns true if there's any budget left (e.g. the clean is finished)
 158  **/
 159 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 160 {
 161         u16 i = tx_ring->next_to_clean;
 162         struct i40e_tx_buffer *tx_buf;
 163         struct i40e_tx_desc *tx_head;
 164         struct i40e_tx_desc *tx_desc;
 165         unsigned int total_packets = 0;
 166         unsigned int total_bytes = 0;
 167
 168         tx_buf = &tx_ring->tx_bi[i];
 169         tx_desc = I40E_TX_DESC(tx_ring, i);
 170         i -= tx_ring->count;
 171
 172         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 173
 174         do {
 175                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 176
 177                 /* if next_to_watch is not set then there is no work pending */
 178                 if (!eop_desc)
 179                         break;
 180
 181                 /* prevent any other reads prior to eop_desc */
 182                 read_barrier_depends();
 183
 184                 /* we have caught up to head, no work left to do */
 185                 if (tx_head == tx_desc)
 186                         break;
 187
 188                 /* clear next_to_watch to prevent false hangs */
 189                 tx_buf->next_to_watch = NULL;
 190
 191                 /* update the statistics for this packet */
 192                 total_bytes += tx_buf->bytecount;
 193                 total_packets += tx_buf->gso_segs;
 194
 195                 /* free the skb */
 196                 dev_kfree_skb_any(tx_buf->skb);
 197
 198                 /* unmap skb header data */
 199                 dma_unmap_single(tx_ring->dev,
 200                                  dma_unmap_addr(tx_buf, dma),
 201                                  dma_unmap_len(tx_buf, len),
 202                                  DMA_TO_DEVICE);
 203
 204                 /* clear tx_buffer data */
 205                 tx_buf->skb = NULL;
 206                 dma_unmap_len_set(tx_buf, len, 0);
 207
 208                 /* unmap remaining buffers */
 209                 while (tx_desc != eop_desc) {
 210
 211                         tx_buf++;
 212                         tx_desc++;
 213                         i++;
 214                         if (unlikely(!i)) {
 215                                 i -= tx_ring->count;
 216                                 tx_buf = tx_ring->tx_bi;
 217                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 218                         }
 219
 220                         /* unmap any remaining paged data */
 221                         if (dma_unmap_len(tx_buf, len)) {
 222                                 dma_unmap_page(tx_ring->dev,
 223                                                dma_unmap_addr(tx_buf, dma),
 224                                                dma_unmap_len(tx_buf, len),
 225                                                DMA_TO_DEVICE);
 226                                 dma_unmap_len_set(tx_buf, len, 0);
 227                         }
 228                 }
 229
 230                 /* move us one more past the eop_desc for start of next pkt */
 231                 tx_buf++;
 232                 tx_desc++;
 233                 i++;
 234                 if (unlikely(!i)) {
 235                         i -= tx_ring->count;
 236                         tx_buf = tx_ring->tx_bi;
 237                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 238                 }
 239
 240                 prefetch(tx_desc);
 241
 242                 /* update budget accounting */
 243                 budget--;
 244         } while (likely(budget));
 245
 246         i += tx_ring->count;
 247         tx_ring->next_to_clean = i;
 248         u64_stats_update_begin(&tx_ring->syncp);
 249         tx_ring->stats.bytes += total_bytes;
 250         tx_ring->stats.packets += total_packets;
 251         u64_stats_update_end(&tx_ring->syncp);
 252         tx_ring->q_vector->tx.total_bytes += total_bytes;
 253         tx_ring->q_vector->tx.total_packets += total_packets;
 254
 255         if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 256                 unsigned int j = 0;
 257                 /* check to see if there are < 4 descriptors
 258                  * waiting to be written back, then kick the hardware to force
 259                  * them to be written back in case we stay in NAPI.
 260                  * In this mode on X722 we do not enable Interrupt.
 261                  */
 262                 j = i40evf_get_tx_pending(tx_ring);
 263
 264                 if (budget &&
 265                     ((j / (WB_STRIDE + 1)) == 0) && (j > 0) &&
 266                     !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 267                     (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 268                         tx_ring->arm_wb = true;
 269         }
 270
 271         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 272                                                       tx_ring->queue_index),
 273                                   total_packets, total_bytes);
 274
 275 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 276         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 277                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 278                 /* Make sure that anybody stopping the queue after this
 279                  * sees the new next_to_clean.
 280                  */
 281                 smp_mb();
 282                 if (__netif_subqueue_stopped(tx_ring->netdev,
 283                                              tx_ring->queue_index) &&
 284                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 285                         netif_wake_subqueue(tx_ring->netdev,
 286                                             tx_ring->queue_index);
 287                         ++tx_ring->tx_stats.restart_queue;
 288                 }
 289         }
 290
 291         return !!budget;
 292 }
 293
 294 /**
 295  * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
 296  * @vsi: the VSI we care about
 297  * @q_vector: the vector  on which to force writeback
 298  *
 299  **/
 300 static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 301 {
 302         u16 flags = q_vector->tx.ring[0].flags;
 303
 304         if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 305                 u32 val;
 306
 307                 if (q_vector->arm_wb_state)
 308                         return;
 309
 310                 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
 311                       I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
 312
 313                 wr32(&vsi->back->hw,
 314                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 315                                           vsi->base_vector - 1),
 316                      val);
 317                 q_vector->arm_wb_state = true;
 318         } else {
 319                 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 320                           I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 321                           I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 322                           I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
 323                           /* allow 00 to be written to the index */
 324
 325                 wr32(&vsi->back->hw,
 326                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 327                                           vsi->base_vector - 1), val);
 328         }
 329 }
 330
 331 /**
 332  * i40e_set_new_dynamic_itr - Find new ITR level
 333  * @rc: structure containing ring performance data
 334  *
 335  * Returns true if ITR changed, false if not
 336  *
 337  * Stores a new ITR value based on packets and byte counts during
 338  * the last interrupt.  The advantage of per interrupt computation
 339  * is faster updates and more accurate ITR for the current traffic
 340  * pattern.  Constants in this function were computed based on
 341  * theoretical maximum wire speed and thresholds were set based on
 342  * testing data as well as attempting to minimize response time
 343  * while increasing bulk throughput.
 344  **/
 345 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 346 {
 347         enum i40e_latency_range new_latency_range = rc->latency_range;
 348         struct i40e_q_vector *qv = rc->ring->q_vector;
 349         u32 new_itr = rc->itr;
 350         int bytes_per_int;
 351         int usecs;
 352
 353         if (rc->total_packets == 0 || !rc->itr)
 354                 return false;
 355
 356         /* simple throttlerate management
 357          *   0-10MB/s   lowest (50000 ints/s)
 358          *  10-20MB/s   low    (20000 ints/s)
 359          *  20-1249MB/s bulk   (18000 ints/s)
 360          *  > 40000 Rx packets per second (8000 ints/s)
 361          *
 362          * The math works out because the divisor is in 10^(-6) which
 363          * turns the bytes/us input value into MB/s values, but
 364          * make sure to use usecs, as the register values written
 365          * are in 2 usec increments in the ITR registers, and make sure
 366          * to use the smoothed values that the countdown timer gives us.
 367          */
 368         usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
 369         bytes_per_int = rc->total_bytes / usecs;
 370
 371         switch (new_latency_range) {
 372         case I40E_LOWEST_LATENCY:
 373                 if (bytes_per_int > 10)
 374                         new_latency_range = I40E_LOW_LATENCY;
 375                 break;
 376         case I40E_LOW_LATENCY:
 377                 if (bytes_per_int > 20)
 378                         new_latency_range = I40E_BULK_LATENCY;
 379                 else if (bytes_per_int <= 10)
 380                         new_latency_range = I40E_LOWEST_LATENCY;
 381                 break;
 382         case I40E_BULK_LATENCY:
 383         case I40E_ULTRA_LATENCY:
 384         default:
 385                 if (bytes_per_int <= 20)
 386                         new_latency_range = I40E_LOW_LATENCY;
 387                 break;
 388         }
 389
 390         /* this is to adjust RX more aggressively when streaming small
 391          * packets.  The value of 40000 was picked as it is just beyond
 392          * what the hardware can receive per second if in low latency
 393          * mode.
 394          */
 395 #define RX_ULTRA_PACKET_RATE 40000
 396
 397         if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
 398             (&qv->rx == rc))
 399                 new_latency_range = I40E_ULTRA_LATENCY;
 400
 401         rc->latency_range = new_latency_range;
 402
 403         switch (new_latency_range) {
 404         case I40E_LOWEST_LATENCY:
 405                 new_itr = I40E_ITR_50K;
 406                 break;
 407         case I40E_LOW_LATENCY:
 408                 new_itr = I40E_ITR_20K;
 409                 break;
 410         case I40E_BULK_LATENCY:
 411                 new_itr = I40E_ITR_18K;
 412                 break;
 413         case I40E_ULTRA_LATENCY:
 414                 new_itr = I40E_ITR_8K;
 415                 break;
 416         default:
 417                 break;
 418         }
 419
 420         rc->total_bytes = 0;
 421         rc->total_packets = 0;
 422
 423         if (new_itr != rc->itr) {
 424                 rc->itr = new_itr;
 425                 return true;
 426         }
 427
 428         return false;
 429 }
 430
 431 /**
 432  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 433  * @tx_ring: the tx ring to set up
 434  *
 435  * Return 0 on success, negative on error
 436  **/
 437 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 438 {
 439         struct device *dev = tx_ring->dev;
 440         int bi_size;
 441
 442         if (!dev)
 443                 return -ENOMEM;
 444
 445         /* warn if we are about to overwrite the pointer */
 446         WARN_ON(tx_ring->tx_bi);
 447         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 448         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 449         if (!tx_ring->tx_bi)
 450                 goto err;
 451
 452         /* round up to nearest 4K */
 453         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 454         /* add u32 for head writeback, align after this takes care of
 455          * guaranteeing this is at least one cache line in size
 456          */
 457         tx_ring->size += sizeof(u32);
 458         tx_ring->size = ALIGN(tx_ring->size, 4096);
 459         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 460                                            &tx_ring->dma, GFP_KERNEL);
 461         if (!tx_ring->desc) {
 462                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 463                          tx_ring->size);
 464                 goto err;
 465         }
 466
 467         tx_ring->next_to_use = 0;
 468         tx_ring->next_to_clean = 0;
 469         return 0;
 470
 471 err:
 472         kfree(tx_ring->tx_bi);
 473         tx_ring->tx_bi = NULL;
 474         return -ENOMEM;
 475 }
 476
 477 /**
 478  * i40evf_clean_rx_ring - Free Rx buffers
 479  * @rx_ring: ring to be cleaned
 480  **/
 481 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 482 {
 483         struct device *dev = rx_ring->dev;
 484         struct i40e_rx_buffer *rx_bi;
 485         unsigned long bi_size;
 486         u16 i;
 487
 488         /* ring already cleared, nothing to do */
 489         if (!rx_ring->rx_bi)
 490                 return;
 491
 492         if (ring_is_ps_enabled(rx_ring)) {
 493                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 494
 495                 rx_bi = &rx_ring->rx_bi[0];
 496                 if (rx_bi->hdr_buf) {
 497                         dma_free_coherent(dev,
 498                                           bufsz,
 499                                           rx_bi->hdr_buf,
 500                                           rx_bi->dma);
 501                         for (i = 0; i < rx_ring->count; i++) {
 502                                 rx_bi = &rx_ring->rx_bi[i];
 503                                 rx_bi->dma = 0;
 504                                 rx_bi->hdr_buf = NULL;
 505                         }
 506                 }
 507         }
 508         /* Free all the Rx ring sk_buffs */
 509         for (i = 0; i < rx_ring->count; i++) {
 510                 rx_bi = &rx_ring->rx_bi[i];
 511                 if (rx_bi->dma) {
 512                         dma_unmap_single(dev,
 513                                          rx_bi->dma,
 514                                          rx_ring->rx_buf_len,
 515                                          DMA_FROM_DEVICE);
 516                         rx_bi->dma = 0;
 517                 }
 518                 if (rx_bi->skb) {
 519                         dev_kfree_skb(rx_bi->skb);
 520                         rx_bi->skb = NULL;
 521                 }
 522                 if (rx_bi->page) {
 523                         if (rx_bi->page_dma) {
 524                                 dma_unmap_page(dev,
 525                                                rx_bi->page_dma,
 526                                                PAGE_SIZE / 2,
 527                                                DMA_FROM_DEVICE);
 528                                 rx_bi->page_dma = 0;
 529                         }
 530                         __free_page(rx_bi->page);
 531                         rx_bi->page = NULL;
 532                         rx_bi->page_offset = 0;
 533                 }
 534         }
 535
 536         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 537         memset(rx_ring->rx_bi, 0, bi_size);
 538
 539         /* Zero out the descriptor ring */
 540         memset(rx_ring->desc, 0, rx_ring->size);
 541
 542         rx_ring->next_to_clean = 0;
 543         rx_ring->next_to_use = 0;
 544 }
 545
 546 /**
 547  * i40evf_free_rx_resources - Free Rx resources
 548  * @rx_ring: ring to clean the resources from
 549  *
 550  * Free all receive software resources
 551  **/
 552 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 553 {
 554         i40evf_clean_rx_ring(rx_ring);
 555         kfree(rx_ring->rx_bi);
 556         rx_ring->rx_bi = NULL;
 557
 558         if (rx_ring->desc) {
 559                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 560                                   rx_ring->desc, rx_ring->dma);
 561                 rx_ring->desc = NULL;
 562         }
 563 }
 564
 565 /**
 566  * i40evf_alloc_rx_headers - allocate rx header buffers
 567  * @rx_ring: ring to alloc buffers
 568  *
 569  * Allocate rx header buffers for the entire ring. As these are static,
 570  * this is only called when setting up a new ring.
 571  **/
 572 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 573 {
 574         struct device *dev = rx_ring->dev;
 575         struct i40e_rx_buffer *rx_bi;
 576         dma_addr_t dma;
 577         void *buffer;
 578         int buf_size;
 579         int i;
 580
 581         if (rx_ring->rx_bi[0].hdr_buf)
 582                 return;
 583         /* Make sure the buffers don't cross cache line boundaries. */
 584         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 585         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 586                                     &dma, GFP_KERNEL);
 587         if (!buffer)
 588                 return;
 589         for (i = 0; i < rx_ring->count; i++) {
 590                 rx_bi = &rx_ring->rx_bi[i];
 591                 rx_bi->dma = dma + (i * buf_size);
 592                 rx_bi->hdr_buf = buffer + (i * buf_size);
 593         }
 594 }
 595
 596 /**
 597  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 598  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 599  *
 600  * Returns 0 on success, negative on failure
 601  **/
 602 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 603 {
 604         struct device *dev = rx_ring->dev;
 605         int bi_size;
 606
 607         /* warn if we are about to overwrite the pointer */
 608         WARN_ON(rx_ring->rx_bi);
 609         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 610         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 611         if (!rx_ring->rx_bi)
 612                 goto err;
 613
 614         u64_stats_init(&rx_ring->syncp);
 615
 616         /* Round up to nearest 4K */
 617         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 618                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 619                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 620         rx_ring->size = ALIGN(rx_ring->size, 4096);
 621         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 622                                            &rx_ring->dma, GFP_KERNEL);
 623
 624         if (!rx_ring->desc) {
 625                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 626                          rx_ring->size);
 627                 goto err;
 628         }
 629
 630         rx_ring->next_to_clean = 0;
 631         rx_ring->next_to_use = 0;
 632
 633         return 0;
 634 err:
 635         kfree(rx_ring->rx_bi);
 636         rx_ring->rx_bi = NULL;
 637         return -ENOMEM;
 638 }
 639
 640 /**
 641  * i40e_release_rx_desc - Store the new tail and head values
 642  * @rx_ring: ring to bump
 643  * @val: new head index
 644  **/
 645 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 646 {
 647         rx_ring->next_to_use = val;
 648         /* Force memory writes to complete before letting h/w
 649          * know there are new descriptors to fetch.  (Only
 650          * applicable for weak-ordered memory model archs,
 651          * such as IA-64).
 652          */
 653         wmb();
 654         writel(val, rx_ring->tail);
 655 }
 656
 657 /**
 658  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 659  * @rx_ring: ring to place buffers on
 660  * @cleaned_count: number of buffers to replace
 661  **/
 662 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 663 {
 664         u16 i = rx_ring->next_to_use;
 665         union i40e_rx_desc *rx_desc;
 666         struct i40e_rx_buffer *bi;
 667
 668         /* do nothing if no valid netdev defined */
 669         if (!rx_ring->netdev || !cleaned_count)
 670                 return;
 671
 672         while (cleaned_count--) {
 673                 rx_desc = I40E_RX_DESC(rx_ring, i);
 674                 bi = &rx_ring->rx_bi[i];
 675
 676                 if (bi->skb) /* desc is in use */
 677                         goto no_buffers;
 678                 if (!bi->page) {
 679                         bi->page = alloc_page(GFP_ATOMIC);
 680                         if (!bi->page) {
 681                                 rx_ring->rx_stats.alloc_page_failed++;
 682                                 goto no_buffers;
 683                         }
 684                 }
 685
 686                 if (!bi->page_dma) {
 687                         /* use a half page if we're re-using */
 688                         bi->page_offset ^= PAGE_SIZE / 2;
 689                         bi->page_dma = dma_map_page(rx_ring->dev,
 690                                                     bi->page,
 691                                                     bi->page_offset,
 692                                                     PAGE_SIZE / 2,
 693                                                     DMA_FROM_DEVICE);
 694                         if (dma_mapping_error(rx_ring->dev,
 695                                               bi->page_dma)) {
 696                                 rx_ring->rx_stats.alloc_page_failed++;
 697                                 bi->page_dma = 0;
 698                                 goto no_buffers;
 699                         }
 700                 }
 701
 702                 dma_sync_single_range_for_device(rx_ring->dev,
 703                                                  rx_ring->rx_bi[0].dma,
 704                                                  i * rx_ring->rx_hdr_len,
 705                                                  rx_ring->rx_hdr_len,
 706                                                  DMA_FROM_DEVICE);
 707                 /* Refresh the desc even if buffer_addrs didn't change
 708                  * because each write-back erases this info.
 709                  */
 710                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 711                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 712                 i++;
 713                 if (i == rx_ring->count)
 714                         i = 0;
 715         }
 716
 717 no_buffers:
 718         if (rx_ring->next_to_use != i)
 719                 i40e_release_rx_desc(rx_ring, i);
 720 }
 721
 722 /**
 723  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 724  * @rx_ring: ring to place buffers on
 725  * @cleaned_count: number of buffers to replace
 726  **/
 727 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 728 {
 729         u16 i = rx_ring->next_to_use;
 730         union i40e_rx_desc *rx_desc;
 731         struct i40e_rx_buffer *bi;
 732         struct sk_buff *skb;
 733
 734         /* do nothing if no valid netdev defined */
 735         if (!rx_ring->netdev || !cleaned_count)
 736                 return;
 737
 738         while (cleaned_count--) {
 739                 rx_desc = I40E_RX_DESC(rx_ring, i);
 740                 bi = &rx_ring->rx_bi[i];
 741                 skb = bi->skb;
 742
 743                 if (!skb) {
 744                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 745                                                         rx_ring->rx_buf_len);
 746                         if (!skb) {
 747                                 rx_ring->rx_stats.alloc_buff_failed++;
 748                                 goto no_buffers;
 749                         }
 750                         /* initialize queue mapping */
 751                         skb_record_rx_queue(skb, rx_ring->queue_index);
 752                         bi->skb = skb;
 753                 }
 754
 755                 if (!bi->dma) {
 756                         bi->dma = dma_map_single(rx_ring->dev,
 757                                                  skb->data,
 758                                                  rx_ring->rx_buf_len,
 759                                                  DMA_FROM_DEVICE);
 760                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 761                                 rx_ring->rx_stats.alloc_buff_failed++;
 762                                 bi->dma = 0;
 763                                 goto no_buffers;
 764                         }
 765                 }
 766
 767                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 768                 rx_desc->read.hdr_addr = 0;
 769                 i++;
 770                 if (i == rx_ring->count)
 771                         i = 0;
 772         }
 773
 774 no_buffers:
 775         if (rx_ring->next_to_use != i)
 776                 i40e_release_rx_desc(rx_ring, i);
 777 }
 778
 779 /**
 780  * i40e_receive_skb - Send a completed packet up the stack
 781  * @rx_ring:  rx ring in play
 782  * @skb: packet to send up
 783  * @vlan_tag: vlan tag for packet
 784  **/
 785 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 786                              struct sk_buff *skb, u16 vlan_tag)
 787 {
 788         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 789
 790         if (vlan_tag & VLAN_VID_MASK)
 791                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 792
 793         napi_gro_receive(&q_vector->napi, skb);
 794 }
 795
 796 /**
 797  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 798  * @vsi: the VSI we care about
 799  * @skb: skb currently being received and modified
 800  * @rx_status: status value of last descriptor in packet
 801  * @rx_error: error value of last descriptor in packet
 802  * @rx_ptype: ptype value of last descriptor in packet
 803  **/
 804 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 805                                     struct sk_buff *skb,
 806                                     u32 rx_status,
 807                                     u32 rx_error,
 808                                     u16 rx_ptype)
 809 {
 810         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 811         bool ipv4 = false, ipv6 = false;
 812         bool ipv4_tunnel, ipv6_tunnel;
 813         __wsum rx_udp_csum;
 814         struct iphdr *iph;
 815         __sum16 csum;
 816
 817         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 818                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 819         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 820                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 821
 822         skb->ip_summed = CHECKSUM_NONE;
 823
 824         /* Rx csum enabled and ip headers found? */
 825         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 826                 return;
 827
 828         /* did the hardware decode the packet and checksum? */
 829         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 830                 return;
 831
 832         /* both known and outer_ip must be set for the below code to work */
 833         if (!(decoded.known && decoded.outer_ip))
 834                 return;
 835
 836         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 837             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 838                 ipv4 = true;
 839         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 840                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 841                 ipv6 = true;
 842
 843         if (ipv4 &&
 844             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
 845                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 846                 goto checksum_fail;
 847
 848         /* likely incorrect csum if alternate IP extension headers found */
 849         if (ipv6 &&
 850             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 851                 /* don't increment checksum err here, non-fatal err */
 852                 return;
 853
 854         /* there was some L4 error, count error and punt packet to the stack */
 855         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
 856                 goto checksum_fail;
 857
 858         /* handle packets that were not able to be checksummed due
 859          * to arrival speed, in this case the stack can compute
 860          * the csum.
 861          */
 862         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
 863                 return;
 864
 865         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 866          * it in the driver, hardware does not do it for us.
 867          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 868          * so the total length of IPv4 header is IHL*4 bytes
 869          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 870          */
 871         if (ipv4_tunnel) {
 872                 skb->transport_header = skb->mac_header +
 873                                         sizeof(struct ethhdr) +
 874                                         (ip_hdr(skb)->ihl * 4);
 875
 876                 /* Add 4 bytes for VLAN tagged packets */
 877                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 878                                           skb->protocol == htons(ETH_P_8021AD))
 879                                           ? VLAN_HLEN : 0;
 880
 881                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
 882                     (udp_hdr(skb)->check != 0)) {
 883                         rx_udp_csum = udp_csum(skb);
 884                         iph = ip_hdr(skb);
 885                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
 886                                                  (skb->len -
 887                                                   skb_transport_offset(skb)),
 888                                                  IPPROTO_UDP, rx_udp_csum);
 889
 890                         if (udp_hdr(skb)->check != csum)
 891                                 goto checksum_fail;
 892
 893                 } /* else its GRE and so no outer UDP header */
 894         }
 895
 896         skb->ip_summed = CHECKSUM_UNNECESSARY;
 897         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 898
 899         return;
 900
 901 checksum_fail:
 902         vsi->back->hw_csum_rx_error++;
 903 }
 904
 905 /**
 906  * i40e_ptype_to_htype - get a hash type
 907  * @ptype: the ptype value from the descriptor
 908  *
 909  * Returns a hash type to be used by skb_set_hash
 910  **/
 911 static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
 912 {
 913         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 914
 915         if (!decoded.known)
 916                 return PKT_HASH_TYPE_NONE;
 917
 918         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 919             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 920                 return PKT_HASH_TYPE_L4;
 921         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 922                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 923                 return PKT_HASH_TYPE_L3;
 924         else
 925                 return PKT_HASH_TYPE_L2;
 926 }
 927
 928 /**
 929  * i40e_rx_hash - set the hash value in the skb
 930  * @ring: descriptor ring
 931  * @rx_desc: specific descriptor
 932  **/
 933 static inline void i40e_rx_hash(struct i40e_ring *ring,
 934                                 union i40e_rx_desc *rx_desc,
 935                                 struct sk_buff *skb,
 936                                 u8 rx_ptype)
 937 {
 938         u32 hash;
 939         const __le64 rss_mask  =
 940                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 941                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 942
 943         if (ring->netdev->features & NETIF_F_RXHASH)
 944                 return;
 945
 946         if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
 947                 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 948                 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
 949         }
 950 }
 951
 952 /**
 953  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
 954  * @rx_ring:  rx ring to clean
 955  * @budget:   how many cleans we're allowed
 956  *
 957  * Returns true if there's any budget left (e.g. the clean is finished)
 958  **/
 959 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
 960 {
 961         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 962         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 963         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
 964         const int current_node = numa_mem_id();
 965         struct i40e_vsi *vsi = rx_ring->vsi;
 966         u16 i = rx_ring->next_to_clean;
 967         union i40e_rx_desc *rx_desc;
 968         u32 rx_error, rx_status;
 969         u8 rx_ptype;
 970         u64 qword;
 971
 972         do {
 973                 struct i40e_rx_buffer *rx_bi;
 974                 struct sk_buff *skb;
 975                 u16 vlan_tag;
 976                 /* return some buffers to hardware, one at a time is too slow */
 977                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
 978                         i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
 979                         cleaned_count = 0;
 980                 }
 981
 982                 i = rx_ring->next_to_clean;
 983                 rx_desc = I40E_RX_DESC(rx_ring, i);
 984                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 985                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
 986                         I40E_RXD_QW1_STATUS_SHIFT;
 987
 988                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
 989                         break;
 990
 991                 /* This memory barrier is needed to keep us from reading
 992                  * any other fields out of the rx_desc until we know the
 993                  * DD bit is set.
 994                  */
 995                 dma_rmb();
 996                 rx_bi = &rx_ring->rx_bi[i];
 997                 skb = rx_bi->skb;
 998                 if (likely(!skb)) {
 999                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1000                                                         rx_ring->rx_hdr_len);
1001                         if (!skb) {
1002                                 rx_ring->rx_stats.alloc_buff_failed++;
1003                                 break;
1004                         }
1005
1006                         /* initialize queue mapping */
1007                         skb_record_rx_queue(skb, rx_ring->queue_index);
1008                         /* we are reusing so sync this buffer for CPU use */
1009                         dma_sync_single_range_for_cpu(rx_ring->dev,
1010                                                       rx_ring->rx_bi[0].dma,
1011                                                       i * rx_ring->rx_hdr_len,
1012                                                       rx_ring->rx_hdr_len,
1013                                                       DMA_FROM_DEVICE);
1014                 }
1015                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1016                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1017                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1018                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1019                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1020                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1021
1022                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1023                            I40E_RXD_QW1_ERROR_SHIFT;
1024                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1025                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1026
1027                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1028                            I40E_RXD_QW1_PTYPE_SHIFT;
1029                 prefetch(rx_bi->page);
1030                 rx_bi->skb = NULL;
1031                 cleaned_count++;
1032                 if (rx_hbo || rx_sph) {
1033                         int len;
1034
1035                         if (rx_hbo)
1036                                 len = I40E_RX_HDR_SIZE;
1037                         else
1038                                 len = rx_header_len;
1039                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1040                 } else if (skb->len == 0) {
1041                         int len;
1042
1043                         len = (rx_packet_len > skb_headlen(skb) ?
1044                                 skb_headlen(skb) : rx_packet_len);
1045                         memcpy(__skb_put(skb, len),
1046                                rx_bi->page + rx_bi->page_offset,
1047                                len);
1048                         rx_bi->page_offset += len;
1049                         rx_packet_len -= len;
1050                 }
1051
1052                 /* Get the rest of the data if this was a header split */
1053                 if (rx_packet_len) {
1054                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1055                                            rx_bi->page,
1056                                            rx_bi->page_offset,
1057                                            rx_packet_len);
1058
1059                         skb->len += rx_packet_len;
1060                         skb->data_len += rx_packet_len;
1061                         skb->truesize += rx_packet_len;
1062
1063                         if ((page_count(rx_bi->page) == 1) &&
1064                             (page_to_nid(rx_bi->page) == current_node))
1065                                 get_page(rx_bi->page);
1066                         else
1067                                 rx_bi->page = NULL;
1068
1069                         dma_unmap_page(rx_ring->dev,
1070                                        rx_bi->page_dma,
1071                                        PAGE_SIZE / 2,
1072                                        DMA_FROM_DEVICE);
1073                         rx_bi->page_dma = 0;
1074                 }
1075                 I40E_RX_INCREMENT(rx_ring, i);
1076
1077                 if (unlikely(
1078                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1079                         struct i40e_rx_buffer *next_buffer;
1080
1081                         next_buffer = &rx_ring->rx_bi[i];
1082                         next_buffer->skb = skb;
1083                         rx_ring->rx_stats.non_eop_descs++;
1084                         continue;
1085                 }
1086
1087                 /* ERR_MASK will only have valid bits if EOP set */
1088                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1089                         dev_kfree_skb_any(skb);
1090                         continue;
1091                 }
1092
1093                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1094
1095                 /* probably a little skewed due to removing CRC */
1096                 total_rx_bytes += skb->len;
1097                 total_rx_packets++;
1098
1099                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1100
1101                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1102
1103                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1104                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1105                          : 0;
1106 #ifdef I40E_FCOE
1107                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1108                         dev_kfree_skb_any(skb);
1109                         continue;
1110                 }
1111 #endif
1112                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1113
1114                 rx_desc->wb.qword1.status_error_len = 0;
1115
1116         } while (likely(total_rx_packets < budget));
1117
1118         u64_stats_update_begin(&rx_ring->syncp);
1119         rx_ring->stats.packets += total_rx_packets;
1120         rx_ring->stats.bytes += total_rx_bytes;
1121         u64_stats_update_end(&rx_ring->syncp);
1122         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1123         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1124
1125         return total_rx_packets;
1126 }
1127
1128 /**
1129  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1130  * @rx_ring:  rx ring to clean
1131  * @budget:   how many cleans we're allowed
1132  *
1133  * Returns number of packets cleaned
1134  **/
1135 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1136 {
1137         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1138         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1139         struct i40e_vsi *vsi = rx_ring->vsi;
1140         union i40e_rx_desc *rx_desc;
1141         u32 rx_error, rx_status;
1142         u16 rx_packet_len;
1143         u8 rx_ptype;
1144         u64 qword;
1145         u16 i;
1146
1147         do {
1148                 struct i40e_rx_buffer *rx_bi;
1149                 struct sk_buff *skb;
1150                 u16 vlan_tag;
1151                 /* return some buffers to hardware, one at a time is too slow */
1152                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1153                         i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1154                         cleaned_count = 0;
1155                 }
1156
1157                 i = rx_ring->next_to_clean;
1158                 rx_desc = I40E_RX_DESC(rx_ring, i);
1159                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1160                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1161                         I40E_RXD_QW1_STATUS_SHIFT;
1162
1163                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1164                         break;
1165
1166                 /* This memory barrier is needed to keep us from reading
1167                  * any other fields out of the rx_desc until we know the
1168                  * DD bit is set.
1169                  */
1170                 dma_rmb();
1171
1172                 rx_bi = &rx_ring->rx_bi[i];
1173                 skb = rx_bi->skb;
1174                 prefetch(skb->data);
1175
1176                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1177                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1178
1179                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1180                            I40E_RXD_QW1_ERROR_SHIFT;
1181                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1182
1183                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1184                            I40E_RXD_QW1_PTYPE_SHIFT;
1185                 rx_bi->skb = NULL;
1186                 cleaned_count++;
1187
1188                 /* Get the header and possibly the whole packet
1189                  * If this is an skb from previous receive dma will be 0
1190                  */
1191                 skb_put(skb, rx_packet_len);
1192                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1193                                  DMA_FROM_DEVICE);
1194                 rx_bi->dma = 0;
1195
1196                 I40E_RX_INCREMENT(rx_ring, i);
1197
1198                 if (unlikely(
1199                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1200                         rx_ring->rx_stats.non_eop_descs++;
1201                         continue;
1202                 }
1203
1204                 /* ERR_MASK will only have valid bits if EOP set */
1205                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1206                         dev_kfree_skb_any(skb);
1207                         continue;
1208                 }
1209
1210                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1211                 /* probably a little skewed due to removing CRC */
1212                 total_rx_bytes += skb->len;
1213                 total_rx_packets++;
1214
1215                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1216
1217                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1218
1219                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1220                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1221                          : 0;
1222                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1223
1224                 rx_desc->wb.qword1.status_error_len = 0;
1225         } while (likely(total_rx_packets < budget));
1226
1227         u64_stats_update_begin(&rx_ring->syncp);
1228         rx_ring->stats.packets += total_rx_packets;
1229         rx_ring->stats.bytes += total_rx_bytes;
1230         u64_stats_update_end(&rx_ring->syncp);
1231         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1232         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1233
1234         return total_rx_packets;
1235 }
1236
1237 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1238 {
1239         u32 val;
1240
1241         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1242               I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1243               (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1244               (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1245
1246         return val;
1247 }
1248
1249 /* a small macro to shorten up some long lines */
1250 #define INTREG I40E_VFINT_DYN_CTLN1
1251
1252 /**
1253  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1254  * @vsi: the VSI we care about
1255  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1256  *
1257  **/
1258 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1259                                           struct i40e_q_vector *q_vector)
1260 {
1261         struct i40e_hw *hw = &vsi->back->hw;
1262         bool rx = false, tx = false;
1263         u32 rxval, txval;
1264         int vector;
1265
1266         vector = (q_vector->v_idx + vsi->base_vector);
1267
1268         /* avoid dynamic calculation if in countdown mode OR if
1269          * all dynamic is disabled
1270          */
1271         rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1272
1273         if (q_vector->itr_countdown > 0 ||
1274             (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1275              !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1276                 goto enable_int;
1277         }
1278
1279         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1280                 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1281                 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1282         }
1283
1284         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1285                 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1286                 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1287         }
1288
1289         if (rx || tx) {
1290                 /* get the higher of the two ITR adjustments and
1291                  * use the same value for both ITR registers
1292                  * when in adaptive mode (Rx and/or Tx)
1293                  */
1294                 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1295
1296                 q_vector->tx.itr = q_vector->rx.itr = itr;
1297                 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1298                 tx = true;
1299                 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1300                 rx = true;
1301         }
1302
1303         /* only need to enable the interrupt once, but need
1304          * to possibly update both ITR values
1305          */
1306         if (rx) {
1307                 /* set the INTENA_MSK_MASK so that this first write
1308                  * won't actually enable the interrupt, instead just
1309                  * updating the ITR (it's bit 31 PF and VF)
1310                  */
1311                 rxval |= BIT(31);
1312                 /* don't check _DOWN because interrupt isn't being enabled */
1313                 wr32(hw, INTREG(vector - 1), rxval);
1314         }
1315
1316 enable_int:
1317         if (!test_bit(__I40E_DOWN, &vsi->state))
1318                 wr32(hw, INTREG(vector - 1), txval);
1319
1320         if (q_vector->itr_countdown)
1321                 q_vector->itr_countdown--;
1322         else
1323                 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1324 }
1325
1326 /**
1327  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1328  * @napi: napi struct with our devices info in it
1329  * @budget: amount of work driver is allowed to do this pass, in packets
1330  *
1331  * This function will clean all queues associated with a q_vector.
1332  *
1333  * Returns the amount of work done
1334  **/
1335 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1336 {
1337         struct i40e_q_vector *q_vector =
1338                                container_of(napi, struct i40e_q_vector, napi);
1339         struct i40e_vsi *vsi = q_vector->vsi;
1340         struct i40e_ring *ring;
1341         bool clean_complete = true;
1342         bool arm_wb = false;
1343         int budget_per_ring;
1344         int work_done = 0;
1345
1346         if (test_bit(__I40E_DOWN, &vsi->state)) {
1347                 napi_complete(napi);
1348                 return 0;
1349         }
1350
1351         /* Since the actual Tx work is minimal, we can give the Tx a larger
1352          * budget and be more aggressive about cleaning up the Tx descriptors.
1353          */
1354         i40e_for_each_ring(ring, q_vector->tx) {
1355                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1356                 arm_wb = arm_wb || ring->arm_wb;
1357                 ring->arm_wb = false;
1358         }
1359
1360         /* Handle case where we are called by netpoll with a budget of 0 */
1361         if (budget <= 0)
1362                 goto tx_only;
1363
1364         /* We attempt to distribute budget to each Rx queue fairly, but don't
1365          * allow the budget to go below 1 because that would exit polling early.
1366          */
1367         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1368
1369         i40e_for_each_ring(ring, q_vector->rx) {
1370                 int cleaned;
1371
1372                 if (ring_is_ps_enabled(ring))
1373                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1374                 else
1375                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1376
1377                 work_done += cleaned;
1378                 /* if we didn't clean as many as budgeted, we must be done */
1379                 clean_complete &= (budget_per_ring != cleaned);
1380         }
1381
1382         /* If work not completed, return budget and polling will return */
1383         if (!clean_complete) {
1384 tx_only:
1385                 if (arm_wb) {
1386                         q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1387                         i40evf_force_wb(vsi, q_vector);
1388                 }
1389                 return budget;
1390         }
1391
1392         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1393                 q_vector->arm_wb_state = false;
1394
1395         /* Work is done so exit the polling mode and re-enable the interrupt */
1396         napi_complete_done(napi, work_done);
1397         i40e_update_enable_itr(vsi, q_vector);
1398         return 0;
1399 }
1400
1401 /**
1402  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1403  * @skb:     send buffer
1404  * @tx_ring: ring to send buffer on
1405  * @flags:   the tx flags to be set
1406  *
1407  * Checks the skb and set up correspondingly several generic transmit flags
1408  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1409  *
1410  * Returns error code indicate the frame should be dropped upon error and the
1411  * otherwise  returns 0 to indicate the flags has been set properly.
1412  **/
1413 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1414                                                struct i40e_ring *tx_ring,
1415                                                u32 *flags)
1416 {
1417         __be16 protocol = skb->protocol;
1418         u32  tx_flags = 0;
1419
1420         if (protocol == htons(ETH_P_8021Q) &&
1421             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1422                 /* When HW VLAN acceleration is turned off by the user the
1423                  * stack sets the protocol to 8021q so that the driver
1424                  * can take any steps required to support the SW only
1425                  * VLAN handling.  In our case the driver doesn't need
1426                  * to take any further steps so just set the protocol
1427                  * to the encapsulated ethertype.
1428                  */
1429                 skb->protocol = vlan_get_protocol(skb);
1430                 goto out;
1431         }
1432
1433         /* if we have a HW VLAN tag being added, default to the HW one */
1434         if (skb_vlan_tag_present(skb)) {
1435                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1436                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1437         /* else if it is a SW VLAN, check the next protocol and store the tag */
1438         } else if (protocol == htons(ETH_P_8021Q)) {
1439                 struct vlan_hdr *vhdr, _vhdr;
1440
1441                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1442                 if (!vhdr)
1443                         return -EINVAL;
1444
1445                 protocol = vhdr->h_vlan_encapsulated_proto;
1446                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1447                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1448         }
1449
1450 out:
1451         *flags = tx_flags;
1452         return 0;
1453 }
1454
1455 /**
1456  * i40e_tso - set up the tso context descriptor
1457  * @tx_ring:  ptr to the ring to send
1458  * @skb:      ptr to the skb we're sending
1459  * @hdr_len:  ptr to the size of the packet header
1460  * @cd_type_cmd_tso_mss: Quad Word 1
1461  *
1462  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1463  **/
1464 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1465                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
1466 {
1467         u32 cd_cmd, cd_tso_len, cd_mss;
1468         struct ipv6hdr *ipv6h;
1469         struct tcphdr *tcph;
1470         struct iphdr *iph;
1471         u32 l4len;
1472         int err;
1473
1474         if (!skb_is_gso(skb))
1475                 return 0;
1476
1477         err = skb_cow_head(skb, 0);
1478         if (err < 0)
1479                 return err;
1480
1481         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1482         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1483
1484         if (iph->version == 4) {
1485                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1486                 iph->tot_len = 0;
1487                 iph->check = 0;
1488                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1489                                                  0, IPPROTO_TCP, 0);
1490         } else if (ipv6h->version == 6) {
1491                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1492                 ipv6h->payload_len = 0;
1493                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1494                                                0, IPPROTO_TCP, 0);
1495         }
1496
1497         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1498         *hdr_len = (skb->encapsulation
1499                     ? (skb_inner_transport_header(skb) - skb->data)
1500                     : skb_transport_offset(skb)) + l4len;
1501
1502         /* find the field values */
1503         cd_cmd = I40E_TX_CTX_DESC_TSO;
1504         cd_tso_len = skb->len - *hdr_len;
1505         cd_mss = skb_shinfo(skb)->gso_size;
1506         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1507                                 ((u64)cd_tso_len <<
1508                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1509                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1510         return 1;
1511 }
1512
1513 /**
1514  * i40e_tx_enable_csum - Enable Tx checksum offloads
1515  * @skb: send buffer
1516  * @tx_flags: pointer to Tx flags currently set
1517  * @td_cmd: Tx descriptor command bits to set
1518  * @td_offset: Tx descriptor header offsets to set
1519  * @cd_tunneling: ptr to context desc bits
1520  **/
1521 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1522                                 u32 *td_cmd, u32 *td_offset,
1523                                 struct i40e_ring *tx_ring,
1524                                 u32 *cd_tunneling)
1525 {
1526         struct ipv6hdr *this_ipv6_hdr;
1527         unsigned int this_tcp_hdrlen;
1528         struct iphdr *this_ip_hdr;
1529         u32 network_hdr_len;
1530         u8 l4_hdr = 0;
1531         struct udphdr *oudph;
1532         struct iphdr *oiph;
1533         u32 l4_tunnel = 0;
1534
1535         if (skb->encapsulation) {
1536                 switch (ip_hdr(skb)->protocol) {
1537                 case IPPROTO_UDP:
1538                         oudph = udp_hdr(skb);
1539                         oiph = ip_hdr(skb);
1540                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1541                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1542                         break;
1543                 default:
1544                         return;
1545                 }
1546                 network_hdr_len = skb_inner_network_header_len(skb);
1547                 this_ip_hdr = inner_ip_hdr(skb);
1548                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1549                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1550
1551                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1552                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1553                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1554                                 ip_hdr(skb)->check = 0;
1555                         } else {
1556                                 *cd_tunneling |=
1557                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1558                         }
1559                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1560                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1561                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1562                                 ip_hdr(skb)->check = 0;
1563                 }
1564
1565                 /* Now set the ctx descriptor fields */
1566                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1567                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1568                                    l4_tunnel                             |
1569                                    ((skb_inner_network_offset(skb) -
1570                                         skb_transport_offset(skb)) >> 1) <<
1571                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1572                 if (this_ip_hdr->version == 6) {
1573                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1574                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1575                 }
1576
1577                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1578                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
1579                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1580                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1581                                         oiph->daddr,
1582                                         (skb->len - skb_transport_offset(skb)),
1583                                         IPPROTO_UDP, 0);
1584                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1585                 }
1586         } else {
1587                 network_hdr_len = skb_network_header_len(skb);
1588                 this_ip_hdr = ip_hdr(skb);
1589                 this_ipv6_hdr = ipv6_hdr(skb);
1590                 this_tcp_hdrlen = tcp_hdrlen(skb);
1591         }
1592
1593         /* Enable IP checksum offloads */
1594         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1595                 l4_hdr = this_ip_hdr->protocol;
1596                 /* the stack computes the IP header already, the only time we
1597                  * need the hardware to recompute it is in the case of TSO.
1598                  */
1599                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1600                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1601                         this_ip_hdr->check = 0;
1602                 } else {
1603                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1604                 }
1605                 /* Now set the td_offset for IP header length */
1606                 *td_offset = (network_hdr_len >> 2) <<
1607                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1608         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1609                 l4_hdr = this_ipv6_hdr->nexthdr;
1610                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1611                 /* Now set the td_offset for IP header length */
1612                 *td_offset = (network_hdr_len >> 2) <<
1613                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1614         }
1615         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1616         *td_offset |= (skb_network_offset(skb) >> 1) <<
1617                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1618
1619         /* Enable L4 checksum offloads */
1620         switch (l4_hdr) {
1621         case IPPROTO_TCP:
1622                 /* enable checksum offloads */
1623                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1624                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1625                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1626                 break;
1627         case IPPROTO_SCTP:
1628                 /* enable SCTP checksum offload */
1629                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1630                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1631                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1632                 break;
1633         case IPPROTO_UDP:
1634                 /* enable UDP checksum offload */
1635                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1636                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1637                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1638                 break;
1639         default:
1640                 break;
1641         }
1642 }
1643
1644 /**
1645  * i40e_create_tx_ctx Build the Tx context descriptor
1646  * @tx_ring:  ring to create the descriptor on
1647  * @cd_type_cmd_tso_mss: Quad Word 1
1648  * @cd_tunneling: Quad Word 0 - bits 0-31
1649  * @cd_l2tag2: Quad Word 0 - bits 32-63
1650  **/
1651 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1652                                const u64 cd_type_cmd_tso_mss,
1653                                const u32 cd_tunneling, const u32 cd_l2tag2)
1654 {
1655         struct i40e_tx_context_desc *context_desc;
1656         int i = tx_ring->next_to_use;
1657
1658         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1659             !cd_tunneling && !cd_l2tag2)
1660                 return;
1661
1662         /* grab the next descriptor */
1663         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1664
1665         i++;
1666         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1667
1668         /* cpu_to_le32 and assign to struct fields */
1669         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1670         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1671         context_desc->rsvd = cpu_to_le16(0);
1672         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1673 }
1674
1675 /**
1676  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1677  * @skb:      send buffer
1678  * @tx_flags: collected send information
1679  *
1680  * Note: Our HW can't scatter-gather more than 8 fragments to build
1681  * a packet on the wire and so we need to figure out the cases where we
1682  * need to linearize the skb.
1683  **/
1684 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1685 {
1686         struct skb_frag_struct *frag;
1687         bool linearize = false;
1688         unsigned int size = 0;
1689         u16 num_frags;
1690         u16 gso_segs;
1691
1692         num_frags = skb_shinfo(skb)->nr_frags;
1693         gso_segs = skb_shinfo(skb)->gso_segs;
1694
1695         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1696                 u16 j = 0;
1697
1698                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1699                         goto linearize_chk_done;
1700                 /* try the simple math, if we have too many frags per segment */
1701                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1702                     I40E_MAX_BUFFER_TXD) {
1703                         linearize = true;
1704                         goto linearize_chk_done;
1705                 }
1706                 frag = &skb_shinfo(skb)->frags[0];
1707                 /* we might still have more fragments per segment */
1708                 do {
1709                         size += skb_frag_size(frag);
1710                         frag++; j++;
1711                         if ((size >= skb_shinfo(skb)->gso_size) &&
1712                             (j < I40E_MAX_BUFFER_TXD)) {
1713                                 size = (size % skb_shinfo(skb)->gso_size);
1714                                 j = (size) ? 1 : 0;
1715                         }
1716                         if (j == I40E_MAX_BUFFER_TXD) {
1717                                 linearize = true;
1718                                 break;
1719                         }
1720                         num_frags--;
1721                 } while (num_frags);
1722         } else {
1723                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1724                         linearize = true;
1725         }
1726
1727 linearize_chk_done:
1728         return linearize;
1729 }
1730
1731 /**
1732  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1733  * @tx_ring: the ring to be checked
1734  * @size:    the size buffer we want to assure is available
1735  *
1736  * Returns -EBUSY if a stop is needed, else 0
1737  **/
1738 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1739 {
1740         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1741         /* Memory barrier before checking head and tail */
1742         smp_mb();
1743
1744         /* Check again in a case another CPU has just made room available. */
1745         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1746                 return -EBUSY;
1747
1748         /* A reprieve! - use start_queue because it doesn't call schedule */
1749         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1750         ++tx_ring->tx_stats.restart_queue;
1751         return 0;
1752 }
1753
1754 /**
1755  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1756  * @tx_ring: the ring to be checked
1757  * @size:    the size buffer we want to assure is available
1758  *
1759  * Returns 0 if stop is not needed
1760  **/
1761 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1762 {
1763         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1764                 return 0;
1765         return __i40evf_maybe_stop_tx(tx_ring, size);
1766 }
1767
1768 /**
1769  * i40evf_tx_map - Build the Tx descriptor
1770  * @tx_ring:  ring to send buffer on
1771  * @skb:      send buffer
1772  * @first:    first buffer info buffer to use
1773  * @tx_flags: collected send information
1774  * @hdr_len:  size of the packet header
1775  * @td_cmd:   the command field in the descriptor
1776  * @td_offset: offset for checksum or crc
1777  **/
1778 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1779                                  struct i40e_tx_buffer *first, u32 tx_flags,
1780                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1781 {
1782         unsigned int data_len = skb->data_len;
1783         unsigned int size = skb_headlen(skb);
1784         struct skb_frag_struct *frag;
1785         struct i40e_tx_buffer *tx_bi;
1786         struct i40e_tx_desc *tx_desc;
1787         u16 i = tx_ring->next_to_use;
1788         u32 td_tag = 0;
1789         dma_addr_t dma;
1790         u16 gso_segs;
1791         u16 desc_count = 0;
1792         bool tail_bump = true;
1793         bool do_rs = false;
1794
1795         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1796                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1797                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1798                          I40E_TX_FLAGS_VLAN_SHIFT;
1799         }
1800
1801         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1802                 gso_segs = skb_shinfo(skb)->gso_segs;
1803         else
1804                 gso_segs = 1;
1805
1806         /* multiply data chunks by size of headers */
1807         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1808         first->gso_segs = gso_segs;
1809         first->skb = skb;
1810         first->tx_flags = tx_flags;
1811
1812         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1813
1814         tx_desc = I40E_TX_DESC(tx_ring, i);
1815         tx_bi = first;
1816
1817         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1818                 if (dma_mapping_error(tx_ring->dev, dma))
1819                         goto dma_error;
1820
1821                 /* record length, and DMA address */
1822                 dma_unmap_len_set(tx_bi, len, size);
1823                 dma_unmap_addr_set(tx_bi, dma, dma);
1824
1825                 tx_desc->buffer_addr = cpu_to_le64(dma);
1826
1827                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1828                         tx_desc->cmd_type_offset_bsz =
1829                                 build_ctob(td_cmd, td_offset,
1830                                            I40E_MAX_DATA_PER_TXD, td_tag);
1831
1832                         tx_desc++;
1833                         i++;
1834                         desc_count++;
1835
1836                         if (i == tx_ring->count) {
1837                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1838                                 i = 0;
1839                         }
1840
1841                         dma += I40E_MAX_DATA_PER_TXD;
1842                         size -= I40E_MAX_DATA_PER_TXD;
1843
1844                         tx_desc->buffer_addr = cpu_to_le64(dma);
1845                 }
1846
1847                 if (likely(!data_len))
1848                         break;
1849
1850                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1851                                                           size, td_tag);
1852
1853                 tx_desc++;
1854                 i++;
1855                 desc_count++;
1856
1857                 if (i == tx_ring->count) {
1858                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1859                         i = 0;
1860                 }
1861
1862                 size = skb_frag_size(frag);
1863                 data_len -= size;
1864
1865                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1866                                        DMA_TO_DEVICE);
1867
1868                 tx_bi = &tx_ring->tx_bi[i];
1869         }
1870
1871         /* set next_to_watch value indicating a packet is present */
1872         first->next_to_watch = tx_desc;
1873
1874         i++;
1875         if (i == tx_ring->count)
1876                 i = 0;
1877
1878         tx_ring->next_to_use = i;
1879
1880         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1881                                                  tx_ring->queue_index),
1882                                                  first->bytecount);
1883         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1884
1885         /* Algorithm to optimize tail and RS bit setting:
1886          * if xmit_more is supported
1887          *      if xmit_more is true
1888          *              do not update tail and do not mark RS bit.
1889          *      if xmit_more is false and last xmit_more was false
1890          *              if every packet spanned less than 4 desc
1891          *                      then set RS bit on 4th packet and update tail
1892          *                      on every packet
1893          *              else
1894          *                      update tail and set RS bit on every packet.
1895          *      if xmit_more is false and last_xmit_more was true
1896          *              update tail and set RS bit.
1897          *
1898          * Optimization: wmb to be issued only in case of tail update.
1899          * Also optimize the Descriptor WB path for RS bit with the same
1900          * algorithm.
1901          *
1902          * Note: If there are less than 4 packets
1903          * pending and interrupts were disabled the service task will
1904          * trigger a force WB.
1905          */
1906         if (skb->xmit_more  &&
1907             !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1908                                                     tx_ring->queue_index))) {
1909                 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1910                 tail_bump = false;
1911         } else if (!skb->xmit_more &&
1912                    !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1913                                                        tx_ring->queue_index)) &&
1914                    (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
1915                    (tx_ring->packet_stride < WB_STRIDE) &&
1916                    (desc_count < WB_STRIDE)) {
1917                 tx_ring->packet_stride++;
1918         } else {
1919                 tx_ring->packet_stride = 0;
1920                 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1921                 do_rs = true;
1922         }
1923         if (do_rs)
1924                 tx_ring->packet_stride = 0;
1925
1926         tx_desc->cmd_type_offset_bsz =
1927                         build_ctob(td_cmd, td_offset, size, td_tag) |
1928                         cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
1929                                                   I40E_TX_DESC_CMD_EOP) <<
1930                                                   I40E_TXD_QW1_CMD_SHIFT);
1931
1932         /* notify HW of packet */
1933         if (!tail_bump)
1934                 prefetchw(tx_desc + 1);
1935
1936         if (tail_bump) {
1937                 /* Force memory writes to complete before letting h/w
1938                  * know there are new descriptors to fetch.  (Only
1939                  * applicable for weak-ordered memory model archs,
1940                  * such as IA-64).
1941                  */
1942                 wmb();
1943                 writel(i, tx_ring->tail);
1944         }
1945
1946         return;
1947
1948 dma_error:
1949         dev_info(tx_ring->dev, "TX DMA map failed\n");
1950
1951         /* clear dma mappings for failed tx_bi map */
1952         for (;;) {
1953                 tx_bi = &tx_ring->tx_bi[i];
1954                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1955                 if (tx_bi == first)
1956                         break;
1957                 if (i == 0)
1958                         i = tx_ring->count;
1959                 i--;
1960         }
1961
1962         tx_ring->next_to_use = i;
1963 }
1964
1965 /**
1966  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1967  * @skb:     send buffer
1968  * @tx_ring: ring to send buffer on
1969  *
1970  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1971  * there is not enough descriptors available in this ring since we need at least
1972  * one descriptor.
1973  **/
1974 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1975                                                struct i40e_ring *tx_ring)
1976 {
1977         unsigned int f;
1978         int count = 0;
1979
1980         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1981          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1982          *       + 4 desc gap to avoid the cache line where head is,
1983          *       + 1 desc for context descriptor,
1984          * otherwise try next time
1985          */
1986         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1987                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1988
1989         count += TXD_USE_COUNT(skb_headlen(skb));
1990         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1991                 tx_ring->tx_stats.tx_busy++;
1992                 return 0;
1993         }
1994         return count;
1995 }
1996
1997 /**
1998  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1999  * @skb:     send buffer
2000  * @tx_ring: ring to send buffer on
2001  *
2002  * Returns NETDEV_TX_OK if sent, else an error code
2003  **/
2004 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2005                                         struct i40e_ring *tx_ring)
2006 {
2007         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2008         u32 cd_tunneling = 0, cd_l2tag2 = 0;
2009         struct i40e_tx_buffer *first;
2010         u32 td_offset = 0;
2011         u32 tx_flags = 0;
2012         __be16 protocol;
2013         u32 td_cmd = 0;
2014         u8 hdr_len = 0;
2015         int tso;
2016
2017         /* prefetch the data, we'll need it later */
2018         prefetch(skb->data);
2019
2020         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
2021                 return NETDEV_TX_BUSY;
2022
2023         /* prepare the xmit flags */
2024         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2025                 goto out_drop;
2026
2027         /* obtain protocol of skb */
2028         protocol = vlan_get_protocol(skb);
2029
2030         /* record the location of the first descriptor for this packet */
2031         first = &tx_ring->tx_bi[tx_ring->next_to_use];
2032
2033         /* setup IPv4/IPv6 offloads */
2034         if (protocol == htons(ETH_P_IP))
2035                 tx_flags |= I40E_TX_FLAGS_IPV4;
2036         else if (protocol == htons(ETH_P_IPV6))
2037                 tx_flags |= I40E_TX_FLAGS_IPV6;
2038
2039         tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss);
2040
2041         if (tso < 0)
2042                 goto out_drop;
2043         else if (tso)
2044                 tx_flags |= I40E_TX_FLAGS_TSO;
2045
2046         if (i40e_chk_linearize(skb, tx_flags)) {
2047                 if (skb_linearize(skb))
2048                         goto out_drop;
2049                 tx_ring->tx_stats.tx_linearize++;
2050         }
2051         skb_tx_timestamp(skb);
2052
2053         /* always enable CRC insertion offload */
2054         td_cmd |= I40E_TX_DESC_CMD_ICRC;
2055
2056         /* Always offload the checksum, since it's in the data descriptor */
2057         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2058                 tx_flags |= I40E_TX_FLAGS_CSUM;
2059
2060                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2061                                     tx_ring, &cd_tunneling);
2062         }
2063
2064         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2065                            cd_tunneling, cd_l2tag2);
2066
2067         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2068                       td_cmd, td_offset);
2069
2070         return NETDEV_TX_OK;
2071
2072 out_drop:
2073         dev_kfree_skb_any(skb);
2074         return NETDEV_TX_OK;
2075 }
2076
2077 /**
2078  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2079  * @skb:    send buffer
2080  * @netdev: network interface device structure
2081  *
2082  * Returns NETDEV_TX_OK if sent, else an error code
2083  **/
2084 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2085 {
2086         struct i40evf_adapter *adapter = netdev_priv(netdev);
2087         struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2088
2089         /* hardware can't handle really short frames, hardware padding works
2090          * beyond this point
2091          */
2092         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2093                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2094                         return NETDEV_TX_OK;
2095                 skb->len = I40E_MIN_TX_LEN;
2096                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2097         }
2098
2099         return i40e_xmit_frame_ring(skb, tx_ring);
2100 }