1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include <linux/prefetch.h>
28 #include <net/busy_poll.h>
31 #include "i40e_prototype.h"
33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
37 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
38 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
39 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
40 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
51 struct i40e_tx_buffer *tx_buffer)
54 dev_kfree_skb_any(tx_buffer->skb);
55 if (dma_unmap_len(tx_buffer, len))
56 dma_unmap_single(ring->dev,
57 dma_unmap_addr(tx_buffer, dma),
58 dma_unmap_len(tx_buffer, len),
60 } else if (dma_unmap_len(tx_buffer, len)) {
61 dma_unmap_page(ring->dev,
62 dma_unmap_addr(tx_buffer, dma),
63 dma_unmap_len(tx_buffer, len),
67 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
68 kfree(tx_buffer->raw_buf);
70 tx_buffer->next_to_watch = NULL;
71 tx_buffer->skb = NULL;
72 dma_unmap_len_set(tx_buffer, len, 0);
73 /* tx_buffer must be completely set up in the transmit path */
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
82 unsigned long bi_size;
85 /* ring already cleared, nothing to do */
89 /* Free all the Tx ring sk_buffs */
90 for (i = 0; i < tx_ring->count; i++)
91 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
93 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
94 memset(tx_ring->tx_bi, 0, bi_size);
96 /* Zero out the descriptor ring */
97 memset(tx_ring->desc, 0, tx_ring->size);
99 tx_ring->next_to_use = 0;
100 tx_ring->next_to_clean = 0;
102 if (!tx_ring->netdev)
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
107 tx_ring->queue_index));
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
114 * Free all transmit software resources
116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
118 i40evf_clean_tx_ring(tx_ring);
119 kfree(tx_ring->tx_bi);
120 tx_ring->tx_bi = NULL;
123 dma_free_coherent(tx_ring->dev, tx_ring->size,
124 tx_ring->desc, tx_ring->dma);
125 tx_ring->desc = NULL;
130 * i40evf_get_tx_pending - how many Tx descriptors not processed
131 * @tx_ring: the ring of descriptors
133 * Since there is no access to the ring head register
134 * in XL710, we need to use our local copies
136 u32 i40evf_get_tx_pending(struct i40e_ring *ring)
140 head = i40e_get_head(ring);
141 tail = readl(ring->tail);
144 return (head < tail) ?
145 tail - head : (tail + ring->count - head);
150 #define WB_STRIDE 0x3
153 * i40e_clean_tx_irq - Reclaim resources after transmit completes
154 * @tx_ring: tx ring to clean
155 * @budget: how many cleans we're allowed
157 * Returns true if there's any budget left (e.g. the clean is finished)
159 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
161 u16 i = tx_ring->next_to_clean;
162 struct i40e_tx_buffer *tx_buf;
163 struct i40e_tx_desc *tx_head;
164 struct i40e_tx_desc *tx_desc;
165 unsigned int total_packets = 0;
166 unsigned int total_bytes = 0;
168 tx_buf = &tx_ring->tx_bi[i];
169 tx_desc = I40E_TX_DESC(tx_ring, i);
172 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
175 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
177 /* if next_to_watch is not set then there is no work pending */
181 /* prevent any other reads prior to eop_desc */
182 read_barrier_depends();
184 /* we have caught up to head, no work left to do */
185 if (tx_head == tx_desc)
188 /* clear next_to_watch to prevent false hangs */
189 tx_buf->next_to_watch = NULL;
191 /* update the statistics for this packet */
192 total_bytes += tx_buf->bytecount;
193 total_packets += tx_buf->gso_segs;
196 dev_kfree_skb_any(tx_buf->skb);
198 /* unmap skb header data */
199 dma_unmap_single(tx_ring->dev,
200 dma_unmap_addr(tx_buf, dma),
201 dma_unmap_len(tx_buf, len),
204 /* clear tx_buffer data */
206 dma_unmap_len_set(tx_buf, len, 0);
208 /* unmap remaining buffers */
209 while (tx_desc != eop_desc) {
216 tx_buf = tx_ring->tx_bi;
217 tx_desc = I40E_TX_DESC(tx_ring, 0);
220 /* unmap any remaining paged data */
221 if (dma_unmap_len(tx_buf, len)) {
222 dma_unmap_page(tx_ring->dev,
223 dma_unmap_addr(tx_buf, dma),
224 dma_unmap_len(tx_buf, len),
226 dma_unmap_len_set(tx_buf, len, 0);
230 /* move us one more past the eop_desc for start of next pkt */
236 tx_buf = tx_ring->tx_bi;
237 tx_desc = I40E_TX_DESC(tx_ring, 0);
242 /* update budget accounting */
244 } while (likely(budget));
247 tx_ring->next_to_clean = i;
248 u64_stats_update_begin(&tx_ring->syncp);
249 tx_ring->stats.bytes += total_bytes;
250 tx_ring->stats.packets += total_packets;
251 u64_stats_update_end(&tx_ring->syncp);
252 tx_ring->q_vector->tx.total_bytes += total_bytes;
253 tx_ring->q_vector->tx.total_packets += total_packets;
255 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
257 /* check to see if there are < 4 descriptors
258 * waiting to be written back, then kick the hardware to force
259 * them to be written back in case we stay in NAPI.
260 * In this mode on X722 we do not enable Interrupt.
262 j = i40evf_get_tx_pending(tx_ring);
265 ((j / (WB_STRIDE + 1)) == 0) && (j > 0) &&
266 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
267 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
268 tx_ring->arm_wb = true;
271 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
272 tx_ring->queue_index),
273 total_packets, total_bytes);
275 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
276 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
277 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
278 /* Make sure that anybody stopping the queue after this
279 * sees the new next_to_clean.
282 if (__netif_subqueue_stopped(tx_ring->netdev,
283 tx_ring->queue_index) &&
284 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
285 netif_wake_subqueue(tx_ring->netdev,
286 tx_ring->queue_index);
287 ++tx_ring->tx_stats.restart_queue;
295 * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
296 * @vsi: the VSI we care about
297 * @q_vector: the vector on which to force writeback
300 static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
302 u16 flags = q_vector->tx.ring[0].flags;
304 if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
307 if (q_vector->arm_wb_state)
310 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK;
313 I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
314 vsi->base_vector - 1),
316 q_vector->arm_wb_state = true;
318 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
319 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
320 I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
321 I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
322 /* allow 00 to be written to the index */
325 I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
326 vsi->base_vector - 1), val);
331 * i40e_set_new_dynamic_itr - Find new ITR level
332 * @rc: structure containing ring performance data
334 * Returns true if ITR changed, false if not
336 * Stores a new ITR value based on packets and byte counts during
337 * the last interrupt. The advantage of per interrupt computation
338 * is faster updates and more accurate ITR for the current traffic
339 * pattern. Constants in this function were computed based on
340 * theoretical maximum wire speed and thresholds were set based on
341 * testing data as well as attempting to minimize response time
342 * while increasing bulk throughput.
344 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
346 enum i40e_latency_range new_latency_range = rc->latency_range;
347 struct i40e_q_vector *qv = rc->ring->q_vector;
348 u32 new_itr = rc->itr;
352 if (rc->total_packets == 0 || !rc->itr)
355 /* simple throttlerate management
356 * 0-10MB/s lowest (50000 ints/s)
357 * 10-20MB/s low (20000 ints/s)
358 * 20-1249MB/s bulk (18000 ints/s)
359 * > 40000 Rx packets per second (8000 ints/s)
361 * The math works out because the divisor is in 10^(-6) which
362 * turns the bytes/us input value into MB/s values, but
363 * make sure to use usecs, as the register values written
364 * are in 2 usec increments in the ITR registers, and make sure
365 * to use the smoothed values that the countdown timer gives us.
367 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
368 bytes_per_int = rc->total_bytes / usecs;
370 switch (new_latency_range) {
371 case I40E_LOWEST_LATENCY:
372 if (bytes_per_int > 10)
373 new_latency_range = I40E_LOW_LATENCY;
375 case I40E_LOW_LATENCY:
376 if (bytes_per_int > 20)
377 new_latency_range = I40E_BULK_LATENCY;
378 else if (bytes_per_int <= 10)
379 new_latency_range = I40E_LOWEST_LATENCY;
381 case I40E_BULK_LATENCY:
382 case I40E_ULTRA_LATENCY:
384 if (bytes_per_int <= 20)
385 new_latency_range = I40E_LOW_LATENCY;
389 /* this is to adjust RX more aggressively when streaming small
390 * packets. The value of 40000 was picked as it is just beyond
391 * what the hardware can receive per second if in low latency
394 #define RX_ULTRA_PACKET_RATE 40000
396 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
398 new_latency_range = I40E_ULTRA_LATENCY;
400 rc->latency_range = new_latency_range;
402 switch (new_latency_range) {
403 case I40E_LOWEST_LATENCY:
404 new_itr = I40E_ITR_50K;
406 case I40E_LOW_LATENCY:
407 new_itr = I40E_ITR_20K;
409 case I40E_BULK_LATENCY:
410 new_itr = I40E_ITR_18K;
412 case I40E_ULTRA_LATENCY:
413 new_itr = I40E_ITR_8K;
420 rc->total_packets = 0;
422 if (new_itr != rc->itr) {
431 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
432 * @tx_ring: the tx ring to set up
434 * Return 0 on success, negative on error
436 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
438 struct device *dev = tx_ring->dev;
444 /* warn if we are about to overwrite the pointer */
445 WARN_ON(tx_ring->tx_bi);
446 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
447 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
451 /* round up to nearest 4K */
452 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
453 /* add u32 for head writeback, align after this takes care of
454 * guaranteeing this is at least one cache line in size
456 tx_ring->size += sizeof(u32);
457 tx_ring->size = ALIGN(tx_ring->size, 4096);
458 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
459 &tx_ring->dma, GFP_KERNEL);
460 if (!tx_ring->desc) {
461 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
466 tx_ring->next_to_use = 0;
467 tx_ring->next_to_clean = 0;
471 kfree(tx_ring->tx_bi);
472 tx_ring->tx_bi = NULL;
477 * i40evf_clean_rx_ring - Free Rx buffers
478 * @rx_ring: ring to be cleaned
480 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
482 struct device *dev = rx_ring->dev;
483 struct i40e_rx_buffer *rx_bi;
484 unsigned long bi_size;
487 /* ring already cleared, nothing to do */
491 if (ring_is_ps_enabled(rx_ring)) {
492 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
494 rx_bi = &rx_ring->rx_bi[0];
495 if (rx_bi->hdr_buf) {
496 dma_free_coherent(dev,
500 for (i = 0; i < rx_ring->count; i++) {
501 rx_bi = &rx_ring->rx_bi[i];
503 rx_bi->hdr_buf = NULL;
507 /* Free all the Rx ring sk_buffs */
508 for (i = 0; i < rx_ring->count; i++) {
509 rx_bi = &rx_ring->rx_bi[i];
511 dma_unmap_single(dev,
518 dev_kfree_skb(rx_bi->skb);
522 if (rx_bi->page_dma) {
529 __free_page(rx_bi->page);
531 rx_bi->page_offset = 0;
535 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
536 memset(rx_ring->rx_bi, 0, bi_size);
538 /* Zero out the descriptor ring */
539 memset(rx_ring->desc, 0, rx_ring->size);
541 rx_ring->next_to_clean = 0;
542 rx_ring->next_to_use = 0;
546 * i40evf_free_rx_resources - Free Rx resources
547 * @rx_ring: ring to clean the resources from
549 * Free all receive software resources
551 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
553 i40evf_clean_rx_ring(rx_ring);
554 kfree(rx_ring->rx_bi);
555 rx_ring->rx_bi = NULL;
558 dma_free_coherent(rx_ring->dev, rx_ring->size,
559 rx_ring->desc, rx_ring->dma);
560 rx_ring->desc = NULL;
565 * i40evf_alloc_rx_headers - allocate rx header buffers
566 * @rx_ring: ring to alloc buffers
568 * Allocate rx header buffers for the entire ring. As these are static,
569 * this is only called when setting up a new ring.
571 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
573 struct device *dev = rx_ring->dev;
574 struct i40e_rx_buffer *rx_bi;
580 if (rx_ring->rx_bi[0].hdr_buf)
582 /* Make sure the buffers don't cross cache line boundaries. */
583 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
584 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
588 for (i = 0; i < rx_ring->count; i++) {
589 rx_bi = &rx_ring->rx_bi[i];
590 rx_bi->dma = dma + (i * buf_size);
591 rx_bi->hdr_buf = buffer + (i * buf_size);
596 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
597 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
599 * Returns 0 on success, negative on failure
601 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
603 struct device *dev = rx_ring->dev;
606 /* warn if we are about to overwrite the pointer */
607 WARN_ON(rx_ring->rx_bi);
608 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
609 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
613 u64_stats_init(&rx_ring->syncp);
615 /* Round up to nearest 4K */
616 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
617 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
618 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
619 rx_ring->size = ALIGN(rx_ring->size, 4096);
620 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
621 &rx_ring->dma, GFP_KERNEL);
623 if (!rx_ring->desc) {
624 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
629 rx_ring->next_to_clean = 0;
630 rx_ring->next_to_use = 0;
634 kfree(rx_ring->rx_bi);
635 rx_ring->rx_bi = NULL;
640 * i40e_release_rx_desc - Store the new tail and head values
641 * @rx_ring: ring to bump
642 * @val: new head index
644 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
646 rx_ring->next_to_use = val;
647 /* Force memory writes to complete before letting h/w
648 * know there are new descriptors to fetch. (Only
649 * applicable for weak-ordered memory model archs,
653 writel(val, rx_ring->tail);
657 * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
658 * @rx_ring: ring to place buffers on
659 * @cleaned_count: number of buffers to replace
661 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
663 u16 i = rx_ring->next_to_use;
664 union i40e_rx_desc *rx_desc;
665 struct i40e_rx_buffer *bi;
667 /* do nothing if no valid netdev defined */
668 if (!rx_ring->netdev || !cleaned_count)
671 while (cleaned_count--) {
672 rx_desc = I40E_RX_DESC(rx_ring, i);
673 bi = &rx_ring->rx_bi[i];
675 if (bi->skb) /* desc is in use */
678 bi->page = alloc_page(GFP_ATOMIC);
680 rx_ring->rx_stats.alloc_page_failed++;
686 /* use a half page if we're re-using */
687 bi->page_offset ^= PAGE_SIZE / 2;
688 bi->page_dma = dma_map_page(rx_ring->dev,
693 if (dma_mapping_error(rx_ring->dev,
695 rx_ring->rx_stats.alloc_page_failed++;
701 dma_sync_single_range_for_device(rx_ring->dev,
706 /* Refresh the desc even if buffer_addrs didn't change
707 * because each write-back erases this info.
709 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
710 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
712 if (i == rx_ring->count)
717 if (rx_ring->next_to_use != i)
718 i40e_release_rx_desc(rx_ring, i);
722 * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
723 * @rx_ring: ring to place buffers on
724 * @cleaned_count: number of buffers to replace
726 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
728 u16 i = rx_ring->next_to_use;
729 union i40e_rx_desc *rx_desc;
730 struct i40e_rx_buffer *bi;
733 /* do nothing if no valid netdev defined */
734 if (!rx_ring->netdev || !cleaned_count)
737 while (cleaned_count--) {
738 rx_desc = I40E_RX_DESC(rx_ring, i);
739 bi = &rx_ring->rx_bi[i];
743 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
744 rx_ring->rx_buf_len);
746 rx_ring->rx_stats.alloc_buff_failed++;
749 /* initialize queue mapping */
750 skb_record_rx_queue(skb, rx_ring->queue_index);
755 bi->dma = dma_map_single(rx_ring->dev,
759 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
760 rx_ring->rx_stats.alloc_buff_failed++;
766 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
767 rx_desc->read.hdr_addr = 0;
769 if (i == rx_ring->count)
774 if (rx_ring->next_to_use != i)
775 i40e_release_rx_desc(rx_ring, i);
779 * i40e_receive_skb - Send a completed packet up the stack
780 * @rx_ring: rx ring in play
781 * @skb: packet to send up
782 * @vlan_tag: vlan tag for packet
784 static void i40e_receive_skb(struct i40e_ring *rx_ring,
785 struct sk_buff *skb, u16 vlan_tag)
787 struct i40e_q_vector *q_vector = rx_ring->q_vector;
789 if (vlan_tag & VLAN_VID_MASK)
790 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
792 napi_gro_receive(&q_vector->napi, skb);
796 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
797 * @vsi: the VSI we care about
798 * @skb: skb currently being received and modified
799 * @rx_status: status value of last descriptor in packet
800 * @rx_error: error value of last descriptor in packet
801 * @rx_ptype: ptype value of last descriptor in packet
803 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
809 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
810 bool ipv4 = false, ipv6 = false;
811 bool ipv4_tunnel, ipv6_tunnel;
816 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
817 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
818 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
819 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
821 skb->ip_summed = CHECKSUM_NONE;
823 /* Rx csum enabled and ip headers found? */
824 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
827 /* did the hardware decode the packet and checksum? */
828 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
831 /* both known and outer_ip must be set for the below code to work */
832 if (!(decoded.known && decoded.outer_ip))
835 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
836 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
838 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
839 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
843 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
844 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
847 /* likely incorrect csum if alternate IP extension headers found */
849 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
850 /* don't increment checksum err here, non-fatal err */
853 /* there was some L4 error, count error and punt packet to the stack */
854 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
857 /* handle packets that were not able to be checksummed due
858 * to arrival speed, in this case the stack can compute
861 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
864 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
865 * it in the driver, hardware does not do it for us.
866 * Since L3L4P bit was set we assume a valid IHL value (>=5)
867 * so the total length of IPv4 header is IHL*4 bytes
868 * The UDP_0 bit *may* bet set if the *inner* header is UDP
871 skb->transport_header = skb->mac_header +
872 sizeof(struct ethhdr) +
873 (ip_hdr(skb)->ihl * 4);
875 /* Add 4 bytes for VLAN tagged packets */
876 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
877 skb->protocol == htons(ETH_P_8021AD))
880 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
881 (udp_hdr(skb)->check != 0)) {
882 rx_udp_csum = udp_csum(skb);
884 csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
886 skb_transport_offset(skb)),
887 IPPROTO_UDP, rx_udp_csum);
889 if (udp_hdr(skb)->check != csum)
892 } /* else its GRE and so no outer UDP header */
895 skb->ip_summed = CHECKSUM_UNNECESSARY;
896 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
901 vsi->back->hw_csum_rx_error++;
905 * i40e_ptype_to_htype - get a hash type
906 * @ptype: the ptype value from the descriptor
908 * Returns a hash type to be used by skb_set_hash
910 static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
912 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
915 return PKT_HASH_TYPE_NONE;
917 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
918 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
919 return PKT_HASH_TYPE_L4;
920 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
921 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
922 return PKT_HASH_TYPE_L3;
924 return PKT_HASH_TYPE_L2;
928 * i40e_rx_hash - set the hash value in the skb
929 * @ring: descriptor ring
930 * @rx_desc: specific descriptor
932 static inline void i40e_rx_hash(struct i40e_ring *ring,
933 union i40e_rx_desc *rx_desc,
938 const __le64 rss_mask =
939 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
940 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
942 if (ring->netdev->features & NETIF_F_RXHASH)
945 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
946 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
947 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
952 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
953 * @rx_ring: rx ring to clean
954 * @budget: how many cleans we're allowed
956 * Returns true if there's any budget left (e.g. the clean is finished)
958 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
960 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
961 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
962 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
963 const int current_node = numa_mem_id();
964 struct i40e_vsi *vsi = rx_ring->vsi;
965 u16 i = rx_ring->next_to_clean;
966 union i40e_rx_desc *rx_desc;
967 u32 rx_error, rx_status;
972 struct i40e_rx_buffer *rx_bi;
975 /* return some buffers to hardware, one at a time is too slow */
976 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
977 i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
981 i = rx_ring->next_to_clean;
982 rx_desc = I40E_RX_DESC(rx_ring, i);
983 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
984 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
985 I40E_RXD_QW1_STATUS_SHIFT;
987 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
990 /* This memory barrier is needed to keep us from reading
991 * any other fields out of the rx_desc until we know the
995 rx_bi = &rx_ring->rx_bi[i];
998 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
999 rx_ring->rx_hdr_len);
1001 rx_ring->rx_stats.alloc_buff_failed++;
1005 /* initialize queue mapping */
1006 skb_record_rx_queue(skb, rx_ring->queue_index);
1007 /* we are reusing so sync this buffer for CPU use */
1008 dma_sync_single_range_for_cpu(rx_ring->dev,
1011 rx_ring->rx_hdr_len,
1014 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1015 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1016 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1017 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1018 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1019 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1021 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1022 I40E_RXD_QW1_ERROR_SHIFT;
1023 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1024 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1026 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1027 I40E_RXD_QW1_PTYPE_SHIFT;
1028 prefetch(rx_bi->page);
1031 if (rx_hbo || rx_sph) {
1035 len = I40E_RX_HDR_SIZE;
1037 len = rx_header_len;
1038 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1039 } else if (skb->len == 0) {
1042 len = (rx_packet_len > skb_headlen(skb) ?
1043 skb_headlen(skb) : rx_packet_len);
1044 memcpy(__skb_put(skb, len),
1045 rx_bi->page + rx_bi->page_offset,
1047 rx_bi->page_offset += len;
1048 rx_packet_len -= len;
1051 /* Get the rest of the data if this was a header split */
1052 if (rx_packet_len) {
1053 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1058 skb->len += rx_packet_len;
1059 skb->data_len += rx_packet_len;
1060 skb->truesize += rx_packet_len;
1062 if ((page_count(rx_bi->page) == 1) &&
1063 (page_to_nid(rx_bi->page) == current_node))
1064 get_page(rx_bi->page);
1068 dma_unmap_page(rx_ring->dev,
1072 rx_bi->page_dma = 0;
1074 I40E_RX_INCREMENT(rx_ring, i);
1077 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1078 struct i40e_rx_buffer *next_buffer;
1080 next_buffer = &rx_ring->rx_bi[i];
1081 next_buffer->skb = skb;
1082 rx_ring->rx_stats.non_eop_descs++;
1086 /* ERR_MASK will only have valid bits if EOP set */
1087 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1088 dev_kfree_skb_any(skb);
1092 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1094 /* probably a little skewed due to removing CRC */
1095 total_rx_bytes += skb->len;
1098 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1100 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1102 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1103 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1106 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1107 dev_kfree_skb_any(skb);
1111 i40e_receive_skb(rx_ring, skb, vlan_tag);
1113 rx_desc->wb.qword1.status_error_len = 0;
1115 } while (likely(total_rx_packets < budget));
1117 u64_stats_update_begin(&rx_ring->syncp);
1118 rx_ring->stats.packets += total_rx_packets;
1119 rx_ring->stats.bytes += total_rx_bytes;
1120 u64_stats_update_end(&rx_ring->syncp);
1121 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1122 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1124 return total_rx_packets;
1128 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1129 * @rx_ring: rx ring to clean
1130 * @budget: how many cleans we're allowed
1132 * Returns number of packets cleaned
1134 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1136 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1137 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1138 struct i40e_vsi *vsi = rx_ring->vsi;
1139 union i40e_rx_desc *rx_desc;
1140 u32 rx_error, rx_status;
1147 struct i40e_rx_buffer *rx_bi;
1148 struct sk_buff *skb;
1150 /* return some buffers to hardware, one at a time is too slow */
1151 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1152 i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1156 i = rx_ring->next_to_clean;
1157 rx_desc = I40E_RX_DESC(rx_ring, i);
1158 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1159 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1160 I40E_RXD_QW1_STATUS_SHIFT;
1162 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1165 /* This memory barrier is needed to keep us from reading
1166 * any other fields out of the rx_desc until we know the
1171 rx_bi = &rx_ring->rx_bi[i];
1173 prefetch(skb->data);
1175 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1176 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1178 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1179 I40E_RXD_QW1_ERROR_SHIFT;
1180 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1182 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1183 I40E_RXD_QW1_PTYPE_SHIFT;
1187 /* Get the header and possibly the whole packet
1188 * If this is an skb from previous receive dma will be 0
1190 skb_put(skb, rx_packet_len);
1191 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1195 I40E_RX_INCREMENT(rx_ring, i);
1198 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1199 rx_ring->rx_stats.non_eop_descs++;
1203 /* ERR_MASK will only have valid bits if EOP set */
1204 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1205 dev_kfree_skb_any(skb);
1209 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1210 /* probably a little skewed due to removing CRC */
1211 total_rx_bytes += skb->len;
1214 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1216 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1218 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1219 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1221 i40e_receive_skb(rx_ring, skb, vlan_tag);
1223 rx_desc->wb.qword1.status_error_len = 0;
1224 } while (likely(total_rx_packets < budget));
1226 u64_stats_update_begin(&rx_ring->syncp);
1227 rx_ring->stats.packets += total_rx_packets;
1228 rx_ring->stats.bytes += total_rx_bytes;
1229 u64_stats_update_end(&rx_ring->syncp);
1230 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1231 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1233 return total_rx_packets;
1236 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1240 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1241 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1242 (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1243 (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1248 /* a small macro to shorten up some long lines */
1249 #define INTREG I40E_VFINT_DYN_CTLN1
1252 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1253 * @vsi: the VSI we care about
1254 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1257 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1258 struct i40e_q_vector *q_vector)
1260 struct i40e_hw *hw = &vsi->back->hw;
1261 bool rx = false, tx = false;
1265 vector = (q_vector->v_idx + vsi->base_vector);
1267 /* avoid dynamic calculation if in countdown mode OR if
1268 * all dynamic is disabled
1270 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1272 if (q_vector->itr_countdown > 0 ||
1273 (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1274 !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1278 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1279 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1280 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1283 if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1284 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1285 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1289 /* get the higher of the two ITR adjustments and
1290 * use the same value for both ITR registers
1291 * when in adaptive mode (Rx and/or Tx)
1293 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1295 q_vector->tx.itr = q_vector->rx.itr = itr;
1296 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1298 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1302 /* only need to enable the interrupt once, but need
1303 * to possibly update both ITR values
1306 /* set the INTENA_MSK_MASK so that this first write
1307 * won't actually enable the interrupt, instead just
1308 * updating the ITR (it's bit 31 PF and VF)
1311 /* don't check _DOWN because interrupt isn't being enabled */
1312 wr32(hw, INTREG(vector - 1), rxval);
1316 if (!test_bit(__I40E_DOWN, &vsi->state))
1317 wr32(hw, INTREG(vector - 1), txval);
1319 if (q_vector->itr_countdown)
1320 q_vector->itr_countdown--;
1322 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1326 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1327 * @napi: napi struct with our devices info in it
1328 * @budget: amount of work driver is allowed to do this pass, in packets
1330 * This function will clean all queues associated with a q_vector.
1332 * Returns the amount of work done
1334 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1336 struct i40e_q_vector *q_vector =
1337 container_of(napi, struct i40e_q_vector, napi);
1338 struct i40e_vsi *vsi = q_vector->vsi;
1339 struct i40e_ring *ring;
1340 bool clean_complete = true;
1341 bool arm_wb = false;
1342 int budget_per_ring;
1345 if (test_bit(__I40E_DOWN, &vsi->state)) {
1346 napi_complete(napi);
1350 /* Since the actual Tx work is minimal, we can give the Tx a larger
1351 * budget and be more aggressive about cleaning up the Tx descriptors.
1353 i40e_for_each_ring(ring, q_vector->tx) {
1354 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1355 arm_wb = arm_wb || ring->arm_wb;
1356 ring->arm_wb = false;
1359 /* Handle case where we are called by netpoll with a budget of 0 */
1363 /* We attempt to distribute budget to each Rx queue fairly, but don't
1364 * allow the budget to go below 1 because that would exit polling early.
1366 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1368 i40e_for_each_ring(ring, q_vector->rx) {
1371 if (ring_is_ps_enabled(ring))
1372 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1374 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1376 work_done += cleaned;
1377 /* if we didn't clean as many as budgeted, we must be done */
1378 clean_complete &= (budget_per_ring != cleaned);
1381 /* If work not completed, return budget and polling will return */
1382 if (!clean_complete) {
1385 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1386 i40evf_force_wb(vsi, q_vector);
1391 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1392 q_vector->arm_wb_state = false;
1394 /* Work is done so exit the polling mode and re-enable the interrupt */
1395 napi_complete_done(napi, work_done);
1396 i40e_update_enable_itr(vsi, q_vector);
1401 * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1403 * @tx_ring: ring to send buffer on
1404 * @flags: the tx flags to be set
1406 * Checks the skb and set up correspondingly several generic transmit flags
1407 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1409 * Returns error code indicate the frame should be dropped upon error and the
1410 * otherwise returns 0 to indicate the flags has been set properly.
1412 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1413 struct i40e_ring *tx_ring,
1416 __be16 protocol = skb->protocol;
1419 if (protocol == htons(ETH_P_8021Q) &&
1420 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1421 /* When HW VLAN acceleration is turned off by the user the
1422 * stack sets the protocol to 8021q so that the driver
1423 * can take any steps required to support the SW only
1424 * VLAN handling. In our case the driver doesn't need
1425 * to take any further steps so just set the protocol
1426 * to the encapsulated ethertype.
1428 skb->protocol = vlan_get_protocol(skb);
1432 /* if we have a HW VLAN tag being added, default to the HW one */
1433 if (skb_vlan_tag_present(skb)) {
1434 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1435 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1436 /* else if it is a SW VLAN, check the next protocol and store the tag */
1437 } else if (protocol == htons(ETH_P_8021Q)) {
1438 struct vlan_hdr *vhdr, _vhdr;
1440 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1444 protocol = vhdr->h_vlan_encapsulated_proto;
1445 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1446 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1455 * i40e_tso - set up the tso context descriptor
1456 * @tx_ring: ptr to the ring to send
1457 * @skb: ptr to the skb we're sending
1458 * @hdr_len: ptr to the size of the packet header
1459 * @cd_type_cmd_tso_mss: Quad Word 1
1461 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1463 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1464 u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
1466 u32 cd_cmd, cd_tso_len, cd_mss;
1467 struct ipv6hdr *ipv6h;
1468 struct tcphdr *tcph;
1473 if (!skb_is_gso(skb))
1476 err = skb_cow_head(skb, 0);
1480 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1481 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1483 if (iph->version == 4) {
1484 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1487 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1489 } else if (ipv6h->version == 6) {
1490 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1491 ipv6h->payload_len = 0;
1492 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1496 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1497 *hdr_len = (skb->encapsulation
1498 ? (skb_inner_transport_header(skb) - skb->data)
1499 : skb_transport_offset(skb)) + l4len;
1501 /* find the field values */
1502 cd_cmd = I40E_TX_CTX_DESC_TSO;
1503 cd_tso_len = skb->len - *hdr_len;
1504 cd_mss = skb_shinfo(skb)->gso_size;
1505 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1507 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1508 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1513 * i40e_tx_enable_csum - Enable Tx checksum offloads
1515 * @tx_flags: pointer to Tx flags currently set
1516 * @td_cmd: Tx descriptor command bits to set
1517 * @td_offset: Tx descriptor header offsets to set
1518 * @cd_tunneling: ptr to context desc bits
1520 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1521 u32 *td_cmd, u32 *td_offset,
1522 struct i40e_ring *tx_ring,
1525 struct ipv6hdr *this_ipv6_hdr;
1526 unsigned int this_tcp_hdrlen;
1527 struct iphdr *this_ip_hdr;
1528 u32 network_hdr_len;
1530 struct udphdr *oudph;
1534 if (skb->encapsulation) {
1535 switch (ip_hdr(skb)->protocol) {
1537 oudph = udp_hdr(skb);
1539 l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1540 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1545 network_hdr_len = skb_inner_network_header_len(skb);
1546 this_ip_hdr = inner_ip_hdr(skb);
1547 this_ipv6_hdr = inner_ipv6_hdr(skb);
1548 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1550 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1551 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1552 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1553 ip_hdr(skb)->check = 0;
1556 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1558 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1559 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1560 if (*tx_flags & I40E_TX_FLAGS_TSO)
1561 ip_hdr(skb)->check = 0;
1564 /* Now set the ctx descriptor fields */
1565 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1566 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1568 ((skb_inner_network_offset(skb) -
1569 skb_transport_offset(skb)) >> 1) <<
1570 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1571 if (this_ip_hdr->version == 6) {
1572 *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1573 *tx_flags |= I40E_TX_FLAGS_IPV6;
1576 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1577 (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING) &&
1578 (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1579 oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1581 (skb->len - skb_transport_offset(skb)),
1583 *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1586 network_hdr_len = skb_network_header_len(skb);
1587 this_ip_hdr = ip_hdr(skb);
1588 this_ipv6_hdr = ipv6_hdr(skb);
1589 this_tcp_hdrlen = tcp_hdrlen(skb);
1592 /* Enable IP checksum offloads */
1593 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1594 l4_hdr = this_ip_hdr->protocol;
1595 /* the stack computes the IP header already, the only time we
1596 * need the hardware to recompute it is in the case of TSO.
1598 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1599 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1600 this_ip_hdr->check = 0;
1602 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1604 /* Now set the td_offset for IP header length */
1605 *td_offset = (network_hdr_len >> 2) <<
1606 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1607 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1608 l4_hdr = this_ipv6_hdr->nexthdr;
1609 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1610 /* Now set the td_offset for IP header length */
1611 *td_offset = (network_hdr_len >> 2) <<
1612 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1614 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1615 *td_offset |= (skb_network_offset(skb) >> 1) <<
1616 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1618 /* Enable L4 checksum offloads */
1621 /* enable checksum offloads */
1622 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1623 *td_offset |= (this_tcp_hdrlen >> 2) <<
1624 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1627 /* enable SCTP checksum offload */
1628 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1629 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1630 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1633 /* enable UDP checksum offload */
1634 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1635 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1636 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1644 * i40e_create_tx_ctx Build the Tx context descriptor
1645 * @tx_ring: ring to create the descriptor on
1646 * @cd_type_cmd_tso_mss: Quad Word 1
1647 * @cd_tunneling: Quad Word 0 - bits 0-31
1648 * @cd_l2tag2: Quad Word 0 - bits 32-63
1650 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1651 const u64 cd_type_cmd_tso_mss,
1652 const u32 cd_tunneling, const u32 cd_l2tag2)
1654 struct i40e_tx_context_desc *context_desc;
1655 int i = tx_ring->next_to_use;
1657 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1658 !cd_tunneling && !cd_l2tag2)
1661 /* grab the next descriptor */
1662 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1665 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1667 /* cpu_to_le32 and assign to struct fields */
1668 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1669 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1670 context_desc->rsvd = cpu_to_le16(0);
1671 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1675 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1677 * @tx_flags: collected send information
1679 * Note: Our HW can't scatter-gather more than 8 fragments to build
1680 * a packet on the wire and so we need to figure out the cases where we
1681 * need to linearize the skb.
1683 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1685 struct skb_frag_struct *frag;
1686 bool linearize = false;
1687 unsigned int size = 0;
1691 num_frags = skb_shinfo(skb)->nr_frags;
1692 gso_segs = skb_shinfo(skb)->gso_segs;
1694 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1697 if (num_frags < (I40E_MAX_BUFFER_TXD))
1698 goto linearize_chk_done;
1699 /* try the simple math, if we have too many frags per segment */
1700 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1701 I40E_MAX_BUFFER_TXD) {
1703 goto linearize_chk_done;
1705 frag = &skb_shinfo(skb)->frags[0];
1706 /* we might still have more fragments per segment */
1708 size += skb_frag_size(frag);
1710 if ((size >= skb_shinfo(skb)->gso_size) &&
1711 (j < I40E_MAX_BUFFER_TXD)) {
1712 size = (size % skb_shinfo(skb)->gso_size);
1715 if (j == I40E_MAX_BUFFER_TXD) {
1720 } while (num_frags);
1722 if (num_frags >= I40E_MAX_BUFFER_TXD)
1731 * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1732 * @tx_ring: the ring to be checked
1733 * @size: the size buffer we want to assure is available
1735 * Returns -EBUSY if a stop is needed, else 0
1737 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1739 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1740 /* Memory barrier before checking head and tail */
1743 /* Check again in a case another CPU has just made room available. */
1744 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1747 /* A reprieve! - use start_queue because it doesn't call schedule */
1748 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1749 ++tx_ring->tx_stats.restart_queue;
1754 * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1755 * @tx_ring: the ring to be checked
1756 * @size: the size buffer we want to assure is available
1758 * Returns 0 if stop is not needed
1760 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1762 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1764 return __i40evf_maybe_stop_tx(tx_ring, size);
1768 * i40evf_tx_map - Build the Tx descriptor
1769 * @tx_ring: ring to send buffer on
1771 * @first: first buffer info buffer to use
1772 * @tx_flags: collected send information
1773 * @hdr_len: size of the packet header
1774 * @td_cmd: the command field in the descriptor
1775 * @td_offset: offset for checksum or crc
1777 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1778 struct i40e_tx_buffer *first, u32 tx_flags,
1779 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1781 unsigned int data_len = skb->data_len;
1782 unsigned int size = skb_headlen(skb);
1783 struct skb_frag_struct *frag;
1784 struct i40e_tx_buffer *tx_bi;
1785 struct i40e_tx_desc *tx_desc;
1786 u16 i = tx_ring->next_to_use;
1791 bool tail_bump = true;
1794 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1795 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1796 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1797 I40E_TX_FLAGS_VLAN_SHIFT;
1800 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1801 gso_segs = skb_shinfo(skb)->gso_segs;
1805 /* multiply data chunks by size of headers */
1806 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1807 first->gso_segs = gso_segs;
1809 first->tx_flags = tx_flags;
1811 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1813 tx_desc = I40E_TX_DESC(tx_ring, i);
1816 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1817 if (dma_mapping_error(tx_ring->dev, dma))
1820 /* record length, and DMA address */
1821 dma_unmap_len_set(tx_bi, len, size);
1822 dma_unmap_addr_set(tx_bi, dma, dma);
1824 tx_desc->buffer_addr = cpu_to_le64(dma);
1826 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1827 tx_desc->cmd_type_offset_bsz =
1828 build_ctob(td_cmd, td_offset,
1829 I40E_MAX_DATA_PER_TXD, td_tag);
1835 if (i == tx_ring->count) {
1836 tx_desc = I40E_TX_DESC(tx_ring, 0);
1840 dma += I40E_MAX_DATA_PER_TXD;
1841 size -= I40E_MAX_DATA_PER_TXD;
1843 tx_desc->buffer_addr = cpu_to_le64(dma);
1846 if (likely(!data_len))
1849 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1856 if (i == tx_ring->count) {
1857 tx_desc = I40E_TX_DESC(tx_ring, 0);
1861 size = skb_frag_size(frag);
1864 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1867 tx_bi = &tx_ring->tx_bi[i];
1870 /* set next_to_watch value indicating a packet is present */
1871 first->next_to_watch = tx_desc;
1874 if (i == tx_ring->count)
1877 tx_ring->next_to_use = i;
1879 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1880 tx_ring->queue_index),
1882 i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1884 /* Algorithm to optimize tail and RS bit setting:
1885 * if xmit_more is supported
1886 * if xmit_more is true
1887 * do not update tail and do not mark RS bit.
1888 * if xmit_more is false and last xmit_more was false
1889 * if every packet spanned less than 4 desc
1890 * then set RS bit on 4th packet and update tail
1893 * update tail and set RS bit on every packet.
1894 * if xmit_more is false and last_xmit_more was true
1895 * update tail and set RS bit.
1897 * Optimization: wmb to be issued only in case of tail update.
1898 * Also optimize the Descriptor WB path for RS bit with the same
1901 * Note: If there are less than 4 packets
1902 * pending and interrupts were disabled the service task will
1903 * trigger a force WB.
1905 if (skb->xmit_more &&
1906 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1907 tx_ring->queue_index))) {
1908 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1910 } else if (!skb->xmit_more &&
1911 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1912 tx_ring->queue_index)) &&
1913 (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
1914 (tx_ring->packet_stride < WB_STRIDE) &&
1915 (desc_count < WB_STRIDE)) {
1916 tx_ring->packet_stride++;
1918 tx_ring->packet_stride = 0;
1919 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1923 tx_ring->packet_stride = 0;
1925 tx_desc->cmd_type_offset_bsz =
1926 build_ctob(td_cmd, td_offset, size, td_tag) |
1927 cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
1928 I40E_TX_DESC_CMD_EOP) <<
1929 I40E_TXD_QW1_CMD_SHIFT);
1931 /* notify HW of packet */
1933 prefetchw(tx_desc + 1);
1936 /* Force memory writes to complete before letting h/w
1937 * know there are new descriptors to fetch. (Only
1938 * applicable for weak-ordered memory model archs,
1942 writel(i, tx_ring->tail);
1948 dev_info(tx_ring->dev, "TX DMA map failed\n");
1950 /* clear dma mappings for failed tx_bi map */
1952 tx_bi = &tx_ring->tx_bi[i];
1953 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1961 tx_ring->next_to_use = i;
1965 * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1967 * @tx_ring: ring to send buffer on
1969 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1970 * there is not enough descriptors available in this ring since we need at least
1973 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1974 struct i40e_ring *tx_ring)
1979 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1980 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1981 * + 4 desc gap to avoid the cache line where head is,
1982 * + 1 desc for context descriptor,
1983 * otherwise try next time
1985 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1986 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1988 count += TXD_USE_COUNT(skb_headlen(skb));
1989 if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1990 tx_ring->tx_stats.tx_busy++;
1997 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1999 * @tx_ring: ring to send buffer on
2001 * Returns NETDEV_TX_OK if sent, else an error code
2003 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2004 struct i40e_ring *tx_ring)
2006 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2007 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2008 struct i40e_tx_buffer *first;
2016 /* prefetch the data, we'll need it later */
2017 prefetch(skb->data);
2019 if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
2020 return NETDEV_TX_BUSY;
2022 /* prepare the xmit flags */
2023 if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2026 /* obtain protocol of skb */
2027 protocol = vlan_get_protocol(skb);
2029 /* record the location of the first descriptor for this packet */
2030 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2032 /* setup IPv4/IPv6 offloads */
2033 if (protocol == htons(ETH_P_IP))
2034 tx_flags |= I40E_TX_FLAGS_IPV4;
2035 else if (protocol == htons(ETH_P_IPV6))
2036 tx_flags |= I40E_TX_FLAGS_IPV6;
2038 tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss);
2043 tx_flags |= I40E_TX_FLAGS_TSO;
2045 if (i40e_chk_linearize(skb, tx_flags)) {
2046 if (skb_linearize(skb))
2048 tx_ring->tx_stats.tx_linearize++;
2050 skb_tx_timestamp(skb);
2052 /* always enable CRC insertion offload */
2053 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2055 /* Always offload the checksum, since it's in the data descriptor */
2056 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2057 tx_flags |= I40E_TX_FLAGS_CSUM;
2059 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2060 tx_ring, &cd_tunneling);
2063 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2064 cd_tunneling, cd_l2tag2);
2066 i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2069 return NETDEV_TX_OK;
2072 dev_kfree_skb_any(skb);
2073 return NETDEV_TX_OK;
2077 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2079 * @netdev: network interface device structure
2081 * Returns NETDEV_TX_OK if sent, else an error code
2083 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2085 struct i40evf_adapter *adapter = netdev_priv(netdev);
2086 struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2088 /* hardware can't handle really short frames, hardware padding works
2091 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2092 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2093 return NETDEV_TX_OK;
2094 skb->len = I40E_MIN_TX_LEN;
2095 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2098 return i40e_xmit_frame_ring(skb, tx_ring);