drivers/net/ethernet/intel/igb/e1000_i210.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_I210_H_
  29 #define _E1000_I210_H_
  30
  31 extern s32 igb_update_flash_i210(struct e1000_hw *hw);
  32 extern s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw);
  33 extern s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw);
  34 extern s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset,
  35                               u16 words, u16 *data);
  36 extern s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset,
  37                              u16 words, u16 *data);
  38 extern s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
  39 extern void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
  40 extern s32 igb_acquire_nvm_i210(struct e1000_hw *hw);
  41 extern void igb_release_nvm_i210(struct e1000_hw *hw);
  42 extern s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data);
  43 extern s32 igb_read_invm_version(struct e1000_hw *hw,
  44                                  struct e1000_fw_version *invm_ver);
  45 extern s32 igb_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
  46                               u16 *data);
  47 extern s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
  48                                u16 data);
  49 extern s32 igb_init_nvm_params_i210(struct e1000_hw *hw);
  50 extern bool igb_get_flash_presence_i210(struct e1000_hw *hw);
  51
  52 #define E1000_STM_OPCODE                0xDB00
  53 #define E1000_EEPROM_FLASH_SIZE_WORD    0x11
  54
  55 #define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \
  56         (u8)((invm_dword) & 0x7)
  57 #define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \
  58         (u8)(((invm_dword) & 0x0000FE00) >> 9)
  59 #define INVM_DWORD_TO_WORD_DATA(invm_dword) \
  60         (u16)(((invm_dword) & 0xFFFF0000) >> 16)
  61
  62 enum E1000_INVM_STRUCTURE_TYPE {
  63         E1000_INVM_UNINITIALIZED_STRUCTURE              = 0x00,
  64         E1000_INVM_WORD_AUTOLOAD_STRUCTURE              = 0x01,
  65         E1000_INVM_CSR_AUTOLOAD_STRUCTURE               = 0x02,
  66         E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE      = 0x03,
  67         E1000_INVM_RSA_KEY_SHA256_STRUCTURE             = 0x04,
  68         E1000_INVM_INVALIDATED_STRUCTURE                = 0x0F,
  69 };
  70
  71 #define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS   8
  72 #define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS     1
  73 #define E1000_INVM_ULT_BYTES_SIZE                       8
  74 #define E1000_INVM_RECORD_SIZE_IN_BYTES                 4
  75 #define E1000_INVM_VER_FIELD_ONE                        0x1FF8
  76 #define E1000_INVM_VER_FIELD_TWO                        0x7FE000
  77 #define E1000_INVM_IMGTYPE_FIELD                        0x1F800000
  78
  79 #define E1000_INVM_MAJOR_MASK           0x3F0
  80 #define E1000_INVM_MINOR_MASK           0xF
  81 #define E1000_INVM_MAJOR_SHIFT          4
  82
  83 #define ID_LED_DEFAULT_I210             ((ID_LED_OFF1_ON2  << 8) | \
  84                                          (ID_LED_DEF1_DEF2 <<  4) | \
  85                                          (ID_LED_OFF1_OFF2))
  86 #define ID_LED_DEFAULT_I210_SERDES      ((ID_LED_DEF1_DEF2 << 8) | \
  87                                          (ID_LED_DEF1_DEF2 <<  4) | \
  88                                          (ID_LED_OFF1_ON2))
  89
  90 /* NVM offset defaults for i211 device */
  91 #define NVM_INIT_CTRL_2_DEFAULT_I211    0X7243
  92 #define NVM_INIT_CTRL_4_DEFAULT_I211    0x00C1
  93 #define NVM_LED_1_CFG_DEFAULT_I211      0x0184
  94 #define NVM_LED_0_2_CFG_DEFAULT_I211    0x200C
  95
  96 #endif