drivers/net/ethernet/intel/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29
  30 #include <linux/module.h>
  31 #include <linux/types.h>
  32 #include <linux/init.h>
  33 #include <linux/bitops.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/ipv6.h>
  38 #include <linux/slab.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/net_tstamp.h>
  42 #include <linux/mii.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/pci.h>
  47 #include <linux/pci-aspm.h>
  48 #include <linux/delay.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/ip.h>
  51 #include <linux/tcp.h>
  52 #include <linux/sctp.h>
  53 #include <linux/if_ether.h>
  54 #include <linux/aer.h>
  55 #include <linux/prefetch.h>
  56 #include <linux/pm_runtime.h>
  57 #ifdef CONFIG_IGB_DCA
  58 #include <linux/dca.h>
  59 #endif
  60 #include <linux/i2c.h>
  61 #include "igb.h"
  62
  63 #define MAJ 5
  64 #define MIN 0
  65 #define BUILD 5
  66 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  67 __stringify(BUILD) "-k"
  68 char igb_driver_name[] = "igb";
  69 char igb_driver_version[] = DRV_VERSION;
  70 static const char igb_driver_string[] =
  71                                 "Intel(R) Gigabit Ethernet Network Driver";
  72 static const char igb_copyright[] =
  73                                 "Copyright (c) 2007-2013 Intel Corporation.";
  74
  75 static const struct e1000_info *igb_info_tbl[] = {
  76         [board_82575] = &e1000_82575_info,
  77 };
  78
  79 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
  80         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
  81         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
  82         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
  83         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
  84         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
  85         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
  86         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
  87         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
  88         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
  89         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
  90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
  91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
  92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
  93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
  94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
  95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
  96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
  97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
  98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
  99         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
 100         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
 101         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
 102         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
 103         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
 104         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
 105         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
 106         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
 107         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
 108         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
 109         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
 110         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
 111         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
 112         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
 113         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
 114         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
 115         /* required last entry */
 116         {0, }
 117 };
 118
 119 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
 120
 121 void igb_reset(struct igb_adapter *);
 122 static int igb_setup_all_tx_resources(struct igb_adapter *);
 123 static int igb_setup_all_rx_resources(struct igb_adapter *);
 124 static void igb_free_all_tx_resources(struct igb_adapter *);
 125 static void igb_free_all_rx_resources(struct igb_adapter *);
 126 static void igb_setup_mrqc(struct igb_adapter *);
 127 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
 128 static void igb_remove(struct pci_dev *pdev);
 129 static int igb_sw_init(struct igb_adapter *);
 130 static int igb_open(struct net_device *);
 131 static int igb_close(struct net_device *);
 132 static void igb_configure(struct igb_adapter *);
 133 static void igb_configure_tx(struct igb_adapter *);
 134 static void igb_configure_rx(struct igb_adapter *);
 135 static void igb_clean_all_tx_rings(struct igb_adapter *);
 136 static void igb_clean_all_rx_rings(struct igb_adapter *);
 137 static void igb_clean_tx_ring(struct igb_ring *);
 138 static void igb_clean_rx_ring(struct igb_ring *);
 139 static void igb_set_rx_mode(struct net_device *);
 140 static void igb_update_phy_info(unsigned long);
 141 static void igb_watchdog(unsigned long);
 142 static void igb_watchdog_task(struct work_struct *);
 143 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
 144 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
 145                                                  struct rtnl_link_stats64 *stats);
 146 static int igb_change_mtu(struct net_device *, int);
 147 static int igb_set_mac(struct net_device *, void *);
 148 static void igb_set_uta(struct igb_adapter *adapter);
 149 static irqreturn_t igb_intr(int irq, void *);
 150 static irqreturn_t igb_intr_msi(int irq, void *);
 151 static irqreturn_t igb_msix_other(int irq, void *);
 152 static irqreturn_t igb_msix_ring(int irq, void *);
 153 #ifdef CONFIG_IGB_DCA
 154 static void igb_update_dca(struct igb_q_vector *);
 155 static void igb_setup_dca(struct igb_adapter *);
 156 #endif /* CONFIG_IGB_DCA */
 157 static int igb_poll(struct napi_struct *, int);
 158 static bool igb_clean_tx_irq(struct igb_q_vector *);
 159 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
 160 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 161 static void igb_tx_timeout(struct net_device *);
 162 static void igb_reset_task(struct work_struct *);
 163 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
 164 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
 165 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
 166 static void igb_restore_vlan(struct igb_adapter *);
 167 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
 168 static void igb_ping_all_vfs(struct igb_adapter *);
 169 static void igb_msg_task(struct igb_adapter *);
 170 static void igb_vmm_control(struct igb_adapter *);
 171 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
 172 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 173 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
 174 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 175                                int vf, u16 vlan, u8 qos);
 176 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
 177 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
 178                                    bool setting);
 179 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
 180                                  struct ifla_vf_info *ivi);
 181 static void igb_check_vf_rate_limit(struct igb_adapter *);
 182
 183 #ifdef CONFIG_PCI_IOV
 184 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
 185 #endif
 186
 187 #ifdef CONFIG_PM
 188 #ifdef CONFIG_PM_SLEEP
 189 static int igb_suspend(struct device *);
 190 #endif
 191 static int igb_resume(struct device *);
 192 #ifdef CONFIG_PM_RUNTIME
 193 static int igb_runtime_suspend(struct device *dev);
 194 static int igb_runtime_resume(struct device *dev);
 195 static int igb_runtime_idle(struct device *dev);
 196 #endif
 197 static const struct dev_pm_ops igb_pm_ops = {
 198         SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
 199         SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
 200                         igb_runtime_idle)
 201 };
 202 #endif
 203 static void igb_shutdown(struct pci_dev *);
 204 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
 205 #ifdef CONFIG_IGB_DCA
 206 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 207 static struct notifier_block dca_notifier = {
 208         .notifier_call  = igb_notify_dca,
 209         .next           = NULL,
 210         .priority       = 0
 211 };
 212 #endif
 213 #ifdef CONFIG_NET_POLL_CONTROLLER
 214 /* for netdump / net console */
 215 static void igb_netpoll(struct net_device *);
 216 #endif
 217 #ifdef CONFIG_PCI_IOV
 218 static unsigned int max_vfs = 0;
 219 module_param(max_vfs, uint, 0);
 220 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 221                  "per physical function");
 222 #endif /* CONFIG_PCI_IOV */
 223
 224 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 225                      pci_channel_state_t);
 226 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 227 static void igb_io_resume(struct pci_dev *);
 228
 229 static const struct pci_error_handlers igb_err_handler = {
 230         .error_detected = igb_io_error_detected,
 231         .slot_reset = igb_io_slot_reset,
 232         .resume = igb_io_resume,
 233 };
 234
 235 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
 236
 237 static struct pci_driver igb_driver = {
 238         .name     = igb_driver_name,
 239         .id_table = igb_pci_tbl,
 240         .probe    = igb_probe,
 241         .remove   = igb_remove,
 242 #ifdef CONFIG_PM
 243         .driver.pm = &igb_pm_ops,
 244 #endif
 245         .shutdown = igb_shutdown,
 246         .sriov_configure = igb_pci_sriov_configure,
 247         .err_handler = &igb_err_handler
 248 };
 249
 250 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 251 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 252 MODULE_LICENSE("GPL");
 253 MODULE_VERSION(DRV_VERSION);
 254
 255 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
 256 static int debug = -1;
 257 module_param(debug, int, 0);
 258 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 259
 260 struct igb_reg_info {
 261         u32 ofs;
 262         char *name;
 263 };
 264
 265 static const struct igb_reg_info igb_reg_info_tbl[] = {
 266
 267         /* General Registers */
 268         {E1000_CTRL, "CTRL"},
 269         {E1000_STATUS, "STATUS"},
 270         {E1000_CTRL_EXT, "CTRL_EXT"},
 271
 272         /* Interrupt Registers */
 273         {E1000_ICR, "ICR"},
 274
 275         /* RX Registers */
 276         {E1000_RCTL, "RCTL"},
 277         {E1000_RDLEN(0), "RDLEN"},
 278         {E1000_RDH(0), "RDH"},
 279         {E1000_RDT(0), "RDT"},
 280         {E1000_RXDCTL(0), "RXDCTL"},
 281         {E1000_RDBAL(0), "RDBAL"},
 282         {E1000_RDBAH(0), "RDBAH"},
 283
 284         /* TX Registers */
 285         {E1000_TCTL, "TCTL"},
 286         {E1000_TDBAL(0), "TDBAL"},
 287         {E1000_TDBAH(0), "TDBAH"},
 288         {E1000_TDLEN(0), "TDLEN"},
 289         {E1000_TDH(0), "TDH"},
 290         {E1000_TDT(0), "TDT"},
 291         {E1000_TXDCTL(0), "TXDCTL"},
 292         {E1000_TDFH, "TDFH"},
 293         {E1000_TDFT, "TDFT"},
 294         {E1000_TDFHS, "TDFHS"},
 295         {E1000_TDFPC, "TDFPC"},
 296
 297         /* List Terminator */
 298         {}
 299 };
 300
 301 /* igb_regdump - register printout routine */
 302 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
 303 {
 304         int n = 0;
 305         char rname[16];
 306         u32 regs[8];
 307
 308         switch (reginfo->ofs) {
 309         case E1000_RDLEN(0):
 310                 for (n = 0; n < 4; n++)
 311                         regs[n] = rd32(E1000_RDLEN(n));
 312                 break;
 313         case E1000_RDH(0):
 314                 for (n = 0; n < 4; n++)
 315                         regs[n] = rd32(E1000_RDH(n));
 316                 break;
 317         case E1000_RDT(0):
 318                 for (n = 0; n < 4; n++)
 319                         regs[n] = rd32(E1000_RDT(n));
 320                 break;
 321         case E1000_RXDCTL(0):
 322                 for (n = 0; n < 4; n++)
 323                         regs[n] = rd32(E1000_RXDCTL(n));
 324                 break;
 325         case E1000_RDBAL(0):
 326                 for (n = 0; n < 4; n++)
 327                         regs[n] = rd32(E1000_RDBAL(n));
 328                 break;
 329         case E1000_RDBAH(0):
 330                 for (n = 0; n < 4; n++)
 331                         regs[n] = rd32(E1000_RDBAH(n));
 332                 break;
 333         case E1000_TDBAL(0):
 334                 for (n = 0; n < 4; n++)
 335                         regs[n] = rd32(E1000_RDBAL(n));
 336                 break;
 337         case E1000_TDBAH(0):
 338                 for (n = 0; n < 4; n++)
 339                         regs[n] = rd32(E1000_TDBAH(n));
 340                 break;
 341         case E1000_TDLEN(0):
 342                 for (n = 0; n < 4; n++)
 343                         regs[n] = rd32(E1000_TDLEN(n));
 344                 break;
 345         case E1000_TDH(0):
 346                 for (n = 0; n < 4; n++)
 347                         regs[n] = rd32(E1000_TDH(n));
 348                 break;
 349         case E1000_TDT(0):
 350                 for (n = 0; n < 4; n++)
 351                         regs[n] = rd32(E1000_TDT(n));
 352                 break;
 353         case E1000_TXDCTL(0):
 354                 for (n = 0; n < 4; n++)
 355                         regs[n] = rd32(E1000_TXDCTL(n));
 356                 break;
 357         default:
 358                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
 359                 return;
 360         }
 361
 362         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
 363         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
 364                 regs[2], regs[3]);
 365 }
 366
 367 /* igb_dump - Print registers, Tx-rings and Rx-rings */
 368 static void igb_dump(struct igb_adapter *adapter)
 369 {
 370         struct net_device *netdev = adapter->netdev;
 371         struct e1000_hw *hw = &adapter->hw;
 372         struct igb_reg_info *reginfo;
 373         struct igb_ring *tx_ring;
 374         union e1000_adv_tx_desc *tx_desc;
 375         struct my_u0 { u64 a; u64 b; } *u0;
 376         struct igb_ring *rx_ring;
 377         union e1000_adv_rx_desc *rx_desc;
 378         u32 staterr;
 379         u16 i, n;
 380
 381         if (!netif_msg_hw(adapter))
 382                 return;
 383
 384         /* Print netdevice Info */
 385         if (netdev) {
 386                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 387                 pr_info("Device Name     state            trans_start      "
 388                         "last_rx\n");
 389                 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
 390                         netdev->state, netdev->trans_start, netdev->last_rx);
 391         }
 392
 393         /* Print Registers */
 394         dev_info(&adapter->pdev->dev, "Register Dump\n");
 395         pr_info(" Register Name   Value\n");
 396         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
 397              reginfo->name; reginfo++) {
 398                 igb_regdump(hw, reginfo);
 399         }
 400
 401         /* Print TX Ring Summary */
 402         if (!netdev || !netif_running(netdev))
 403                 goto exit;
 404
 405         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 406         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 407         for (n = 0; n < adapter->num_tx_queues; n++) {
 408                 struct igb_tx_buffer *buffer_info;
 409                 tx_ring = adapter->tx_ring[n];
 410                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 411                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 412                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
 413                         (u64)dma_unmap_addr(buffer_info, dma),
 414                         dma_unmap_len(buffer_info, len),
 415                         buffer_info->next_to_watch,
 416                         (u64)buffer_info->time_stamp);
 417         }
 418
 419         /* Print TX Rings */
 420         if (!netif_msg_tx_done(adapter))
 421                 goto rx_ring_summary;
 422
 423         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 424
 425         /* Transmit Descriptor Formats
 426          *
 427          * Advanced Transmit Descriptor
 428          *   +--------------------------------------------------------------+
 429          * 0 |         Buffer Address [63:0]                                |
 430          *   +--------------------------------------------------------------+
 431          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
 432          *   +--------------------------------------------------------------+
 433          *   63      46 45    40 39 38 36 35 32 31   24             15       0
 434          */
 435
 436         for (n = 0; n < adapter->num_tx_queues; n++) {
 437                 tx_ring = adapter->tx_ring[n];
 438                 pr_info("------------------------------------\n");
 439                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 440                 pr_info("------------------------------------\n");
 441                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] "
 442                         "[bi->dma       ] leng  ntw timestamp        "
 443                         "bi->skb\n");
 444
 445                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 446                         const char *next_desc;
 447                         struct igb_tx_buffer *buffer_info;
 448                         tx_desc = IGB_TX_DESC(tx_ring, i);
 449                         buffer_info = &tx_ring->tx_buffer_info[i];
 450                         u0 = (struct my_u0 *)tx_desc;
 451                         if (i == tx_ring->next_to_use &&
 452                             i == tx_ring->next_to_clean)
 453                                 next_desc = " NTC/U";
 454                         else if (i == tx_ring->next_to_use)
 455                                 next_desc = " NTU";
 456                         else if (i == tx_ring->next_to_clean)
 457                                 next_desc = " NTC";
 458                         else
 459                                 next_desc = "";
 460
 461                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 462                                 " %04X  %p %016llX %p%s\n", i,
 463                                 le64_to_cpu(u0->a),
 464                                 le64_to_cpu(u0->b),
 465                                 (u64)dma_unmap_addr(buffer_info, dma),
 466                                 dma_unmap_len(buffer_info, len),
 467                                 buffer_info->next_to_watch,
 468                                 (u64)buffer_info->time_stamp,
 469                                 buffer_info->skb, next_desc);
 470
 471                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
 472                                 print_hex_dump(KERN_INFO, "",
 473                                         DUMP_PREFIX_ADDRESS,
 474                                         16, 1, buffer_info->skb->data,
 475                                         dma_unmap_len(buffer_info, len),
 476                                         true);
 477                 }
 478         }
 479
 480         /* Print RX Rings Summary */
 481 rx_ring_summary:
 482         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 483         pr_info("Queue [NTU] [NTC]\n");
 484         for (n = 0; n < adapter->num_rx_queues; n++) {
 485                 rx_ring = adapter->rx_ring[n];
 486                 pr_info(" %5d %5X %5X\n",
 487                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 488         }
 489
 490         /* Print RX Rings */
 491         if (!netif_msg_rx_status(adapter))
 492                 goto exit;
 493
 494         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 495
 496         /* Advanced Receive Descriptor (Read) Format
 497          *    63                                           1        0
 498          *    +-----------------------------------------------------+
 499          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 500          *    +----------------------------------------------+------+
 501          *  8 |       Header Buffer Address [63:1]           |  DD  |
 502          *    +-----------------------------------------------------+
 503          *
 504          *
 505          * Advanced Receive Descriptor (Write-Back) Format
 506          *
 507          *   63       48 47    32 31  30      21 20 17 16   4 3     0
 508          *   +------------------------------------------------------+
 509          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 510          *   | Checksum   Ident  |   |           |    | Type | Type |
 511          *   +------------------------------------------------------+
 512          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 513          *   +------------------------------------------------------+
 514          *   63       48 47    32 31            20 19               0
 515          */
 516
 517         for (n = 0; n < adapter->num_rx_queues; n++) {
 518                 rx_ring = adapter->rx_ring[n];
 519                 pr_info("------------------------------------\n");
 520                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 521                 pr_info("------------------------------------\n");
 522                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] "
 523                         "[bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
 524                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] -----"
 525                         "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
 526
 527                 for (i = 0; i < rx_ring->count; i++) {
 528                         const char *next_desc;
 529                         struct igb_rx_buffer *buffer_info;
 530                         buffer_info = &rx_ring->rx_buffer_info[i];
 531                         rx_desc = IGB_RX_DESC(rx_ring, i);
 532                         u0 = (struct my_u0 *)rx_desc;
 533                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 534
 535                         if (i == rx_ring->next_to_use)
 536                                 next_desc = " NTU";
 537                         else if (i == rx_ring->next_to_clean)
 538                                 next_desc = " NTC";
 539                         else
 540                                 next_desc = "";
 541
 542                         if (staterr & E1000_RXD_STAT_DD) {
 543                                 /* Descriptor Done */
 544                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
 545                                         "RWB", i,
 546                                         le64_to_cpu(u0->a),
 547                                         le64_to_cpu(u0->b),
 548                                         next_desc);
 549                         } else {
 550                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
 551                                         "R  ", i,
 552                                         le64_to_cpu(u0->a),
 553                                         le64_to_cpu(u0->b),
 554                                         (u64)buffer_info->dma,
 555                                         next_desc);
 556
 557                                 if (netif_msg_pktdata(adapter) &&
 558                                     buffer_info->dma && buffer_info->page) {
 559                                         print_hex_dump(KERN_INFO, "",
 560                                           DUMP_PREFIX_ADDRESS,
 561                                           16, 1,
 562                                           page_address(buffer_info->page) +
 563                                                       buffer_info->page_offset,
 564                                           IGB_RX_BUFSZ, true);
 565                                 }
 566                         }
 567                 }
 568         }
 569
 570 exit:
 571         return;
 572 }
 573
 574 /**
 575  *  igb_get_i2c_data - Reads the I2C SDA data bit
 576  *  @hw: pointer to hardware structure
 577  *  @i2cctl: Current value of I2CCTL register
 578  *
 579  *  Returns the I2C data bit value
 580  **/
 581 static int igb_get_i2c_data(void *data)
 582 {
 583         struct igb_adapter *adapter = (struct igb_adapter *)data;
 584         struct e1000_hw *hw = &adapter->hw;
 585         s32 i2cctl = rd32(E1000_I2CPARAMS);
 586
 587         return ((i2cctl & E1000_I2C_DATA_IN) != 0);
 588 }
 589
 590 /**
 591  *  igb_set_i2c_data - Sets the I2C data bit
 592  *  @data: pointer to hardware structure
 593  *  @state: I2C data value (0 or 1) to set
 594  *
 595  *  Sets the I2C data bit
 596  **/
 597 static void igb_set_i2c_data(void *data, int state)
 598 {
 599         struct igb_adapter *adapter = (struct igb_adapter *)data;
 600         struct e1000_hw *hw = &adapter->hw;
 601         s32 i2cctl = rd32(E1000_I2CPARAMS);
 602
 603         if (state)
 604                 i2cctl |= E1000_I2C_DATA_OUT;
 605         else
 606                 i2cctl &= ~E1000_I2C_DATA_OUT;
 607
 608         i2cctl &= ~E1000_I2C_DATA_OE_N;
 609         i2cctl |= E1000_I2C_CLK_OE_N;
 610         wr32(E1000_I2CPARAMS, i2cctl);
 611         wrfl();
 612
 613 }
 614
 615 /**
 616  *  igb_set_i2c_clk - Sets the I2C SCL clock
 617  *  @data: pointer to hardware structure
 618  *  @state: state to set clock
 619  *
 620  *  Sets the I2C clock line to state
 621  **/
 622 static void igb_set_i2c_clk(void *data, int state)
 623 {
 624         struct igb_adapter *adapter = (struct igb_adapter *)data;
 625         struct e1000_hw *hw = &adapter->hw;
 626         s32 i2cctl = rd32(E1000_I2CPARAMS);
 627
 628         if (state) {
 629                 i2cctl |= E1000_I2C_CLK_OUT;
 630                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 631         } else {
 632                 i2cctl &= ~E1000_I2C_CLK_OUT;
 633                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 634         }
 635         wr32(E1000_I2CPARAMS, i2cctl);
 636         wrfl();
 637 }
 638
 639 /**
 640  *  igb_get_i2c_clk - Gets the I2C SCL clock state
 641  *  @data: pointer to hardware structure
 642  *
 643  *  Gets the I2C clock state
 644  **/
 645 static int igb_get_i2c_clk(void *data)
 646 {
 647         struct igb_adapter *adapter = (struct igb_adapter *)data;
 648         struct e1000_hw *hw = &adapter->hw;
 649         s32 i2cctl = rd32(E1000_I2CPARAMS);
 650
 651         return ((i2cctl & E1000_I2C_CLK_IN) != 0);
 652 }
 653
 654 static const struct i2c_algo_bit_data igb_i2c_algo = {
 655         .setsda         = igb_set_i2c_data,
 656         .setscl         = igb_set_i2c_clk,
 657         .getsda         = igb_get_i2c_data,
 658         .getscl         = igb_get_i2c_clk,
 659         .udelay         = 5,
 660         .timeout        = 20,
 661 };
 662
 663 /**
 664  *  igb_get_hw_dev - return device
 665  *  @hw: pointer to hardware structure
 666  *
 667  *  used by hardware layer to print debugging information
 668  **/
 669 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
 670 {
 671         struct igb_adapter *adapter = hw->back;
 672         return adapter->netdev;
 673 }
 674
 675 /**
 676  *  igb_init_module - Driver Registration Routine
 677  *
 678  *  igb_init_module is the first routine called when the driver is
 679  *  loaded. All it does is register with the PCI subsystem.
 680  **/
 681 static int __init igb_init_module(void)
 682 {
 683         int ret;
 684         pr_info("%s - version %s\n",
 685                igb_driver_string, igb_driver_version);
 686
 687         pr_info("%s\n", igb_copyright);
 688
 689 #ifdef CONFIG_IGB_DCA
 690         dca_register_notify(&dca_notifier);
 691 #endif
 692         ret = pci_register_driver(&igb_driver);
 693         return ret;
 694 }
 695
 696 module_init(igb_init_module);
 697
 698 /**
 699  *  igb_exit_module - Driver Exit Cleanup Routine
 700  *
 701  *  igb_exit_module is called just before the driver is removed
 702  *  from memory.
 703  **/
 704 static void __exit igb_exit_module(void)
 705 {
 706 #ifdef CONFIG_IGB_DCA
 707         dca_unregister_notify(&dca_notifier);
 708 #endif
 709         pci_unregister_driver(&igb_driver);
 710 }
 711
 712 module_exit(igb_exit_module);
 713
 714 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 715 /**
 716  *  igb_cache_ring_register - Descriptor ring to register mapping
 717  *  @adapter: board private structure to initialize
 718  *
 719  *  Once we know the feature-set enabled for the device, we'll cache
 720  *  the register offset the descriptor ring is assigned to.
 721  **/
 722 static void igb_cache_ring_register(struct igb_adapter *adapter)
 723 {
 724         int i = 0, j = 0;
 725         u32 rbase_offset = adapter->vfs_allocated_count;
 726
 727         switch (adapter->hw.mac.type) {
 728         case e1000_82576:
 729                 /* The queues are allocated for virtualization such that VF 0
 730                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 731                  * In order to avoid collision we start at the first free queue
 732                  * and continue consuming queues in the same sequence
 733                  */
 734                 if (adapter->vfs_allocated_count) {
 735                         for (; i < adapter->rss_queues; i++)
 736                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
 737                                                                Q_IDX_82576(i);
 738                 }
 739         case e1000_82575:
 740         case e1000_82580:
 741         case e1000_i350:
 742         case e1000_i354:
 743         case e1000_i210:
 744         case e1000_i211:
 745         default:
 746                 for (; i < adapter->num_rx_queues; i++)
 747                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
 748                 for (; j < adapter->num_tx_queues; j++)
 749                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
 750                 break;
 751         }
 752 }
 753
 754 /**
 755  *  igb_write_ivar - configure ivar for given MSI-X vector
 756  *  @hw: pointer to the HW structure
 757  *  @msix_vector: vector number we are allocating to a given ring
 758  *  @index: row index of IVAR register to write within IVAR table
 759  *  @offset: column offset of in IVAR, should be multiple of 8
 760  *
 761  *  This function is intended to handle the writing of the IVAR register
 762  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 763  *  each containing an cause allocation for an Rx and Tx ring, and a
 764  *  variable number of rows depending on the number of queues supported.
 765  **/
 766 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
 767                            int index, int offset)
 768 {
 769         u32 ivar = array_rd32(E1000_IVAR0, index);
 770
 771         /* clear any bits that are currently set */
 772         ivar &= ~((u32)0xFF << offset);
 773
 774         /* write vector and valid bit */
 775         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
 776
 777         array_wr32(E1000_IVAR0, index, ivar);
 778 }
 779
 780 #define IGB_N0_QUEUE -1
 781 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
 782 {
 783         struct igb_adapter *adapter = q_vector->adapter;
 784         struct e1000_hw *hw = &adapter->hw;
 785         int rx_queue = IGB_N0_QUEUE;
 786         int tx_queue = IGB_N0_QUEUE;
 787         u32 msixbm = 0;
 788
 789         if (q_vector->rx.ring)
 790                 rx_queue = q_vector->rx.ring->reg_idx;
 791         if (q_vector->tx.ring)
 792                 tx_queue = q_vector->tx.ring->reg_idx;
 793
 794         switch (hw->mac.type) {
 795         case e1000_82575:
 796                 /* The 82575 assigns vectors using a bitmask, which matches the
 797                  * bitmask for the EICR/EIMS/EIMC registers.  To assign one
 798                  * or more queues to a vector, we write the appropriate bits
 799                  * into the MSIXBM register for that vector.
 800                  */
 801                 if (rx_queue > IGB_N0_QUEUE)
 802                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 803                 if (tx_queue > IGB_N0_QUEUE)
 804                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 805                 if (!adapter->msix_entries && msix_vector == 0)
 806                         msixbm |= E1000_EIMS_OTHER;
 807                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 808                 q_vector->eims_value = msixbm;
 809                 break;
 810         case e1000_82576:
 811                 /* 82576 uses a table that essentially consists of 2 columns
 812                  * with 8 rows.  The ordering is column-major so we use the
 813                  * lower 3 bits as the row index, and the 4th bit as the
 814                  * column offset.
 815                  */
 816                 if (rx_queue > IGB_N0_QUEUE)
 817                         igb_write_ivar(hw, msix_vector,
 818                                        rx_queue & 0x7,
 819                                        (rx_queue & 0x8) << 1);
 820                 if (tx_queue > IGB_N0_QUEUE)
 821                         igb_write_ivar(hw, msix_vector,
 822                                        tx_queue & 0x7,
 823                                        ((tx_queue & 0x8) << 1) + 8);
 824                 q_vector->eims_value = 1 << msix_vector;
 825                 break;
 826         case e1000_82580:
 827         case e1000_i350:
 828         case e1000_i354:
 829         case e1000_i210:
 830         case e1000_i211:
 831                 /* On 82580 and newer adapters the scheme is similar to 82576
 832                  * however instead of ordering column-major we have things
 833                  * ordered row-major.  So we traverse the table by using
 834                  * bit 0 as the column offset, and the remaining bits as the
 835                  * row index.
 836                  */
 837                 if (rx_queue > IGB_N0_QUEUE)
 838                         igb_write_ivar(hw, msix_vector,
 839                                        rx_queue >> 1,
 840                                        (rx_queue & 0x1) << 4);
 841                 if (tx_queue > IGB_N0_QUEUE)
 842                         igb_write_ivar(hw, msix_vector,
 843                                        tx_queue >> 1,
 844                                        ((tx_queue & 0x1) << 4) + 8);
 845                 q_vector->eims_value = 1 << msix_vector;
 846                 break;
 847         default:
 848                 BUG();
 849                 break;
 850         }
 851
 852         /* add q_vector eims value to global eims_enable_mask */
 853         adapter->eims_enable_mask |= q_vector->eims_value;
 854
 855         /* configure q_vector to set itr on first interrupt */
 856         q_vector->set_itr = 1;
 857 }
 858
 859 /**
 860  *  igb_configure_msix - Configure MSI-X hardware
 861  *  @adapter: board private structure to initialize
 862  *
 863  *  igb_configure_msix sets up the hardware to properly
 864  *  generate MSI-X interrupts.
 865  **/
 866 static void igb_configure_msix(struct igb_adapter *adapter)
 867 {
 868         u32 tmp;
 869         int i, vector = 0;
 870         struct e1000_hw *hw = &adapter->hw;
 871
 872         adapter->eims_enable_mask = 0;
 873
 874         /* set vector for other causes, i.e. link changes */
 875         switch (hw->mac.type) {
 876         case e1000_82575:
 877                 tmp = rd32(E1000_CTRL_EXT);
 878                 /* enable MSI-X PBA support*/
 879                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 880
 881                 /* Auto-Mask interrupts upon ICR read. */
 882                 tmp |= E1000_CTRL_EXT_EIAME;
 883                 tmp |= E1000_CTRL_EXT_IRCA;
 884
 885                 wr32(E1000_CTRL_EXT, tmp);
 886
 887                 /* enable msix_other interrupt */
 888                 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
 889                 adapter->eims_other = E1000_EIMS_OTHER;
 890
 891                 break;
 892
 893         case e1000_82576:
 894         case e1000_82580:
 895         case e1000_i350:
 896         case e1000_i354:
 897         case e1000_i210:
 898         case e1000_i211:
 899                 /* Turn on MSI-X capability first, or our settings
 900                  * won't stick.  And it will take days to debug.
 901                  */
 902                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 903                      E1000_GPIE_PBA | E1000_GPIE_EIAME |
 904                      E1000_GPIE_NSICR);
 905
 906                 /* enable msix_other interrupt */
 907                 adapter->eims_other = 1 << vector;
 908                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 909
 910                 wr32(E1000_IVAR_MISC, tmp);
 911                 break;
 912         default:
 913                 /* do nothing, since nothing else supports MSI-X */
 914                 break;
 915         } /* switch (hw->mac.type) */
 916
 917         adapter->eims_enable_mask |= adapter->eims_other;
 918
 919         for (i = 0; i < adapter->num_q_vectors; i++)
 920                 igb_assign_vector(adapter->q_vector[i], vector++);
 921
 922         wrfl();
 923 }
 924
 925 /**
 926  *  igb_request_msix - Initialize MSI-X interrupts
 927  *  @adapter: board private structure to initialize
 928  *
 929  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
 930  *  kernel.
 931  **/
 932 static int igb_request_msix(struct igb_adapter *adapter)
 933 {
 934         struct net_device *netdev = adapter->netdev;
 935         struct e1000_hw *hw = &adapter->hw;
 936         int i, err = 0, vector = 0, free_vector = 0;
 937
 938         err = request_irq(adapter->msix_entries[vector].vector,
 939                           igb_msix_other, 0, netdev->name, adapter);
 940         if (err)
 941                 goto err_out;
 942
 943         for (i = 0; i < adapter->num_q_vectors; i++) {
 944                 struct igb_q_vector *q_vector = adapter->q_vector[i];
 945
 946                 vector++;
 947
 948                 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
 949
 950                 if (q_vector->rx.ring && q_vector->tx.ring)
 951                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
 952                                 q_vector->rx.ring->queue_index);
 953                 else if (q_vector->tx.ring)
 954                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
 955                                 q_vector->tx.ring->queue_index);
 956                 else if (q_vector->rx.ring)
 957                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
 958                                 q_vector->rx.ring->queue_index);
 959                 else
 960                         sprintf(q_vector->name, "%s-unused", netdev->name);
 961
 962                 err = request_irq(adapter->msix_entries[vector].vector,
 963                                   igb_msix_ring, 0, q_vector->name,
 964                                   q_vector);
 965                 if (err)
 966                         goto err_free;
 967         }
 968
 969         igb_configure_msix(adapter);
 970         return 0;
 971
 972 err_free:
 973         /* free already assigned IRQs */
 974         free_irq(adapter->msix_entries[free_vector++].vector, adapter);
 975
 976         vector--;
 977         for (i = 0; i < vector; i++) {
 978                 free_irq(adapter->msix_entries[free_vector++].vector,
 979                          adapter->q_vector[i]);
 980         }
 981 err_out:
 982         return err;
 983 }
 984
 985 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 986 {
 987         if (adapter->msix_entries) {
 988                 pci_disable_msix(adapter->pdev);
 989                 kfree(adapter->msix_entries);
 990                 adapter->msix_entries = NULL;
 991         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
 992                 pci_disable_msi(adapter->pdev);
 993         }
 994 }
 995
 996 /**
 997  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
 998  *  @adapter: board private structure to initialize
 999  *  @v_idx: Index of vector to be freed
1000  *
1001  *  This function frees the memory allocated to the q_vector.  In addition if
1002  *  NAPI is enabled it will delete any references to the NAPI struct prior
1003  *  to freeing the q_vector.
1004  **/
1005 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006 {
1007         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
1009         if (q_vector->tx.ring)
1010                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1011
1012         if (q_vector->rx.ring)
1013                 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1014
1015         adapter->q_vector[v_idx] = NULL;
1016         netif_napi_del(&q_vector->napi);
1017
1018         /* igb_get_stats64() might access the rings on this vector,
1019          * we must wait a grace period before freeing it.
1020          */
1021         kfree_rcu(q_vector, rcu);
1022 }
1023
1024 /**
1025  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1026  *  @adapter: board private structure to initialize
1027  *
1028  *  This function frees the memory allocated to the q_vectors.  In addition if
1029  *  NAPI is enabled it will delete any references to the NAPI struct prior
1030  *  to freeing the q_vector.
1031  **/
1032 static void igb_free_q_vectors(struct igb_adapter *adapter)
1033 {
1034         int v_idx = adapter->num_q_vectors;
1035
1036         adapter->num_tx_queues = 0;
1037         adapter->num_rx_queues = 0;
1038         adapter->num_q_vectors = 0;
1039
1040         while (v_idx--)
1041                 igb_free_q_vector(adapter, v_idx);
1042 }
1043
1044 /**
1045  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1046  *  @adapter: board private structure to initialize
1047  *
1048  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1049  *  MSI-X interrupts allocated.
1050  */
1051 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1052 {
1053         igb_free_q_vectors(adapter);
1054         igb_reset_interrupt_capability(adapter);
1055 }
1056
1057 /**
1058  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1059  *  @adapter: board private structure to initialize
1060  *  @msix: boolean value of MSIX capability
1061  *
1062  *  Attempt to configure interrupts using the best available
1063  *  capabilities of the hardware and kernel.
1064  **/
1065 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1066 {
1067         int err;
1068         int numvecs, i;
1069
1070         if (!msix)
1071                 goto msi_only;
1072
1073         /* Number of supported queues. */
1074         adapter->num_rx_queues = adapter->rss_queues;
1075         if (adapter->vfs_allocated_count)
1076                 adapter->num_tx_queues = 1;
1077         else
1078                 adapter->num_tx_queues = adapter->rss_queues;
1079
1080         /* start with one vector for every Rx queue */
1081         numvecs = adapter->num_rx_queues;
1082
1083         /* if Tx handler is separate add 1 for every Tx queue */
1084         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1085                 numvecs += adapter->num_tx_queues;
1086
1087         /* store the number of vectors reserved for queues */
1088         adapter->num_q_vectors = numvecs;
1089
1090         /* add 1 vector for link status interrupts */
1091         numvecs++;
1092         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1093                                         GFP_KERNEL);
1094
1095         if (!adapter->msix_entries)
1096                 goto msi_only;
1097
1098         for (i = 0; i < numvecs; i++)
1099                 adapter->msix_entries[i].entry = i;
1100
1101         err = pci_enable_msix(adapter->pdev,
1102                               adapter->msix_entries,
1103                               numvecs);
1104         if (err == 0)
1105                 return;
1106
1107         igb_reset_interrupt_capability(adapter);
1108
1109         /* If we can't do MSI-X, try MSI */
1110 msi_only:
1111 #ifdef CONFIG_PCI_IOV
1112         /* disable SR-IOV for non MSI-X configurations */
1113         if (adapter->vf_data) {
1114                 struct e1000_hw *hw = &adapter->hw;
1115                 /* disable iov and allow time for transactions to clear */
1116                 pci_disable_sriov(adapter->pdev);
1117                 msleep(500);
1118
1119                 kfree(adapter->vf_data);
1120                 adapter->vf_data = NULL;
1121                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1122                 wrfl();
1123                 msleep(100);
1124                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1125         }
1126 #endif
1127         adapter->vfs_allocated_count = 0;
1128         adapter->rss_queues = 1;
1129         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1130         adapter->num_rx_queues = 1;
1131         adapter->num_tx_queues = 1;
1132         adapter->num_q_vectors = 1;
1133         if (!pci_enable_msi(adapter->pdev))
1134                 adapter->flags |= IGB_FLAG_HAS_MSI;
1135 }
1136
1137 static void igb_add_ring(struct igb_ring *ring,
1138                          struct igb_ring_container *head)
1139 {
1140         head->ring = ring;
1141         head->count++;
1142 }
1143
1144 /**
1145  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1146  *  @adapter: board private structure to initialize
1147  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1148  *  @v_idx: index of vector in adapter struct
1149  *  @txr_count: total number of Tx rings to allocate
1150  *  @txr_idx: index of first Tx ring to allocate
1151  *  @rxr_count: total number of Rx rings to allocate
1152  *  @rxr_idx: index of first Rx ring to allocate
1153  *
1154  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1155  **/
1156 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1157                               int v_count, int v_idx,
1158                               int txr_count, int txr_idx,
1159                               int rxr_count, int rxr_idx)
1160 {
1161         struct igb_q_vector *q_vector;
1162         struct igb_ring *ring;
1163         int ring_count, size;
1164
1165         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1166         if (txr_count > 1 || rxr_count > 1)
1167                 return -ENOMEM;
1168
1169         ring_count = txr_count + rxr_count;
1170         size = sizeof(struct igb_q_vector) +
1171                (sizeof(struct igb_ring) * ring_count);
1172
1173         /* allocate q_vector and rings */
1174         q_vector = kzalloc(size, GFP_KERNEL);
1175         if (!q_vector)
1176                 return -ENOMEM;
1177
1178         /* initialize NAPI */
1179         netif_napi_add(adapter->netdev, &q_vector->napi,
1180                        igb_poll, 64);
1181
1182         /* tie q_vector and adapter together */
1183         adapter->q_vector[v_idx] = q_vector;
1184         q_vector->adapter = adapter;
1185
1186         /* initialize work limits */
1187         q_vector->tx.work_limit = adapter->tx_work_limit;
1188
1189         /* initialize ITR configuration */
1190         q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1191         q_vector->itr_val = IGB_START_ITR;
1192
1193         /* initialize pointer to rings */
1194         ring = q_vector->ring;
1195
1196         /* intialize ITR */
1197         if (rxr_count) {
1198                 /* rx or rx/tx vector */
1199                 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1200                         q_vector->itr_val = adapter->rx_itr_setting;
1201         } else {
1202                 /* tx only vector */
1203                 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1204                         q_vector->itr_val = adapter->tx_itr_setting;
1205         }
1206
1207         if (txr_count) {
1208                 /* assign generic ring traits */
1209                 ring->dev = &adapter->pdev->dev;
1210                 ring->netdev = adapter->netdev;
1211
1212                 /* configure backlink on ring */
1213                 ring->q_vector = q_vector;
1214
1215                 /* update q_vector Tx values */
1216                 igb_add_ring(ring, &q_vector->tx);
1217
1218                 /* For 82575, context index must be unique per ring. */
1219                 if (adapter->hw.mac.type == e1000_82575)
1220                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1221
1222                 /* apply Tx specific ring traits */
1223                 ring->count = adapter->tx_ring_count;
1224                 ring->queue_index = txr_idx;
1225
1226                 /* assign ring to adapter */
1227                 adapter->tx_ring[txr_idx] = ring;
1228
1229                 /* push pointer to next ring */
1230                 ring++;
1231         }
1232
1233         if (rxr_count) {
1234                 /* assign generic ring traits */
1235                 ring->dev = &adapter->pdev->dev;
1236                 ring->netdev = adapter->netdev;
1237
1238                 /* configure backlink on ring */
1239                 ring->q_vector = q_vector;
1240
1241                 /* update q_vector Rx values */
1242                 igb_add_ring(ring, &q_vector->rx);
1243
1244                 /* set flag indicating ring supports SCTP checksum offload */
1245                 if (adapter->hw.mac.type >= e1000_82576)
1246                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1247
1248                 /*
1249                  * On i350, i354, i210, and i211, loopback VLAN packets
1250                  * have the tag byte-swapped.
1251                  */
1252                 if (adapter->hw.mac.type >= e1000_i350)
1253                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1254
1255                 /* apply Rx specific ring traits */
1256                 ring->count = adapter->rx_ring_count;
1257                 ring->queue_index = rxr_idx;
1258
1259                 /* assign ring to adapter */
1260                 adapter->rx_ring[rxr_idx] = ring;
1261         }
1262
1263         return 0;
1264 }
1265
1266
1267 /**
1268  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1269  *  @adapter: board private structure to initialize
1270  *
1271  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1272  *  return -ENOMEM.
1273  **/
1274 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1275 {
1276         int q_vectors = adapter->num_q_vectors;
1277         int rxr_remaining = adapter->num_rx_queues;
1278         int txr_remaining = adapter->num_tx_queues;
1279         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1280         int err;
1281
1282         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1283                 for (; rxr_remaining; v_idx++) {
1284                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1285                                                  0, 0, 1, rxr_idx);
1286
1287                         if (err)
1288                                 goto err_out;
1289
1290                         /* update counts and index */
1291                         rxr_remaining--;
1292                         rxr_idx++;
1293                 }
1294         }
1295
1296         for (; v_idx < q_vectors; v_idx++) {
1297                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1298                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1299                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1300                                          tqpv, txr_idx, rqpv, rxr_idx);
1301
1302                 if (err)
1303                         goto err_out;
1304
1305                 /* update counts and index */
1306                 rxr_remaining -= rqpv;
1307                 txr_remaining -= tqpv;
1308                 rxr_idx++;
1309                 txr_idx++;
1310         }
1311
1312         return 0;
1313
1314 err_out:
1315         adapter->num_tx_queues = 0;
1316         adapter->num_rx_queues = 0;
1317         adapter->num_q_vectors = 0;
1318
1319         while (v_idx--)
1320                 igb_free_q_vector(adapter, v_idx);
1321
1322         return -ENOMEM;
1323 }
1324
1325 /**
1326  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1327  *  @adapter: board private structure to initialize
1328  *  @msix: boolean value of MSIX capability
1329  *
1330  *  This function initializes the interrupts and allocates all of the queues.
1331  **/
1332 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1333 {
1334         struct pci_dev *pdev = adapter->pdev;
1335         int err;
1336
1337         igb_set_interrupt_capability(adapter, msix);
1338
1339         err = igb_alloc_q_vectors(adapter);
1340         if (err) {
1341                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1342                 goto err_alloc_q_vectors;
1343         }
1344
1345         igb_cache_ring_register(adapter);
1346
1347         return 0;
1348
1349 err_alloc_q_vectors:
1350         igb_reset_interrupt_capability(adapter);
1351         return err;
1352 }
1353
1354 /**
1355  *  igb_request_irq - initialize interrupts
1356  *  @adapter: board private structure to initialize
1357  *
1358  *  Attempts to configure interrupts using the best available
1359  *  capabilities of the hardware and kernel.
1360  **/
1361 static int igb_request_irq(struct igb_adapter *adapter)
1362 {
1363         struct net_device *netdev = adapter->netdev;
1364         struct pci_dev *pdev = adapter->pdev;
1365         int err = 0;
1366
1367         if (adapter->msix_entries) {
1368                 err = igb_request_msix(adapter);
1369                 if (!err)
1370                         goto request_done;
1371                 /* fall back to MSI */
1372                 igb_free_all_tx_resources(adapter);
1373                 igb_free_all_rx_resources(adapter);
1374
1375                 igb_clear_interrupt_scheme(adapter);
1376                 err = igb_init_interrupt_scheme(adapter, false);
1377                 if (err)
1378                         goto request_done;
1379
1380                 igb_setup_all_tx_resources(adapter);
1381                 igb_setup_all_rx_resources(adapter);
1382                 igb_configure(adapter);
1383         }
1384
1385         igb_assign_vector(adapter->q_vector[0], 0);
1386
1387         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1388                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1389                                   netdev->name, adapter);
1390                 if (!err)
1391                         goto request_done;
1392
1393                 /* fall back to legacy interrupts */
1394                 igb_reset_interrupt_capability(adapter);
1395                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1396         }
1397
1398         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1399                           netdev->name, adapter);
1400
1401         if (err)
1402                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1403                         err);
1404
1405 request_done:
1406         return err;
1407 }
1408
1409 static void igb_free_irq(struct igb_adapter *adapter)
1410 {
1411         if (adapter->msix_entries) {
1412                 int vector = 0, i;
1413
1414                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1415
1416                 for (i = 0; i < adapter->num_q_vectors; i++)
1417                         free_irq(adapter->msix_entries[vector++].vector,
1418                                  adapter->q_vector[i]);
1419         } else {
1420                 free_irq(adapter->pdev->irq, adapter);
1421         }
1422 }
1423
1424 /**
1425  *  igb_irq_disable - Mask off interrupt generation on the NIC
1426  *  @adapter: board private structure
1427  **/
1428 static void igb_irq_disable(struct igb_adapter *adapter)
1429 {
1430         struct e1000_hw *hw = &adapter->hw;
1431
1432         /* we need to be careful when disabling interrupts.  The VFs are also
1433          * mapped into these registers and so clearing the bits can cause
1434          * issues on the VF drivers so we only need to clear what we set
1435          */
1436         if (adapter->msix_entries) {
1437                 u32 regval = rd32(E1000_EIAM);
1438                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1439                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1440                 regval = rd32(E1000_EIAC);
1441                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1442         }
1443
1444         wr32(E1000_IAM, 0);
1445         wr32(E1000_IMC, ~0);
1446         wrfl();
1447         if (adapter->msix_entries) {
1448                 int i;
1449                 for (i = 0; i < adapter->num_q_vectors; i++)
1450                         synchronize_irq(adapter->msix_entries[i].vector);
1451         } else {
1452                 synchronize_irq(adapter->pdev->irq);
1453         }
1454 }
1455
1456 /**
1457  *  igb_irq_enable - Enable default interrupt generation settings
1458  *  @adapter: board private structure
1459  **/
1460 static void igb_irq_enable(struct igb_adapter *adapter)
1461 {
1462         struct e1000_hw *hw = &adapter->hw;
1463
1464         if (adapter->msix_entries) {
1465                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1466                 u32 regval = rd32(E1000_EIAC);
1467                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1468                 regval = rd32(E1000_EIAM);
1469                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1470                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1471                 if (adapter->vfs_allocated_count) {
1472                         wr32(E1000_MBVFIMR, 0xFF);
1473                         ims |= E1000_IMS_VMMB;
1474                 }
1475                 wr32(E1000_IMS, ims);
1476         } else {
1477                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1478                                 E1000_IMS_DRSTA);
1479                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1480                                 E1000_IMS_DRSTA);
1481         }
1482 }
1483
1484 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1485 {
1486         struct e1000_hw *hw = &adapter->hw;
1487         u16 vid = adapter->hw.mng_cookie.vlan_id;
1488         u16 old_vid = adapter->mng_vlan_id;
1489
1490         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1491                 /* add VID to filter table */
1492                 igb_vfta_set(hw, vid, true);
1493                 adapter->mng_vlan_id = vid;
1494         } else {
1495                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1496         }
1497
1498         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1499             (vid != old_vid) &&
1500             !test_bit(old_vid, adapter->active_vlans)) {
1501                 /* remove VID from filter table */
1502                 igb_vfta_set(hw, old_vid, false);
1503         }
1504 }
1505
1506 /**
1507  *  igb_release_hw_control - release control of the h/w to f/w
1508  *  @adapter: address of board private structure
1509  *
1510  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1511  *  For ASF and Pass Through versions of f/w this means that the
1512  *  driver is no longer loaded.
1513  **/
1514 static void igb_release_hw_control(struct igb_adapter *adapter)
1515 {
1516         struct e1000_hw *hw = &adapter->hw;
1517         u32 ctrl_ext;
1518
1519         /* Let firmware take over control of h/w */
1520         ctrl_ext = rd32(E1000_CTRL_EXT);
1521         wr32(E1000_CTRL_EXT,
1522                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1523 }
1524
1525 /**
1526  *  igb_get_hw_control - get control of the h/w from f/w
1527  *  @adapter: address of board private structure
1528  *
1529  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1530  *  For ASF and Pass Through versions of f/w this means that
1531  *  the driver is loaded.
1532  **/
1533 static void igb_get_hw_control(struct igb_adapter *adapter)
1534 {
1535         struct e1000_hw *hw = &adapter->hw;
1536         u32 ctrl_ext;
1537
1538         /* Let firmware know the driver has taken over */
1539         ctrl_ext = rd32(E1000_CTRL_EXT);
1540         wr32(E1000_CTRL_EXT,
1541                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1542 }
1543
1544 /**
1545  *  igb_configure - configure the hardware for RX and TX
1546  *  @adapter: private board structure
1547  **/
1548 static void igb_configure(struct igb_adapter *adapter)
1549 {
1550         struct net_device *netdev = adapter->netdev;
1551         int i;
1552
1553         igb_get_hw_control(adapter);
1554         igb_set_rx_mode(netdev);
1555
1556         igb_restore_vlan(adapter);
1557
1558         igb_setup_tctl(adapter);
1559         igb_setup_mrqc(adapter);
1560         igb_setup_rctl(adapter);
1561
1562         igb_configure_tx(adapter);
1563         igb_configure_rx(adapter);
1564
1565         igb_rx_fifo_flush_82575(&adapter->hw);
1566
1567         /* call igb_desc_unused which always leaves
1568          * at least 1 descriptor unused to make sure
1569          * next_to_use != next_to_clean
1570          */
1571         for (i = 0; i < adapter->num_rx_queues; i++) {
1572                 struct igb_ring *ring = adapter->rx_ring[i];
1573                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1574         }
1575 }
1576
1577 /**
1578  *  igb_power_up_link - Power up the phy/serdes link
1579  *  @adapter: address of board private structure
1580  **/
1581 void igb_power_up_link(struct igb_adapter *adapter)
1582 {
1583         igb_reset_phy(&adapter->hw);
1584
1585         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1586                 igb_power_up_phy_copper(&adapter->hw);
1587         else
1588                 igb_power_up_serdes_link_82575(&adapter->hw);
1589 }
1590
1591 /**
1592  *  igb_power_down_link - Power down the phy/serdes link
1593  *  @adapter: address of board private structure
1594  */
1595 static void igb_power_down_link(struct igb_adapter *adapter)
1596 {
1597         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1598                 igb_power_down_phy_copper_82575(&adapter->hw);
1599         else
1600                 igb_shutdown_serdes_link_82575(&adapter->hw);
1601 }
1602
1603 /**
1604  *  igb_up - Open the interface and prepare it to handle traffic
1605  *  @adapter: board private structure
1606  **/
1607 int igb_up(struct igb_adapter *adapter)
1608 {
1609         struct e1000_hw *hw = &adapter->hw;
1610         int i;
1611
1612         /* hardware has been reset, we need to reload some things */
1613         igb_configure(adapter);
1614
1615         clear_bit(__IGB_DOWN, &adapter->state);
1616
1617         for (i = 0; i < adapter->num_q_vectors; i++)
1618                 napi_enable(&(adapter->q_vector[i]->napi));
1619
1620         if (adapter->msix_entries)
1621                 igb_configure_msix(adapter);
1622         else
1623                 igb_assign_vector(adapter->q_vector[0], 0);
1624
1625         /* Clear any pending interrupts. */
1626         rd32(E1000_ICR);
1627         igb_irq_enable(adapter);
1628
1629         /* notify VFs that reset has been completed */
1630         if (adapter->vfs_allocated_count) {
1631                 u32 reg_data = rd32(E1000_CTRL_EXT);
1632                 reg_data |= E1000_CTRL_EXT_PFRSTD;
1633                 wr32(E1000_CTRL_EXT, reg_data);
1634         }
1635
1636         netif_tx_start_all_queues(adapter->netdev);
1637
1638         /* start the watchdog. */
1639         hw->mac.get_link_status = 1;
1640         schedule_work(&adapter->watchdog_task);
1641
1642         return 0;
1643 }
1644
1645 void igb_down(struct igb_adapter *adapter)
1646 {
1647         struct net_device *netdev = adapter->netdev;
1648         struct e1000_hw *hw = &adapter->hw;
1649         u32 tctl, rctl;
1650         int i;
1651
1652         /* signal that we're down so the interrupt handler does not
1653          * reschedule our watchdog timer
1654          */
1655         set_bit(__IGB_DOWN, &adapter->state);
1656
1657         /* disable receives in the hardware */
1658         rctl = rd32(E1000_RCTL);
1659         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1660         /* flush and sleep below */
1661
1662         netif_tx_stop_all_queues(netdev);
1663
1664         /* disable transmits in the hardware */
1665         tctl = rd32(E1000_TCTL);
1666         tctl &= ~E1000_TCTL_EN;
1667         wr32(E1000_TCTL, tctl);
1668         /* flush both disables and wait for them to finish */
1669         wrfl();
1670         msleep(10);
1671
1672         igb_irq_disable(adapter);
1673
1674         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1675
1676         for (i = 0; i < adapter->num_q_vectors; i++) {
1677                 napi_synchronize(&(adapter->q_vector[i]->napi));
1678                 napi_disable(&(adapter->q_vector[i]->napi));
1679         }
1680
1681
1682         del_timer_sync(&adapter->watchdog_timer);
1683         del_timer_sync(&adapter->phy_info_timer);
1684
1685         netif_carrier_off(netdev);
1686
1687         /* record the stats before reset*/
1688         spin_lock(&adapter->stats64_lock);
1689         igb_update_stats(adapter, &adapter->stats64);
1690         spin_unlock(&adapter->stats64_lock);
1691
1692         adapter->link_speed = 0;
1693         adapter->link_duplex = 0;
1694
1695         if (!pci_channel_offline(adapter->pdev))
1696                 igb_reset(adapter);
1697         igb_clean_all_tx_rings(adapter);
1698         igb_clean_all_rx_rings(adapter);
1699 #ifdef CONFIG_IGB_DCA
1700
1701         /* since we reset the hardware DCA settings were cleared */
1702         igb_setup_dca(adapter);
1703 #endif
1704 }
1705
1706 void igb_reinit_locked(struct igb_adapter *adapter)
1707 {
1708         WARN_ON(in_interrupt());
1709         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1710                 msleep(1);
1711         igb_down(adapter);
1712         igb_up(adapter);
1713         clear_bit(__IGB_RESETTING, &adapter->state);
1714 }
1715
1716 void igb_reset(struct igb_adapter *adapter)
1717 {
1718         struct pci_dev *pdev = adapter->pdev;
1719         struct e1000_hw *hw = &adapter->hw;
1720         struct e1000_mac_info *mac = &hw->mac;
1721         struct e1000_fc_info *fc = &hw->fc;
1722         u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1723
1724         /* Repartition Pba for greater than 9k mtu
1725          * To take effect CTRL.RST is required.
1726          */
1727         switch (mac->type) {
1728         case e1000_i350:
1729         case e1000_i354:
1730         case e1000_82580:
1731                 pba = rd32(E1000_RXPBS);
1732                 pba = igb_rxpbs_adjust_82580(pba);
1733                 break;
1734         case e1000_82576:
1735                 pba = rd32(E1000_RXPBS);
1736                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1737                 break;
1738         case e1000_82575:
1739         case e1000_i210:
1740         case e1000_i211:
1741         default:
1742                 pba = E1000_PBA_34K;
1743                 break;
1744         }
1745
1746         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1747             (mac->type < e1000_82576)) {
1748                 /* adjust PBA for jumbo frames */
1749                 wr32(E1000_PBA, pba);
1750
1751                 /* To maintain wire speed transmits, the Tx FIFO should be
1752                  * large enough to accommodate two full transmit packets,
1753                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1754                  * the Rx FIFO should be large enough to accommodate at least
1755                  * one full receive packet and is similarly rounded up and
1756                  * expressed in KB.
1757                  */
1758                 pba = rd32(E1000_PBA);
1759                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1760                 tx_space = pba >> 16;
1761                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1762                 pba &= 0xffff;
1763                 /* the Tx fifo also stores 16 bytes of information about the Tx
1764                  * but don't include ethernet FCS because hardware appends it
1765                  */
1766                 min_tx_space = (adapter->max_frame_size +
1767                                 sizeof(union e1000_adv_tx_desc) -
1768                                 ETH_FCS_LEN) * 2;
1769                 min_tx_space = ALIGN(min_tx_space, 1024);
1770                 min_tx_space >>= 10;
1771                 /* software strips receive CRC, so leave room for it */
1772                 min_rx_space = adapter->max_frame_size;
1773                 min_rx_space = ALIGN(min_rx_space, 1024);
1774                 min_rx_space >>= 10;
1775
1776                 /* If current Tx allocation is less than the min Tx FIFO size,
1777                  * and the min Tx FIFO size is less than the current Rx FIFO
1778                  * allocation, take space away from current Rx allocation
1779                  */
1780                 if (tx_space < min_tx_space &&
1781                     ((min_tx_space - tx_space) < pba)) {
1782                         pba = pba - (min_tx_space - tx_space);
1783
1784                         /* if short on Rx space, Rx wins and must trump Tx
1785                          * adjustment
1786                          */
1787                         if (pba < min_rx_space)
1788                                 pba = min_rx_space;
1789                 }
1790                 wr32(E1000_PBA, pba);
1791         }
1792
1793         /* flow control settings */
1794         /* The high water mark must be low enough to fit one full frame
1795          * (or the size used for early receive) above it in the Rx FIFO.
1796          * Set it to the lower of:
1797          * - 90% of the Rx FIFO size, or
1798          * - the full Rx FIFO size minus one full frame
1799          */
1800         hwm = min(((pba << 10) * 9 / 10),
1801                         ((pba << 10) - 2 * adapter->max_frame_size));
1802
1803         fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
1804         fc->low_water = fc->high_water - 16;
1805         fc->pause_time = 0xFFFF;
1806         fc->send_xon = 1;
1807         fc->current_mode = fc->requested_mode;
1808
1809         /* disable receive for all VFs and wait one second */
1810         if (adapter->vfs_allocated_count) {
1811                 int i;
1812                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1813                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1814
1815                 /* ping all the active vfs to let them know we are going down */
1816                 igb_ping_all_vfs(adapter);
1817
1818                 /* disable transmits and receives */
1819                 wr32(E1000_VFRE, 0);
1820                 wr32(E1000_VFTE, 0);
1821         }
1822
1823         /* Allow time for pending master requests to run */
1824         hw->mac.ops.reset_hw(hw);
1825         wr32(E1000_WUC, 0);
1826
1827         if (hw->mac.ops.init_hw(hw))
1828                 dev_err(&pdev->dev, "Hardware Error\n");
1829
1830         /* Flow control settings reset on hardware reset, so guarantee flow
1831          * control is off when forcing speed.
1832          */
1833         if (!hw->mac.autoneg)
1834                 igb_force_mac_fc(hw);
1835
1836         igb_init_dmac(adapter, pba);
1837 #ifdef CONFIG_IGB_HWMON
1838         /* Re-initialize the thermal sensor on i350 devices. */
1839         if (!test_bit(__IGB_DOWN, &adapter->state)) {
1840                 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1841                         /* If present, re-initialize the external thermal sensor
1842                          * interface.
1843                          */
1844                         if (adapter->ets)
1845                                 mac->ops.init_thermal_sensor_thresh(hw);
1846                 }
1847         }
1848 #endif
1849         if (!netif_running(adapter->netdev))
1850                 igb_power_down_link(adapter);
1851
1852         igb_update_mng_vlan(adapter);
1853
1854         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1855         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1856
1857         /* Re-enable PTP, where applicable. */
1858         igb_ptp_reset(adapter);
1859
1860         igb_get_phy_info(hw);
1861 }
1862
1863 static netdev_features_t igb_fix_features(struct net_device *netdev,
1864         netdev_features_t features)
1865 {
1866         /* Since there is no support for separate Rx/Tx vlan accel
1867          * enable/disable make sure Tx flag is always in same state as Rx.
1868          */
1869         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1870                 features |= NETIF_F_HW_VLAN_CTAG_TX;
1871         else
1872                 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1873
1874         return features;
1875 }
1876
1877 static int igb_set_features(struct net_device *netdev,
1878         netdev_features_t features)
1879 {
1880         netdev_features_t changed = netdev->features ^ features;
1881         struct igb_adapter *adapter = netdev_priv(netdev);
1882
1883         if (changed & NETIF_F_HW_VLAN_CTAG_RX)
1884                 igb_vlan_mode(netdev, features);
1885
1886         if (!(changed & NETIF_F_RXALL))
1887                 return 0;
1888
1889         netdev->features = features;
1890
1891         if (netif_running(netdev))
1892                 igb_reinit_locked(adapter);
1893         else
1894                 igb_reset(adapter);
1895
1896         return 0;
1897 }
1898
1899 static const struct net_device_ops igb_netdev_ops = {
1900         .ndo_open               = igb_open,
1901         .ndo_stop               = igb_close,
1902         .ndo_start_xmit         = igb_xmit_frame,
1903         .ndo_get_stats64        = igb_get_stats64,
1904         .ndo_set_rx_mode        = igb_set_rx_mode,
1905         .ndo_set_mac_address    = igb_set_mac,
1906         .ndo_change_mtu         = igb_change_mtu,
1907         .ndo_do_ioctl           = igb_ioctl,
1908         .ndo_tx_timeout         = igb_tx_timeout,
1909         .ndo_validate_addr      = eth_validate_addr,
1910         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1911         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1912         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
1913         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
1914         .ndo_set_vf_tx_rate     = igb_ndo_set_vf_bw,
1915         .ndo_set_vf_spoofchk    = igb_ndo_set_vf_spoofchk,
1916         .ndo_get_vf_config      = igb_ndo_get_vf_config,
1917 #ifdef CONFIG_NET_POLL_CONTROLLER
1918         .ndo_poll_controller    = igb_netpoll,
1919 #endif
1920         .ndo_fix_features       = igb_fix_features,
1921         .ndo_set_features       = igb_set_features,
1922 };
1923
1924 /**
1925  * igb_set_fw_version - Configure version string for ethtool
1926  * @adapter: adapter struct
1927  **/
1928 void igb_set_fw_version(struct igb_adapter *adapter)
1929 {
1930         struct e1000_hw *hw = &adapter->hw;
1931         struct e1000_fw_version fw;
1932
1933         igb_get_fw_version(hw, &fw);
1934
1935         switch (hw->mac.type) {
1936         case e1000_i210:
1937         case e1000_i211:
1938                 if (!(igb_get_flash_presence_i210(hw))) {
1939                         snprintf(adapter->fw_version,
1940                                  sizeof(adapter->fw_version),
1941                                  "%2d.%2d-%d",
1942                                  fw.invm_major, fw.invm_minor,
1943                                  fw.invm_img_type);
1944                         break;
1945                 }
1946                 /* fall through */
1947         default:
1948                 /* if option is rom valid, display its version too */
1949                 if (fw.or_valid) {
1950                         snprintf(adapter->fw_version,
1951                                  sizeof(adapter->fw_version),
1952                                  "%d.%d, 0x%08x, %d.%d.%d",
1953                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
1954                                  fw.or_major, fw.or_build, fw.or_patch);
1955                 /* no option rom */
1956                 } else if (fw.etrack_id != 0X0000) {
1957                         snprintf(adapter->fw_version,
1958                             sizeof(adapter->fw_version),
1959                             "%d.%d, 0x%08x",
1960                             fw.eep_major, fw.eep_minor, fw.etrack_id);
1961                 } else {
1962                 snprintf(adapter->fw_version,
1963                     sizeof(adapter->fw_version),
1964                     "%d.%d.%d",
1965                     fw.eep_major, fw.eep_minor, fw.eep_build);
1966                 }
1967                 break;
1968         }
1969         return;
1970 }
1971
1972 /**
1973  *  igb_init_i2c - Init I2C interface
1974  *  @adapter: pointer to adapter structure
1975  **/
1976 static s32 igb_init_i2c(struct igb_adapter *adapter)
1977 {
1978         s32 status = E1000_SUCCESS;
1979
1980         /* I2C interface supported on i350 devices */
1981         if (adapter->hw.mac.type != e1000_i350)
1982                 return E1000_SUCCESS;
1983
1984         /* Initialize the i2c bus which is controlled by the registers.
1985          * This bus will use the i2c_algo_bit structue that implements
1986          * the protocol through toggling of the 4 bits in the register.
1987          */
1988         adapter->i2c_adap.owner = THIS_MODULE;
1989         adapter->i2c_algo = igb_i2c_algo;
1990         adapter->i2c_algo.data = adapter;
1991         adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1992         adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1993         strlcpy(adapter->i2c_adap.name, "igb BB",
1994                 sizeof(adapter->i2c_adap.name));
1995         status = i2c_bit_add_bus(&adapter->i2c_adap);
1996         return status;
1997 }
1998
1999 /**
2000  *  igb_probe - Device Initialization Routine
2001  *  @pdev: PCI device information struct
2002  *  @ent: entry in igb_pci_tbl
2003  *
2004  *  Returns 0 on success, negative on failure
2005  *
2006  *  igb_probe initializes an adapter identified by a pci_dev structure.
2007  *  The OS initialization, configuring of the adapter private structure,
2008  *  and a hardware reset occur.
2009  **/
2010 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2011 {
2012         struct net_device *netdev;
2013         struct igb_adapter *adapter;
2014         struct e1000_hw *hw;
2015         u16 eeprom_data = 0;
2016         s32 ret_val;
2017         static int global_quad_port_a; /* global quad port a indication */
2018         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2019         unsigned long mmio_start, mmio_len;
2020         int err, pci_using_dac;
2021         u8 part_str[E1000_PBANUM_LENGTH];
2022
2023         /* Catch broken hardware that put the wrong VF device ID in
2024          * the PCIe SR-IOV capability.
2025          */
2026         if (pdev->is_virtfn) {
2027                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2028                         pci_name(pdev), pdev->vendor, pdev->device);
2029                 return -EINVAL;
2030         }
2031
2032         err = pci_enable_device_mem(pdev);
2033         if (err)
2034                 return err;
2035
2036         pci_using_dac = 0;
2037         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2038         if (!err) {
2039                 pci_using_dac = 1;
2040         } else {
2041                 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2042                 if (err) {
2043                         dev_err(&pdev->dev,
2044                                 "No usable DMA configuration, aborting\n");
2045                         goto err_dma;
2046                 }
2047         }
2048
2049         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2050                                            IORESOURCE_MEM),
2051                                            igb_driver_name);
2052         if (err)
2053                 goto err_pci_reg;
2054
2055         pci_enable_pcie_error_reporting(pdev);
2056
2057         pci_set_master(pdev);
2058         pci_save_state(pdev);
2059
2060         err = -ENOMEM;
2061         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2062                                    IGB_MAX_TX_QUEUES);
2063         if (!netdev)
2064                 goto err_alloc_etherdev;
2065
2066         SET_NETDEV_DEV(netdev, &pdev->dev);
2067
2068         pci_set_drvdata(pdev, netdev);
2069         adapter = netdev_priv(netdev);
2070         adapter->netdev = netdev;
2071         adapter->pdev = pdev;
2072         hw = &adapter->hw;
2073         hw->back = adapter;
2074         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2075
2076         mmio_start = pci_resource_start(pdev, 0);
2077         mmio_len = pci_resource_len(pdev, 0);
2078
2079         err = -EIO;
2080         hw->hw_addr = ioremap(mmio_start, mmio_len);
2081         if (!hw->hw_addr)
2082                 goto err_ioremap;
2083
2084         netdev->netdev_ops = &igb_netdev_ops;
2085         igb_set_ethtool_ops(netdev);
2086         netdev->watchdog_timeo = 5 * HZ;
2087
2088         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2089
2090         netdev->mem_start = mmio_start;
2091         netdev->mem_end = mmio_start + mmio_len;
2092
2093         /* PCI config space info */
2094         hw->vendor_id = pdev->vendor;
2095         hw->device_id = pdev->device;
2096         hw->revision_id = pdev->revision;
2097         hw->subsystem_vendor_id = pdev->subsystem_vendor;
2098         hw->subsystem_device_id = pdev->subsystem_device;
2099
2100         /* Copy the default MAC, PHY and NVM function pointers */
2101         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2102         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2103         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2104         /* Initialize skew-specific constants */
2105         err = ei->get_invariants(hw);
2106         if (err)
2107                 goto err_sw_init;
2108
2109         /* setup the private structure */
2110         err = igb_sw_init(adapter);
2111         if (err)
2112                 goto err_sw_init;
2113
2114         igb_get_bus_info_pcie(hw);
2115
2116         hw->phy.autoneg_wait_to_complete = false;
2117
2118         /* Copper options */
2119         if (hw->phy.media_type == e1000_media_type_copper) {
2120                 hw->phy.mdix = AUTO_ALL_MODES;
2121                 hw->phy.disable_polarity_correction = false;
2122                 hw->phy.ms_type = e1000_ms_hw_default;
2123         }
2124
2125         if (igb_check_reset_block(hw))
2126                 dev_info(&pdev->dev,
2127                         "PHY reset is blocked due to SOL/IDER session.\n");
2128
2129         /* features is initialized to 0 in allocation, it might have bits
2130          * set by igb_sw_init so we should use an or instead of an
2131          * assignment.
2132          */
2133         netdev->features |= NETIF_F_SG |
2134                             NETIF_F_IP_CSUM |
2135                             NETIF_F_IPV6_CSUM |
2136                             NETIF_F_TSO |
2137                             NETIF_F_TSO6 |
2138                             NETIF_F_RXHASH |
2139                             NETIF_F_RXCSUM |
2140                             NETIF_F_HW_VLAN_CTAG_RX |
2141                             NETIF_F_HW_VLAN_CTAG_TX;
2142
2143         /* copy netdev features into list of user selectable features */
2144         netdev->hw_features |= netdev->features;
2145         netdev->hw_features |= NETIF_F_RXALL;
2146
2147         /* set this bit last since it cannot be part of hw_features */
2148         netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2149
2150         netdev->vlan_features |= NETIF_F_TSO |
2151                                  NETIF_F_TSO6 |
2152                                  NETIF_F_IP_CSUM |
2153                                  NETIF_F_IPV6_CSUM |
2154                                  NETIF_F_SG;
2155
2156         netdev->priv_flags |= IFF_SUPP_NOFCS;
2157
2158         if (pci_using_dac) {
2159                 netdev->features |= NETIF_F_HIGHDMA;
2160                 netdev->vlan_features |= NETIF_F_HIGHDMA;
2161         }
2162
2163         if (hw->mac.type >= e1000_82576) {
2164                 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2165                 netdev->features |= NETIF_F_SCTP_CSUM;
2166         }
2167
2168         netdev->priv_flags |= IFF_UNICAST_FLT;
2169
2170         adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2171
2172         /* before reading the NVM, reset the controller to put the device in a
2173          * known good starting state
2174          */
2175         hw->mac.ops.reset_hw(hw);
2176
2177         /* make sure the NVM is good , i211/i210 parts can have special NVM
2178          * that doesn't contain a checksum
2179          */
2180         switch (hw->mac.type) {
2181         case e1000_i210:
2182         case e1000_i211:
2183                 if (igb_get_flash_presence_i210(hw)) {
2184                         if (hw->nvm.ops.validate(hw) < 0) {
2185                                 dev_err(&pdev->dev,
2186                                         "The NVM Checksum Is Not Valid\n");
2187                                 err = -EIO;
2188                                 goto err_eeprom;
2189                         }
2190                 }
2191                 break;
2192         default:
2193                 if (hw->nvm.ops.validate(hw) < 0) {
2194                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2195                         err = -EIO;
2196                         goto err_eeprom;
2197                 }
2198                 break;
2199         }
2200
2201         /* copy the MAC address out of the NVM */
2202         if (hw->mac.ops.read_mac_addr(hw))
2203                 dev_err(&pdev->dev, "NVM Read Error\n");
2204
2205         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2206
2207         if (!is_valid_ether_addr(netdev->dev_addr)) {
2208                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2209                 err = -EIO;
2210                 goto err_eeprom;
2211         }
2212
2213         /* get firmware version for ethtool -i */
2214         igb_set_fw_version(adapter);
2215
2216         setup_timer(&adapter->watchdog_timer, igb_watchdog,
2217                     (unsigned long) adapter);
2218         setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2219                     (unsigned long) adapter);
2220
2221         INIT_WORK(&adapter->reset_task, igb_reset_task);
2222         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2223
2224         /* Initialize link properties that are user-changeable */
2225         adapter->fc_autoneg = true;
2226         hw->mac.autoneg = true;
2227         hw->phy.autoneg_advertised = 0x2f;
2228
2229         hw->fc.requested_mode = e1000_fc_default;
2230         hw->fc.current_mode = e1000_fc_default;
2231
2232         igb_validate_mdi_setting(hw);
2233
2234         /* By default, support wake on port A */
2235         if (hw->bus.func == 0)
2236                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2237
2238         /* Check the NVM for wake support on non-port A ports */
2239         if (hw->mac.type >= e1000_82580)
2240                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2241                                  NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2242                                  &eeprom_data);
2243         else if (hw->bus.func == 1)
2244                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2245
2246         if (eeprom_data & IGB_EEPROM_APME)
2247                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2248
2249         /* now that we have the eeprom settings, apply the special cases where
2250          * the eeprom may be wrong or the board simply won't support wake on
2251          * lan on a particular port
2252          */
2253         switch (pdev->device) {
2254         case E1000_DEV_ID_82575GB_QUAD_COPPER:
2255                 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2256                 break;
2257         case E1000_DEV_ID_82575EB_FIBER_SERDES:
2258         case E1000_DEV_ID_82576_FIBER:
2259         case E1000_DEV_ID_82576_SERDES:
2260                 /* Wake events only supported on port A for dual fiber
2261                  * regardless of eeprom setting
2262                  */
2263                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2264                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2265                 break;
2266         case E1000_DEV_ID_82576_QUAD_COPPER:
2267         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2268                 /* if quad port adapter, disable WoL on all but port A */
2269                 if (global_quad_port_a != 0)
2270                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2271                 else
2272                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2273                 /* Reset for multiple quad port adapters */
2274                 if (++global_quad_port_a == 4)
2275                         global_quad_port_a = 0;
2276                 break;
2277         default:
2278                 /* If the device can't wake, don't set software support */
2279                 if (!device_can_wakeup(&adapter->pdev->dev))
2280                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2281         }
2282
2283         /* initialize the wol settings based on the eeprom settings */
2284         if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2285                 adapter->wol |= E1000_WUFC_MAG;
2286
2287         /* Some vendors want WoL disabled by default, but still supported */
2288         if ((hw->mac.type == e1000_i350) &&
2289             (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2290                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2291                 adapter->wol = 0;
2292         }
2293
2294         device_set_wakeup_enable(&adapter->pdev->dev,
2295                                  adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2296
2297         /* reset the hardware with the new settings */
2298         igb_reset(adapter);
2299
2300         /* Init the I2C interface */
2301         err = igb_init_i2c(adapter);
2302         if (err) {
2303                 dev_err(&pdev->dev, "failed to init i2c interface\n");
2304                 goto err_eeprom;
2305         }
2306
2307         /* let the f/w know that the h/w is now under the control of the
2308          * driver. */
2309         igb_get_hw_control(adapter);
2310
2311         strcpy(netdev->name, "eth%d");
2312         err = register_netdev(netdev);
2313         if (err)
2314                 goto err_register;
2315
2316         /* carrier off reporting is important to ethtool even BEFORE open */
2317         netif_carrier_off(netdev);
2318
2319 #ifdef CONFIG_IGB_DCA
2320         if (dca_add_requester(&pdev->dev) == 0) {
2321                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2322                 dev_info(&pdev->dev, "DCA enabled\n");
2323                 igb_setup_dca(adapter);
2324         }
2325
2326 #endif
2327 #ifdef CONFIG_IGB_HWMON
2328         /* Initialize the thermal sensor on i350 devices. */
2329         if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2330                 u16 ets_word;
2331
2332                 /* Read the NVM to determine if this i350 device supports an
2333                  * external thermal sensor.
2334                  */
2335                 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2336                 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2337                         adapter->ets = true;
2338                 else
2339                         adapter->ets = false;
2340                 if (igb_sysfs_init(adapter))
2341                         dev_err(&pdev->dev,
2342                                 "failed to allocate sysfs resources\n");
2343         } else {
2344                 adapter->ets = false;
2345         }
2346 #endif
2347         /* do hw tstamp init after resetting */
2348         igb_ptp_init(adapter);
2349
2350         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2351         /* print bus type/speed/width info, not applicable to i354 */
2352         if (hw->mac.type != e1000_i354) {
2353                 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2354                          netdev->name,
2355                          ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2356                           (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2357                            "unknown"),
2358                          ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2359                           "Width x4" :
2360                           (hw->bus.width == e1000_bus_width_pcie_x2) ?
2361                           "Width x2" :
2362                           (hw->bus.width == e1000_bus_width_pcie_x1) ?
2363                           "Width x1" : "unknown"), netdev->dev_addr);
2364         }
2365
2366         if ((hw->mac.type >= e1000_i210 ||
2367              igb_get_flash_presence_i210(hw))) {
2368                 ret_val = igb_read_part_string(hw, part_str,
2369                                                E1000_PBANUM_LENGTH);
2370         } else {
2371                 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2372         }
2373
2374         if (ret_val)
2375                 strcpy(part_str, "Unknown");
2376         dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2377         dev_info(&pdev->dev,
2378                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2379                 adapter->msix_entries ? "MSI-X" :
2380                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2381                 adapter->num_rx_queues, adapter->num_tx_queues);
2382         switch (hw->mac.type) {
2383         case e1000_i350:
2384         case e1000_i210:
2385         case e1000_i211:
2386                 igb_set_eee_i350(hw);
2387                 break;
2388         case e1000_i354:
2389                 if (hw->phy.media_type == e1000_media_type_copper) {
2390                         if ((rd32(E1000_CTRL_EXT) &
2391                             E1000_CTRL_EXT_LINK_MODE_SGMII))
2392                                 igb_set_eee_i354(hw);
2393                 }
2394                 break;
2395         default:
2396                 break;
2397         }
2398
2399         pm_runtime_put_noidle(&pdev->dev);
2400         return 0;
2401
2402 err_register:
2403         igb_release_hw_control(adapter);
2404         memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2405 err_eeprom:
2406         if (!igb_check_reset_block(hw))
2407                 igb_reset_phy(hw);
2408
2409         if (hw->flash_address)
2410                 iounmap(hw->flash_address);
2411 err_sw_init:
2412         igb_clear_interrupt_scheme(adapter);
2413         iounmap(hw->hw_addr);
2414 err_ioremap:
2415         free_netdev(netdev);
2416 err_alloc_etherdev:
2417         pci_release_selected_regions(pdev,
2418                                      pci_select_bars(pdev, IORESOURCE_MEM));
2419 err_pci_reg:
2420 err_dma:
2421         pci_disable_device(pdev);
2422         return err;
2423 }
2424
2425 #ifdef CONFIG_PCI_IOV
2426 static int  igb_disable_sriov(struct pci_dev *pdev)
2427 {
2428         struct net_device *netdev = pci_get_drvdata(pdev);
2429         struct igb_adapter *adapter = netdev_priv(netdev);
2430         struct e1000_hw *hw = &adapter->hw;
2431
2432         /* reclaim resources allocated to VFs */
2433         if (adapter->vf_data) {
2434                 /* disable iov and allow time for transactions to clear */
2435                 if (pci_vfs_assigned(pdev)) {
2436                         dev_warn(&pdev->dev,
2437                                  "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2438                         return -EPERM;
2439                 } else {
2440                         pci_disable_sriov(pdev);
2441                         msleep(500);
2442                 }
2443
2444                 kfree(adapter->vf_data);
2445                 adapter->vf_data = NULL;
2446                 adapter->vfs_allocated_count = 0;
2447                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2448                 wrfl();
2449                 msleep(100);
2450                 dev_info(&pdev->dev, "IOV Disabled\n");
2451
2452                 /* Re-enable DMA Coalescing flag since IOV is turned off */
2453                 adapter->flags |= IGB_FLAG_DMAC;
2454         }
2455
2456         return 0;
2457 }
2458
2459 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2460 {
2461         struct net_device *netdev = pci_get_drvdata(pdev);
2462         struct igb_adapter *adapter = netdev_priv(netdev);
2463         int old_vfs = pci_num_vf(pdev);
2464         int err = 0;
2465         int i;
2466
2467         if (!adapter->msix_entries) {
2468                 err = -EPERM;
2469                 goto out;
2470         }
2471
2472         if (!num_vfs)
2473                 goto out;
2474         else if (old_vfs && old_vfs == num_vfs)
2475                 goto out;
2476         else if (old_vfs && old_vfs != num_vfs)
2477                 err = igb_disable_sriov(pdev);
2478
2479         if (err)
2480                 goto out;
2481
2482         if (num_vfs > 7) {
2483                 err = -EPERM;
2484                 goto out;
2485         }
2486
2487         adapter->vfs_allocated_count = num_vfs;
2488
2489         adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2490                                 sizeof(struct vf_data_storage), GFP_KERNEL);
2491
2492         /* if allocation failed then we do not support SR-IOV */
2493         if (!adapter->vf_data) {
2494                 adapter->vfs_allocated_count = 0;
2495                 dev_err(&pdev->dev,
2496                         "Unable to allocate memory for VF Data Storage\n");
2497                 err = -ENOMEM;
2498                 goto out;
2499         }
2500
2501         err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2502         if (err)
2503                 goto err_out;
2504
2505         dev_info(&pdev->dev, "%d VFs allocated\n",
2506                  adapter->vfs_allocated_count);
2507         for (i = 0; i < adapter->vfs_allocated_count; i++)
2508                 igb_vf_configure(adapter, i);
2509
2510         /* DMA Coalescing is not supported in IOV mode. */
2511         adapter->flags &= ~IGB_FLAG_DMAC;
2512         goto out;
2513
2514 err_out:
2515         kfree(adapter->vf_data);
2516         adapter->vf_data = NULL;
2517         adapter->vfs_allocated_count = 0;
2518 out:
2519         return err;
2520 }
2521
2522 #endif
2523 /**
2524  *  igb_remove_i2c - Cleanup  I2C interface
2525  *  @adapter: pointer to adapter structure
2526  **/
2527 static void igb_remove_i2c(struct igb_adapter *adapter)
2528 {
2529         /* free the adapter bus structure */
2530         i2c_del_adapter(&adapter->i2c_adap);
2531 }
2532
2533 /**
2534  *  igb_remove - Device Removal Routine
2535  *  @pdev: PCI device information struct
2536  *
2537  *  igb_remove is called by the PCI subsystem to alert the driver
2538  *  that it should release a PCI device.  The could be caused by a
2539  *  Hot-Plug event, or because the driver is going to be removed from
2540  *  memory.
2541  **/
2542 static void igb_remove(struct pci_dev *pdev)
2543 {
2544         struct net_device *netdev = pci_get_drvdata(pdev);
2545         struct igb_adapter *adapter = netdev_priv(netdev);
2546         struct e1000_hw *hw = &adapter->hw;
2547
2548         pm_runtime_get_noresume(&pdev->dev);
2549 #ifdef CONFIG_IGB_HWMON
2550         igb_sysfs_exit(adapter);
2551 #endif
2552         igb_remove_i2c(adapter);
2553         igb_ptp_stop(adapter);
2554         /* The watchdog timer may be rescheduled, so explicitly
2555          * disable watchdog from being rescheduled.
2556          */
2557         set_bit(__IGB_DOWN, &adapter->state);
2558         del_timer_sync(&adapter->watchdog_timer);
2559         del_timer_sync(&adapter->phy_info_timer);
2560
2561         cancel_work_sync(&adapter->reset_task);
2562         cancel_work_sync(&adapter->watchdog_task);
2563
2564 #ifdef CONFIG_IGB_DCA
2565         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2566                 dev_info(&pdev->dev, "DCA disabled\n");
2567                 dca_remove_requester(&pdev->dev);
2568                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2569                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2570         }
2571 #endif
2572
2573         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
2574          * would have already happened in close and is redundant.
2575          */
2576         igb_release_hw_control(adapter);
2577
2578         unregister_netdev(netdev);
2579
2580         igb_clear_interrupt_scheme(adapter);
2581
2582 #ifdef CONFIG_PCI_IOV
2583         igb_disable_sriov(pdev);
2584 #endif
2585
2586         iounmap(hw->hw_addr);
2587         if (hw->flash_address)
2588                 iounmap(hw->flash_address);
2589         pci_release_selected_regions(pdev,
2590                                      pci_select_bars(pdev, IORESOURCE_MEM));
2591
2592         kfree(adapter->shadow_vfta);
2593         free_netdev(netdev);
2594
2595         pci_disable_pcie_error_reporting(pdev);
2596
2597         pci_disable_device(pdev);
2598 }
2599
2600 /**
2601  *  igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2602  *  @adapter: board private structure to initialize
2603  *
2604  *  This function initializes the vf specific data storage and then attempts to
2605  *  allocate the VFs.  The reason for ordering it this way is because it is much
2606  *  mor expensive time wise to disable SR-IOV than it is to allocate and free
2607  *  the memory for the VFs.
2608  **/
2609 static void igb_probe_vfs(struct igb_adapter *adapter)
2610 {
2611 #ifdef CONFIG_PCI_IOV
2612         struct pci_dev *pdev = adapter->pdev;
2613         struct e1000_hw *hw = &adapter->hw;
2614
2615         /* Virtualization features not supported on i210 family. */
2616         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2617                 return;
2618
2619         pci_sriov_set_totalvfs(pdev, 7);
2620         igb_enable_sriov(pdev, max_vfs);
2621
2622 #endif /* CONFIG_PCI_IOV */
2623 }
2624
2625 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2626 {
2627         struct e1000_hw *hw = &adapter->hw;
2628         u32 max_rss_queues;
2629
2630         /* Determine the maximum number of RSS queues supported. */
2631         switch (hw->mac.type) {
2632         case e1000_i211:
2633                 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2634                 break;
2635         case e1000_82575:
2636         case e1000_i210:
2637                 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2638                 break;
2639         case e1000_i350:
2640                 /* I350 cannot do RSS and SR-IOV at the same time */
2641                 if (!!adapter->vfs_allocated_count) {
2642                         max_rss_queues = 1;
2643                         break;
2644                 }
2645                 /* fall through */
2646         case e1000_82576:
2647                 if (!!adapter->vfs_allocated_count) {
2648                         max_rss_queues = 2;
2649                         break;
2650                 }
2651                 /* fall through */
2652         case e1000_82580:
2653         case e1000_i354:
2654         default:
2655                 max_rss_queues = IGB_MAX_RX_QUEUES;
2656                 break;
2657         }
2658
2659         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2660
2661         /* Determine if we need to pair queues. */
2662         switch (hw->mac.type) {
2663         case e1000_82575:
2664         case e1000_i211:
2665                 /* Device supports enough interrupts without queue pairing. */
2666                 break;
2667         case e1000_82576:
2668                 /* If VFs are going to be allocated with RSS queues then we
2669                  * should pair the queues in order to conserve interrupts due
2670                  * to limited supply.
2671                  */
2672                 if ((adapter->rss_queues > 1) &&
2673                     (adapter->vfs_allocated_count > 6))
2674                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2675                 /* fall through */
2676         case e1000_82580:
2677         case e1000_i350:
2678         case e1000_i354:
2679         case e1000_i210:
2680         default:
2681                 /* If rss_queues > half of max_rss_queues, pair the queues in
2682                  * order to conserve interrupts due to limited supply.
2683                  */
2684                 if (adapter->rss_queues > (max_rss_queues / 2))
2685                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2686                 break;
2687         }
2688 }
2689
2690 /**
2691  *  igb_sw_init - Initialize general software structures (struct igb_adapter)
2692  *  @adapter: board private structure to initialize
2693  *
2694  *  igb_sw_init initializes the Adapter private data structure.
2695  *  Fields are initialized based on PCI device information and
2696  *  OS network device settings (MTU size).
2697  **/
2698 static int igb_sw_init(struct igb_adapter *adapter)
2699 {
2700         struct e1000_hw *hw = &adapter->hw;
2701         struct net_device *netdev = adapter->netdev;
2702         struct pci_dev *pdev = adapter->pdev;
2703
2704         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2705
2706         /* set default ring sizes */
2707         adapter->tx_ring_count = IGB_DEFAULT_TXD;
2708         adapter->rx_ring_count = IGB_DEFAULT_RXD;
2709
2710         /* set default ITR values */
2711         adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2712         adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2713
2714         /* set default work limits */
2715         adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2716
2717         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2718                                   VLAN_HLEN;
2719         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2720
2721         spin_lock_init(&adapter->stats64_lock);
2722 #ifdef CONFIG_PCI_IOV
2723         switch (hw->mac.type) {
2724         case e1000_82576:
2725         case e1000_i350:
2726                 if (max_vfs > 7) {
2727                         dev_warn(&pdev->dev,
2728                                  "Maximum of 7 VFs per PF, using max\n");
2729                         max_vfs = adapter->vfs_allocated_count = 7;
2730                 } else
2731                         adapter->vfs_allocated_count = max_vfs;
2732                 if (adapter->vfs_allocated_count)
2733                         dev_warn(&pdev->dev,
2734                                  "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2735                 break;
2736         default:
2737                 break;
2738         }
2739 #endif /* CONFIG_PCI_IOV */
2740
2741         igb_init_queue_configuration(adapter);
2742
2743         /* Setup and initialize a copy of the hw vlan table array */
2744         adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2745                                        GFP_ATOMIC);
2746
2747         /* This call may decrease the number of queues */
2748         if (igb_init_interrupt_scheme(adapter, true)) {
2749                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2750                 return -ENOMEM;
2751         }
2752
2753         igb_probe_vfs(adapter);
2754
2755         /* Explicitly disable IRQ since the NIC can be in any state. */
2756         igb_irq_disable(adapter);
2757
2758         if (hw->mac.type >= e1000_i350)
2759                 adapter->flags &= ~IGB_FLAG_DMAC;
2760
2761         set_bit(__IGB_DOWN, &adapter->state);
2762         return 0;
2763 }
2764
2765 /**
2766  *  igb_open - Called when a network interface is made active
2767  *  @netdev: network interface device structure
2768  *
2769  *  Returns 0 on success, negative value on failure
2770  *
2771  *  The open entry point is called when a network interface is made
2772  *  active by the system (IFF_UP).  At this point all resources needed
2773  *  for transmit and receive operations are allocated, the interrupt
2774  *  handler is registered with the OS, the watchdog timer is started,
2775  *  and the stack is notified that the interface is ready.
2776  **/
2777 static int __igb_open(struct net_device *netdev, bool resuming)
2778 {
2779         struct igb_adapter *adapter = netdev_priv(netdev);
2780         struct e1000_hw *hw = &adapter->hw;
2781         struct pci_dev *pdev = adapter->pdev;
2782         int err;
2783         int i;
2784
2785         /* disallow open during test */
2786         if (test_bit(__IGB_TESTING, &adapter->state)) {
2787                 WARN_ON(resuming);
2788                 return -EBUSY;
2789         }
2790
2791         if (!resuming)
2792                 pm_runtime_get_sync(&pdev->dev);
2793
2794         netif_carrier_off(netdev);
2795
2796         /* allocate transmit descriptors */
2797         err = igb_setup_all_tx_resources(adapter);
2798         if (err)
2799                 goto err_setup_tx;
2800
2801         /* allocate receive descriptors */
2802         err = igb_setup_all_rx_resources(adapter);
2803         if (err)
2804                 goto err_setup_rx;
2805
2806         igb_power_up_link(adapter);
2807
2808         /* before we allocate an interrupt, we must be ready to handle it.
2809          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2810          * as soon as we call pci_request_irq, so we have to setup our
2811          * clean_rx handler before we do so.
2812          */
2813         igb_configure(adapter);
2814
2815         err = igb_request_irq(adapter);
2816         if (err)
2817                 goto err_req_irq;
2818
2819         /* Notify the stack of the actual queue counts. */
2820         err = netif_set_real_num_tx_queues(adapter->netdev,
2821                                            adapter->num_tx_queues);
2822         if (err)
2823                 goto err_set_queues;
2824
2825         err = netif_set_real_num_rx_queues(adapter->netdev,
2826                                            adapter->num_rx_queues);
2827         if (err)
2828                 goto err_set_queues;
2829
2830         /* From here on the code is the same as igb_up() */
2831         clear_bit(__IGB_DOWN, &adapter->state);
2832
2833         for (i = 0; i < adapter->num_q_vectors; i++)
2834                 napi_enable(&(adapter->q_vector[i]->napi));
2835
2836         /* Clear any pending interrupts. */
2837         rd32(E1000_ICR);
2838
2839         igb_irq_enable(adapter);
2840
2841         /* notify VFs that reset has been completed */
2842         if (adapter->vfs_allocated_count) {
2843                 u32 reg_data = rd32(E1000_CTRL_EXT);
2844                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2845                 wr32(E1000_CTRL_EXT, reg_data);
2846         }
2847
2848         netif_tx_start_all_queues(netdev);
2849
2850         if (!resuming)
2851                 pm_runtime_put(&pdev->dev);
2852
2853         /* start the watchdog. */
2854         hw->mac.get_link_status = 1;
2855         schedule_work(&adapter->watchdog_task);
2856
2857         return 0;
2858
2859 err_set_queues:
2860         igb_free_irq(adapter);
2861 err_req_irq:
2862         igb_release_hw_control(adapter);
2863         igb_power_down_link(adapter);
2864         igb_free_all_rx_resources(adapter);
2865 err_setup_rx:
2866         igb_free_all_tx_resources(adapter);
2867 err_setup_tx:
2868         igb_reset(adapter);
2869         if (!resuming)
2870                 pm_runtime_put(&pdev->dev);
2871
2872         return err;
2873 }
2874
2875 static int igb_open(struct net_device *netdev)
2876 {
2877         return __igb_open(netdev, false);
2878 }
2879
2880 /**
2881  *  igb_close - Disables a network interface
2882  *  @netdev: network interface device structure
2883  *
2884  *  Returns 0, this is not allowed to fail
2885  *
2886  *  The close entry point is called when an interface is de-activated
2887  *  by the OS.  The hardware is still under the driver's control, but
2888  *  needs to be disabled.  A global MAC reset is issued to stop the
2889  *  hardware, and all transmit and receive resources are freed.
2890  **/
2891 static int __igb_close(struct net_device *netdev, bool suspending)
2892 {
2893         struct igb_adapter *adapter = netdev_priv(netdev);
2894         struct pci_dev *pdev = adapter->pdev;
2895
2896         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2897
2898         if (!suspending)
2899                 pm_runtime_get_sync(&pdev->dev);
2900
2901         igb_down(adapter);
2902         igb_free_irq(adapter);
2903
2904         igb_free_all_tx_resources(adapter);
2905         igb_free_all_rx_resources(adapter);
2906
2907         if (!suspending)
2908                 pm_runtime_put_sync(&pdev->dev);
2909         return 0;
2910 }
2911
2912 static int igb_close(struct net_device *netdev)
2913 {
2914         return __igb_close(netdev, false);
2915 }
2916
2917 /**
2918  *  igb_setup_tx_resources - allocate Tx resources (Descriptors)
2919  *  @tx_ring: tx descriptor ring (for a specific queue) to setup
2920  *
2921  *  Return 0 on success, negative on failure
2922  **/
2923 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2924 {
2925         struct device *dev = tx_ring->dev;
2926         int size;
2927
2928         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2929
2930         tx_ring->tx_buffer_info = vzalloc(size);
2931         if (!tx_ring->tx_buffer_info)
2932                 goto err;
2933
2934         /* round up to nearest 4K */
2935         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2936         tx_ring->size = ALIGN(tx_ring->size, 4096);
2937
2938         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2939                                            &tx_ring->dma, GFP_KERNEL);
2940         if (!tx_ring->desc)
2941                 goto err;
2942
2943         tx_ring->next_to_use = 0;
2944         tx_ring->next_to_clean = 0;
2945
2946         return 0;
2947
2948 err:
2949         vfree(tx_ring->tx_buffer_info);
2950         tx_ring->tx_buffer_info = NULL;
2951         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2952         return -ENOMEM;
2953 }
2954
2955 /**
2956  *  igb_setup_all_tx_resources - wrapper to allocate Tx resources
2957  *                               (Descriptors) for all queues
2958  *  @adapter: board private structure
2959  *
2960  *  Return 0 on success, negative on failure
2961  **/
2962 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2963 {
2964         struct pci_dev *pdev = adapter->pdev;
2965         int i, err = 0;
2966
2967         for (i = 0; i < adapter->num_tx_queues; i++) {
2968                 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2969                 if (err) {
2970                         dev_err(&pdev->dev,
2971                                 "Allocation for Tx Queue %u failed\n", i);
2972                         for (i--; i >= 0; i--)
2973                                 igb_free_tx_resources(adapter->tx_ring[i]);
2974                         break;
2975                 }
2976         }
2977
2978         return err;
2979 }
2980
2981 /**
2982  *  igb_setup_tctl - configure the transmit control registers
2983  *  @adapter: Board private structure
2984  **/
2985 void igb_setup_tctl(struct igb_adapter *adapter)
2986 {
2987         struct e1000_hw *hw = &adapter->hw;
2988         u32 tctl;
2989
2990         /* disable queue 0 which is enabled by default on 82575 and 82576 */
2991         wr32(E1000_TXDCTL(0), 0);
2992
2993         /* Program the Transmit Control Register */
2994         tctl = rd32(E1000_TCTL);
2995         tctl &= ~E1000_TCTL_CT;
2996         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2997                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2998
2999         igb_config_collision_dist(hw);
3000
3001         /* Enable transmits */
3002         tctl |= E1000_TCTL_EN;
3003
3004         wr32(E1000_TCTL, tctl);
3005 }
3006
3007 /**
3008  *  igb_configure_tx_ring - Configure transmit ring after Reset
3009  *  @adapter: board private structure
3010  *  @ring: tx ring to configure
3011  *
3012  *  Configure a transmit ring after a reset.
3013  **/
3014 void igb_configure_tx_ring(struct igb_adapter *adapter,
3015                            struct igb_ring *ring)
3016 {
3017         struct e1000_hw *hw = &adapter->hw;
3018         u32 txdctl = 0;
3019         u64 tdba = ring->dma;
3020         int reg_idx = ring->reg_idx;
3021
3022         /* disable the queue */
3023         wr32(E1000_TXDCTL(reg_idx), 0);
3024         wrfl();
3025         mdelay(10);
3026
3027         wr32(E1000_TDLEN(reg_idx),
3028              ring->count * sizeof(union e1000_adv_tx_desc));
3029         wr32(E1000_TDBAL(reg_idx),
3030              tdba & 0x00000000ffffffffULL);
3031         wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3032
3033         ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3034         wr32(E1000_TDH(reg_idx), 0);
3035         writel(0, ring->tail);
3036
3037         txdctl |= IGB_TX_PTHRESH;
3038         txdctl |= IGB_TX_HTHRESH << 8;
3039         txdctl |= IGB_TX_WTHRESH << 16;
3040
3041         txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3042         wr32(E1000_TXDCTL(reg_idx), txdctl);
3043 }
3044
3045 /**
3046  *  igb_configure_tx - Configure transmit Unit after Reset
3047  *  @adapter: board private structure
3048  *
3049  *  Configure the Tx unit of the MAC after a reset.
3050  **/
3051 static void igb_configure_tx(struct igb_adapter *adapter)
3052 {
3053         int i;
3054
3055         for (i = 0; i < adapter->num_tx_queues; i++)
3056                 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3057 }
3058
3059 /**
3060  *  igb_setup_rx_resources - allocate Rx resources (Descriptors)
3061  *  @rx_ring: Rx descriptor ring (for a specific queue) to setup
3062  *
3063  *  Returns 0 on success, negative on failure
3064  **/
3065 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3066 {
3067         struct device *dev = rx_ring->dev;
3068         int size;
3069
3070         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3071
3072         rx_ring->rx_buffer_info = vzalloc(size);
3073         if (!rx_ring->rx_buffer_info)
3074                 goto err;
3075
3076         /* Round up to nearest 4K */
3077         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3078         rx_ring->size = ALIGN(rx_ring->size, 4096);
3079
3080         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3081                                            &rx_ring->dma, GFP_KERNEL);
3082         if (!rx_ring->desc)
3083                 goto err;
3084
3085         rx_ring->next_to_alloc = 0;
3086         rx_ring->next_to_clean = 0;
3087         rx_ring->next_to_use = 0;
3088
3089         return 0;
3090
3091 err:
3092         vfree(rx_ring->rx_buffer_info);
3093         rx_ring->rx_buffer_info = NULL;
3094         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3095         return -ENOMEM;
3096 }
3097
3098 /**
3099  *  igb_setup_all_rx_resources - wrapper to allocate Rx resources
3100  *                               (Descriptors) for all queues
3101  *  @adapter: board private structure
3102  *
3103  *  Return 0 on success, negative on failure
3104  **/
3105 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3106 {
3107         struct pci_dev *pdev = adapter->pdev;
3108         int i, err = 0;
3109
3110         for (i = 0; i < adapter->num_rx_queues; i++) {
3111                 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3112                 if (err) {
3113                         dev_err(&pdev->dev,
3114                                 "Allocation for Rx Queue %u failed\n", i);
3115                         for (i--; i >= 0; i--)
3116                                 igb_free_rx_resources(adapter->rx_ring[i]);
3117                         break;
3118                 }
3119         }
3120
3121         return err;
3122 }
3123
3124 /**
3125  *  igb_setup_mrqc - configure the multiple receive queue control registers
3126  *  @adapter: Board private structure
3127  **/
3128 static void igb_setup_mrqc(struct igb_adapter *adapter)
3129 {
3130         struct e1000_hw *hw = &adapter->hw;
3131         u32 mrqc, rxcsum;
3132         u32 j, num_rx_queues;
3133         static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3134                                         0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3135                                         0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3136                                         0xFA01ACBE };
3137
3138         /* Fill out hash function seeds */
3139         for (j = 0; j < 10; j++)
3140                 wr32(E1000_RSSRK(j), rsskey[j]);
3141
3142         num_rx_queues = adapter->rss_queues;
3143
3144         switch (hw->mac.type) {
3145         case e1000_82576:
3146                 /* 82576 supports 2 RSS queues for SR-IOV */
3147                 if (adapter->vfs_allocated_count)
3148                         num_rx_queues = 2;
3149                 break;
3150         default:
3151                 break;
3152         }
3153
3154         if (adapter->rss_indir_tbl_init != num_rx_queues) {
3155                 for (j = 0; j < IGB_RETA_SIZE; j++)
3156                         adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3157                 adapter->rss_indir_tbl_init = num_rx_queues;
3158         }
3159         igb_write_rss_indir_tbl(adapter);
3160
3161         /* Disable raw packet checksumming so that RSS hash is placed in
3162          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
3163          * offloads as they are enabled by default
3164          */
3165         rxcsum = rd32(E1000_RXCSUM);
3166         rxcsum |= E1000_RXCSUM_PCSD;
3167
3168         if (adapter->hw.mac.type >= e1000_82576)
3169                 /* Enable Receive Checksum Offload for SCTP */
3170                 rxcsum |= E1000_RXCSUM_CRCOFL;
3171
3172         /* Don't need to set TUOFL or IPOFL, they default to 1 */
3173         wr32(E1000_RXCSUM, rxcsum);
3174
3175         /* Generate RSS hash based on packet types, TCP/UDP
3176          * port numbers and/or IPv4/v6 src and dst addresses
3177          */
3178         mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3179                E1000_MRQC_RSS_FIELD_IPV4_TCP |
3180                E1000_MRQC_RSS_FIELD_IPV6 |
3181                E1000_MRQC_RSS_FIELD_IPV6_TCP |
3182                E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3183
3184         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3185                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3186         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3187                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3188
3189         /* If VMDq is enabled then we set the appropriate mode for that, else
3190          * we default to RSS so that an RSS hash is calculated per packet even
3191          * if we are only using one queue
3192          */
3193         if (adapter->vfs_allocated_count) {
3194                 if (hw->mac.type > e1000_82575) {
3195                         /* Set the default pool for the PF's first queue */
3196                         u32 vtctl = rd32(E1000_VT_CTL);
3197                         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3198                                    E1000_VT_CTL_DISABLE_DEF_POOL);
3199                         vtctl |= adapter->vfs_allocated_count <<
3200                                 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3201                         wr32(E1000_VT_CTL, vtctl);
3202                 }
3203                 if (adapter->rss_queues > 1)
3204                         mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3205                 else
3206                         mrqc |= E1000_MRQC_ENABLE_VMDQ;
3207         } else {
3208                 if (hw->mac.type != e1000_i211)
3209                         mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3210         }
3211         igb_vmm_control(adapter);
3212
3213         wr32(E1000_MRQC, mrqc);
3214 }
3215
3216 /**
3217  *  igb_setup_rctl - configure the receive control registers
3218  *  @adapter: Board private structure
3219  **/
3220 void igb_setup_rctl(struct igb_adapter *adapter)
3221 {
3222         struct e1000_hw *hw = &adapter->hw;
3223         u32 rctl;
3224
3225         rctl = rd32(E1000_RCTL);
3226
3227         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3228         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3229
3230         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3231                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3232
3233         /* enable stripping of CRC. It's unlikely this will break BMC
3234          * redirection as it did with e1000. Newer features require
3235          * that the HW strips the CRC.
3236          */
3237         rctl |= E1000_RCTL_SECRC;
3238
3239         /* disable store bad packets and clear size bits. */
3240         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3241
3242         /* enable LPE to prevent packets larger than max_frame_size */
3243         rctl |= E1000_RCTL_LPE;
3244
3245         /* disable queue 0 to prevent tail write w/o re-config */
3246         wr32(E1000_RXDCTL(0), 0);
3247
3248         /* Attention!!!  For SR-IOV PF driver operations you must enable
3249          * queue drop for all VF and PF queues to prevent head of line blocking
3250          * if an un-trusted VF does not provide descriptors to hardware.
3251          */
3252         if (adapter->vfs_allocated_count) {
3253                 /* set all queue drop enable bits */
3254                 wr32(E1000_QDE, ALL_QUEUES);
3255         }
3256
3257         /* This is useful for sniffing bad packets. */
3258         if (adapter->netdev->features & NETIF_F_RXALL) {
3259                 /* UPE and MPE will be handled by normal PROMISC logic
3260                  * in e1000e_set_rx_mode
3261                  */
3262                 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3263                          E1000_RCTL_BAM | /* RX All Bcast Pkts */
3264                          E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3265
3266                 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3267                           E1000_RCTL_DPF | /* Allow filtered pause */
3268                           E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3269                 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3270                  * and that breaks VLANs.
3271                  */
3272         }
3273
3274         wr32(E1000_RCTL, rctl);
3275 }
3276
3277 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3278                                    int vfn)
3279 {
3280         struct e1000_hw *hw = &adapter->hw;
3281         u32 vmolr;
3282
3283         /* if it isn't the PF check to see if VFs are enabled and
3284          * increase the size to support vlan tags
3285          */
3286         if (vfn < adapter->vfs_allocated_count &&
3287             adapter->vf_data[vfn].vlans_enabled)
3288                 size += VLAN_TAG_SIZE;
3289
3290         vmolr = rd32(E1000_VMOLR(vfn));
3291         vmolr &= ~E1000_VMOLR_RLPML_MASK;
3292         vmolr |= size | E1000_VMOLR_LPE;
3293         wr32(E1000_VMOLR(vfn), vmolr);
3294
3295         return 0;
3296 }
3297
3298 /**
3299  *  igb_rlpml_set - set maximum receive packet size
3300  *  @adapter: board private structure
3301  *
3302  *  Configure maximum receivable packet size.
3303  **/
3304 static void igb_rlpml_set(struct igb_adapter *adapter)
3305 {
3306         u32 max_frame_size = adapter->max_frame_size;
3307         struct e1000_hw *hw = &adapter->hw;
3308         u16 pf_id = adapter->vfs_allocated_count;
3309
3310         if (pf_id) {
3311                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3312                 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3313                  * to our max jumbo frame size, in case we need to enable
3314                  * jumbo frames on one of the rings later.
3315                  * This will not pass over-length frames into the default
3316                  * queue because it's gated by the VMOLR.RLPML.
3317                  */
3318                 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3319         }
3320
3321         wr32(E1000_RLPML, max_frame_size);
3322 }
3323
3324 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3325                                  int vfn, bool aupe)
3326 {
3327         struct e1000_hw *hw = &adapter->hw;
3328         u32 vmolr;
3329
3330         /* This register exists only on 82576 and newer so if we are older then
3331          * we should exit and do nothing
3332          */
3333         if (hw->mac.type < e1000_82576)
3334                 return;
3335
3336         vmolr = rd32(E1000_VMOLR(vfn));
3337         vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3338         if (aupe)
3339                 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3340         else
3341                 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3342
3343         /* clear all bits that might not be set */
3344         vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3345
3346         if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3347                 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3348         /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3349          * multicast packets
3350          */
3351         if (vfn <= adapter->vfs_allocated_count)
3352                 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3353
3354         wr32(E1000_VMOLR(vfn), vmolr);
3355 }
3356
3357 /**
3358  *  igb_configure_rx_ring - Configure a receive ring after Reset
3359  *  @adapter: board private structure
3360  *  @ring: receive ring to be configured
3361  *
3362  *  Configure the Rx unit of the MAC after a reset.
3363  **/
3364 void igb_configure_rx_ring(struct igb_adapter *adapter,
3365                            struct igb_ring *ring)
3366 {
3367         struct e1000_hw *hw = &adapter->hw;
3368         u64 rdba = ring->dma;
3369         int reg_idx = ring->reg_idx;
3370         u32 srrctl = 0, rxdctl = 0;
3371
3372         /* disable the queue */
3373         wr32(E1000_RXDCTL(reg_idx), 0);
3374
3375         /* Set DMA base address registers */
3376         wr32(E1000_RDBAL(reg_idx),
3377              rdba & 0x00000000ffffffffULL);
3378         wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3379         wr32(E1000_RDLEN(reg_idx),
3380              ring->count * sizeof(union e1000_adv_rx_desc));
3381
3382         /* initialize head and tail */
3383         ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3384         wr32(E1000_RDH(reg_idx), 0);
3385         writel(0, ring->tail);
3386
3387         /* set descriptor configuration */
3388         srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3389         srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3390         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3391         if (hw->mac.type >= e1000_82580)
3392                 srrctl |= E1000_SRRCTL_TIMESTAMP;
3393         /* Only set Drop Enable if we are supporting multiple queues */
3394         if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3395                 srrctl |= E1000_SRRCTL_DROP_EN;
3396
3397         wr32(E1000_SRRCTL(reg_idx), srrctl);
3398
3399         /* set filtering for VMDQ pools */
3400         igb_set_vmolr(adapter, reg_idx & 0x7, true);
3401
3402         rxdctl |= IGB_RX_PTHRESH;
3403         rxdctl |= IGB_RX_HTHRESH << 8;
3404         rxdctl |= IGB_RX_WTHRESH << 16;
3405
3406         /* enable receive descriptor fetching */
3407         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3408         wr32(E1000_RXDCTL(reg_idx), rxdctl);
3409 }
3410
3411 /**
3412  *  igb_configure_rx - Configure receive Unit after Reset
3413  *  @adapter: board private structure
3414  *
3415  *  Configure the Rx unit of the MAC after a reset.
3416  **/
3417 static void igb_configure_rx(struct igb_adapter *adapter)
3418 {
3419         int i;
3420
3421         /* set UTA to appropriate mode */
3422         igb_set_uta(adapter);
3423
3424         /* set the correct pool for the PF default MAC address in entry 0 */
3425         igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3426                          adapter->vfs_allocated_count);
3427
3428         /* Setup the HW Rx Head and Tail Descriptor Pointers and
3429          * the Base and Length of the Rx Descriptor Ring
3430          */
3431         for (i = 0; i < adapter->num_rx_queues; i++)
3432                 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3433 }
3434
3435 /**
3436  *  igb_free_tx_resources - Free Tx Resources per Queue
3437  *  @tx_ring: Tx descriptor ring for a specific queue
3438  *
3439  *  Free all transmit software resources
3440  **/
3441 void igb_free_tx_resources(struct igb_ring *tx_ring)
3442 {
3443         igb_clean_tx_ring(tx_ring);
3444
3445         vfree(tx_ring->tx_buffer_info);
3446         tx_ring->tx_buffer_info = NULL;
3447
3448         /* if not set, then don't free */
3449         if (!tx_ring->desc)
3450                 return;
3451
3452         dma_free_coherent(tx_ring->dev, tx_ring->size,
3453                           tx_ring->desc, tx_ring->dma);
3454
3455         tx_ring->desc = NULL;
3456 }
3457
3458 /**
3459  *  igb_free_all_tx_resources - Free Tx Resources for All Queues
3460  *  @adapter: board private structure
3461  *
3462  *  Free all transmit software resources
3463  **/
3464 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3465 {
3466         int i;
3467
3468         for (i = 0; i < adapter->num_tx_queues; i++)
3469                 igb_free_tx_resources(adapter->tx_ring[i]);
3470 }
3471
3472 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3473                                     struct igb_tx_buffer *tx_buffer)
3474 {
3475         if (tx_buffer->skb) {
3476                 dev_kfree_skb_any(tx_buffer->skb);
3477                 if (dma_unmap_len(tx_buffer, len))
3478                         dma_unmap_single(ring->dev,
3479                                          dma_unmap_addr(tx_buffer, dma),
3480                                          dma_unmap_len(tx_buffer, len),
3481                                          DMA_TO_DEVICE);
3482         } else if (dma_unmap_len(tx_buffer, len)) {
3483                 dma_unmap_page(ring->dev,
3484                                dma_unmap_addr(tx_buffer, dma),
3485                                dma_unmap_len(tx_buffer, len),
3486                                DMA_TO_DEVICE);
3487         }
3488         tx_buffer->next_to_watch = NULL;
3489         tx_buffer->skb = NULL;
3490         dma_unmap_len_set(tx_buffer, len, 0);
3491         /* buffer_info must be completely set up in the transmit path */
3492 }
3493
3494 /**
3495  *  igb_clean_tx_ring - Free Tx Buffers
3496  *  @tx_ring: ring to be cleaned
3497  **/
3498 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3499 {
3500         struct igb_tx_buffer *buffer_info;
3501         unsigned long size;
3502         u16 i;
3503
3504         if (!tx_ring->tx_buffer_info)
3505                 return;
3506         /* Free all the Tx ring sk_buffs */
3507
3508         for (i = 0; i < tx_ring->count; i++) {
3509                 buffer_info = &tx_ring->tx_buffer_info[i];
3510                 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3511         }
3512
3513         netdev_tx_reset_queue(txring_txq(tx_ring));
3514
3515         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3516         memset(tx_ring->tx_buffer_info, 0, size);
3517
3518         /* Zero out the descriptor ring */
3519         memset(tx_ring->desc, 0, tx_ring->size);
3520
3521         tx_ring->next_to_use = 0;
3522         tx_ring->next_to_clean = 0;
3523 }
3524
3525 /**
3526  *  igb_clean_all_tx_rings - Free Tx Buffers for all queues
3527  *  @adapter: board private structure
3528  **/
3529 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3530 {
3531         int i;
3532
3533         for (i = 0; i < adapter->num_tx_queues; i++)
3534                 igb_clean_tx_ring(adapter->tx_ring[i]);
3535 }
3536
3537 /**
3538  *  igb_free_rx_resources - Free Rx Resources
3539  *  @rx_ring: ring to clean the resources from
3540  *
3541  *  Free all receive software resources
3542  **/
3543 void igb_free_rx_resources(struct igb_ring *rx_ring)
3544 {
3545         igb_clean_rx_ring(rx_ring);
3546
3547         vfree(rx_ring->rx_buffer_info);
3548         rx_ring->rx_buffer_info = NULL;
3549
3550         /* if not set, then don't free */
3551         if (!rx_ring->desc)
3552                 return;
3553
3554         dma_free_coherent(rx_ring->dev, rx_ring->size,
3555                           rx_ring->desc, rx_ring->dma);
3556
3557         rx_ring->desc = NULL;
3558 }
3559
3560 /**
3561  *  igb_free_all_rx_resources - Free Rx Resources for All Queues
3562  *  @adapter: board private structure
3563  *
3564  *  Free all receive software resources
3565  **/
3566 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3567 {
3568         int i;
3569
3570         for (i = 0; i < adapter->num_rx_queues; i++)
3571                 igb_free_rx_resources(adapter->rx_ring[i]);
3572 }
3573
3574 /**
3575  *  igb_clean_rx_ring - Free Rx Buffers per Queue
3576  *  @rx_ring: ring to free buffers from
3577  **/
3578 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3579 {
3580         unsigned long size;
3581         u16 i;
3582
3583         if (rx_ring->skb)
3584                 dev_kfree_skb(rx_ring->skb);
3585         rx_ring->skb = NULL;
3586
3587         if (!rx_ring->rx_buffer_info)
3588                 return;
3589
3590         /* Free all the Rx ring sk_buffs */
3591         for (i = 0; i < rx_ring->count; i++) {
3592                 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3593
3594                 if (!buffer_info->page)
3595                         continue;
3596
3597                 dma_unmap_page(rx_ring->dev,
3598                                buffer_info->dma,
3599                                PAGE_SIZE,
3600                                DMA_FROM_DEVICE);
3601                 __free_page(buffer_info->page);
3602
3603                 buffer_info->page = NULL;
3604         }
3605
3606         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3607         memset(rx_ring->rx_buffer_info, 0, size);
3608
3609         /* Zero out the descriptor ring */
3610         memset(rx_ring->desc, 0, rx_ring->size);
3611
3612         rx_ring->next_to_alloc = 0;
3613         rx_ring->next_to_clean = 0;
3614         rx_ring->next_to_use = 0;
3615 }
3616
3617 /**
3618  *  igb_clean_all_rx_rings - Free Rx Buffers for all queues
3619  *  @adapter: board private structure
3620  **/
3621 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3622 {
3623         int i;
3624
3625         for (i = 0; i < adapter->num_rx_queues; i++)
3626                 igb_clean_rx_ring(adapter->rx_ring[i]);
3627 }
3628
3629 /**
3630  *  igb_set_mac - Change the Ethernet Address of the NIC
3631  *  @netdev: network interface device structure
3632  *  @p: pointer to an address structure
3633  *
3634  *  Returns 0 on success, negative on failure
3635  **/
3636 static int igb_set_mac(struct net_device *netdev, void *p)
3637 {
3638         struct igb_adapter *adapter = netdev_priv(netdev);
3639         struct e1000_hw *hw = &adapter->hw;
3640         struct sockaddr *addr = p;
3641
3642         if (!is_valid_ether_addr(addr->sa_data))
3643                 return -EADDRNOTAVAIL;
3644
3645         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3646         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3647
3648         /* set the correct pool for the new PF MAC address in entry 0 */
3649         igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3650                          adapter->vfs_allocated_count);
3651
3652         return 0;
3653 }
3654
3655 /**
3656  *  igb_write_mc_addr_list - write multicast addresses to MTA
3657  *  @netdev: network interface device structure
3658  *
3659  *  Writes multicast address list to the MTA hash table.
3660  *  Returns: -ENOMEM on failure
3661  *           0 on no addresses written
3662  *           X on writing X addresses to MTA
3663  **/
3664 static int igb_write_mc_addr_list(struct net_device *netdev)
3665 {
3666         struct igb_adapter *adapter = netdev_priv(netdev);
3667         struct e1000_hw *hw = &adapter->hw;
3668         struct netdev_hw_addr *ha;
3669         u8  *mta_list;
3670         int i;
3671
3672         if (netdev_mc_empty(netdev)) {
3673                 /* nothing to program, so clear mc list */
3674                 igb_update_mc_addr_list(hw, NULL, 0);
3675                 igb_restore_vf_multicasts(adapter);
3676                 return 0;
3677         }
3678
3679         mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3680         if (!mta_list)
3681                 return -ENOMEM;
3682
3683         /* The shared function expects a packed array of only addresses. */
3684         i = 0;
3685         netdev_for_each_mc_addr(ha, netdev)
3686                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3687
3688         igb_update_mc_addr_list(hw, mta_list, i);
3689         kfree(mta_list);
3690
3691         return netdev_mc_count(netdev);
3692 }
3693
3694 /**
3695  *  igb_write_uc_addr_list - write unicast addresses to RAR table
3696  *  @netdev: network interface device structure
3697  *
3698  *  Writes unicast address list to the RAR table.
3699  *  Returns: -ENOMEM on failure/insufficient address space
3700  *           0 on no addresses written
3701  *           X on writing X addresses to the RAR table
3702  **/
3703 static int igb_write_uc_addr_list(struct net_device *netdev)
3704 {
3705         struct igb_adapter *adapter = netdev_priv(netdev);
3706         struct e1000_hw *hw = &adapter->hw;
3707         unsigned int vfn = adapter->vfs_allocated_count;
3708         unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3709         int count = 0;
3710
3711         /* return ENOMEM indicating insufficient memory for addresses */
3712         if (netdev_uc_count(netdev) > rar_entries)
3713                 return -ENOMEM;
3714
3715         if (!netdev_uc_empty(netdev) && rar_entries) {
3716                 struct netdev_hw_addr *ha;
3717
3718                 netdev_for_each_uc_addr(ha, netdev) {
3719                         if (!rar_entries)
3720                                 break;
3721                         igb_rar_set_qsel(adapter, ha->addr,
3722                                          rar_entries--,
3723                                          vfn);
3724                         count++;
3725                 }
3726         }
3727         /* write the addresses in reverse order to avoid write combining */
3728         for (; rar_entries > 0 ; rar_entries--) {
3729                 wr32(E1000_RAH(rar_entries), 0);
3730                 wr32(E1000_RAL(rar_entries), 0);
3731         }
3732         wrfl();
3733
3734         return count;
3735 }
3736
3737 /**
3738  *  igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3739  *  @netdev: network interface device structure
3740  *
3741  *  The set_rx_mode entry point is called whenever the unicast or multicast
3742  *  address lists or the network interface flags are updated.  This routine is
3743  *  responsible for configuring the hardware for proper unicast, multicast,
3744  *  promiscuous mode, and all-multi behavior.
3745  **/
3746 static void igb_set_rx_mode(struct net_device *netdev)
3747 {
3748         struct igb_adapter *adapter = netdev_priv(netdev);
3749         struct e1000_hw *hw = &adapter->hw;
3750         unsigned int vfn = adapter->vfs_allocated_count;
3751         u32 rctl, vmolr = 0;
3752         int count;
3753
3754         /* Check for Promiscuous and All Multicast modes */
3755         rctl = rd32(E1000_RCTL);
3756
3757         /* clear the effected bits */
3758         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3759
3760         if (netdev->flags & IFF_PROMISC) {
3761                 /* retain VLAN HW filtering if in VT mode */
3762                 if (adapter->vfs_allocated_count)
3763                         rctl |= E1000_RCTL_VFE;
3764                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3765                 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3766         } else {
3767                 if (netdev->flags & IFF_ALLMULTI) {
3768                         rctl |= E1000_RCTL_MPE;
3769                         vmolr |= E1000_VMOLR_MPME;
3770                 } else {
3771                         /* Write addresses to the MTA, if the attempt fails
3772                          * then we should just turn on promiscuous mode so
3773                          * that we can at least receive multicast traffic
3774                          */
3775                         count = igb_write_mc_addr_list(netdev);
3776                         if (count < 0) {
3777                                 rctl |= E1000_RCTL_MPE;
3778                                 vmolr |= E1000_VMOLR_MPME;
3779                         } else if (count) {
3780                                 vmolr |= E1000_VMOLR_ROMPE;
3781                         }
3782                 }
3783                 /* Write addresses to available RAR registers, if there is not
3784                  * sufficient space to store all the addresses then enable
3785                  * unicast promiscuous mode
3786                  */
3787                 count = igb_write_uc_addr_list(netdev);
3788                 if (count < 0) {
3789                         rctl |= E1000_RCTL_UPE;
3790                         vmolr |= E1000_VMOLR_ROPE;
3791                 }
3792                 rctl |= E1000_RCTL_VFE;
3793         }
3794         wr32(E1000_RCTL, rctl);
3795
3796         /* In order to support SR-IOV and eventually VMDq it is necessary to set
3797          * the VMOLR to enable the appropriate modes.  Without this workaround
3798          * we will have issues with VLAN tag stripping not being done for frames
3799          * that are only arriving because we are the default pool
3800          */
3801         if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3802                 return;
3803
3804         vmolr |= rd32(E1000_VMOLR(vfn)) &
3805                  ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3806         wr32(E1000_VMOLR(vfn), vmolr);
3807         igb_restore_vf_multicasts(adapter);
3808 }
3809
3810 static void igb_check_wvbr(struct igb_adapter *adapter)
3811 {
3812         struct e1000_hw *hw = &adapter->hw;
3813         u32 wvbr = 0;
3814
3815         switch (hw->mac.type) {
3816         case e1000_82576:
3817         case e1000_i350:
3818                 if (!(wvbr = rd32(E1000_WVBR)))
3819                         return;
3820                 break;
3821         default:
3822                 break;
3823         }
3824
3825         adapter->wvbr |= wvbr;
3826 }
3827
3828 #define IGB_STAGGERED_QUEUE_OFFSET 8
3829
3830 static void igb_spoof_check(struct igb_adapter *adapter)
3831 {
3832         int j;
3833
3834         if (!adapter->wvbr)
3835                 return;
3836
3837         for(j = 0; j < adapter->vfs_allocated_count; j++) {
3838                 if (adapter->wvbr & (1 << j) ||
3839                     adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3840                         dev_warn(&adapter->pdev->dev,
3841                                 "Spoof event(s) detected on VF %d\n", j);
3842                         adapter->wvbr &=
3843                                 ~((1 << j) |
3844                                   (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3845                 }
3846         }
3847 }
3848
3849 /* Need to wait a few seconds after link up to get diagnostic information from
3850  * the phy
3851  */
3852 static void igb_update_phy_info(unsigned long data)
3853 {
3854         struct igb_adapter *adapter = (struct igb_adapter *) data;
3855         igb_get_phy_info(&adapter->hw);
3856 }
3857
3858 /**
3859  *  igb_has_link - check shared code for link and determine up/down
3860  *  @adapter: pointer to driver private info
3861  **/
3862 bool igb_has_link(struct igb_adapter *adapter)
3863 {
3864         struct e1000_hw *hw = &adapter->hw;
3865         bool link_active = false;
3866
3867         /* get_link_status is set on LSC (link status) interrupt or
3868          * rx sequence error interrupt.  get_link_status will stay
3869          * false until the e1000_check_for_link establishes link
3870          * for copper adapters ONLY
3871          */
3872         switch (hw->phy.media_type) {
3873         case e1000_media_type_copper:
3874                 if (!hw->mac.get_link_status)
3875                         return true;
3876         case e1000_media_type_internal_serdes:
3877                 hw->mac.ops.check_for_link(hw);
3878                 link_active = !hw->mac.get_link_status;
3879                 break;
3880         default:
3881         case e1000_media_type_unknown:
3882                 break;
3883         }
3884
3885         if (((hw->mac.type == e1000_i210) ||
3886              (hw->mac.type == e1000_i211)) &&
3887              (hw->phy.id == I210_I_PHY_ID)) {
3888                 if (!netif_carrier_ok(adapter->netdev)) {
3889                         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3890                 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
3891                         adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
3892                         adapter->link_check_timeout = jiffies;
3893                 }
3894         }
3895
3896         return link_active;
3897 }
3898
3899 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3900 {
3901         bool ret = false;
3902         u32 ctrl_ext, thstat;
3903
3904         /* check for thermal sensor event on i350 copper only */
3905         if (hw->mac.type == e1000_i350) {
3906                 thstat = rd32(E1000_THSTAT);
3907                 ctrl_ext = rd32(E1000_CTRL_EXT);
3908
3909                 if ((hw->phy.media_type == e1000_media_type_copper) &&
3910                     !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
3911                         ret = !!(thstat & event);
3912         }
3913
3914         return ret;
3915 }
3916
3917 /**
3918  *  igb_watchdog - Timer Call-back
3919  *  @data: pointer to adapter cast into an unsigned long
3920  **/
3921 static void igb_watchdog(unsigned long data)
3922 {
3923         struct igb_adapter *adapter = (struct igb_adapter *)data;
3924         /* Do the rest outside of interrupt context */
3925         schedule_work(&adapter->watchdog_task);
3926 }
3927
3928 static void igb_watchdog_task(struct work_struct *work)
3929 {
3930         struct igb_adapter *adapter = container_of(work,
3931                                                    struct igb_adapter,
3932                                                    watchdog_task);
3933         struct e1000_hw *hw = &adapter->hw;
3934         struct e1000_phy_info *phy = &hw->phy;
3935         struct net_device *netdev = adapter->netdev;
3936         u32 link;
3937         int i;
3938
3939         link = igb_has_link(adapter);
3940
3941         if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
3942                 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
3943                         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3944                 else
3945                         link = false;
3946         }
3947
3948         if (link) {
3949                 /* Cancel scheduled suspend requests. */
3950                 pm_runtime_resume(netdev->dev.parent);
3951
3952                 if (!netif_carrier_ok(netdev)) {
3953                         u32 ctrl;
3954                         hw->mac.ops.get_speed_and_duplex(hw,
3955                                                          &adapter->link_speed,
3956                                                          &adapter->link_duplex);
3957
3958                         ctrl = rd32(E1000_CTRL);
3959                         /* Links status message must follow this format */
3960                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3961                                "Duplex, Flow Control: %s\n",
3962                                netdev->name,
3963                                adapter->link_speed,
3964                                adapter->link_duplex == FULL_DUPLEX ?
3965                                "Full" : "Half",
3966                                (ctrl & E1000_CTRL_TFCE) &&
3967                                (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3968                                (ctrl & E1000_CTRL_RFCE) ?  "RX" :
3969                                (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
3970
3971                         /* check if SmartSpeed worked */
3972                         igb_check_downshift(hw);
3973                         if (phy->speed_downgraded)
3974                                 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3975
3976                         /* check for thermal sensor event */
3977                         if (igb_thermal_sensor_event(hw,
3978                             E1000_THSTAT_LINK_THROTTLE)) {
3979                                 netdev_info(netdev, "The network adapter link "
3980                                             "speed was downshifted because it "
3981                                             "overheated\n");
3982                         }
3983
3984                         /* adjust timeout factor according to speed/duplex */
3985                         adapter->tx_timeout_factor = 1;
3986                         switch (adapter->link_speed) {
3987                         case SPEED_10:
3988                                 adapter->tx_timeout_factor = 14;
3989                                 break;
3990                         case SPEED_100:
3991                                 /* maybe add some timeout factor ? */
3992                                 break;
3993                         }
3994
3995                         netif_carrier_on(netdev);
3996
3997                         igb_ping_all_vfs(adapter);
3998                         igb_check_vf_rate_limit(adapter);
3999
4000                         /* link state has changed, schedule phy info update */
4001                         if (!test_bit(__IGB_DOWN, &adapter->state))
4002                                 mod_timer(&adapter->phy_info_timer,
4003                                           round_jiffies(jiffies + 2 * HZ));
4004                 }
4005         } else {
4006                 if (netif_carrier_ok(netdev)) {
4007                         adapter->link_speed = 0;
4008                         adapter->link_duplex = 0;
4009
4010                         /* check for thermal sensor event */
4011                         if (igb_thermal_sensor_event(hw,
4012                             E1000_THSTAT_PWR_DOWN)) {
4013                                 netdev_err(netdev, "The network adapter was "
4014                                            "stopped because it overheated\n");
4015                         }
4016
4017                         /* Links status message must follow this format */
4018                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
4019                                netdev->name);
4020                         netif_carrier_off(netdev);
4021
4022                         igb_ping_all_vfs(adapter);
4023
4024                         /* link state has changed, schedule phy info update */
4025                         if (!test_bit(__IGB_DOWN, &adapter->state))
4026                                 mod_timer(&adapter->phy_info_timer,
4027                                           round_jiffies(jiffies + 2 * HZ));
4028
4029                         pm_schedule_suspend(netdev->dev.parent,
4030                                             MSEC_PER_SEC * 5);
4031                 }
4032         }
4033
4034         spin_lock(&adapter->stats64_lock);
4035         igb_update_stats(adapter, &adapter->stats64);
4036         spin_unlock(&adapter->stats64_lock);
4037
4038         for (i = 0; i < adapter->num_tx_queues; i++) {
4039                 struct igb_ring *tx_ring = adapter->tx_ring[i];
4040                 if (!netif_carrier_ok(netdev)) {
4041                         /* We've lost link, so the controller stops DMA,
4042                          * but we've got queued Tx work that's never going
4043                          * to get done, so reset controller to flush Tx.
4044                          * (Do the reset outside of interrupt context).
4045                          */
4046                         if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4047                                 adapter->tx_timeout_count++;
4048                                 schedule_work(&adapter->reset_task);
4049                                 /* return immediately since reset is imminent */
4050                                 return;
4051                         }
4052                 }
4053
4054                 /* Force detection of hung controller every watchdog period */
4055                 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4056         }
4057
4058         /* Cause software interrupt to ensure Rx ring is cleaned */
4059         if (adapter->msix_entries) {
4060                 u32 eics = 0;
4061                 for (i = 0; i < adapter->num_q_vectors; i++)
4062                         eics |= adapter->q_vector[i]->eims_value;
4063                 wr32(E1000_EICS, eics);
4064         } else {
4065                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4066         }
4067
4068         igb_spoof_check(adapter);
4069         igb_ptp_rx_hang(adapter);
4070
4071         /* Reset the timer */
4072         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4073                 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4074                         mod_timer(&adapter->watchdog_timer,
4075                                   round_jiffies(jiffies +  HZ));
4076                 else
4077                         mod_timer(&adapter->watchdog_timer,
4078                                   round_jiffies(jiffies + 2 * HZ));
4079         }
4080 }
4081
4082 enum latency_range {
4083         lowest_latency = 0,
4084         low_latency = 1,
4085         bulk_latency = 2,
4086         latency_invalid = 255
4087 };
4088
4089 /**
4090  *  igb_update_ring_itr - update the dynamic ITR value based on packet size
4091  *  @q_vector: pointer to q_vector
4092  *
4093  *  Stores a new ITR value based on strictly on packet size.  This
4094  *  algorithm is less sophisticated than that used in igb_update_itr,
4095  *  due to the difficulty of synchronizing statistics across multiple
4096  *  receive rings.  The divisors and thresholds used by this function
4097  *  were determined based on theoretical maximum wire speed and testing
4098  *  data, in order to minimize response time while increasing bulk
4099  *  throughput.
4100  *  This functionality is controlled by the InterruptThrottleRate module
4101  *  parameter (see igb_param.c)
4102  *  NOTE:  This function is called only when operating in a multiqueue
4103  *         receive environment.
4104  **/
4105 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4106 {
4107         int new_val = q_vector->itr_val;
4108         int avg_wire_size = 0;
4109         struct igb_adapter *adapter = q_vector->adapter;
4110         unsigned int packets;
4111
4112         /* For non-gigabit speeds, just fix the interrupt rate at 4000
4113          * ints/sec - ITR timer value of 120 ticks.
4114          */
4115         if (adapter->link_speed != SPEED_1000) {
4116                 new_val = IGB_4K_ITR;
4117                 goto set_itr_val;
4118         }
4119
4120         packets = q_vector->rx.total_packets;
4121         if (packets)
4122                 avg_wire_size = q_vector->rx.total_bytes / packets;
4123
4124         packets = q_vector->tx.total_packets;
4125         if (packets)
4126                 avg_wire_size = max_t(u32, avg_wire_size,
4127                                       q_vector->tx.total_bytes / packets);
4128
4129         /* if avg_wire_size isn't set no work was done */
4130         if (!avg_wire_size)
4131                 goto clear_counts;
4132
4133         /* Add 24 bytes to size to account for CRC, preamble, and gap */
4134         avg_wire_size += 24;
4135
4136         /* Don't starve jumbo frames */
4137         avg_wire_size = min(avg_wire_size, 3000);
4138
4139         /* Give a little boost to mid-size frames */
4140         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4141                 new_val = avg_wire_size / 3;
4142         else
4143                 new_val = avg_wire_size / 2;
4144
4145         /* conservative mode (itr 3) eliminates the lowest_latency setting */
4146         if (new_val < IGB_20K_ITR &&
4147             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4148              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4149                 new_val = IGB_20K_ITR;
4150
4151 set_itr_val:
4152         if (new_val != q_vector->itr_val) {
4153                 q_vector->itr_val = new_val;
4154                 q_vector->set_itr = 1;
4155         }
4156 clear_counts:
4157         q_vector->rx.total_bytes = 0;
4158         q_vector->rx.total_packets = 0;
4159         q_vector->tx.total_bytes = 0;
4160         q_vector->tx.total_packets = 0;
4161 }
4162
4163 /**
4164  *  igb_update_itr - update the dynamic ITR value based on statistics
4165  *  @q_vector: pointer to q_vector
4166  *  @ring_container: ring info to update the itr for
4167  *
4168  *  Stores a new ITR value based on packets and byte
4169  *  counts during the last interrupt.  The advantage of per interrupt
4170  *  computation is faster updates and more accurate ITR for the current
4171  *  traffic pattern.  Constants in this function were computed
4172  *  based on theoretical maximum wire speed and thresholds were set based
4173  *  on testing data as well as attempting to minimize response time
4174  *  while increasing bulk throughput.
4175  *  this functionality is controlled by the InterruptThrottleRate module
4176  *  parameter (see igb_param.c)
4177  *  NOTE:  These calculations are only valid when operating in a single-
4178  *         queue environment.
4179  **/
4180 static void igb_update_itr(struct igb_q_vector *q_vector,
4181                            struct igb_ring_container *ring_container)
4182 {
4183         unsigned int packets = ring_container->total_packets;
4184         unsigned int bytes = ring_container->total_bytes;
4185         u8 itrval = ring_container->itr;
4186
4187         /* no packets, exit with status unchanged */
4188         if (packets == 0)
4189                 return;
4190
4191         switch (itrval) {
4192         case lowest_latency:
4193                 /* handle TSO and jumbo frames */
4194                 if (bytes/packets > 8000)
4195                         itrval = bulk_latency;
4196                 else if ((packets < 5) && (bytes > 512))
4197                         itrval = low_latency;
4198                 break;
4199         case low_latency:  /* 50 usec aka 20000 ints/s */
4200                 if (bytes > 10000) {
4201                         /* this if handles the TSO accounting */
4202                         if (bytes/packets > 8000) {
4203                                 itrval = bulk_latency;
4204                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
4205                                 itrval = bulk_latency;
4206                         } else if ((packets > 35)) {
4207                                 itrval = lowest_latency;
4208                         }
4209                 } else if (bytes/packets > 2000) {
4210                         itrval = bulk_latency;
4211                 } else if (packets <= 2 && bytes < 512) {
4212                         itrval = lowest_latency;
4213                 }
4214                 break;
4215         case bulk_latency: /* 250 usec aka 4000 ints/s */
4216                 if (bytes > 25000) {
4217                         if (packets > 35)
4218                                 itrval = low_latency;
4219                 } else if (bytes < 1500) {
4220                         itrval = low_latency;
4221                 }
4222                 break;
4223         }
4224
4225         /* clear work counters since we have the values we need */
4226         ring_container->total_bytes = 0;
4227         ring_container->total_packets = 0;
4228
4229         /* write updated itr to ring container */
4230         ring_container->itr = itrval;
4231 }
4232
4233 static void igb_set_itr(struct igb_q_vector *q_vector)
4234 {
4235         struct igb_adapter *adapter = q_vector->adapter;
4236         u32 new_itr = q_vector->itr_val;
4237         u8 current_itr = 0;
4238
4239         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4240         if (adapter->link_speed != SPEED_1000) {
4241                 current_itr = 0;
4242                 new_itr = IGB_4K_ITR;
4243                 goto set_itr_now;
4244         }
4245
4246         igb_update_itr(q_vector, &q_vector->tx);
4247         igb_update_itr(q_vector, &q_vector->rx);
4248
4249         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4250
4251         /* conservative mode (itr 3) eliminates the lowest_latency setting */
4252         if (current_itr == lowest_latency &&
4253             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4254              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4255                 current_itr = low_latency;
4256
4257         switch (current_itr) {
4258         /* counts and packets in update_itr are dependent on these numbers */
4259         case lowest_latency:
4260                 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4261                 break;
4262         case low_latency:
4263                 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4264                 break;
4265         case bulk_latency:
4266                 new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
4267                 break;
4268         default:
4269                 break;
4270         }
4271
4272 set_itr_now:
4273         if (new_itr != q_vector->itr_val) {
4274                 /* this attempts to bias the interrupt rate towards Bulk
4275                  * by adding intermediate steps when interrupt rate is
4276                  * increasing
4277                  */
4278                 new_itr = new_itr > q_vector->itr_val ?
4279                           max((new_itr * q_vector->itr_val) /
4280                           (new_itr + (q_vector->itr_val >> 2)),
4281                           new_itr) : new_itr;
4282                 /* Don't write the value here; it resets the adapter's
4283                  * internal timer, and causes us to delay far longer than
4284                  * we should between interrupts.  Instead, we write the ITR
4285                  * value at the beginning of the next interrupt so the timing
4286                  * ends up being correct.
4287                  */
4288                 q_vector->itr_val = new_itr;
4289                 q_vector->set_itr = 1;
4290         }
4291 }
4292
4293 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4294                             u32 type_tucmd, u32 mss_l4len_idx)
4295 {
4296         struct e1000_adv_tx_context_desc *context_desc;
4297         u16 i = tx_ring->next_to_use;
4298
4299         context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4300
4301         i++;
4302         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4303
4304         /* set bits to identify this as an advanced context descriptor */
4305         type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4306
4307         /* For 82575, context index must be unique per ring. */
4308         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4309                 mss_l4len_idx |= tx_ring->reg_idx << 4;
4310
4311         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
4312         context_desc->seqnum_seed       = 0;
4313         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
4314         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
4315 }
4316
4317 static int igb_tso(struct igb_ring *tx_ring,
4318                    struct igb_tx_buffer *first,
4319                    u8 *hdr_len)
4320 {
4321         struct sk_buff *skb = first->skb;
4322         u32 vlan_macip_lens, type_tucmd;
4323         u32 mss_l4len_idx, l4len;
4324
4325         if (skb->ip_summed != CHECKSUM_PARTIAL)
4326                 return 0;
4327
4328         if (!skb_is_gso(skb))
4329                 return 0;
4330
4331         if (skb_header_cloned(skb)) {
4332                 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4333                 if (err)
4334                         return err;
4335         }
4336
4337         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4338         type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4339
4340         if (first->protocol == __constant_htons(ETH_P_IP)) {
4341                 struct iphdr *iph = ip_hdr(skb);
4342                 iph->tot_len = 0;
4343                 iph->check = 0;
4344                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4345                                                          iph->daddr, 0,
4346                                                          IPPROTO_TCP,
4347                                                          0);
4348                 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4349                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4350                                    IGB_TX_FLAGS_CSUM |
4351                                    IGB_TX_FLAGS_IPV4;
4352         } else if (skb_is_gso_v6(skb)) {
4353                 ipv6_hdr(skb)->payload_len = 0;
4354                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4355                                                        &ipv6_hdr(skb)->daddr,
4356                                                        0, IPPROTO_TCP, 0);
4357                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4358                                    IGB_TX_FLAGS_CSUM;
4359         }
4360
4361         /* compute header lengths */
4362         l4len = tcp_hdrlen(skb);
4363         *hdr_len = skb_transport_offset(skb) + l4len;
4364
4365         /* update gso size and bytecount with header size */
4366         first->gso_segs = skb_shinfo(skb)->gso_segs;
4367         first->bytecount += (first->gso_segs - 1) * *hdr_len;
4368
4369         /* MSS L4LEN IDX */
4370         mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4371         mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4372
4373         /* VLAN MACLEN IPLEN */
4374         vlan_macip_lens = skb_network_header_len(skb);
4375         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4376         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4377
4378         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4379
4380         return 1;
4381 }
4382
4383 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4384 {
4385         struct sk_buff *skb = first->skb;
4386         u32 vlan_macip_lens = 0;
4387         u32 mss_l4len_idx = 0;
4388         u32 type_tucmd = 0;
4389
4390         if (skb->ip_summed != CHECKSUM_PARTIAL) {
4391                 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4392                         return;
4393         } else {
4394                 u8 l4_hdr = 0;
4395                 switch (first->protocol) {
4396                 case __constant_htons(ETH_P_IP):
4397                         vlan_macip_lens |= skb_network_header_len(skb);
4398                         type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4399                         l4_hdr = ip_hdr(skb)->protocol;
4400                         break;
4401                 case __constant_htons(ETH_P_IPV6):
4402                         vlan_macip_lens |= skb_network_header_len(skb);
4403                         l4_hdr = ipv6_hdr(skb)->nexthdr;
4404                         break;
4405                 default:
4406                         if (unlikely(net_ratelimit())) {
4407                                 dev_warn(tx_ring->dev,
4408                                          "partial checksum but proto=%x!\n",
4409                                          first->protocol);
4410                         }
4411                         break;
4412                 }
4413
4414                 switch (l4_hdr) {
4415                 case IPPROTO_TCP:
4416                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4417                         mss_l4len_idx = tcp_hdrlen(skb) <<
4418                                         E1000_ADVTXD_L4LEN_SHIFT;
4419                         break;
4420                 case IPPROTO_SCTP:
4421                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4422                         mss_l4len_idx = sizeof(struct sctphdr) <<
4423                                         E1000_ADVTXD_L4LEN_SHIFT;
4424                         break;
4425                 case IPPROTO_UDP:
4426                         mss_l4len_idx = sizeof(struct udphdr) <<
4427                                         E1000_ADVTXD_L4LEN_SHIFT;
4428                         break;
4429                 default:
4430                         if (unlikely(net_ratelimit())) {
4431                                 dev_warn(tx_ring->dev,
4432                                          "partial checksum but l4 proto=%x!\n",
4433                                          l4_hdr);
4434                         }
4435                         break;
4436                 }
4437
4438                 /* update TX checksum flag */
4439                 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4440         }
4441
4442         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4443         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4444
4445         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4446 }
4447
4448 #define IGB_SET_FLAG(_input, _flag, _result) \
4449         ((_flag <= _result) ? \
4450          ((u32)(_input & _flag) * (_result / _flag)) : \
4451          ((u32)(_input & _flag) / (_flag / _result)))
4452
4453 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4454 {
4455         /* set type for advanced descriptor with frame checksum insertion */
4456         u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4457                        E1000_ADVTXD_DCMD_DEXT |
4458                        E1000_ADVTXD_DCMD_IFCS;
4459
4460         /* set HW vlan bit if vlan is present */
4461         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4462                                  (E1000_ADVTXD_DCMD_VLE));
4463
4464         /* set segmentation bits for TSO */
4465         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4466                                  (E1000_ADVTXD_DCMD_TSE));
4467
4468         /* set timestamp bit if present */
4469         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4470                                  (E1000_ADVTXD_MAC_TSTAMP));
4471
4472         /* insert frame checksum */
4473         cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4474
4475         return cmd_type;
4476 }
4477
4478 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4479                                  union e1000_adv_tx_desc *tx_desc,
4480                                  u32 tx_flags, unsigned int paylen)
4481 {
4482         u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4483
4484         /* 82575 requires a unique index per ring */
4485         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4486                 olinfo_status |= tx_ring->reg_idx << 4;
4487
4488         /* insert L4 checksum */
4489         olinfo_status |= IGB_SET_FLAG(tx_flags,
4490                                       IGB_TX_FLAGS_CSUM,
4491                                       (E1000_TXD_POPTS_TXSM << 8));
4492
4493         /* insert IPv4 checksum */
4494         olinfo_status |= IGB_SET_FLAG(tx_flags,
4495                                       IGB_TX_FLAGS_IPV4,
4496                                       (E1000_TXD_POPTS_IXSM << 8));
4497
4498         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4499 }
4500
4501 static void igb_tx_map(struct igb_ring *tx_ring,
4502                        struct igb_tx_buffer *first,
4503                        const u8 hdr_len)
4504 {
4505         struct sk_buff *skb = first->skb;
4506         struct igb_tx_buffer *tx_buffer;
4507         union e1000_adv_tx_desc *tx_desc;
4508         struct skb_frag_struct *frag;
4509         dma_addr_t dma;
4510         unsigned int data_len, size;
4511         u32 tx_flags = first->tx_flags;
4512         u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4513         u16 i = tx_ring->next_to_use;
4514
4515         tx_desc = IGB_TX_DESC(tx_ring, i);
4516
4517         igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4518
4519         size = skb_headlen(skb);
4520         data_len = skb->data_len;
4521
4522         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4523
4524         tx_buffer = first;
4525
4526         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4527                 if (dma_mapping_error(tx_ring->dev, dma))
4528                         goto dma_error;
4529
4530                 /* record length, and DMA address */
4531                 dma_unmap_len_set(tx_buffer, len, size);
4532                 dma_unmap_addr_set(tx_buffer, dma, dma);
4533
4534                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4535
4536                 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4537                         tx_desc->read.cmd_type_len =
4538                                 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4539
4540                         i++;
4541                         tx_desc++;
4542                         if (i == tx_ring->count) {
4543                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
4544                                 i = 0;
4545                         }
4546                         tx_desc->read.olinfo_status = 0;
4547
4548                         dma += IGB_MAX_DATA_PER_TXD;
4549                         size -= IGB_MAX_DATA_PER_TXD;
4550
4551                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
4552                 }
4553
4554                 if (likely(!data_len))
4555                         break;
4556
4557                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4558
4559                 i++;
4560                 tx_desc++;
4561                 if (i == tx_ring->count) {
4562                         tx_desc = IGB_TX_DESC(tx_ring, 0);
4563                         i = 0;
4564                 }
4565                 tx_desc->read.olinfo_status = 0;
4566
4567                 size = skb_frag_size(frag);
4568                 data_len -= size;
4569
4570                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4571                                        size, DMA_TO_DEVICE);
4572
4573                 tx_buffer = &tx_ring->tx_buffer_info[i];
4574         }
4575
4576         /* write last descriptor with RS and EOP bits */
4577         cmd_type |= size | IGB_TXD_DCMD;
4578         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4579
4580         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4581
4582         /* set the timestamp */
4583         first->time_stamp = jiffies;
4584
4585         /* Force memory writes to complete before letting h/w know there
4586          * are new descriptors to fetch.  (Only applicable for weak-ordered
4587          * memory model archs, such as IA-64).
4588          *
4589          * We also need this memory barrier to make certain all of the
4590          * status bits have been updated before next_to_watch is written.
4591          */
4592         wmb();
4593
4594         /* set next_to_watch value indicating a packet is present */
4595         first->next_to_watch = tx_desc;
4596
4597         i++;
4598         if (i == tx_ring->count)
4599                 i = 0;
4600
4601         tx_ring->next_to_use = i;
4602
4603         writel(i, tx_ring->tail);
4604
4605         /* we need this if more than one processor can write to our tail
4606          * at a time, it synchronizes IO on IA64/Altix systems
4607          */
4608         mmiowb();
4609
4610         return;
4611
4612 dma_error:
4613         dev_err(tx_ring->dev, "TX DMA map failed\n");
4614
4615         /* clear dma mappings for failed tx_buffer_info map */
4616         for (;;) {
4617                 tx_buffer = &tx_ring->tx_buffer_info[i];
4618                 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4619                 if (tx_buffer == first)
4620                         break;
4621                 if (i == 0)
4622                         i = tx_ring->count;
4623                 i--;
4624         }
4625
4626         tx_ring->next_to_use = i;
4627 }
4628
4629 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4630 {
4631         struct net_device *netdev = tx_ring->netdev;
4632
4633         netif_stop_subqueue(netdev, tx_ring->queue_index);
4634
4635         /* Herbert's original patch had:
4636          *  smp_mb__after_netif_stop_queue();
4637          * but since that doesn't exist yet, just open code it.
4638          */
4639         smp_mb();
4640
4641         /* We need to check again in a case another CPU has just
4642          * made room available.
4643          */
4644         if (igb_desc_unused(tx_ring) < size)
4645                 return -EBUSY;
4646
4647         /* A reprieve! */
4648         netif_wake_subqueue(netdev, tx_ring->queue_index);
4649
4650         u64_stats_update_begin(&tx_ring->tx_syncp2);
4651         tx_ring->tx_stats.restart_queue2++;
4652         u64_stats_update_end(&tx_ring->tx_syncp2);
4653
4654         return 0;
4655 }
4656
4657 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4658 {
4659         if (igb_desc_unused(tx_ring) >= size)
4660                 return 0;
4661         return __igb_maybe_stop_tx(tx_ring, size);
4662 }
4663
4664 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4665                                 struct igb_ring *tx_ring)
4666 {
4667         struct igb_tx_buffer *first;
4668         int tso;
4669         u32 tx_flags = 0;
4670         u16 count = TXD_USE_COUNT(skb_headlen(skb));
4671         __be16 protocol = vlan_get_protocol(skb);
4672         u8 hdr_len = 0;
4673
4674         /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4675          *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4676          *       + 2 desc gap to keep tail from touching head,
4677          *       + 1 desc for context descriptor,
4678          * otherwise try next time
4679          */
4680         if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4681                 unsigned short f;
4682                 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4683                         count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4684         } else {
4685                 count += skb_shinfo(skb)->nr_frags;
4686         }
4687
4688         if (igb_maybe_stop_tx(tx_ring, count + 3)) {
4689                 /* this is a hard error */
4690                 return NETDEV_TX_BUSY;
4691         }
4692
4693         /* record the location of the first descriptor for this packet */
4694         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4695         first->skb = skb;
4696         first->bytecount = skb->len;
4697         first->gso_segs = 1;
4698
4699         skb_tx_timestamp(skb);
4700
4701         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4702                 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4703
4704                 if (!(adapter->ptp_tx_skb)) {
4705                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4706                         tx_flags |= IGB_TX_FLAGS_TSTAMP;
4707
4708                         adapter->ptp_tx_skb = skb_get(skb);
4709                         adapter->ptp_tx_start = jiffies;
4710                         if (adapter->hw.mac.type == e1000_82576)
4711                                 schedule_work(&adapter->ptp_tx_work);
4712                 }
4713         }
4714
4715         if (vlan_tx_tag_present(skb)) {
4716                 tx_flags |= IGB_TX_FLAGS_VLAN;
4717                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4718         }
4719
4720         /* record initial flags and protocol */
4721         first->tx_flags = tx_flags;
4722         first->protocol = protocol;
4723
4724         tso = igb_tso(tx_ring, first, &hdr_len);
4725         if (tso < 0)
4726                 goto out_drop;
4727         else if (!tso)
4728                 igb_tx_csum(tx_ring, first);
4729
4730         igb_tx_map(tx_ring, first, hdr_len);
4731
4732         /* Make sure there is space in the ring for the next send. */
4733         igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4734
4735         return NETDEV_TX_OK;
4736
4737 out_drop:
4738         igb_unmap_and_free_tx_resource(tx_ring, first);
4739
4740         return NETDEV_TX_OK;
4741 }
4742
4743 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4744                                                     struct sk_buff *skb)
4745 {
4746         unsigned int r_idx = skb->queue_mapping;
4747
4748         if (r_idx >= adapter->num_tx_queues)
4749                 r_idx = r_idx % adapter->num_tx_queues;
4750
4751         return adapter->tx_ring[r_idx];
4752 }
4753
4754 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4755                                   struct net_device *netdev)
4756 {
4757         struct igb_adapter *adapter = netdev_priv(netdev);
4758
4759         if (test_bit(__IGB_DOWN, &adapter->state)) {
4760                 dev_kfree_skb_any(skb);
4761                 return NETDEV_TX_OK;
4762         }
4763
4764         if (skb->len <= 0) {
4765                 dev_kfree_skb_any(skb);
4766                 return NETDEV_TX_OK;
4767         }
4768
4769         /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
4770          * in order to meet this minimum size requirement.
4771          */
4772         if (unlikely(skb->len < 17)) {
4773                 if (skb_pad(skb, 17 - skb->len))
4774                         return NETDEV_TX_OK;
4775                 skb->len = 17;
4776                 skb_set_tail_pointer(skb, 17);
4777         }
4778
4779         return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4780 }
4781
4782 /**
4783  *  igb_tx_timeout - Respond to a Tx Hang
4784  *  @netdev: network interface device structure
4785  **/
4786 static void igb_tx_timeout(struct net_device *netdev)
4787 {
4788         struct igb_adapter *adapter = netdev_priv(netdev);
4789         struct e1000_hw *hw = &adapter->hw;
4790
4791         /* Do the reset outside of interrupt context */
4792         adapter->tx_timeout_count++;
4793
4794         if (hw->mac.type >= e1000_82580)
4795                 hw->dev_spec._82575.global_device_reset = true;
4796
4797         schedule_work(&adapter->reset_task);
4798         wr32(E1000_EICS,
4799              (adapter->eims_enable_mask & ~adapter->eims_other));
4800 }
4801
4802 static void igb_reset_task(struct work_struct *work)
4803 {
4804         struct igb_adapter *adapter;
4805         adapter = container_of(work, struct igb_adapter, reset_task);
4806
4807         igb_dump(adapter);
4808         netdev_err(adapter->netdev, "Reset adapter\n");
4809         igb_reinit_locked(adapter);
4810 }
4811
4812 /**
4813  *  igb_get_stats64 - Get System Network Statistics
4814  *  @netdev: network interface device structure
4815  *  @stats: rtnl_link_stats64 pointer
4816  **/
4817 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4818                                                 struct rtnl_link_stats64 *stats)
4819 {
4820         struct igb_adapter *adapter = netdev_priv(netdev);
4821
4822         spin_lock(&adapter->stats64_lock);
4823         igb_update_stats(adapter, &adapter->stats64);
4824         memcpy(stats, &adapter->stats64, sizeof(*stats));
4825         spin_unlock(&adapter->stats64_lock);
4826
4827         return stats;
4828 }
4829
4830 /**
4831  *  igb_change_mtu - Change the Maximum Transfer Unit
4832  *  @netdev: network interface device structure
4833  *  @new_mtu: new value for maximum frame size
4834  *
4835  *  Returns 0 on success, negative on failure
4836  **/
4837 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4838 {
4839         struct igb_adapter *adapter = netdev_priv(netdev);
4840         struct pci_dev *pdev = adapter->pdev;
4841         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4842
4843         if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4844                 dev_err(&pdev->dev, "Invalid MTU setting\n");
4845                 return -EINVAL;
4846         }
4847
4848 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4849         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4850                 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4851                 return -EINVAL;
4852         }
4853
4854         /* adjust max frame to be at least the size of a standard frame */
4855         if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4856                 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4857
4858         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4859                 msleep(1);
4860
4861         /* igb_down has a dependency on max_frame_size */
4862         adapter->max_frame_size = max_frame;
4863
4864         if (netif_running(netdev))
4865                 igb_down(adapter);
4866
4867         dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4868                  netdev->mtu, new_mtu);
4869         netdev->mtu = new_mtu;
4870
4871         if (netif_running(netdev))
4872                 igb_up(adapter);
4873         else
4874                 igb_reset(adapter);
4875
4876         clear_bit(__IGB_RESETTING, &adapter->state);
4877
4878         return 0;
4879 }
4880
4881 /**
4882  *  igb_update_stats - Update the board statistics counters
4883  *  @adapter: board private structure
4884  **/
4885 void igb_update_stats(struct igb_adapter *adapter,
4886                       struct rtnl_link_stats64 *net_stats)
4887 {
4888         struct e1000_hw *hw = &adapter->hw;
4889         struct pci_dev *pdev = adapter->pdev;
4890         u32 reg, mpc;
4891         u16 phy_tmp;
4892         int i;
4893         u64 bytes, packets;
4894         unsigned int start;
4895         u64 _bytes, _packets;
4896
4897 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4898
4899         /* Prevent stats update while adapter is being reset, or if the pci
4900          * connection is down.
4901          */
4902         if (adapter->link_speed == 0)
4903                 return;
4904         if (pci_channel_offline(pdev))
4905                 return;
4906
4907         bytes = 0;
4908         packets = 0;
4909
4910         rcu_read_lock();
4911         for (i = 0; i < adapter->num_rx_queues; i++) {
4912                 u32 rqdpc = rd32(E1000_RQDPC(i));
4913                 struct igb_ring *ring = adapter->rx_ring[i];
4914
4915                 if (rqdpc) {
4916                         ring->rx_stats.drops += rqdpc;
4917                         net_stats->rx_fifo_errors += rqdpc;
4918                 }
4919
4920                 do {
4921                         start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4922                         _bytes = ring->rx_stats.bytes;
4923                         _packets = ring->rx_stats.packets;
4924                 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4925                 bytes += _bytes;
4926                 packets += _packets;
4927         }
4928
4929         net_stats->rx_bytes = bytes;
4930         net_stats->rx_packets = packets;
4931
4932         bytes = 0;
4933         packets = 0;
4934         for (i = 0; i < adapter->num_tx_queues; i++) {
4935                 struct igb_ring *ring = adapter->tx_ring[i];
4936                 do {
4937                         start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4938                         _bytes = ring->tx_stats.bytes;
4939                         _packets = ring->tx_stats.packets;
4940                 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4941                 bytes += _bytes;
4942                 packets += _packets;
4943         }
4944         net_stats->tx_bytes = bytes;
4945         net_stats->tx_packets = packets;
4946         rcu_read_unlock();
4947
4948         /* read stats registers */
4949         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4950         adapter->stats.gprc += rd32(E1000_GPRC);
4951         adapter->stats.gorc += rd32(E1000_GORCL);
4952         rd32(E1000_GORCH); /* clear GORCL */
4953         adapter->stats.bprc += rd32(E1000_BPRC);
4954         adapter->stats.mprc += rd32(E1000_MPRC);
4955         adapter->stats.roc += rd32(E1000_ROC);
4956
4957         adapter->stats.prc64 += rd32(E1000_PRC64);
4958         adapter->stats.prc127 += rd32(E1000_PRC127);
4959         adapter->stats.prc255 += rd32(E1000_PRC255);
4960         adapter->stats.prc511 += rd32(E1000_PRC511);
4961         adapter->stats.prc1023 += rd32(E1000_PRC1023);
4962         adapter->stats.prc1522 += rd32(E1000_PRC1522);
4963         adapter->stats.symerrs += rd32(E1000_SYMERRS);
4964         adapter->stats.sec += rd32(E1000_SEC);
4965
4966         mpc = rd32(E1000_MPC);
4967         adapter->stats.mpc += mpc;
4968         net_stats->rx_fifo_errors += mpc;
4969         adapter->stats.scc += rd32(E1000_SCC);
4970         adapter->stats.ecol += rd32(E1000_ECOL);
4971         adapter->stats.mcc += rd32(E1000_MCC);
4972         adapter->stats.latecol += rd32(E1000_LATECOL);
4973         adapter->stats.dc += rd32(E1000_DC);
4974         adapter->stats.rlec += rd32(E1000_RLEC);
4975         adapter->stats.xonrxc += rd32(E1000_XONRXC);
4976         adapter->stats.xontxc += rd32(E1000_XONTXC);
4977         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4978         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4979         adapter->stats.fcruc += rd32(E1000_FCRUC);
4980         adapter->stats.gptc += rd32(E1000_GPTC);
4981         adapter->stats.gotc += rd32(E1000_GOTCL);
4982         rd32(E1000_GOTCH); /* clear GOTCL */
4983         adapter->stats.rnbc += rd32(E1000_RNBC);
4984         adapter->stats.ruc += rd32(E1000_RUC);
4985         adapter->stats.rfc += rd32(E1000_RFC);
4986         adapter->stats.rjc += rd32(E1000_RJC);
4987         adapter->stats.tor += rd32(E1000_TORH);
4988         adapter->stats.tot += rd32(E1000_TOTH);
4989         adapter->stats.tpr += rd32(E1000_TPR);
4990
4991         adapter->stats.ptc64 += rd32(E1000_PTC64);
4992         adapter->stats.ptc127 += rd32(E1000_PTC127);
4993         adapter->stats.ptc255 += rd32(E1000_PTC255);
4994         adapter->stats.ptc511 += rd32(E1000_PTC511);
4995         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4996         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4997
4998         adapter->stats.mptc += rd32(E1000_MPTC);
4999         adapter->stats.bptc += rd32(E1000_BPTC);
5000
5001         adapter->stats.tpt += rd32(E1000_TPT);
5002         adapter->stats.colc += rd32(E1000_COLC);
5003
5004         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5005         /* read internal phy specific stats */
5006         reg = rd32(E1000_CTRL_EXT);
5007         if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5008                 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5009
5010                 /* this stat has invalid values on i210/i211 */
5011                 if ((hw->mac.type != e1000_i210) &&
5012                     (hw->mac.type != e1000_i211))
5013                         adapter->stats.tncrs += rd32(E1000_TNCRS);
5014         }
5015
5016         adapter->stats.tsctc += rd32(E1000_TSCTC);
5017         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5018
5019         adapter->stats.iac += rd32(E1000_IAC);
5020         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5021         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5022         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5023         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5024         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5025         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5026         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5027         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5028
5029         /* Fill out the OS statistics structure */
5030         net_stats->multicast = adapter->stats.mprc;
5031         net_stats->collisions = adapter->stats.colc;
5032
5033         /* Rx Errors */
5034
5035         /* RLEC on some newer hardware can be incorrect so build
5036          * our own version based on RUC and ROC
5037          */
5038         net_stats->rx_errors = adapter->stats.rxerrc +
5039                 adapter->stats.crcerrs + adapter->stats.algnerrc +
5040                 adapter->stats.ruc + adapter->stats.roc +
5041                 adapter->stats.cexterr;
5042         net_stats->rx_length_errors = adapter->stats.ruc +
5043                                       adapter->stats.roc;
5044         net_stats->rx_crc_errors = adapter->stats.crcerrs;
5045         net_stats->rx_frame_errors = adapter->stats.algnerrc;
5046         net_stats->rx_missed_errors = adapter->stats.mpc;
5047
5048         /* Tx Errors */
5049         net_stats->tx_errors = adapter->stats.ecol +
5050                                adapter->stats.latecol;
5051         net_stats->tx_aborted_errors = adapter->stats.ecol;
5052         net_stats->tx_window_errors = adapter->stats.latecol;
5053         net_stats->tx_carrier_errors = adapter->stats.tncrs;
5054
5055         /* Tx Dropped needs to be maintained elsewhere */
5056
5057         /* Phy Stats */
5058         if (hw->phy.media_type == e1000_media_type_copper) {
5059                 if ((adapter->link_speed == SPEED_1000) &&
5060                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
5061                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5062                         adapter->phy_stats.idle_errors += phy_tmp;
5063                 }
5064         }
5065
5066         /* Management Stats */
5067         adapter->stats.mgptc += rd32(E1000_MGTPTC);
5068         adapter->stats.mgprc += rd32(E1000_MGTPRC);
5069         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5070
5071         /* OS2BMC Stats */
5072         reg = rd32(E1000_MANC);
5073         if (reg & E1000_MANC_EN_BMC2OS) {
5074                 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5075                 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5076                 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5077                 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5078         }
5079 }
5080
5081 static irqreturn_t igb_msix_other(int irq, void *data)
5082 {
5083         struct igb_adapter *adapter = data;
5084         struct e1000_hw *hw = &adapter->hw;
5085         u32 icr = rd32(E1000_ICR);
5086         /* reading ICR causes bit 31 of EICR to be cleared */
5087
5088         if (icr & E1000_ICR_DRSTA)
5089                 schedule_work(&adapter->reset_task);
5090
5091         if (icr & E1000_ICR_DOUTSYNC) {
5092                 /* HW is reporting DMA is out of sync */
5093                 adapter->stats.doosync++;
5094                 /* The DMA Out of Sync is also indication of a spoof event
5095                  * in IOV mode. Check the Wrong VM Behavior register to
5096                  * see if it is really a spoof event.
5097                  */
5098                 igb_check_wvbr(adapter);
5099         }
5100
5101         /* Check for a mailbox event */
5102         if (icr & E1000_ICR_VMMB)
5103                 igb_msg_task(adapter);
5104
5105         if (icr & E1000_ICR_LSC) {
5106                 hw->mac.get_link_status = 1;
5107                 /* guard against interrupt when we're going down */
5108                 if (!test_bit(__IGB_DOWN, &adapter->state))
5109                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5110         }
5111
5112         if (icr & E1000_ICR_TS) {
5113                 u32 tsicr = rd32(E1000_TSICR);
5114
5115                 if (tsicr & E1000_TSICR_TXTS) {
5116                         /* acknowledge the interrupt */
5117                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5118                         /* retrieve hardware timestamp */
5119                         schedule_work(&adapter->ptp_tx_work);
5120                 }
5121         }
5122
5123         wr32(E1000_EIMS, adapter->eims_other);
5124
5125         return IRQ_HANDLED;
5126 }
5127
5128 static void igb_write_itr(struct igb_q_vector *q_vector)
5129 {
5130         struct igb_adapter *adapter = q_vector->adapter;
5131         u32 itr_val = q_vector->itr_val & 0x7FFC;
5132
5133         if (!q_vector->set_itr)
5134                 return;
5135
5136         if (!itr_val)
5137                 itr_val = 0x4;
5138
5139         if (adapter->hw.mac.type == e1000_82575)
5140                 itr_val |= itr_val << 16;
5141         else
5142                 itr_val |= E1000_EITR_CNT_IGNR;
5143
5144         writel(itr_val, q_vector->itr_register);
5145         q_vector->set_itr = 0;
5146 }
5147
5148 static irqreturn_t igb_msix_ring(int irq, void *data)
5149 {
5150         struct igb_q_vector *q_vector = data;
5151
5152         /* Write the ITR value calculated from the previous interrupt. */
5153         igb_write_itr(q_vector);
5154
5155         napi_schedule(&q_vector->napi);
5156
5157         return IRQ_HANDLED;
5158 }
5159
5160 #ifdef CONFIG_IGB_DCA
5161 static void igb_update_tx_dca(struct igb_adapter *adapter,
5162                               struct igb_ring *tx_ring,
5163                               int cpu)
5164 {
5165         struct e1000_hw *hw = &adapter->hw;
5166         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5167
5168         if (hw->mac.type != e1000_82575)
5169                 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5170
5171         /* We can enable relaxed ordering for reads, but not writes when
5172          * DCA is enabled.  This is due to a known issue in some chipsets
5173          * which will cause the DCA tag to be cleared.
5174          */
5175         txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5176                   E1000_DCA_TXCTRL_DATA_RRO_EN |
5177                   E1000_DCA_TXCTRL_DESC_DCA_EN;
5178
5179         wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5180 }
5181
5182 static void igb_update_rx_dca(struct igb_adapter *adapter,
5183                               struct igb_ring *rx_ring,
5184                               int cpu)
5185 {
5186         struct e1000_hw *hw = &adapter->hw;
5187         u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5188
5189         if (hw->mac.type != e1000_82575)
5190                 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5191
5192         /* We can enable relaxed ordering for reads, but not writes when
5193          * DCA is enabled.  This is due to a known issue in some chipsets
5194          * which will cause the DCA tag to be cleared.
5195          */
5196         rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5197                   E1000_DCA_RXCTRL_DESC_DCA_EN;
5198
5199         wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5200 }
5201
5202 static void igb_update_dca(struct igb_q_vector *q_vector)
5203 {
5204         struct igb_adapter *adapter = q_vector->adapter;
5205         int cpu = get_cpu();
5206
5207         if (q_vector->cpu == cpu)
5208                 goto out_no_update;
5209
5210         if (q_vector->tx.ring)
5211                 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5212
5213         if (q_vector->rx.ring)
5214                 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5215
5216         q_vector->cpu = cpu;
5217 out_no_update:
5218         put_cpu();
5219 }
5220
5221 static void igb_setup_dca(struct igb_adapter *adapter)
5222 {
5223         struct e1000_hw *hw = &adapter->hw;
5224         int i;
5225
5226         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5227                 return;
5228
5229         /* Always use CB2 mode, difference is masked in the CB driver. */
5230         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5231
5232         for (i = 0; i < adapter->num_q_vectors; i++) {
5233                 adapter->q_vector[i]->cpu = -1;
5234                 igb_update_dca(adapter->q_vector[i]);
5235         }
5236 }
5237
5238 static int __igb_notify_dca(struct device *dev, void *data)
5239 {
5240         struct net_device *netdev = dev_get_drvdata(dev);
5241         struct igb_adapter *adapter = netdev_priv(netdev);
5242         struct pci_dev *pdev = adapter->pdev;
5243         struct e1000_hw *hw = &adapter->hw;
5244         unsigned long event = *(unsigned long *)data;
5245
5246         switch (event) {
5247         case DCA_PROVIDER_ADD:
5248                 /* if already enabled, don't do it again */
5249                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5250                         break;
5251                 if (dca_add_requester(dev) == 0) {
5252                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
5253                         dev_info(&pdev->dev, "DCA enabled\n");
5254                         igb_setup_dca(adapter);
5255                         break;
5256                 }
5257                 /* Fall Through since DCA is disabled. */
5258         case DCA_PROVIDER_REMOVE:
5259                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5260                         /* without this a class_device is left
5261                          * hanging around in the sysfs model
5262                          */
5263                         dca_remove_requester(dev);
5264                         dev_info(&pdev->dev, "DCA disabled\n");
5265                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5266                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5267                 }
5268                 break;
5269         }
5270
5271         return 0;
5272 }
5273
5274 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5275                           void *p)
5276 {
5277         int ret_val;
5278
5279         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5280                                          __igb_notify_dca);
5281
5282         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5283 }
5284 #endif /* CONFIG_IGB_DCA */
5285
5286 #ifdef CONFIG_PCI_IOV
5287 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5288 {
5289         unsigned char mac_addr[ETH_ALEN];
5290
5291         eth_zero_addr(mac_addr);
5292         igb_set_vf_mac(adapter, vf, mac_addr);
5293
5294         /* By default spoof check is enabled for all VFs */
5295         adapter->vf_data[vf].spoofchk_enabled = true;
5296
5297         return 0;
5298 }
5299
5300 #endif
5301 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5302 {
5303         struct e1000_hw *hw = &adapter->hw;
5304         u32 ping;
5305         int i;
5306
5307         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5308                 ping = E1000_PF_CONTROL_MSG;
5309                 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5310                         ping |= E1000_VT_MSGTYPE_CTS;
5311                 igb_write_mbx(hw, &ping, 1, i);
5312         }
5313 }
5314
5315 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5316 {
5317         struct e1000_hw *hw = &adapter->hw;
5318         u32 vmolr = rd32(E1000_VMOLR(vf));
5319         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5320
5321         vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5322                             IGB_VF_FLAG_MULTI_PROMISC);
5323         vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5324
5325         if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5326                 vmolr |= E1000_VMOLR_MPME;
5327                 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5328                 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5329         } else {
5330                 /* if we have hashes and we are clearing a multicast promisc
5331                  * flag we need to write the hashes to the MTA as this step
5332                  * was previously skipped
5333                  */
5334                 if (vf_data->num_vf_mc_hashes > 30) {
5335                         vmolr |= E1000_VMOLR_MPME;
5336                 } else if (vf_data->num_vf_mc_hashes) {
5337                         int j;
5338                         vmolr |= E1000_VMOLR_ROMPE;
5339                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5340                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5341                 }
5342         }
5343
5344         wr32(E1000_VMOLR(vf), vmolr);
5345
5346         /* there are flags left unprocessed, likely not supported */
5347         if (*msgbuf & E1000_VT_MSGINFO_MASK)
5348                 return -EINVAL;
5349
5350         return 0;
5351 }
5352
5353 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5354                                   u32 *msgbuf, u32 vf)
5355 {
5356         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5357         u16 *hash_list = (u16 *)&msgbuf[1];
5358         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5359         int i;
5360
5361         /* salt away the number of multicast addresses assigned
5362          * to this VF for later use to restore when the PF multi cast
5363          * list changes
5364          */
5365         vf_data->num_vf_mc_hashes = n;
5366
5367         /* only up to 30 hash values supported */
5368         if (n > 30)
5369                 n = 30;
5370
5371         /* store the hashes for later use */
5372         for (i = 0; i < n; i++)
5373                 vf_data->vf_mc_hashes[i] = hash_list[i];
5374
5375         /* Flush and reset the mta with the new values */
5376         igb_set_rx_mode(adapter->netdev);
5377
5378         return 0;
5379 }
5380
5381 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5382 {
5383         struct e1000_hw *hw = &adapter->hw;
5384         struct vf_data_storage *vf_data;
5385         int i, j;
5386
5387         for (i = 0; i < adapter->vfs_allocated_count; i++) {
5388                 u32 vmolr = rd32(E1000_VMOLR(i));
5389                 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5390
5391                 vf_data = &adapter->vf_data[i];
5392
5393                 if ((vf_data->num_vf_mc_hashes > 30) ||
5394                     (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5395                         vmolr |= E1000_VMOLR_MPME;
5396                 } else if (vf_data->num_vf_mc_hashes) {
5397                         vmolr |= E1000_VMOLR_ROMPE;
5398                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5399                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5400                 }
5401                 wr32(E1000_VMOLR(i), vmolr);
5402         }
5403 }
5404
5405 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5406 {
5407         struct e1000_hw *hw = &adapter->hw;
5408         u32 pool_mask, reg, vid;
5409         int i;
5410
5411         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5412
5413         /* Find the vlan filter for this id */
5414         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5415                 reg = rd32(E1000_VLVF(i));
5416
5417                 /* remove the vf from the pool */
5418                 reg &= ~pool_mask;
5419
5420                 /* if pool is empty then remove entry from vfta */
5421                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5422                     (reg & E1000_VLVF_VLANID_ENABLE)) {
5423                         reg = 0;
5424                         vid = reg & E1000_VLVF_VLANID_MASK;
5425                         igb_vfta_set(hw, vid, false);
5426                 }
5427
5428                 wr32(E1000_VLVF(i), reg);
5429         }
5430
5431         adapter->vf_data[vf].vlans_enabled = 0;
5432 }
5433
5434 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5435 {
5436         struct e1000_hw *hw = &adapter->hw;
5437         u32 reg, i;
5438
5439         /* The vlvf table only exists on 82576 hardware and newer */
5440         if (hw->mac.type < e1000_82576)
5441                 return -1;
5442
5443         /* we only need to do this if VMDq is enabled */
5444         if (!adapter->vfs_allocated_count)
5445                 return -1;
5446
5447         /* Find the vlan filter for this id */
5448         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5449                 reg = rd32(E1000_VLVF(i));
5450                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5451                     vid == (reg & E1000_VLVF_VLANID_MASK))
5452                         break;
5453         }
5454
5455         if (add) {
5456                 if (i == E1000_VLVF_ARRAY_SIZE) {
5457                         /* Did not find a matching VLAN ID entry that was
5458                          * enabled.  Search for a free filter entry, i.e.
5459                          * one without the enable bit set
5460                          */
5461                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5462                                 reg = rd32(E1000_VLVF(i));
5463                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5464                                         break;
5465                         }
5466                 }
5467                 if (i < E1000_VLVF_ARRAY_SIZE) {
5468                         /* Found an enabled/available entry */
5469                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5470
5471                         /* if !enabled we need to set this up in vfta */
5472                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5473                                 /* add VID to filter table */
5474                                 igb_vfta_set(hw, vid, true);
5475                                 reg |= E1000_VLVF_VLANID_ENABLE;
5476                         }
5477                         reg &= ~E1000_VLVF_VLANID_MASK;
5478                         reg |= vid;
5479                         wr32(E1000_VLVF(i), reg);
5480
5481                         /* do not modify RLPML for PF devices */
5482                         if (vf >= adapter->vfs_allocated_count)
5483                                 return 0;
5484
5485                         if (!adapter->vf_data[vf].vlans_enabled) {
5486                                 u32 size;
5487                                 reg = rd32(E1000_VMOLR(vf));
5488                                 size = reg & E1000_VMOLR_RLPML_MASK;
5489                                 size += 4;
5490                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5491                                 reg |= size;
5492                                 wr32(E1000_VMOLR(vf), reg);
5493                         }
5494
5495                         adapter->vf_data[vf].vlans_enabled++;
5496                 }
5497         } else {
5498                 if (i < E1000_VLVF_ARRAY_SIZE) {
5499                         /* remove vf from the pool */
5500                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5501                         /* if pool is empty then remove entry from vfta */
5502                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5503                                 reg = 0;
5504                                 igb_vfta_set(hw, vid, false);
5505                         }
5506                         wr32(E1000_VLVF(i), reg);
5507
5508                         /* do not modify RLPML for PF devices */
5509                         if (vf >= adapter->vfs_allocated_count)
5510                                 return 0;
5511
5512                         adapter->vf_data[vf].vlans_enabled--;
5513                         if (!adapter->vf_data[vf].vlans_enabled) {
5514                                 u32 size;
5515                                 reg = rd32(E1000_VMOLR(vf));
5516                                 size = reg & E1000_VMOLR_RLPML_MASK;
5517                                 size -= 4;
5518                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5519                                 reg |= size;
5520                                 wr32(E1000_VMOLR(vf), reg);
5521                         }
5522                 }
5523         }
5524         return 0;
5525 }
5526
5527 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5528 {
5529         struct e1000_hw *hw = &adapter->hw;
5530
5531         if (vid)
5532                 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5533         else
5534                 wr32(E1000_VMVIR(vf), 0);
5535 }
5536
5537 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5538                                int vf, u16 vlan, u8 qos)
5539 {
5540         int err = 0;
5541         struct igb_adapter *adapter = netdev_priv(netdev);
5542
5543         if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5544                 return -EINVAL;
5545         if (vlan || qos) {
5546                 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5547                 if (err)
5548                         goto out;
5549                 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5550                 igb_set_vmolr(adapter, vf, !vlan);
5551                 adapter->vf_data[vf].pf_vlan = vlan;
5552                 adapter->vf_data[vf].pf_qos = qos;
5553                 dev_info(&adapter->pdev->dev,
5554                          "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5555                 if (test_bit(__IGB_DOWN, &adapter->state)) {
5556                         dev_warn(&adapter->pdev->dev,
5557                                  "The VF VLAN has been set, but the PF device is not up.\n");
5558                         dev_warn(&adapter->pdev->dev,
5559                                  "Bring the PF device up before attempting to use the VF device.\n");
5560                 }
5561         } else {
5562                 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5563                              false, vf);
5564                 igb_set_vmvir(adapter, vlan, vf);
5565                 igb_set_vmolr(adapter, vf, true);
5566                 adapter->vf_data[vf].pf_vlan = 0;
5567                 adapter->vf_data[vf].pf_qos = 0;
5568         }
5569 out:
5570         return err;
5571 }
5572
5573 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5574 {
5575         struct e1000_hw *hw = &adapter->hw;
5576         int i;
5577         u32 reg;
5578
5579         /* Find the vlan filter for this id */
5580         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5581                 reg = rd32(E1000_VLVF(i));
5582                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5583                     vid == (reg & E1000_VLVF_VLANID_MASK))
5584                         break;
5585         }
5586
5587         if (i >= E1000_VLVF_ARRAY_SIZE)
5588                 i = -1;
5589
5590         return i;
5591 }
5592
5593 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5594 {
5595         struct e1000_hw *hw = &adapter->hw;
5596         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5597         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5598         int err = 0;
5599
5600         /* If in promiscuous mode we need to make sure the PF also has
5601          * the VLAN filter set.
5602          */
5603         if (add && (adapter->netdev->flags & IFF_PROMISC))
5604                 err = igb_vlvf_set(adapter, vid, add,
5605                                    adapter->vfs_allocated_count);
5606         if (err)
5607                 goto out;
5608
5609         err = igb_vlvf_set(adapter, vid, add, vf);
5610
5611         if (err)
5612                 goto out;
5613
5614         /* Go through all the checks to see if the VLAN filter should
5615          * be wiped completely.
5616          */
5617         if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5618                 u32 vlvf, bits;
5619
5620                 int regndx = igb_find_vlvf_entry(adapter, vid);
5621                 if (regndx < 0)
5622                         goto out;
5623                 /* See if any other pools are set for this VLAN filter
5624                  * entry other than the PF.
5625                  */
5626                 vlvf = bits = rd32(E1000_VLVF(regndx));
5627                 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5628                               adapter->vfs_allocated_count);
5629                 /* If the filter was removed then ensure PF pool bit
5630                  * is cleared if the PF only added itself to the pool
5631                  * because the PF is in promiscuous mode.
5632                  */
5633                 if ((vlvf & VLAN_VID_MASK) == vid &&
5634                     !test_bit(vid, adapter->active_vlans) &&
5635                     !bits)
5636                         igb_vlvf_set(adapter, vid, add,
5637                                      adapter->vfs_allocated_count);
5638         }
5639
5640 out:
5641         return err;
5642 }
5643
5644 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5645 {
5646         /* clear flags - except flag that indicates PF has set the MAC */
5647         adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5648         adapter->vf_data[vf].last_nack = jiffies;
5649
5650         /* reset offloads to defaults */
5651         igb_set_vmolr(adapter, vf, true);
5652
5653         /* reset vlans for device */
5654         igb_clear_vf_vfta(adapter, vf);
5655         if (adapter->vf_data[vf].pf_vlan)
5656                 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5657                                     adapter->vf_data[vf].pf_vlan,
5658                                     adapter->vf_data[vf].pf_qos);
5659         else
5660                 igb_clear_vf_vfta(adapter, vf);
5661
5662         /* reset multicast table array for vf */
5663         adapter->vf_data[vf].num_vf_mc_hashes = 0;
5664
5665         /* Flush and reset the mta with the new values */
5666         igb_set_rx_mode(adapter->netdev);
5667 }
5668
5669 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5670 {
5671         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5672
5673         /* clear mac address as we were hotplug removed/added */
5674         if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5675                 eth_zero_addr(vf_mac);
5676
5677         /* process remaining reset events */
5678         igb_vf_reset(adapter, vf);
5679 }
5680
5681 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5682 {
5683         struct e1000_hw *hw = &adapter->hw;
5684         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5685         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5686         u32 reg, msgbuf[3];
5687         u8 *addr = (u8 *)(&msgbuf[1]);
5688
5689         /* process all the same items cleared in a function level reset */
5690         igb_vf_reset(adapter, vf);
5691
5692         /* set vf mac address */
5693         igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5694
5695         /* enable transmit and receive for vf */
5696         reg = rd32(E1000_VFTE);
5697         wr32(E1000_VFTE, reg | (1 << vf));
5698         reg = rd32(E1000_VFRE);
5699         wr32(E1000_VFRE, reg | (1 << vf));
5700
5701         adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5702
5703         /* reply to reset with ack and vf mac address */
5704         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5705         memcpy(addr, vf_mac, 6);
5706         igb_write_mbx(hw, msgbuf, 3, vf);
5707 }
5708
5709 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5710 {
5711         /* The VF MAC Address is stored in a packed array of bytes
5712          * starting at the second 32 bit word of the msg array
5713          */
5714         unsigned char *addr = (char *)&msg[1];
5715         int err = -1;
5716
5717         if (is_valid_ether_addr(addr))
5718                 err = igb_set_vf_mac(adapter, vf, addr);
5719
5720         return err;
5721 }
5722
5723 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5724 {
5725         struct e1000_hw *hw = &adapter->hw;
5726         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5727         u32 msg = E1000_VT_MSGTYPE_NACK;
5728
5729         /* if device isn't clear to send it shouldn't be reading either */
5730         if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5731             time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5732                 igb_write_mbx(hw, &msg, 1, vf);
5733                 vf_data->last_nack = jiffies;
5734         }
5735 }
5736
5737 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5738 {
5739         struct pci_dev *pdev = adapter->pdev;
5740         u32 msgbuf[E1000_VFMAILBOX_SIZE];
5741         struct e1000_hw *hw = &adapter->hw;
5742         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5743         s32 retval;
5744
5745         retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5746
5747         if (retval) {
5748                 /* if receive failed revoke VF CTS stats and restart init */
5749                 dev_err(&pdev->dev, "Error receiving message from VF\n");
5750                 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5751                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5752                         return;
5753                 goto out;
5754         }
5755
5756         /* this is a message we already processed, do nothing */
5757         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5758                 return;
5759
5760         /* until the vf completes a reset it should not be
5761          * allowed to start any configuration.
5762          */
5763         if (msgbuf[0] == E1000_VF_RESET) {
5764                 igb_vf_reset_msg(adapter, vf);
5765                 return;
5766         }
5767
5768         if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5769                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5770                         return;
5771                 retval = -1;
5772                 goto out;
5773         }
5774
5775         switch ((msgbuf[0] & 0xFFFF)) {
5776         case E1000_VF_SET_MAC_ADDR:
5777                 retval = -EINVAL;
5778                 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5779                         retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5780                 else
5781                         dev_warn(&pdev->dev,
5782                                  "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5783                                  vf);
5784                 break;
5785         case E1000_VF_SET_PROMISC:
5786                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5787                 break;
5788         case E1000_VF_SET_MULTICAST:
5789                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5790                 break;
5791         case E1000_VF_SET_LPE:
5792                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5793                 break;
5794         case E1000_VF_SET_VLAN:
5795                 retval = -1;
5796                 if (vf_data->pf_vlan)
5797                         dev_warn(&pdev->dev,
5798                                  "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5799                                  vf);
5800                 else
5801                         retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5802                 break;
5803         default:
5804                 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5805                 retval = -1;
5806                 break;
5807         }
5808
5809         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5810 out:
5811         /* notify the VF of the results of what it sent us */
5812         if (retval)
5813                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5814         else
5815                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5816
5817         igb_write_mbx(hw, msgbuf, 1, vf);
5818 }
5819
5820 static void igb_msg_task(struct igb_adapter *adapter)
5821 {
5822         struct e1000_hw *hw = &adapter->hw;
5823         u32 vf;
5824
5825         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5826                 /* process any reset requests */
5827                 if (!igb_check_for_rst(hw, vf))
5828                         igb_vf_reset_event(adapter, vf);
5829
5830                 /* process any messages pending */
5831                 if (!igb_check_for_msg(hw, vf))
5832                         igb_rcv_msg_from_vf(adapter, vf);
5833
5834                 /* process any acks */
5835                 if (!igb_check_for_ack(hw, vf))
5836                         igb_rcv_ack_from_vf(adapter, vf);
5837         }
5838 }
5839
5840 /**
5841  *  igb_set_uta - Set unicast filter table address
5842  *  @adapter: board private structure
5843  *
5844  *  The unicast table address is a register array of 32-bit registers.
5845  *  The table is meant to be used in a way similar to how the MTA is used
5846  *  however due to certain limitations in the hardware it is necessary to
5847  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5848  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
5849  **/
5850 static void igb_set_uta(struct igb_adapter *adapter)
5851 {
5852         struct e1000_hw *hw = &adapter->hw;
5853         int i;
5854
5855         /* The UTA table only exists on 82576 hardware and newer */
5856         if (hw->mac.type < e1000_82576)
5857                 return;
5858
5859         /* we only need to do this if VMDq is enabled */
5860         if (!adapter->vfs_allocated_count)
5861                 return;
5862
5863         for (i = 0; i < hw->mac.uta_reg_count; i++)
5864                 array_wr32(E1000_UTA, i, ~0);
5865 }
5866
5867 /**
5868  *  igb_intr_msi - Interrupt Handler
5869  *  @irq: interrupt number
5870  *  @data: pointer to a network interface device structure
5871  **/
5872 static irqreturn_t igb_intr_msi(int irq, void *data)
5873 {
5874         struct igb_adapter *adapter = data;
5875         struct igb_q_vector *q_vector = adapter->q_vector[0];
5876         struct e1000_hw *hw = &adapter->hw;
5877         /* read ICR disables interrupts using IAM */
5878         u32 icr = rd32(E1000_ICR);
5879
5880         igb_write_itr(q_vector);
5881
5882         if (icr & E1000_ICR_DRSTA)
5883                 schedule_work(&adapter->reset_task);
5884
5885         if (icr & E1000_ICR_DOUTSYNC) {
5886                 /* HW is reporting DMA is out of sync */
5887                 adapter->stats.doosync++;
5888         }
5889
5890         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5891                 hw->mac.get_link_status = 1;
5892                 if (!test_bit(__IGB_DOWN, &adapter->state))
5893                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5894         }
5895
5896         if (icr & E1000_ICR_TS) {
5897                 u32 tsicr = rd32(E1000_TSICR);
5898
5899                 if (tsicr & E1000_TSICR_TXTS) {
5900                         /* acknowledge the interrupt */
5901                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5902                         /* retrieve hardware timestamp */
5903                         schedule_work(&adapter->ptp_tx_work);
5904                 }
5905         }
5906
5907         napi_schedule(&q_vector->napi);
5908
5909         return IRQ_HANDLED;
5910 }
5911
5912 /**
5913  *  igb_intr - Legacy Interrupt Handler
5914  *  @irq: interrupt number
5915  *  @data: pointer to a network interface device structure
5916  **/
5917 static irqreturn_t igb_intr(int irq, void *data)
5918 {
5919         struct igb_adapter *adapter = data;
5920         struct igb_q_vector *q_vector = adapter->q_vector[0];
5921         struct e1000_hw *hw = &adapter->hw;
5922         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
5923          * need for the IMC write
5924          */
5925         u32 icr = rd32(E1000_ICR);
5926
5927         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5928          * not set, then the adapter didn't send an interrupt
5929          */
5930         if (!(icr & E1000_ICR_INT_ASSERTED))
5931                 return IRQ_NONE;
5932
5933         igb_write_itr(q_vector);
5934
5935         if (icr & E1000_ICR_DRSTA)
5936                 schedule_work(&adapter->reset_task);
5937
5938         if (icr & E1000_ICR_DOUTSYNC) {
5939                 /* HW is reporting DMA is out of sync */
5940                 adapter->stats.doosync++;
5941         }
5942
5943         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5944                 hw->mac.get_link_status = 1;
5945                 /* guard against interrupt when we're going down */
5946                 if (!test_bit(__IGB_DOWN, &adapter->state))
5947                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5948         }
5949
5950         if (icr & E1000_ICR_TS) {
5951                 u32 tsicr = rd32(E1000_TSICR);
5952
5953                 if (tsicr & E1000_TSICR_TXTS) {
5954                         /* acknowledge the interrupt */
5955                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5956                         /* retrieve hardware timestamp */
5957                         schedule_work(&adapter->ptp_tx_work);
5958                 }
5959         }
5960
5961         napi_schedule(&q_vector->napi);
5962
5963         return IRQ_HANDLED;
5964 }
5965
5966 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5967 {
5968         struct igb_adapter *adapter = q_vector->adapter;
5969         struct e1000_hw *hw = &adapter->hw;
5970
5971         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5972             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5973                 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5974                         igb_set_itr(q_vector);
5975                 else
5976                         igb_update_ring_itr(q_vector);
5977         }
5978
5979         if (!test_bit(__IGB_DOWN, &adapter->state)) {
5980                 if (adapter->msix_entries)
5981                         wr32(E1000_EIMS, q_vector->eims_value);
5982                 else
5983                         igb_irq_enable(adapter);
5984         }
5985 }
5986
5987 /**
5988  *  igb_poll - NAPI Rx polling callback
5989  *  @napi: napi polling structure
5990  *  @budget: count of how many packets we should handle
5991  **/
5992 static int igb_poll(struct napi_struct *napi, int budget)
5993 {
5994         struct igb_q_vector *q_vector = container_of(napi,
5995                                                      struct igb_q_vector,
5996                                                      napi);
5997         bool clean_complete = true;
5998
5999 #ifdef CONFIG_IGB_DCA
6000         if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6001                 igb_update_dca(q_vector);
6002 #endif
6003         if (q_vector->tx.ring)
6004                 clean_complete = igb_clean_tx_irq(q_vector);
6005
6006         if (q_vector->rx.ring)
6007                 clean_complete &= igb_clean_rx_irq(q_vector, budget);
6008
6009         /* If all work not completed, return budget and keep polling */
6010         if (!clean_complete)
6011                 return budget;
6012
6013         /* If not enough Rx work done, exit the polling mode */
6014         napi_complete(napi);
6015         igb_ring_irq_enable(q_vector);
6016
6017         return 0;
6018 }
6019
6020 /**
6021  *  igb_clean_tx_irq - Reclaim resources after transmit completes
6022  *  @q_vector: pointer to q_vector containing needed info
6023  *
6024  *  returns true if ring is completely cleaned
6025  **/
6026 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6027 {
6028         struct igb_adapter *adapter = q_vector->adapter;
6029         struct igb_ring *tx_ring = q_vector->tx.ring;
6030         struct igb_tx_buffer *tx_buffer;
6031         union e1000_adv_tx_desc *tx_desc;
6032         unsigned int total_bytes = 0, total_packets = 0;
6033         unsigned int budget = q_vector->tx.work_limit;
6034         unsigned int i = tx_ring->next_to_clean;
6035
6036         if (test_bit(__IGB_DOWN, &adapter->state))
6037                 return true;
6038
6039         tx_buffer = &tx_ring->tx_buffer_info[i];
6040         tx_desc = IGB_TX_DESC(tx_ring, i);
6041         i -= tx_ring->count;
6042
6043         do {
6044                 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6045
6046                 /* if next_to_watch is not set then there is no work pending */
6047                 if (!eop_desc)
6048                         break;
6049
6050                 /* prevent any other reads prior to eop_desc */
6051                 read_barrier_depends();
6052
6053                 /* if DD is not set pending work has not been completed */
6054                 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6055                         break;
6056
6057                 /* clear next_to_watch to prevent false hangs */
6058                 tx_buffer->next_to_watch = NULL;
6059
6060                 /* update the statistics for this packet */
6061                 total_bytes += tx_buffer->bytecount;
6062                 total_packets += tx_buffer->gso_segs;
6063
6064                 /* free the skb */
6065                 dev_kfree_skb_any(tx_buffer->skb);
6066
6067                 /* unmap skb header data */
6068                 dma_unmap_single(tx_ring->dev,
6069                                  dma_unmap_addr(tx_buffer, dma),
6070                                  dma_unmap_len(tx_buffer, len),
6071                                  DMA_TO_DEVICE);
6072
6073                 /* clear tx_buffer data */
6074                 tx_buffer->skb = NULL;
6075                 dma_unmap_len_set(tx_buffer, len, 0);
6076
6077                 /* clear last DMA location and unmap remaining buffers */
6078                 while (tx_desc != eop_desc) {
6079                         tx_buffer++;
6080                         tx_desc++;
6081                         i++;
6082                         if (unlikely(!i)) {
6083                                 i -= tx_ring->count;
6084                                 tx_buffer = tx_ring->tx_buffer_info;
6085                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
6086                         }
6087
6088                         /* unmap any remaining paged data */
6089                         if (dma_unmap_len(tx_buffer, len)) {
6090                                 dma_unmap_page(tx_ring->dev,
6091                                                dma_unmap_addr(tx_buffer, dma),
6092                                                dma_unmap_len(tx_buffer, len),
6093                                                DMA_TO_DEVICE);
6094                                 dma_unmap_len_set(tx_buffer, len, 0);
6095                         }
6096                 }
6097
6098                 /* move us one more past the eop_desc for start of next pkt */
6099                 tx_buffer++;
6100                 tx_desc++;
6101                 i++;
6102                 if (unlikely(!i)) {
6103                         i -= tx_ring->count;
6104                         tx_buffer = tx_ring->tx_buffer_info;
6105                         tx_desc = IGB_TX_DESC(tx_ring, 0);
6106                 }
6107
6108                 /* issue prefetch for next Tx descriptor */
6109                 prefetch(tx_desc);
6110
6111                 /* update budget accounting */
6112                 budget--;
6113         } while (likely(budget));
6114
6115         netdev_tx_completed_queue(txring_txq(tx_ring),
6116                                   total_packets, total_bytes);
6117         i += tx_ring->count;
6118         tx_ring->next_to_clean = i;
6119         u64_stats_update_begin(&tx_ring->tx_syncp);
6120         tx_ring->tx_stats.bytes += total_bytes;
6121         tx_ring->tx_stats.packets += total_packets;
6122         u64_stats_update_end(&tx_ring->tx_syncp);
6123         q_vector->tx.total_bytes += total_bytes;
6124         q_vector->tx.total_packets += total_packets;
6125
6126         if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6127                 struct e1000_hw *hw = &adapter->hw;
6128
6129                 /* Detect a transmit hang in hardware, this serializes the
6130                  * check with the clearing of time_stamp and movement of i
6131                  */
6132                 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6133                 if (tx_buffer->next_to_watch &&
6134                     time_after(jiffies, tx_buffer->time_stamp +
6135                                (adapter->tx_timeout_factor * HZ)) &&
6136                     !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6137
6138                         /* detected Tx unit hang */
6139                         dev_err(tx_ring->dev,
6140                                 "Detected Tx Unit Hang\n"
6141                                 "  Tx Queue             <%d>\n"
6142                                 "  TDH                  <%x>\n"
6143                                 "  TDT                  <%x>\n"
6144                                 "  next_to_use          <%x>\n"
6145                                 "  next_to_clean        <%x>\n"
6146                                 "buffer_info[next_to_clean]\n"
6147                                 "  time_stamp           <%lx>\n"
6148                                 "  next_to_watch        <%p>\n"
6149                                 "  jiffies              <%lx>\n"
6150                                 "  desc.status          <%x>\n",
6151                                 tx_ring->queue_index,
6152                                 rd32(E1000_TDH(tx_ring->reg_idx)),
6153                                 readl(tx_ring->tail),
6154                                 tx_ring->next_to_use,
6155                                 tx_ring->next_to_clean,
6156                                 tx_buffer->time_stamp,
6157                                 tx_buffer->next_to_watch,
6158                                 jiffies,
6159                                 tx_buffer->next_to_watch->wb.status);
6160                         netif_stop_subqueue(tx_ring->netdev,
6161                                             tx_ring->queue_index);
6162
6163                         /* we are about to reset, no point in enabling stuff */
6164                         return true;
6165                 }
6166         }
6167
6168 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6169         if (unlikely(total_packets &&
6170             netif_carrier_ok(tx_ring->netdev) &&
6171             igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6172                 /* Make sure that anybody stopping the queue after this
6173                  * sees the new next_to_clean.
6174                  */
6175                 smp_mb();
6176                 if (__netif_subqueue_stopped(tx_ring->netdev,
6177                                              tx_ring->queue_index) &&
6178                     !(test_bit(__IGB_DOWN, &adapter->state))) {
6179                         netif_wake_subqueue(tx_ring->netdev,
6180                                             tx_ring->queue_index);
6181
6182                         u64_stats_update_begin(&tx_ring->tx_syncp);
6183                         tx_ring->tx_stats.restart_queue++;
6184                         u64_stats_update_end(&tx_ring->tx_syncp);
6185                 }
6186         }
6187
6188         return !!budget;
6189 }
6190
6191 /**
6192  *  igb_reuse_rx_page - page flip buffer and store it back on the ring
6193  *  @rx_ring: rx descriptor ring to store buffers on
6194  *  @old_buff: donor buffer to have page reused
6195  *
6196  *  Synchronizes page for reuse by the adapter
6197  **/
6198 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6199                               struct igb_rx_buffer *old_buff)
6200 {
6201         struct igb_rx_buffer *new_buff;
6202         u16 nta = rx_ring->next_to_alloc;
6203
6204         new_buff = &rx_ring->rx_buffer_info[nta];
6205
6206         /* update, and store next to alloc */
6207         nta++;
6208         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6209
6210         /* transfer page from old buffer to new buffer */
6211         memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6212
6213         /* sync the buffer for use by the device */
6214         dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6215                                          old_buff->page_offset,
6216                                          IGB_RX_BUFSZ,
6217                                          DMA_FROM_DEVICE);
6218 }
6219
6220 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6221                                   struct page *page,
6222                                   unsigned int truesize)
6223 {
6224         /* avoid re-using remote pages */
6225         if (unlikely(page_to_nid(page) != numa_node_id()))
6226                 return false;
6227
6228 #if (PAGE_SIZE < 8192)
6229         /* if we are only owner of page we can reuse it */
6230         if (unlikely(page_count(page) != 1))
6231                 return false;
6232
6233         /* flip page offset to other buffer */
6234         rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6235
6236         /* since we are the only owner of the page and we need to
6237          * increment it, just set the value to 2 in order to avoid
6238          * an unnecessary locked operation
6239          */
6240         atomic_set(&page->_count, 2);
6241 #else
6242         /* move offset up to the next cache line */
6243         rx_buffer->page_offset += truesize;
6244
6245         if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6246                 return false;
6247
6248         /* bump ref count on page before it is given to the stack */
6249         get_page(page);
6250 #endif
6251
6252         return true;
6253 }
6254
6255 /**
6256  *  igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6257  *  @rx_ring: rx descriptor ring to transact packets on
6258  *  @rx_buffer: buffer containing page to add
6259  *  @rx_desc: descriptor containing length of buffer written by hardware
6260  *  @skb: sk_buff to place the data into
6261  *
6262  *  This function will add the data contained in rx_buffer->page to the skb.
6263  *  This is done either through a direct copy if the data in the buffer is
6264  *  less than the skb header size, otherwise it will just attach the page as
6265  *  a frag to the skb.
6266  *
6267  *  The function will then update the page offset if necessary and return
6268  *  true if the buffer can be reused by the adapter.
6269  **/
6270 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6271                             struct igb_rx_buffer *rx_buffer,
6272                             union e1000_adv_rx_desc *rx_desc,
6273                             struct sk_buff *skb)
6274 {
6275         struct page *page = rx_buffer->page;
6276         unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6277 #if (PAGE_SIZE < 8192)
6278         unsigned int truesize = IGB_RX_BUFSZ;
6279 #else
6280         unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6281 #endif
6282
6283         if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6284                 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6285
6286                 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6287                         igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6288                         va += IGB_TS_HDR_LEN;
6289                         size -= IGB_TS_HDR_LEN;
6290                 }
6291
6292                 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6293
6294                 /* we can reuse buffer as-is, just make sure it is local */
6295                 if (likely(page_to_nid(page) == numa_node_id()))
6296                         return true;
6297
6298                 /* this page cannot be reused so discard it */
6299                 put_page(page);
6300                 return false;
6301         }
6302
6303         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6304                         rx_buffer->page_offset, size, truesize);
6305
6306         return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6307 }
6308
6309 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6310                                            union e1000_adv_rx_desc *rx_desc,
6311                                            struct sk_buff *skb)
6312 {
6313         struct igb_rx_buffer *rx_buffer;
6314         struct page *page;
6315
6316         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6317
6318         page = rx_buffer->page;
6319         prefetchw(page);
6320
6321         if (likely(!skb)) {
6322                 void *page_addr = page_address(page) +
6323                                   rx_buffer->page_offset;
6324
6325                 /* prefetch first cache line of first page */
6326                 prefetch(page_addr);
6327 #if L1_CACHE_BYTES < 128
6328                 prefetch(page_addr + L1_CACHE_BYTES);
6329 #endif
6330
6331                 /* allocate a skb to store the frags */
6332                 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6333                                                 IGB_RX_HDR_LEN);
6334                 if (unlikely(!skb)) {
6335                         rx_ring->rx_stats.alloc_failed++;
6336                         return NULL;
6337                 }
6338
6339                 /* we will be copying header into skb->data in
6340                  * pskb_may_pull so it is in our interest to prefetch
6341                  * it now to avoid a possible cache miss
6342                  */
6343                 prefetchw(skb->data);
6344         }
6345
6346         /* we are reusing so sync this buffer for CPU use */
6347         dma_sync_single_range_for_cpu(rx_ring->dev,
6348                                       rx_buffer->dma,
6349                                       rx_buffer->page_offset,
6350                                       IGB_RX_BUFSZ,
6351                                       DMA_FROM_DEVICE);
6352
6353         /* pull page into skb */
6354         if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6355                 /* hand second half of page back to the ring */
6356                 igb_reuse_rx_page(rx_ring, rx_buffer);
6357         } else {
6358                 /* we are not reusing the buffer so unmap it */
6359                 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6360                                PAGE_SIZE, DMA_FROM_DEVICE);
6361         }
6362
6363         /* clear contents of rx_buffer */
6364         rx_buffer->page = NULL;
6365
6366         return skb;
6367 }
6368
6369 static inline void igb_rx_checksum(struct igb_ring *ring,
6370                                    union e1000_adv_rx_desc *rx_desc,
6371                                    struct sk_buff *skb)
6372 {
6373         skb_checksum_none_assert(skb);
6374
6375         /* Ignore Checksum bit is set */
6376         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6377                 return;
6378
6379         /* Rx checksum disabled via ethtool */
6380         if (!(ring->netdev->features & NETIF_F_RXCSUM))
6381                 return;
6382
6383         /* TCP/UDP checksum error bit is set */
6384         if (igb_test_staterr(rx_desc,
6385                              E1000_RXDEXT_STATERR_TCPE |
6386                              E1000_RXDEXT_STATERR_IPE)) {
6387                 /* work around errata with sctp packets where the TCPE aka
6388                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6389                  * packets, (aka let the stack check the crc32c)
6390                  */
6391                 if (!((skb->len == 60) &&
6392                       test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6393                         u64_stats_update_begin(&ring->rx_syncp);
6394                         ring->rx_stats.csum_err++;
6395                         u64_stats_update_end(&ring->rx_syncp);
6396                 }
6397                 /* let the stack verify checksum errors */
6398                 return;
6399         }
6400         /* It must be a TCP or UDP packet with a valid checksum */
6401         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6402                                       E1000_RXD_STAT_UDPCS))
6403                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6404
6405         dev_dbg(ring->dev, "cksum success: bits %08X\n",
6406                 le32_to_cpu(rx_desc->wb.upper.status_error));
6407 }
6408
6409 static inline void igb_rx_hash(struct igb_ring *ring,
6410                                union e1000_adv_rx_desc *rx_desc,
6411                                struct sk_buff *skb)
6412 {
6413         if (ring->netdev->features & NETIF_F_RXHASH)
6414                 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6415 }
6416
6417 /**
6418  *  igb_is_non_eop - process handling of non-EOP buffers
6419  *  @rx_ring: Rx ring being processed
6420  *  @rx_desc: Rx descriptor for current buffer
6421  *  @skb: current socket buffer containing buffer in progress
6422  *
6423  *  This function updates next to clean.  If the buffer is an EOP buffer
6424  *  this function exits returning false, otherwise it will place the
6425  *  sk_buff in the next buffer to be chained and return true indicating
6426  *  that this is in fact a non-EOP buffer.
6427  **/
6428 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6429                            union e1000_adv_rx_desc *rx_desc)
6430 {
6431         u32 ntc = rx_ring->next_to_clean + 1;
6432
6433         /* fetch, update, and store next to clean */
6434         ntc = (ntc < rx_ring->count) ? ntc : 0;
6435         rx_ring->next_to_clean = ntc;
6436
6437         prefetch(IGB_RX_DESC(rx_ring, ntc));
6438
6439         if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6440                 return false;
6441
6442         return true;
6443 }
6444
6445 /**
6446  *  igb_get_headlen - determine size of header for LRO/GRO
6447  *  @data: pointer to the start of the headers
6448  *  @max_len: total length of section to find headers in
6449  *
6450  *  This function is meant to determine the length of headers that will
6451  *  be recognized by hardware for LRO, and GRO offloads.  The main
6452  *  motivation of doing this is to only perform one pull for IPv4 TCP
6453  *  packets so that we can do basic things like calculating the gso_size
6454  *  based on the average data per packet.
6455  **/
6456 static unsigned int igb_get_headlen(unsigned char *data,
6457                                     unsigned int max_len)
6458 {
6459         union {
6460                 unsigned char *network;
6461                 /* l2 headers */
6462                 struct ethhdr *eth;
6463                 struct vlan_hdr *vlan;
6464                 /* l3 headers */
6465                 struct iphdr *ipv4;
6466                 struct ipv6hdr *ipv6;
6467         } hdr;
6468         __be16 protocol;
6469         u8 nexthdr = 0; /* default to not TCP */
6470         u8 hlen;
6471
6472         /* this should never happen, but better safe than sorry */
6473         if (max_len < ETH_HLEN)
6474                 return max_len;
6475
6476         /* initialize network frame pointer */
6477         hdr.network = data;
6478
6479         /* set first protocol and move network header forward */
6480         protocol = hdr.eth->h_proto;
6481         hdr.network += ETH_HLEN;
6482
6483         /* handle any vlan tag if present */
6484         if (protocol == __constant_htons(ETH_P_8021Q)) {
6485                 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6486                         return max_len;
6487
6488                 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6489                 hdr.network += VLAN_HLEN;
6490         }
6491
6492         /* handle L3 protocols */
6493         if (protocol == __constant_htons(ETH_P_IP)) {
6494                 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6495                         return max_len;
6496
6497                 /* access ihl as a u8 to avoid unaligned access on ia64 */
6498                 hlen = (hdr.network[0] & 0x0F) << 2;
6499
6500                 /* verify hlen meets minimum size requirements */
6501                 if (hlen < sizeof(struct iphdr))
6502                         return hdr.network - data;
6503
6504                 /* record next protocol if header is present */
6505                 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
6506                         nexthdr = hdr.ipv4->protocol;
6507         } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6508                 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6509                         return max_len;
6510
6511                 /* record next protocol */
6512                 nexthdr = hdr.ipv6->nexthdr;
6513                 hlen = sizeof(struct ipv6hdr);
6514         } else {
6515                 return hdr.network - data;
6516         }
6517
6518         /* relocate pointer to start of L4 header */
6519         hdr.network += hlen;
6520
6521         /* finally sort out TCP */
6522         if (nexthdr == IPPROTO_TCP) {
6523                 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6524                         return max_len;
6525
6526                 /* access doff as a u8 to avoid unaligned access on ia64 */
6527                 hlen = (hdr.network[12] & 0xF0) >> 2;
6528
6529                 /* verify hlen meets minimum size requirements */
6530                 if (hlen < sizeof(struct tcphdr))
6531                         return hdr.network - data;
6532
6533                 hdr.network += hlen;
6534         } else if (nexthdr == IPPROTO_UDP) {
6535                 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6536                         return max_len;
6537
6538                 hdr.network += sizeof(struct udphdr);
6539         }
6540
6541         /* If everything has gone correctly hdr.network should be the
6542          * data section of the packet and will be the end of the header.
6543          * If not then it probably represents the end of the last recognized
6544          * header.
6545          */
6546         if ((hdr.network - data) < max_len)
6547                 return hdr.network - data;
6548         else
6549                 return max_len;
6550 }
6551
6552 /**
6553  *  igb_pull_tail - igb specific version of skb_pull_tail
6554  *  @rx_ring: rx descriptor ring packet is being transacted on
6555  *  @rx_desc: pointer to the EOP Rx descriptor
6556  *  @skb: pointer to current skb being adjusted
6557  *
6558  *  This function is an igb specific version of __pskb_pull_tail.  The
6559  *  main difference between this version and the original function is that
6560  *  this function can make several assumptions about the state of things
6561  *  that allow for significant optimizations versus the standard function.
6562  *  As a result we can do things like drop a frag and maintain an accurate
6563  *  truesize for the skb.
6564  */
6565 static void igb_pull_tail(struct igb_ring *rx_ring,
6566                           union e1000_adv_rx_desc *rx_desc,
6567                           struct sk_buff *skb)
6568 {
6569         struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6570         unsigned char *va;
6571         unsigned int pull_len;
6572
6573         /* it is valid to use page_address instead of kmap since we are
6574          * working with pages allocated out of the lomem pool per
6575          * alloc_page(GFP_ATOMIC)
6576          */
6577         va = skb_frag_address(frag);
6578
6579         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6580                 /* retrieve timestamp from buffer */
6581                 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6582
6583                 /* update pointers to remove timestamp header */
6584                 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6585                 frag->page_offset += IGB_TS_HDR_LEN;
6586                 skb->data_len -= IGB_TS_HDR_LEN;
6587                 skb->len -= IGB_TS_HDR_LEN;
6588
6589                 /* move va to start of packet data */
6590                 va += IGB_TS_HDR_LEN;
6591         }
6592
6593         /* we need the header to contain the greater of either ETH_HLEN or
6594          * 60 bytes if the skb->len is less than 60 for skb_pad.
6595          */
6596         pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6597
6598         /* align pull length to size of long to optimize memcpy performance */
6599         skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6600
6601         /* update all of the pointers */
6602         skb_frag_size_sub(frag, pull_len);
6603         frag->page_offset += pull_len;
6604         skb->data_len -= pull_len;
6605         skb->tail += pull_len;
6606 }
6607
6608 /**
6609  *  igb_cleanup_headers - Correct corrupted or empty headers
6610  *  @rx_ring: rx descriptor ring packet is being transacted on
6611  *  @rx_desc: pointer to the EOP Rx descriptor
6612  *  @skb: pointer to current skb being fixed
6613  *
6614  *  Address the case where we are pulling data in on pages only
6615  *  and as such no data is present in the skb header.
6616  *
6617  *  In addition if skb is not at least 60 bytes we need to pad it so that
6618  *  it is large enough to qualify as a valid Ethernet frame.
6619  *
6620  *  Returns true if an error was encountered and skb was freed.
6621  **/
6622 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6623                                 union e1000_adv_rx_desc *rx_desc,
6624                                 struct sk_buff *skb)
6625 {
6626         if (unlikely((igb_test_staterr(rx_desc,
6627                                        E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6628                 struct net_device *netdev = rx_ring->netdev;
6629                 if (!(netdev->features & NETIF_F_RXALL)) {
6630                         dev_kfree_skb_any(skb);
6631                         return true;
6632                 }
6633         }
6634
6635         /* place header in linear portion of buffer */
6636         if (skb_is_nonlinear(skb))
6637                 igb_pull_tail(rx_ring, rx_desc, skb);
6638
6639         /* if skb_pad returns an error the skb was freed */
6640         if (unlikely(skb->len < 60)) {
6641                 int pad_len = 60 - skb->len;
6642
6643                 if (skb_pad(skb, pad_len))
6644                         return true;
6645                 __skb_put(skb, pad_len);
6646         }
6647
6648         return false;
6649 }
6650
6651 /**
6652  *  igb_process_skb_fields - Populate skb header fields from Rx descriptor
6653  *  @rx_ring: rx descriptor ring packet is being transacted on
6654  *  @rx_desc: pointer to the EOP Rx descriptor
6655  *  @skb: pointer to current skb being populated
6656  *
6657  *  This function checks the ring, descriptor, and packet information in
6658  *  order to populate the hash, checksum, VLAN, timestamp, protocol, and
6659  *  other fields within the skb.
6660  **/
6661 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6662                                    union e1000_adv_rx_desc *rx_desc,
6663                                    struct sk_buff *skb)
6664 {
6665         struct net_device *dev = rx_ring->netdev;
6666
6667         igb_rx_hash(rx_ring, rx_desc, skb);
6668
6669         igb_rx_checksum(rx_ring, rx_desc, skb);
6670
6671         igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
6672
6673         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6674             igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6675                 u16 vid;
6676                 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6677                     test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6678                         vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6679                 else
6680                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6681
6682                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6683         }
6684
6685         skb_record_rx_queue(skb, rx_ring->queue_index);
6686
6687         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6688 }
6689
6690 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6691 {
6692         struct igb_ring *rx_ring = q_vector->rx.ring;
6693         struct sk_buff *skb = rx_ring->skb;
6694         unsigned int total_bytes = 0, total_packets = 0;
6695         u16 cleaned_count = igb_desc_unused(rx_ring);
6696
6697         do {
6698                 union e1000_adv_rx_desc *rx_desc;
6699
6700                 /* return some buffers to hardware, one at a time is too slow */
6701                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6702                         igb_alloc_rx_buffers(rx_ring, cleaned_count);
6703                         cleaned_count = 0;
6704                 }
6705
6706                 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6707
6708                 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6709                         break;
6710
6711                 /* This memory barrier is needed to keep us from reading
6712                  * any other fields out of the rx_desc until we know the
6713                  * RXD_STAT_DD bit is set
6714                  */
6715                 rmb();
6716
6717                 /* retrieve a buffer from the ring */
6718                 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6719
6720                 /* exit if we failed to retrieve a buffer */
6721                 if (!skb)
6722                         break;
6723
6724                 cleaned_count++;
6725
6726                 /* fetch next buffer in frame if non-eop */
6727                 if (igb_is_non_eop(rx_ring, rx_desc))
6728                         continue;
6729
6730                 /* verify the packet layout is correct */
6731                 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6732                         skb = NULL;
6733                         continue;
6734                 }
6735
6736                 /* probably a little skewed due to removing CRC */
6737                 total_bytes += skb->len;
6738
6739                 /* populate checksum, timestamp, VLAN, and protocol */
6740                 igb_process_skb_fields(rx_ring, rx_desc, skb);
6741
6742                 napi_gro_receive(&q_vector->napi, skb);
6743
6744                 /* reset skb pointer */
6745                 skb = NULL;
6746
6747                 /* update budget accounting */
6748                 total_packets++;
6749         } while (likely(total_packets < budget));
6750
6751         /* place incomplete frames back on ring for completion */
6752         rx_ring->skb = skb;
6753
6754         u64_stats_update_begin(&rx_ring->rx_syncp);
6755         rx_ring->rx_stats.packets += total_packets;
6756         rx_ring->rx_stats.bytes += total_bytes;
6757         u64_stats_update_end(&rx_ring->rx_syncp);
6758         q_vector->rx.total_packets += total_packets;
6759         q_vector->rx.total_bytes += total_bytes;
6760
6761         if (cleaned_count)
6762                 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6763
6764         return (total_packets < budget);
6765 }
6766
6767 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6768                                   struct igb_rx_buffer *bi)
6769 {
6770         struct page *page = bi->page;
6771         dma_addr_t dma;
6772
6773         /* since we are recycling buffers we should seldom need to alloc */
6774         if (likely(page))
6775                 return true;
6776
6777         /* alloc new page for storage */
6778         page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6779         if (unlikely(!page)) {
6780                 rx_ring->rx_stats.alloc_failed++;
6781                 return false;
6782         }
6783
6784         /* map page for use */
6785         dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6786
6787         /* if mapping failed free memory back to system since
6788          * there isn't much point in holding memory we can't use
6789          */
6790         if (dma_mapping_error(rx_ring->dev, dma)) {
6791                 __free_page(page);
6792
6793                 rx_ring->rx_stats.alloc_failed++;
6794                 return false;
6795         }
6796
6797         bi->dma = dma;
6798         bi->page = page;
6799         bi->page_offset = 0;
6800
6801         return true;
6802 }
6803
6804 /**
6805  *  igb_alloc_rx_buffers - Replace used receive buffers; packet split
6806  *  @adapter: address of board private structure
6807  **/
6808 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6809 {
6810         union e1000_adv_rx_desc *rx_desc;
6811         struct igb_rx_buffer *bi;
6812         u16 i = rx_ring->next_to_use;
6813
6814         /* nothing to do */
6815         if (!cleaned_count)
6816                 return;
6817
6818         rx_desc = IGB_RX_DESC(rx_ring, i);
6819         bi = &rx_ring->rx_buffer_info[i];
6820         i -= rx_ring->count;
6821
6822         do {
6823                 if (!igb_alloc_mapped_page(rx_ring, bi))
6824                         break;
6825
6826                 /* Refresh the desc even if buffer_addrs didn't change
6827                  * because each write-back erases this info.
6828                  */
6829                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
6830
6831                 rx_desc++;
6832                 bi++;
6833                 i++;
6834                 if (unlikely(!i)) {
6835                         rx_desc = IGB_RX_DESC(rx_ring, 0);
6836                         bi = rx_ring->rx_buffer_info;
6837                         i -= rx_ring->count;
6838                 }
6839
6840                 /* clear the hdr_addr for the next_to_use descriptor */
6841                 rx_desc->read.hdr_addr = 0;
6842
6843                 cleaned_count--;
6844         } while (cleaned_count);
6845
6846         i += rx_ring->count;
6847
6848         if (rx_ring->next_to_use != i) {
6849                 /* record the next descriptor to use */
6850                 rx_ring->next_to_use = i;
6851
6852                 /* update next to alloc since we have filled the ring */
6853                 rx_ring->next_to_alloc = i;
6854
6855                 /* Force memory writes to complete before letting h/w
6856                  * know there are new descriptors to fetch.  (Only
6857                  * applicable for weak-ordered memory model archs,
6858                  * such as IA-64).
6859                  */
6860                 wmb();
6861                 writel(i, rx_ring->tail);
6862         }
6863 }
6864
6865 /**
6866  * igb_mii_ioctl -
6867  * @netdev:
6868  * @ifreq:
6869  * @cmd:
6870  **/
6871 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6872 {
6873         struct igb_adapter *adapter = netdev_priv(netdev);
6874         struct mii_ioctl_data *data = if_mii(ifr);
6875
6876         if (adapter->hw.phy.media_type != e1000_media_type_copper)
6877                 return -EOPNOTSUPP;
6878
6879         switch (cmd) {
6880         case SIOCGMIIPHY:
6881                 data->phy_id = adapter->hw.phy.addr;
6882                 break;
6883         case SIOCGMIIREG:
6884                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6885                                      &data->val_out))
6886                         return -EIO;
6887                 break;
6888         case SIOCSMIIREG:
6889         default:
6890                 return -EOPNOTSUPP;
6891         }
6892         return 0;
6893 }
6894
6895 /**
6896  * igb_ioctl -
6897  * @netdev:
6898  * @ifreq:
6899  * @cmd:
6900  **/
6901 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6902 {
6903         switch (cmd) {
6904         case SIOCGMIIPHY:
6905         case SIOCGMIIREG:
6906         case SIOCSMIIREG:
6907                 return igb_mii_ioctl(netdev, ifr, cmd);
6908         case SIOCSHWTSTAMP:
6909                 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
6910         default:
6911                 return -EOPNOTSUPP;
6912         }
6913 }
6914
6915 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6916 {
6917         struct igb_adapter *adapter = hw->back;
6918
6919         if (pcie_capability_read_word(adapter->pdev, reg, value))
6920                 return -E1000_ERR_CONFIG;
6921
6922         return 0;
6923 }
6924
6925 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6926 {
6927         struct igb_adapter *adapter = hw->back;
6928
6929         if (pcie_capability_write_word(adapter->pdev, reg, *value))
6930                 return -E1000_ERR_CONFIG;
6931
6932         return 0;
6933 }
6934
6935 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6936 {
6937         struct igb_adapter *adapter = netdev_priv(netdev);
6938         struct e1000_hw *hw = &adapter->hw;
6939         u32 ctrl, rctl;
6940         bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
6941
6942         if (enable) {
6943                 /* enable VLAN tag insert/strip */
6944                 ctrl = rd32(E1000_CTRL);
6945                 ctrl |= E1000_CTRL_VME;
6946                 wr32(E1000_CTRL, ctrl);
6947
6948                 /* Disable CFI check */
6949                 rctl = rd32(E1000_RCTL);
6950                 rctl &= ~E1000_RCTL_CFIEN;
6951                 wr32(E1000_RCTL, rctl);
6952         } else {
6953                 /* disable VLAN tag insert/strip */
6954                 ctrl = rd32(E1000_CTRL);
6955                 ctrl &= ~E1000_CTRL_VME;
6956                 wr32(E1000_CTRL, ctrl);
6957         }
6958
6959         igb_rlpml_set(adapter);
6960 }
6961
6962 static int igb_vlan_rx_add_vid(struct net_device *netdev,
6963                                __be16 proto, u16 vid)
6964 {
6965         struct igb_adapter *adapter = netdev_priv(netdev);
6966         struct e1000_hw *hw = &adapter->hw;
6967         int pf_id = adapter->vfs_allocated_count;
6968
6969         /* attempt to add filter to vlvf array */
6970         igb_vlvf_set(adapter, vid, true, pf_id);
6971
6972         /* add the filter since PF can receive vlans w/o entry in vlvf */
6973         igb_vfta_set(hw, vid, true);
6974
6975         set_bit(vid, adapter->active_vlans);
6976
6977         return 0;
6978 }
6979
6980 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6981                                 __be16 proto, u16 vid)
6982 {
6983         struct igb_adapter *adapter = netdev_priv(netdev);
6984         struct e1000_hw *hw = &adapter->hw;
6985         int pf_id = adapter->vfs_allocated_count;
6986         s32 err;
6987
6988         /* remove vlan from VLVF table array */
6989         err = igb_vlvf_set(adapter, vid, false, pf_id);
6990
6991         /* if vid was not present in VLVF just remove it from table */
6992         if (err)
6993                 igb_vfta_set(hw, vid, false);
6994
6995         clear_bit(vid, adapter->active_vlans);
6996
6997         return 0;
6998 }
6999
7000 static void igb_restore_vlan(struct igb_adapter *adapter)
7001 {
7002         u16 vid;
7003
7004         igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7005
7006         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7007                 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7008 }
7009
7010 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7011 {
7012         struct pci_dev *pdev = adapter->pdev;
7013         struct e1000_mac_info *mac = &adapter->hw.mac;
7014
7015         mac->autoneg = 0;
7016
7017         /* Make sure dplx is at most 1 bit and lsb of speed is not set
7018          * for the switch() below to work
7019          */
7020         if ((spd & 1) || (dplx & ~1))
7021                 goto err_inval;
7022
7023         /* Fiber NIC's only allow 1000 gbps Full duplex
7024          * and 100Mbps Full duplex for 100baseFx sfp
7025          */
7026         if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7027                 switch (spd + dplx) {
7028                 case SPEED_10 + DUPLEX_HALF:
7029                 case SPEED_10 + DUPLEX_FULL:
7030                 case SPEED_100 + DUPLEX_HALF:
7031                         goto err_inval;
7032                 default:
7033                         break;
7034                 }
7035         }
7036
7037         switch (spd + dplx) {
7038         case SPEED_10 + DUPLEX_HALF:
7039                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7040                 break;
7041         case SPEED_10 + DUPLEX_FULL:
7042                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7043                 break;
7044         case SPEED_100 + DUPLEX_HALF:
7045                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7046                 break;
7047         case SPEED_100 + DUPLEX_FULL:
7048                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7049                 break;
7050         case SPEED_1000 + DUPLEX_FULL:
7051                 mac->autoneg = 1;
7052                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7053                 break;
7054         case SPEED_1000 + DUPLEX_HALF: /* not supported */
7055         default:
7056                 goto err_inval;
7057         }
7058
7059         /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7060         adapter->hw.phy.mdix = AUTO_ALL_MODES;
7061
7062         return 0;
7063
7064 err_inval:
7065         dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7066         return -EINVAL;
7067 }
7068
7069 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7070                           bool runtime)
7071 {
7072         struct net_device *netdev = pci_get_drvdata(pdev);
7073         struct igb_adapter *adapter = netdev_priv(netdev);
7074         struct e1000_hw *hw = &adapter->hw;
7075         u32 ctrl, rctl, status;
7076         u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7077 #ifdef CONFIG_PM
7078         int retval = 0;
7079 #endif
7080
7081         netif_device_detach(netdev);
7082
7083         if (netif_running(netdev))
7084                 __igb_close(netdev, true);
7085
7086         igb_clear_interrupt_scheme(adapter);
7087
7088 #ifdef CONFIG_PM
7089         retval = pci_save_state(pdev);
7090         if (retval)
7091                 return retval;
7092 #endif
7093
7094         status = rd32(E1000_STATUS);
7095         if (status & E1000_STATUS_LU)
7096                 wufc &= ~E1000_WUFC_LNKC;
7097
7098         if (wufc) {
7099                 igb_setup_rctl(adapter);
7100                 igb_set_rx_mode(netdev);
7101
7102                 /* turn on all-multi mode if wake on multicast is enabled */
7103                 if (wufc & E1000_WUFC_MC) {
7104                         rctl = rd32(E1000_RCTL);
7105                         rctl |= E1000_RCTL_MPE;
7106                         wr32(E1000_RCTL, rctl);
7107                 }
7108
7109                 ctrl = rd32(E1000_CTRL);
7110                 /* advertise wake from D3Cold */
7111                 #define E1000_CTRL_ADVD3WUC 0x00100000
7112                 /* phy power management enable */
7113                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7114                 ctrl |= E1000_CTRL_ADVD3WUC;
7115                 wr32(E1000_CTRL, ctrl);
7116
7117                 /* Allow time for pending master requests to run */
7118                 igb_disable_pcie_master(hw);
7119
7120                 wr32(E1000_WUC, E1000_WUC_PME_EN);
7121                 wr32(E1000_WUFC, wufc);
7122         } else {
7123                 wr32(E1000_WUC, 0);
7124                 wr32(E1000_WUFC, 0);
7125         }
7126
7127         *enable_wake = wufc || adapter->en_mng_pt;
7128         if (!*enable_wake)
7129                 igb_power_down_link(adapter);
7130         else
7131                 igb_power_up_link(adapter);
7132
7133         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
7134          * would have already happened in close and is redundant.
7135          */
7136         igb_release_hw_control(adapter);
7137
7138         pci_disable_device(pdev);
7139
7140         return 0;
7141 }
7142
7143 #ifdef CONFIG_PM
7144 #ifdef CONFIG_PM_SLEEP
7145 static int igb_suspend(struct device *dev)
7146 {
7147         int retval;
7148         bool wake;
7149         struct pci_dev *pdev = to_pci_dev(dev);
7150
7151         retval = __igb_shutdown(pdev, &wake, 0);
7152         if (retval)
7153                 return retval;
7154
7155         if (wake) {
7156                 pci_prepare_to_sleep(pdev);
7157         } else {
7158                 pci_wake_from_d3(pdev, false);
7159                 pci_set_power_state(pdev, PCI_D3hot);
7160         }
7161
7162         return 0;
7163 }
7164 #endif /* CONFIG_PM_SLEEP */
7165
7166 static int igb_resume(struct device *dev)
7167 {
7168         struct pci_dev *pdev = to_pci_dev(dev);
7169         struct net_device *netdev = pci_get_drvdata(pdev);
7170         struct igb_adapter *adapter = netdev_priv(netdev);
7171         struct e1000_hw *hw = &adapter->hw;
7172         u32 err;
7173
7174         pci_set_power_state(pdev, PCI_D0);
7175         pci_restore_state(pdev);
7176         pci_save_state(pdev);
7177
7178         err = pci_enable_device_mem(pdev);
7179         if (err) {
7180                 dev_err(&pdev->dev,
7181                         "igb: Cannot enable PCI device from suspend\n");
7182                 return err;
7183         }
7184         pci_set_master(pdev);
7185
7186         pci_enable_wake(pdev, PCI_D3hot, 0);
7187         pci_enable_wake(pdev, PCI_D3cold, 0);
7188
7189         if (igb_init_interrupt_scheme(adapter, true)) {
7190                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7191                 return -ENOMEM;
7192         }
7193
7194         igb_reset(adapter);
7195
7196         /* let the f/w know that the h/w is now under the control of the
7197          * driver.
7198          */
7199         igb_get_hw_control(adapter);
7200
7201         wr32(E1000_WUS, ~0);
7202
7203         if (netdev->flags & IFF_UP) {
7204                 rtnl_lock();
7205                 err = __igb_open(netdev, true);
7206                 rtnl_unlock();
7207                 if (err)
7208                         return err;
7209         }
7210
7211         netif_device_attach(netdev);
7212         return 0;
7213 }
7214
7215 #ifdef CONFIG_PM_RUNTIME
7216 static int igb_runtime_idle(struct device *dev)
7217 {
7218         struct pci_dev *pdev = to_pci_dev(dev);
7219         struct net_device *netdev = pci_get_drvdata(pdev);
7220         struct igb_adapter *adapter = netdev_priv(netdev);
7221
7222         if (!igb_has_link(adapter))
7223                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7224
7225         return -EBUSY;
7226 }
7227
7228 static int igb_runtime_suspend(struct device *dev)
7229 {
7230         struct pci_dev *pdev = to_pci_dev(dev);
7231         int retval;
7232         bool wake;
7233
7234         retval = __igb_shutdown(pdev, &wake, 1);
7235         if (retval)
7236                 return retval;
7237
7238         if (wake) {
7239                 pci_prepare_to_sleep(pdev);
7240         } else {
7241                 pci_wake_from_d3(pdev, false);
7242                 pci_set_power_state(pdev, PCI_D3hot);
7243         }
7244
7245         return 0;
7246 }
7247
7248 static int igb_runtime_resume(struct device *dev)
7249 {
7250         return igb_resume(dev);
7251 }
7252 #endif /* CONFIG_PM_RUNTIME */
7253 #endif
7254
7255 static void igb_shutdown(struct pci_dev *pdev)
7256 {
7257         bool wake;
7258
7259         __igb_shutdown(pdev, &wake, 0);
7260
7261         if (system_state == SYSTEM_POWER_OFF) {
7262                 pci_wake_from_d3(pdev, wake);
7263                 pci_set_power_state(pdev, PCI_D3hot);
7264         }
7265 }
7266
7267 #ifdef CONFIG_PCI_IOV
7268 static int igb_sriov_reinit(struct pci_dev *dev)
7269 {
7270         struct net_device *netdev = pci_get_drvdata(dev);
7271         struct igb_adapter *adapter = netdev_priv(netdev);
7272         struct pci_dev *pdev = adapter->pdev;
7273
7274         rtnl_lock();
7275
7276         if (netif_running(netdev))
7277                 igb_close(netdev);
7278
7279         igb_clear_interrupt_scheme(adapter);
7280
7281         igb_init_queue_configuration(adapter);
7282
7283         if (igb_init_interrupt_scheme(adapter, true)) {
7284                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7285                 return -ENOMEM;
7286         }
7287
7288         if (netif_running(netdev))
7289                 igb_open(netdev);
7290
7291         rtnl_unlock();
7292
7293         return 0;
7294 }
7295
7296 static int igb_pci_disable_sriov(struct pci_dev *dev)
7297 {
7298         int err = igb_disable_sriov(dev);
7299
7300         if (!err)
7301                 err = igb_sriov_reinit(dev);
7302
7303         return err;
7304 }
7305
7306 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7307 {
7308         int err = igb_enable_sriov(dev, num_vfs);
7309
7310         if (err)
7311                 goto out;
7312
7313         err = igb_sriov_reinit(dev);
7314         if (!err)
7315                 return num_vfs;
7316
7317 out:
7318         return err;
7319 }
7320
7321 #endif
7322 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7323 {
7324 #ifdef CONFIG_PCI_IOV
7325         if (num_vfs == 0)
7326                 return igb_pci_disable_sriov(dev);
7327         else
7328                 return igb_pci_enable_sriov(dev, num_vfs);
7329 #endif
7330         return 0;
7331 }
7332
7333 #ifdef CONFIG_NET_POLL_CONTROLLER
7334 /* Polling 'interrupt' - used by things like netconsole to send skbs
7335  * without having to re-enable interrupts. It's not called while
7336  * the interrupt routine is executing.
7337  */
7338 static void igb_netpoll(struct net_device *netdev)
7339 {
7340         struct igb_adapter *adapter = netdev_priv(netdev);
7341         struct e1000_hw *hw = &adapter->hw;
7342         struct igb_q_vector *q_vector;
7343         int i;
7344
7345         for (i = 0; i < adapter->num_q_vectors; i++) {
7346                 q_vector = adapter->q_vector[i];
7347                 if (adapter->msix_entries)
7348                         wr32(E1000_EIMC, q_vector->eims_value);
7349                 else
7350                         igb_irq_disable(adapter);
7351                 napi_schedule(&q_vector->napi);
7352         }
7353 }
7354 #endif /* CONFIG_NET_POLL_CONTROLLER */
7355
7356 /**
7357  *  igb_io_error_detected - called when PCI error is detected
7358  *  @pdev: Pointer to PCI device
7359  *  @state: The current pci connection state
7360  *
7361  *  This function is called after a PCI bus error affecting
7362  *  this device has been detected.
7363  **/
7364 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7365                                               pci_channel_state_t state)
7366 {
7367         struct net_device *netdev = pci_get_drvdata(pdev);
7368         struct igb_adapter *adapter = netdev_priv(netdev);
7369
7370         netif_device_detach(netdev);
7371
7372         if (state == pci_channel_io_perm_failure)
7373                 return PCI_ERS_RESULT_DISCONNECT;
7374
7375         if (netif_running(netdev))
7376                 igb_down(adapter);
7377         pci_disable_device(pdev);
7378
7379         /* Request a slot slot reset. */
7380         return PCI_ERS_RESULT_NEED_RESET;
7381 }
7382
7383 /**
7384  *  igb_io_slot_reset - called after the pci bus has been reset.
7385  *  @pdev: Pointer to PCI device
7386  *
7387  *  Restart the card from scratch, as if from a cold-boot. Implementation
7388  *  resembles the first-half of the igb_resume routine.
7389  **/
7390 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7391 {
7392         struct net_device *netdev = pci_get_drvdata(pdev);
7393         struct igb_adapter *adapter = netdev_priv(netdev);
7394         struct e1000_hw *hw = &adapter->hw;
7395         pci_ers_result_t result;
7396         int err;
7397
7398         if (pci_enable_device_mem(pdev)) {
7399                 dev_err(&pdev->dev,
7400                         "Cannot re-enable PCI device after reset.\n");
7401                 result = PCI_ERS_RESULT_DISCONNECT;
7402         } else {
7403                 pci_set_master(pdev);
7404                 pci_restore_state(pdev);
7405                 pci_save_state(pdev);
7406
7407                 pci_enable_wake(pdev, PCI_D3hot, 0);
7408                 pci_enable_wake(pdev, PCI_D3cold, 0);
7409
7410                 igb_reset(adapter);
7411                 wr32(E1000_WUS, ~0);
7412                 result = PCI_ERS_RESULT_RECOVERED;
7413         }
7414
7415         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7416         if (err) {
7417                 dev_err(&pdev->dev,
7418                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7419                         err);
7420                 /* non-fatal, continue */
7421         }
7422
7423         return result;
7424 }
7425
7426 /**
7427  *  igb_io_resume - called when traffic can start flowing again.
7428  *  @pdev: Pointer to PCI device
7429  *
7430  *  This callback is called when the error recovery driver tells us that
7431  *  its OK to resume normal operation. Implementation resembles the
7432  *  second-half of the igb_resume routine.
7433  */
7434 static void igb_io_resume(struct pci_dev *pdev)
7435 {
7436         struct net_device *netdev = pci_get_drvdata(pdev);
7437         struct igb_adapter *adapter = netdev_priv(netdev);
7438
7439         if (netif_running(netdev)) {
7440                 if (igb_up(adapter)) {
7441                         dev_err(&pdev->dev, "igb_up failed after reset\n");
7442                         return;
7443                 }
7444         }
7445
7446         netif_device_attach(netdev);
7447
7448         /* let the f/w know that the h/w is now under the control of the
7449          * driver.
7450          */
7451         igb_get_hw_control(adapter);
7452 }
7453
7454 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7455                              u8 qsel)
7456 {
7457         u32 rar_low, rar_high;
7458         struct e1000_hw *hw = &adapter->hw;
7459
7460         /* HW expects these in little endian so we reverse the byte order
7461          * from network order (big endian) to little endian
7462          */
7463         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7464                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7465         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7466
7467         /* Indicate to hardware the Address is Valid. */
7468         rar_high |= E1000_RAH_AV;
7469
7470         if (hw->mac.type == e1000_82575)
7471                 rar_high |= E1000_RAH_POOL_1 * qsel;
7472         else
7473                 rar_high |= E1000_RAH_POOL_1 << qsel;
7474
7475         wr32(E1000_RAL(index), rar_low);
7476         wrfl();
7477         wr32(E1000_RAH(index), rar_high);
7478         wrfl();
7479 }
7480
7481 static int igb_set_vf_mac(struct igb_adapter *adapter,
7482                           int vf, unsigned char *mac_addr)
7483 {
7484         struct e1000_hw *hw = &adapter->hw;
7485         /* VF MAC addresses start at end of receive addresses and moves
7486          * towards the first, as a result a collision should not be possible
7487          */
7488         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7489
7490         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7491
7492         igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7493
7494         return 0;
7495 }
7496
7497 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7498 {
7499         struct igb_adapter *adapter = netdev_priv(netdev);
7500         if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7501                 return -EINVAL;
7502         adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7503         dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7504         dev_info(&adapter->pdev->dev,
7505                  "Reload the VF driver to make this change effective.");
7506         if (test_bit(__IGB_DOWN, &adapter->state)) {
7507                 dev_warn(&adapter->pdev->dev,
7508                          "The VF MAC address has been set, but the PF device is not up.\n");
7509                 dev_warn(&adapter->pdev->dev,
7510                          "Bring the PF device up before attempting to use the VF device.\n");
7511         }
7512         return igb_set_vf_mac(adapter, vf, mac);
7513 }
7514
7515 static int igb_link_mbps(int internal_link_speed)
7516 {
7517         switch (internal_link_speed) {
7518         case SPEED_100:
7519                 return 100;
7520         case SPEED_1000:
7521                 return 1000;
7522         default:
7523                 return 0;
7524         }
7525 }
7526
7527 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7528                                   int link_speed)
7529 {
7530         int rf_dec, rf_int;
7531         u32 bcnrc_val;
7532
7533         if (tx_rate != 0) {
7534                 /* Calculate the rate factor values to set */
7535                 rf_int = link_speed / tx_rate;
7536                 rf_dec = (link_speed - (rf_int * tx_rate));
7537                 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7538                          tx_rate;
7539
7540                 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7541                 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7542                               E1000_RTTBCNRC_RF_INT_MASK);
7543                 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7544         } else {
7545                 bcnrc_val = 0;
7546         }
7547
7548         wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7549         /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7550          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7551          */
7552         wr32(E1000_RTTBCNRM, 0x14);
7553         wr32(E1000_RTTBCNRC, bcnrc_val);
7554 }
7555
7556 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7557 {
7558         int actual_link_speed, i;
7559         bool reset_rate = false;
7560
7561         /* VF TX rate limit was not set or not supported */
7562         if ((adapter->vf_rate_link_speed == 0) ||
7563             (adapter->hw.mac.type != e1000_82576))
7564                 return;
7565
7566         actual_link_speed = igb_link_mbps(adapter->link_speed);
7567         if (actual_link_speed != adapter->vf_rate_link_speed) {
7568                 reset_rate = true;
7569                 adapter->vf_rate_link_speed = 0;
7570                 dev_info(&adapter->pdev->dev,
7571                          "Link speed has been changed. VF Transmit rate is disabled\n");
7572         }
7573
7574         for (i = 0; i < adapter->vfs_allocated_count; i++) {
7575                 if (reset_rate)
7576                         adapter->vf_data[i].tx_rate = 0;
7577
7578                 igb_set_vf_rate_limit(&adapter->hw, i,
7579                                       adapter->vf_data[i].tx_rate,
7580                                       actual_link_speed);
7581         }
7582 }
7583
7584 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7585 {
7586         struct igb_adapter *adapter = netdev_priv(netdev);
7587         struct e1000_hw *hw = &adapter->hw;
7588         int actual_link_speed;
7589
7590         if (hw->mac.type != e1000_82576)
7591                 return -EOPNOTSUPP;
7592
7593         actual_link_speed = igb_link_mbps(adapter->link_speed);
7594         if ((vf >= adapter->vfs_allocated_count) ||
7595             (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7596             (tx_rate < 0) || (tx_rate > actual_link_speed))
7597                 return -EINVAL;
7598
7599         adapter->vf_rate_link_speed = actual_link_speed;
7600         adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7601         igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7602
7603         return 0;
7604 }
7605
7606 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7607                                    bool setting)
7608 {
7609         struct igb_adapter *adapter = netdev_priv(netdev);
7610         struct e1000_hw *hw = &adapter->hw;
7611         u32 reg_val, reg_offset;
7612
7613         if (!adapter->vfs_allocated_count)
7614                 return -EOPNOTSUPP;
7615
7616         if (vf >= adapter->vfs_allocated_count)
7617                 return -EINVAL;
7618
7619         reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7620         reg_val = rd32(reg_offset);
7621         if (setting)
7622                 reg_val |= ((1 << vf) |
7623                             (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7624         else
7625                 reg_val &= ~((1 << vf) |
7626                              (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7627         wr32(reg_offset, reg_val);
7628
7629         adapter->vf_data[vf].spoofchk_enabled = setting;
7630         return E1000_SUCCESS;
7631 }
7632
7633 static int igb_ndo_get_vf_config(struct net_device *netdev,
7634                                  int vf, struct ifla_vf_info *ivi)
7635 {
7636         struct igb_adapter *adapter = netdev_priv(netdev);
7637         if (vf >= adapter->vfs_allocated_count)
7638                 return -EINVAL;
7639         ivi->vf = vf;
7640         memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7641         ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7642         ivi->vlan = adapter->vf_data[vf].pf_vlan;
7643         ivi->qos = adapter->vf_data[vf].pf_qos;
7644         ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7645         return 0;
7646 }
7647
7648 static void igb_vmm_control(struct igb_adapter *adapter)
7649 {
7650         struct e1000_hw *hw = &adapter->hw;
7651         u32 reg;
7652
7653         switch (hw->mac.type) {
7654         case e1000_82575:
7655         case e1000_i210:
7656         case e1000_i211:
7657         case e1000_i354:
7658         default:
7659                 /* replication is not supported for 82575 */
7660                 return;
7661         case e1000_82576:
7662                 /* notify HW that the MAC is adding vlan tags */
7663                 reg = rd32(E1000_DTXCTL);
7664                 reg |= E1000_DTXCTL_VLAN_ADDED;
7665                 wr32(E1000_DTXCTL, reg);
7666         case e1000_82580:
7667                 /* enable replication vlan tag stripping */
7668                 reg = rd32(E1000_RPLOLR);
7669                 reg |= E1000_RPLOLR_STRVLAN;
7670                 wr32(E1000_RPLOLR, reg);
7671         case e1000_i350:
7672                 /* none of the above registers are supported by i350 */
7673                 break;
7674         }
7675
7676         if (adapter->vfs_allocated_count) {
7677                 igb_vmdq_set_loopback_pf(hw, true);
7678                 igb_vmdq_set_replication_pf(hw, true);
7679                 igb_vmdq_set_anti_spoofing_pf(hw, true,
7680                                               adapter->vfs_allocated_count);
7681         } else {
7682                 igb_vmdq_set_loopback_pf(hw, false);
7683                 igb_vmdq_set_replication_pf(hw, false);
7684         }
7685 }
7686
7687 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7688 {
7689         struct e1000_hw *hw = &adapter->hw;
7690         u32 dmac_thr;
7691         u16 hwm;
7692
7693         if (hw->mac.type > e1000_82580) {
7694                 if (adapter->flags & IGB_FLAG_DMAC) {
7695                         u32 reg;
7696
7697                         /* force threshold to 0. */
7698                         wr32(E1000_DMCTXTH, 0);
7699
7700                         /* DMA Coalescing high water mark needs to be greater
7701                          * than the Rx threshold. Set hwm to PBA - max frame
7702                          * size in 16B units, capping it at PBA - 6KB.
7703                          */
7704                         hwm = 64 * pba - adapter->max_frame_size / 16;
7705                         if (hwm < 64 * (pba - 6))
7706                                 hwm = 64 * (pba - 6);
7707                         reg = rd32(E1000_FCRTC);
7708                         reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7709                         reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7710                                 & E1000_FCRTC_RTH_COAL_MASK);
7711                         wr32(E1000_FCRTC, reg);
7712
7713                         /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7714                          * frame size, capping it at PBA - 10KB.
7715                          */
7716                         dmac_thr = pba - adapter->max_frame_size / 512;
7717                         if (dmac_thr < pba - 10)
7718                                 dmac_thr = pba - 10;
7719                         reg = rd32(E1000_DMACR);
7720                         reg &= ~E1000_DMACR_DMACTHR_MASK;
7721                         reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7722                                 & E1000_DMACR_DMACTHR_MASK);
7723
7724                         /* transition to L0x or L1 if available..*/
7725                         reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7726
7727                         /* watchdog timer= +-1000 usec in 32usec intervals */
7728                         reg |= (1000 >> 5);
7729
7730                         /* Disable BMC-to-OS Watchdog Enable */
7731                         if (hw->mac.type != e1000_i354)
7732                                 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7733
7734                         wr32(E1000_DMACR, reg);
7735
7736                         /* no lower threshold to disable
7737                          * coalescing(smart fifb)-UTRESH=0
7738                          */
7739                         wr32(E1000_DMCRTRH, 0);
7740
7741                         reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7742
7743                         wr32(E1000_DMCTLX, reg);
7744
7745                         /* free space in tx packet buffer to wake from
7746                          * DMA coal
7747                          */
7748                         wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7749                              (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7750
7751                         /* make low power state decision controlled
7752                          * by DMA coal
7753                          */
7754                         reg = rd32(E1000_PCIEMISC);
7755                         reg &= ~E1000_PCIEMISC_LX_DECISION;
7756                         wr32(E1000_PCIEMISC, reg);
7757                 } /* endif adapter->dmac is not disabled */
7758         } else if (hw->mac.type == e1000_82580) {
7759                 u32 reg = rd32(E1000_PCIEMISC);
7760                 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7761                 wr32(E1000_DMACR, 0);
7762         }
7763 }
7764
7765 /**
7766  *  igb_read_i2c_byte - Reads 8 bit word over I2C
7767  *  @hw: pointer to hardware structure
7768  *  @byte_offset: byte offset to read
7769  *  @dev_addr: device address
7770  *  @data: value read
7771  *
7772  *  Performs byte read operation over I2C interface at
7773  *  a specified device address.
7774  **/
7775 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7776                       u8 dev_addr, u8 *data)
7777 {
7778         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7779         struct i2c_client *this_client = adapter->i2c_client;
7780         s32 status;
7781         u16 swfw_mask = 0;
7782
7783         if (!this_client)
7784                 return E1000_ERR_I2C;
7785
7786         swfw_mask = E1000_SWFW_PHY0_SM;
7787
7788         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7789             != E1000_SUCCESS)
7790                 return E1000_ERR_SWFW_SYNC;
7791
7792         status = i2c_smbus_read_byte_data(this_client, byte_offset);
7793         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7794
7795         if (status < 0)
7796                 return E1000_ERR_I2C;
7797         else {
7798                 *data = status;
7799                 return E1000_SUCCESS;
7800         }
7801 }
7802
7803 /**
7804  *  igb_write_i2c_byte - Writes 8 bit word over I2C
7805  *  @hw: pointer to hardware structure
7806  *  @byte_offset: byte offset to write
7807  *  @dev_addr: device address
7808  *  @data: value to write
7809  *
7810  *  Performs byte write operation over I2C interface at
7811  *  a specified device address.
7812  **/
7813 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7814                        u8 dev_addr, u8 data)
7815 {
7816         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7817         struct i2c_client *this_client = adapter->i2c_client;
7818         s32 status;
7819         u16 swfw_mask = E1000_SWFW_PHY0_SM;
7820
7821         if (!this_client)
7822                 return E1000_ERR_I2C;
7823
7824         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7825                 return E1000_ERR_SWFW_SYNC;
7826         status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7827         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7828
7829         if (status)
7830                 return E1000_ERR_I2C;
7831         else
7832                 return E1000_SUCCESS;
7833
7834 }
7835 /* igb_main.c */