1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
54 #include <linux/dca.h>
56 #include <linux/i2c.h>
62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63 __stringify(BUILD) "-k"
64 char igb_driver_name[] = "igb";
65 char igb_driver_version[] = DRV_VERSION;
66 static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
68 static const char igb_copyright[] =
69 "Copyright (c) 2007-2014 Intel Corporation.";
71 static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
75 static const struct pci_device_id igb_pci_tbl[] = {
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
117 static int igb_setup_all_tx_resources(struct igb_adapter *);
118 static int igb_setup_all_rx_resources(struct igb_adapter *);
119 static void igb_free_all_tx_resources(struct igb_adapter *);
120 static void igb_free_all_rx_resources(struct igb_adapter *);
121 static void igb_setup_mrqc(struct igb_adapter *);
122 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123 static void igb_remove(struct pci_dev *pdev);
124 static int igb_sw_init(struct igb_adapter *);
125 static int igb_open(struct net_device *);
126 static int igb_close(struct net_device *);
127 static void igb_configure(struct igb_adapter *);
128 static void igb_configure_tx(struct igb_adapter *);
129 static void igb_configure_rx(struct igb_adapter *);
130 static void igb_clean_all_tx_rings(struct igb_adapter *);
131 static void igb_clean_all_rx_rings(struct igb_adapter *);
132 static void igb_clean_tx_ring(struct igb_ring *);
133 static void igb_clean_rx_ring(struct igb_ring *);
134 static void igb_set_rx_mode(struct net_device *);
135 static void igb_update_phy_info(unsigned long);
136 static void igb_watchdog(unsigned long);
137 static void igb_watchdog_task(struct work_struct *);
138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
141 static int igb_change_mtu(struct net_device *, int);
142 static int igb_set_mac(struct net_device *, void *);
143 static void igb_set_uta(struct igb_adapter *adapter);
144 static irqreturn_t igb_intr(int irq, void *);
145 static irqreturn_t igb_intr_msi(int irq, void *);
146 static irqreturn_t igb_msix_other(int irq, void *);
147 static irqreturn_t igb_msix_ring(int irq, void *);
148 #ifdef CONFIG_IGB_DCA
149 static void igb_update_dca(struct igb_q_vector *);
150 static void igb_setup_dca(struct igb_adapter *);
151 #endif /* CONFIG_IGB_DCA */
152 static int igb_poll(struct napi_struct *, int);
153 static bool igb_clean_tx_irq(struct igb_q_vector *);
154 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156 static void igb_tx_timeout(struct net_device *);
157 static void igb_reset_task(struct work_struct *);
158 static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162 static void igb_restore_vlan(struct igb_adapter *);
163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164 static void igb_ping_all_vfs(struct igb_adapter *);
165 static void igb_msg_task(struct igb_adapter *);
166 static void igb_vmm_control(struct igb_adapter *);
167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
177 static void igb_check_vf_rate_limit(struct igb_adapter *);
179 #ifdef CONFIG_PCI_IOV
180 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
185 #ifdef CONFIG_PM_SLEEP
186 static int igb_suspend(struct device *);
188 static int igb_resume(struct device *);
189 #ifdef CONFIG_PM_RUNTIME
190 static int igb_runtime_suspend(struct device *dev);
191 static int igb_runtime_resume(struct device *dev);
192 static int igb_runtime_idle(struct device *dev);
194 static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
200 static void igb_shutdown(struct pci_dev *);
201 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
202 #ifdef CONFIG_IGB_DCA
203 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204 static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
210 #ifdef CONFIG_NET_POLL_CONTROLLER
211 /* for netdump / net console */
212 static void igb_netpoll(struct net_device *);
214 #ifdef CONFIG_PCI_IOV
215 static unsigned int max_vfs;
216 module_param(max_vfs, uint, 0);
217 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
218 #endif /* CONFIG_PCI_IOV */
220 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223 static void igb_io_resume(struct pci_dev *);
225 static const struct pci_error_handlers igb_err_handler = {
226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
231 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
233 static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
237 .remove = igb_remove,
239 .driver.pm = &igb_pm_ops,
241 .shutdown = igb_shutdown,
242 .sriov_configure = igb_pci_sriov_configure,
243 .err_handler = &igb_err_handler
246 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248 MODULE_LICENSE("GPL");
249 MODULE_VERSION(DRV_VERSION);
251 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252 static int debug = -1;
253 module_param(debug, int, 0);
254 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
256 struct igb_reg_info {
261 static const struct igb_reg_info igb_reg_info_tbl[] = {
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
268 /* Interrupt Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
293 /* List Terminator */
297 /* igb_regdump - register printout routine */
298 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
304 switch (reginfo->ofs) {
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
363 /* igb_dump - Print registers, Tx-rings and Rx-rings */
364 static void igb_dump(struct igb_adapter *adapter)
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
377 if (!netif_msg_hw(adapter))
380 /* Print netdevice Info */
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
383 pr_info("Device Name state trans_start last_rx\n");
384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
390 pr_info(" Register Name Value\n");
391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
402 for (n = 0; n < adapter->num_tx_queues; n++) {
403 struct igb_tx_buffer *buffer_info;
404 tx_ring = adapter->tx_ring[n];
405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
420 /* Transmit Descriptor Formats
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
439 const char *next_desc;
440 struct igb_tx_buffer *buffer_info;
441 tx_desc = IGB_TX_DESC(tx_ring, i);
442 buffer_info = &tx_ring->tx_buffer_info[i];
443 u0 = (struct my_u0 *)tx_desc;
444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
449 else if (i == tx_ring->next_to_clean)
454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
461 buffer_info->skb, next_desc);
463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
464 print_hex_dump(KERN_INFO, "",
466 16, 1, buffer_info->skb->data,
467 dma_unmap_len(buffer_info, len),
472 /* Print RX Rings Summary */
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
475 pr_info("Queue [NTU] [NTC]\n");
476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
483 if (!netif_msg_rx_status(adapter))
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
488 /* Advanced Receive Descriptor (Read) Format
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
497 * Advanced Receive Descriptor (Write-Back) Format
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
517 for (i = 0; i < rx_ring->count; i++) {
518 const char *next_desc;
519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
521 rx_desc = IGB_RX_DESC(rx_ring, i);
522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
525 if (i == rx_ring->next_to_use)
527 else if (i == rx_ring->next_to_clean)
532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
544 (u64)buffer_info->dma,
547 if (netif_msg_pktdata(adapter) &&
548 buffer_info->dma && buffer_info->page) {
549 print_hex_dump(KERN_INFO, "",
552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
565 * igb_get_i2c_data - Reads the I2C SDA data bit
566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
569 * Returns the I2C data bit value
571 static int igb_get_i2c_data(void *data)
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
577 return !!(i2cctl & E1000_I2C_DATA_IN);
581 * igb_set_i2c_data - Sets the I2C data bit
582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
585 * Sets the I2C data bit
587 static void igb_set_i2c_data(void *data, int state)
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
594 i2cctl |= E1000_I2C_DATA_OUT;
596 i2cctl &= ~E1000_I2C_DATA_OUT;
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
606 * igb_set_i2c_clk - Sets the I2C SCL clock
607 * @data: pointer to hardware structure
608 * @state: state to set clock
610 * Sets the I2C clock line to state
612 static void igb_set_i2c_clk(void *data, int state)
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
625 wr32(E1000_I2CPARAMS, i2cctl);
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
631 * @data: pointer to hardware structure
633 * Gets the I2C clock state
635 static int igb_get_i2c_clk(void *data)
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
641 return !!(i2cctl & E1000_I2C_CLK_IN);
644 static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
657 * used by hardware layer to print debugging information
659 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
661 struct igb_adapter *adapter = hw->back;
662 return adapter->netdev;
666 * igb_init_module - Driver Registration Routine
668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
671 static int __init igb_init_module(void)
675 pr_info("%s - version %s\n",
676 igb_driver_string, igb_driver_version);
677 pr_info("%s\n", igb_copyright);
679 #ifdef CONFIG_IGB_DCA
680 dca_register_notify(&dca_notifier);
682 ret = pci_register_driver(&igb_driver);
686 module_init(igb_init_module);
689 * igb_exit_module - Driver Exit Cleanup Routine
691 * igb_exit_module is called just before the driver is removed
694 static void __exit igb_exit_module(void)
696 #ifdef CONFIG_IGB_DCA
697 dca_unregister_notify(&dca_notifier);
699 pci_unregister_driver(&igb_driver);
702 module_exit(igb_exit_module);
704 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
712 static void igb_cache_ring_register(struct igb_adapter *adapter)
715 u32 rbase_offset = adapter->vfs_allocated_count;
717 switch (adapter->hw.mac.type) {
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
724 if (adapter->vfs_allocated_count) {
725 for (; i < adapter->rss_queues; i++)
726 adapter->rx_ring[i]->reg_idx = rbase_offset +
738 for (; i < adapter->num_rx_queues; i++)
739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
740 for (; j < adapter->num_tx_queues; j++)
741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
746 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
752 if (E1000_REMOVED(hw_addr))
755 value = readl(&hw_addr[reg]);
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
780 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
783 u32 ivar = array_rd32(E1000_IVAR0, index);
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
791 array_wr32(E1000_IVAR0, index, ivar);
794 #define IGB_N0_QUEUE -1
795 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
797 struct igb_adapter *adapter = q_vector->adapter;
798 struct e1000_hw *hw = &adapter->hw;
799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
808 switch (hw->mac.type) {
810 /* The 82575 assigns vectors using a bitmask, which matches the
811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
815 if (rx_queue > IGB_N0_QUEUE)
816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
817 if (tx_queue > IGB_N0_QUEUE)
818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
820 msixbm |= E1000_EIMS_OTHER;
821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
822 q_vector->eims_value = msixbm;
825 /* 82576 uses a table that essentially consists of 2 columns
826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
837 ((tx_queue & 0x8) << 1) + 8);
838 q_vector->eims_value = 1 << msix_vector;
845 /* On 82580 and newer adapters the scheme is similar to 82576
846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
858 ((tx_queue & 0x1) << 4) + 8);
859 q_vector->eims_value = 1 << msix_vector;
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
880 static void igb_configure_msix(struct igb_adapter *adapter)
884 struct e1000_hw *hw = &adapter->hw;
886 adapter->eims_enable_mask = 0;
888 /* set vector for other causes, i.e. link changes */
889 switch (hw->mac.type) {
891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
899 wr32(E1000_CTRL_EXT, tmp);
901 /* enable msix_other interrupt */
902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
903 adapter->eims_other = E1000_EIMS_OTHER;
913 /* Turn on MSI-X capability first, or our settings
914 * won't stick. And it will take days to debug.
916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
924 wr32(E1000_IVAR_MISC, tmp);
927 /* do nothing, since nothing else supports MSI-X */
929 } /* switch (hw->mac.type) */
931 adapter->eims_enable_mask |= adapter->eims_other;
933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
946 static int igb_request_msix(struct igb_adapter *adapter)
948 struct net_device *netdev = adapter->netdev;
949 struct e1000_hw *hw = &adapter->hw;
950 int i, err = 0, vector = 0, free_vector = 0;
952 err = request_irq(adapter->msix_entries[vector].vector,
953 igb_msix_other, 0, netdev->name, adapter);
957 for (i = 0; i < adapter->num_q_vectors; i++) {
958 struct igb_q_vector *q_vector = adapter->q_vector[i];
962 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
964 if (q_vector->rx.ring && q_vector->tx.ring)
965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
966 q_vector->rx.ring->queue_index);
967 else if (q_vector->tx.ring)
968 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
969 q_vector->tx.ring->queue_index);
970 else if (q_vector->rx.ring)
971 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
972 q_vector->rx.ring->queue_index);
974 sprintf(q_vector->name, "%s-unused", netdev->name);
976 err = request_irq(adapter->msix_entries[vector].vector,
977 igb_msix_ring, 0, q_vector->name,
983 igb_configure_msix(adapter);
987 /* free already assigned IRQs */
988 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
991 for (i = 0; i < vector; i++) {
992 free_irq(adapter->msix_entries[free_vector++].vector,
993 adapter->q_vector[i]);
1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1001 * @adapter: board private structure to initialize
1002 * @v_idx: Index of vector to be freed
1004 * This function frees the memory allocated to the q_vector.
1006 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1010 adapter->q_vector[v_idx] = NULL;
1012 /* igb_get_stats64() might access the rings on this vector,
1013 * we must wait a grace period before freeing it.
1015 kfree_rcu(q_vector, rcu);
1019 * igb_reset_q_vector - Reset config for interrupt vector
1020 * @adapter: board private structure to initialize
1021 * @v_idx: Index of vector to be reset
1023 * If NAPI is enabled it will delete any references to the
1024 * NAPI struct. This is preparation for igb_free_q_vector.
1026 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1031 * allocated. So, q_vector is NULL so we should stop here.
1036 if (q_vector->tx.ring)
1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1039 if (q_vector->rx.ring)
1040 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1042 netif_napi_del(&q_vector->napi);
1046 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1048 int v_idx = adapter->num_q_vectors;
1050 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1051 pci_disable_msix(adapter->pdev);
1052 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1053 pci_disable_msi(adapter->pdev);
1056 igb_reset_q_vector(adapter, v_idx);
1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1061 * @adapter: board private structure to initialize
1063 * This function frees the memory allocated to the q_vectors. In addition if
1064 * NAPI is enabled it will delete any references to the NAPI struct prior
1065 * to freeing the q_vector.
1067 static void igb_free_q_vectors(struct igb_adapter *adapter)
1069 int v_idx = adapter->num_q_vectors;
1071 adapter->num_tx_queues = 0;
1072 adapter->num_rx_queues = 0;
1073 adapter->num_q_vectors = 0;
1076 igb_reset_q_vector(adapter, v_idx);
1077 igb_free_q_vector(adapter, v_idx);
1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1083 * @adapter: board private structure to initialize
1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1086 * MSI-X interrupts allocated.
1088 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1090 igb_free_q_vectors(adapter);
1091 igb_reset_interrupt_capability(adapter);
1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1096 * @adapter: board private structure to initialize
1097 * @msix: boolean value of MSIX capability
1099 * Attempt to configure interrupts using the best available
1100 * capabilities of the hardware and kernel.
1102 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1109 adapter->flags |= IGB_FLAG_HAS_MSIX;
1111 /* Number of supported queues. */
1112 adapter->num_rx_queues = adapter->rss_queues;
1113 if (adapter->vfs_allocated_count)
1114 adapter->num_tx_queues = 1;
1116 adapter->num_tx_queues = adapter->rss_queues;
1118 /* start with one vector for every Rx queue */
1119 numvecs = adapter->num_rx_queues;
1121 /* if Tx handler is separate add 1 for every Tx queue */
1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1123 numvecs += adapter->num_tx_queues;
1125 /* store the number of vectors reserved for queues */
1126 adapter->num_q_vectors = numvecs;
1128 /* add 1 vector for link status interrupts */
1130 for (i = 0; i < numvecs; i++)
1131 adapter->msix_entries[i].entry = i;
1133 err = pci_enable_msix_range(adapter->pdev,
1134 adapter->msix_entries,
1140 igb_reset_interrupt_capability(adapter);
1142 /* If we can't do MSI-X, try MSI */
1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1145 #ifdef CONFIG_PCI_IOV
1146 /* disable SR-IOV for non MSI-X configurations */
1147 if (adapter->vf_data) {
1148 struct e1000_hw *hw = &adapter->hw;
1149 /* disable iov and allow time for transactions to clear */
1150 pci_disable_sriov(adapter->pdev);
1153 kfree(adapter->vf_data);
1154 adapter->vf_data = NULL;
1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1161 adapter->vfs_allocated_count = 0;
1162 adapter->rss_queues = 1;
1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1164 adapter->num_rx_queues = 1;
1165 adapter->num_tx_queues = 1;
1166 adapter->num_q_vectors = 1;
1167 if (!pci_enable_msi(adapter->pdev))
1168 adapter->flags |= IGB_FLAG_HAS_MSI;
1171 static void igb_add_ring(struct igb_ring *ring,
1172 struct igb_ring_container *head)
1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1180 * @adapter: board private structure to initialize
1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1182 * @v_idx: index of vector in adapter struct
1183 * @txr_count: total number of Tx rings to allocate
1184 * @txr_idx: index of first Tx ring to allocate
1185 * @rxr_count: total number of Rx rings to allocate
1186 * @rxr_idx: index of first Rx ring to allocate
1188 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1190 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1191 int v_count, int v_idx,
1192 int txr_count, int txr_idx,
1193 int rxr_count, int rxr_idx)
1195 struct igb_q_vector *q_vector;
1196 struct igb_ring *ring;
1197 int ring_count, size;
1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1200 if (txr_count > 1 || rxr_count > 1)
1203 ring_count = txr_count + rxr_count;
1204 size = sizeof(struct igb_q_vector) +
1205 (sizeof(struct igb_ring) * ring_count);
1207 /* allocate q_vector and rings */
1208 q_vector = adapter->q_vector[v_idx];
1210 q_vector = kzalloc(size, GFP_KERNEL);
1214 /* initialize NAPI */
1215 netif_napi_add(adapter->netdev, &q_vector->napi,
1218 /* tie q_vector and adapter together */
1219 adapter->q_vector[v_idx] = q_vector;
1220 q_vector->adapter = adapter;
1222 /* initialize work limits */
1223 q_vector->tx.work_limit = adapter->tx_work_limit;
1225 /* initialize ITR configuration */
1226 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1227 q_vector->itr_val = IGB_START_ITR;
1229 /* initialize pointer to rings */
1230 ring = q_vector->ring;
1234 /* rx or rx/tx vector */
1235 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1236 q_vector->itr_val = adapter->rx_itr_setting;
1238 /* tx only vector */
1239 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1240 q_vector->itr_val = adapter->tx_itr_setting;
1244 /* assign generic ring traits */
1245 ring->dev = &adapter->pdev->dev;
1246 ring->netdev = adapter->netdev;
1248 /* configure backlink on ring */
1249 ring->q_vector = q_vector;
1251 /* update q_vector Tx values */
1252 igb_add_ring(ring, &q_vector->tx);
1254 /* For 82575, context index must be unique per ring. */
1255 if (adapter->hw.mac.type == e1000_82575)
1256 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1258 /* apply Tx specific ring traits */
1259 ring->count = adapter->tx_ring_count;
1260 ring->queue_index = txr_idx;
1262 u64_stats_init(&ring->tx_syncp);
1263 u64_stats_init(&ring->tx_syncp2);
1265 /* assign ring to adapter */
1266 adapter->tx_ring[txr_idx] = ring;
1268 /* push pointer to next ring */
1273 /* assign generic ring traits */
1274 ring->dev = &adapter->pdev->dev;
1275 ring->netdev = adapter->netdev;
1277 /* configure backlink on ring */
1278 ring->q_vector = q_vector;
1280 /* update q_vector Rx values */
1281 igb_add_ring(ring, &q_vector->rx);
1283 /* set flag indicating ring supports SCTP checksum offload */
1284 if (adapter->hw.mac.type >= e1000_82576)
1285 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1287 /* On i350, i354, i210, and i211, loopback VLAN packets
1288 * have the tag byte-swapped.
1290 if (adapter->hw.mac.type >= e1000_i350)
1291 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1293 /* apply Rx specific ring traits */
1294 ring->count = adapter->rx_ring_count;
1295 ring->queue_index = rxr_idx;
1297 u64_stats_init(&ring->rx_syncp);
1299 /* assign ring to adapter */
1300 adapter->rx_ring[rxr_idx] = ring;
1308 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1309 * @adapter: board private structure to initialize
1311 * We allocate one q_vector per queue interrupt. If allocation fails we
1314 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1316 int q_vectors = adapter->num_q_vectors;
1317 int rxr_remaining = adapter->num_rx_queues;
1318 int txr_remaining = adapter->num_tx_queues;
1319 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1322 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1323 for (; rxr_remaining; v_idx++) {
1324 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1330 /* update counts and index */
1336 for (; v_idx < q_vectors; v_idx++) {
1337 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1338 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1340 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1341 tqpv, txr_idx, rqpv, rxr_idx);
1346 /* update counts and index */
1347 rxr_remaining -= rqpv;
1348 txr_remaining -= tqpv;
1356 adapter->num_tx_queues = 0;
1357 adapter->num_rx_queues = 0;
1358 adapter->num_q_vectors = 0;
1361 igb_free_q_vector(adapter, v_idx);
1367 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1368 * @adapter: board private structure to initialize
1369 * @msix: boolean value of MSIX capability
1371 * This function initializes the interrupts and allocates all of the queues.
1373 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1375 struct pci_dev *pdev = adapter->pdev;
1378 igb_set_interrupt_capability(adapter, msix);
1380 err = igb_alloc_q_vectors(adapter);
1382 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1383 goto err_alloc_q_vectors;
1386 igb_cache_ring_register(adapter);
1390 err_alloc_q_vectors:
1391 igb_reset_interrupt_capability(adapter);
1396 * igb_request_irq - initialize interrupts
1397 * @adapter: board private structure to initialize
1399 * Attempts to configure interrupts using the best available
1400 * capabilities of the hardware and kernel.
1402 static int igb_request_irq(struct igb_adapter *adapter)
1404 struct net_device *netdev = adapter->netdev;
1405 struct pci_dev *pdev = adapter->pdev;
1408 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1409 err = igb_request_msix(adapter);
1412 /* fall back to MSI */
1413 igb_free_all_tx_resources(adapter);
1414 igb_free_all_rx_resources(adapter);
1416 igb_clear_interrupt_scheme(adapter);
1417 err = igb_init_interrupt_scheme(adapter, false);
1421 igb_setup_all_tx_resources(adapter);
1422 igb_setup_all_rx_resources(adapter);
1423 igb_configure(adapter);
1426 igb_assign_vector(adapter->q_vector[0], 0);
1428 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1429 err = request_irq(pdev->irq, igb_intr_msi, 0,
1430 netdev->name, adapter);
1434 /* fall back to legacy interrupts */
1435 igb_reset_interrupt_capability(adapter);
1436 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1439 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1440 netdev->name, adapter);
1443 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1450 static void igb_free_irq(struct igb_adapter *adapter)
1452 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1455 free_irq(adapter->msix_entries[vector++].vector, adapter);
1457 for (i = 0; i < adapter->num_q_vectors; i++)
1458 free_irq(adapter->msix_entries[vector++].vector,
1459 adapter->q_vector[i]);
1461 free_irq(adapter->pdev->irq, adapter);
1466 * igb_irq_disable - Mask off interrupt generation on the NIC
1467 * @adapter: board private structure
1469 static void igb_irq_disable(struct igb_adapter *adapter)
1471 struct e1000_hw *hw = &adapter->hw;
1473 /* we need to be careful when disabling interrupts. The VFs are also
1474 * mapped into these registers and so clearing the bits can cause
1475 * issues on the VF drivers so we only need to clear what we set
1477 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1478 u32 regval = rd32(E1000_EIAM);
1480 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1481 wr32(E1000_EIMC, adapter->eims_enable_mask);
1482 regval = rd32(E1000_EIAC);
1483 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1487 wr32(E1000_IMC, ~0);
1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1492 for (i = 0; i < adapter->num_q_vectors; i++)
1493 synchronize_irq(adapter->msix_entries[i].vector);
1495 synchronize_irq(adapter->pdev->irq);
1500 * igb_irq_enable - Enable default interrupt generation settings
1501 * @adapter: board private structure
1503 static void igb_irq_enable(struct igb_adapter *adapter)
1505 struct e1000_hw *hw = &adapter->hw;
1507 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1508 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1509 u32 regval = rd32(E1000_EIAC);
1511 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1512 regval = rd32(E1000_EIAM);
1513 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1514 wr32(E1000_EIMS, adapter->eims_enable_mask);
1515 if (adapter->vfs_allocated_count) {
1516 wr32(E1000_MBVFIMR, 0xFF);
1517 ims |= E1000_IMS_VMMB;
1519 wr32(E1000_IMS, ims);
1521 wr32(E1000_IMS, IMS_ENABLE_MASK |
1523 wr32(E1000_IAM, IMS_ENABLE_MASK |
1528 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1530 struct e1000_hw *hw = &adapter->hw;
1531 u16 vid = adapter->hw.mng_cookie.vlan_id;
1532 u16 old_vid = adapter->mng_vlan_id;
1534 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1535 /* add VID to filter table */
1536 igb_vfta_set(hw, vid, true);
1537 adapter->mng_vlan_id = vid;
1539 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1542 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1544 !test_bit(old_vid, adapter->active_vlans)) {
1545 /* remove VID from filter table */
1546 igb_vfta_set(hw, old_vid, false);
1551 * igb_release_hw_control - release control of the h/w to f/w
1552 * @adapter: address of board private structure
1554 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1555 * For ASF and Pass Through versions of f/w this means that the
1556 * driver is no longer loaded.
1558 static void igb_release_hw_control(struct igb_adapter *adapter)
1560 struct e1000_hw *hw = &adapter->hw;
1563 /* Let firmware take over control of h/w */
1564 ctrl_ext = rd32(E1000_CTRL_EXT);
1565 wr32(E1000_CTRL_EXT,
1566 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1570 * igb_get_hw_control - get control of the h/w from f/w
1571 * @adapter: address of board private structure
1573 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1574 * For ASF and Pass Through versions of f/w this means that
1575 * the driver is loaded.
1577 static void igb_get_hw_control(struct igb_adapter *adapter)
1579 struct e1000_hw *hw = &adapter->hw;
1582 /* Let firmware know the driver has taken over */
1583 ctrl_ext = rd32(E1000_CTRL_EXT);
1584 wr32(E1000_CTRL_EXT,
1585 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1589 * igb_configure - configure the hardware for RX and TX
1590 * @adapter: private board structure
1592 static void igb_configure(struct igb_adapter *adapter)
1594 struct net_device *netdev = adapter->netdev;
1597 igb_get_hw_control(adapter);
1598 igb_set_rx_mode(netdev);
1600 igb_restore_vlan(adapter);
1602 igb_setup_tctl(adapter);
1603 igb_setup_mrqc(adapter);
1604 igb_setup_rctl(adapter);
1606 igb_configure_tx(adapter);
1607 igb_configure_rx(adapter);
1609 igb_rx_fifo_flush_82575(&adapter->hw);
1611 /* call igb_desc_unused which always leaves
1612 * at least 1 descriptor unused to make sure
1613 * next_to_use != next_to_clean
1615 for (i = 0; i < adapter->num_rx_queues; i++) {
1616 struct igb_ring *ring = adapter->rx_ring[i];
1617 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1622 * igb_power_up_link - Power up the phy/serdes link
1623 * @adapter: address of board private structure
1625 void igb_power_up_link(struct igb_adapter *adapter)
1627 igb_reset_phy(&adapter->hw);
1629 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1630 igb_power_up_phy_copper(&adapter->hw);
1632 igb_power_up_serdes_link_82575(&adapter->hw);
1634 igb_setup_link(&adapter->hw);
1638 * igb_power_down_link - Power down the phy/serdes link
1639 * @adapter: address of board private structure
1641 static void igb_power_down_link(struct igb_adapter *adapter)
1643 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1644 igb_power_down_phy_copper_82575(&adapter->hw);
1646 igb_shutdown_serdes_link_82575(&adapter->hw);
1650 * Detect and switch function for Media Auto Sense
1651 * @adapter: address of the board private structure
1653 static void igb_check_swap_media(struct igb_adapter *adapter)
1655 struct e1000_hw *hw = &adapter->hw;
1656 u32 ctrl_ext, connsw;
1657 bool swap_now = false;
1659 ctrl_ext = rd32(E1000_CTRL_EXT);
1660 connsw = rd32(E1000_CONNSW);
1662 /* need to live swap if current media is copper and we have fiber/serdes
1666 if ((hw->phy.media_type == e1000_media_type_copper) &&
1667 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1669 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1670 /* copper signal takes time to appear */
1671 if (adapter->copper_tries < 4) {
1672 adapter->copper_tries++;
1673 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1674 wr32(E1000_CONNSW, connsw);
1677 adapter->copper_tries = 0;
1678 if ((connsw & E1000_CONNSW_PHYSD) &&
1679 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1681 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1682 wr32(E1000_CONNSW, connsw);
1690 switch (hw->phy.media_type) {
1691 case e1000_media_type_copper:
1692 netdev_info(adapter->netdev,
1693 "MAS: changing media to fiber/serdes\n");
1695 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1696 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1697 adapter->copper_tries = 0;
1699 case e1000_media_type_internal_serdes:
1700 case e1000_media_type_fiber:
1701 netdev_info(adapter->netdev,
1702 "MAS: changing media to copper\n");
1704 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1705 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1708 /* shouldn't get here during regular operation */
1709 netdev_err(adapter->netdev,
1710 "AMS: Invalid media type found, returning\n");
1713 wr32(E1000_CTRL_EXT, ctrl_ext);
1717 * igb_up - Open the interface and prepare it to handle traffic
1718 * @adapter: board private structure
1720 int igb_up(struct igb_adapter *adapter)
1722 struct e1000_hw *hw = &adapter->hw;
1725 /* hardware has been reset, we need to reload some things */
1726 igb_configure(adapter);
1728 clear_bit(__IGB_DOWN, &adapter->state);
1730 for (i = 0; i < adapter->num_q_vectors; i++)
1731 napi_enable(&(adapter->q_vector[i]->napi));
1733 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1734 igb_configure_msix(adapter);
1736 igb_assign_vector(adapter->q_vector[0], 0);
1738 /* Clear any pending interrupts. */
1740 igb_irq_enable(adapter);
1742 /* notify VFs that reset has been completed */
1743 if (adapter->vfs_allocated_count) {
1744 u32 reg_data = rd32(E1000_CTRL_EXT);
1746 reg_data |= E1000_CTRL_EXT_PFRSTD;
1747 wr32(E1000_CTRL_EXT, reg_data);
1750 netif_tx_start_all_queues(adapter->netdev);
1752 /* start the watchdog. */
1753 hw->mac.get_link_status = 1;
1754 schedule_work(&adapter->watchdog_task);
1756 if ((adapter->flags & IGB_FLAG_EEE) &&
1757 (!hw->dev_spec._82575.eee_disable))
1758 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1763 void igb_down(struct igb_adapter *adapter)
1765 struct net_device *netdev = adapter->netdev;
1766 struct e1000_hw *hw = &adapter->hw;
1770 /* signal that we're down so the interrupt handler does not
1771 * reschedule our watchdog timer
1773 set_bit(__IGB_DOWN, &adapter->state);
1775 /* disable receives in the hardware */
1776 rctl = rd32(E1000_RCTL);
1777 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1778 /* flush and sleep below */
1780 netif_tx_stop_all_queues(netdev);
1782 /* disable transmits in the hardware */
1783 tctl = rd32(E1000_TCTL);
1784 tctl &= ~E1000_TCTL_EN;
1785 wr32(E1000_TCTL, tctl);
1786 /* flush both disables and wait for them to finish */
1788 usleep_range(10000, 11000);
1790 igb_irq_disable(adapter);
1792 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1794 for (i = 0; i < adapter->num_q_vectors; i++) {
1795 napi_synchronize(&(adapter->q_vector[i]->napi));
1796 napi_disable(&(adapter->q_vector[i]->napi));
1800 del_timer_sync(&adapter->watchdog_timer);
1801 del_timer_sync(&adapter->phy_info_timer);
1803 netif_carrier_off(netdev);
1805 /* record the stats before reset*/
1806 spin_lock(&adapter->stats64_lock);
1807 igb_update_stats(adapter, &adapter->stats64);
1808 spin_unlock(&adapter->stats64_lock);
1810 adapter->link_speed = 0;
1811 adapter->link_duplex = 0;
1813 if (!pci_channel_offline(adapter->pdev))
1815 igb_clean_all_tx_rings(adapter);
1816 igb_clean_all_rx_rings(adapter);
1817 #ifdef CONFIG_IGB_DCA
1819 /* since we reset the hardware DCA settings were cleared */
1820 igb_setup_dca(adapter);
1824 void igb_reinit_locked(struct igb_adapter *adapter)
1826 WARN_ON(in_interrupt());
1827 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1828 usleep_range(1000, 2000);
1831 clear_bit(__IGB_RESETTING, &adapter->state);
1834 /** igb_enable_mas - Media Autosense re-enable after swap
1836 * @adapter: adapter struct
1838 static s32 igb_enable_mas(struct igb_adapter *adapter)
1840 struct e1000_hw *hw = &adapter->hw;
1844 connsw = rd32(E1000_CONNSW);
1845 if (!(hw->phy.media_type == e1000_media_type_copper))
1848 /* configure for SerDes media detect */
1849 if (!(connsw & E1000_CONNSW_SERDESD)) {
1850 connsw |= E1000_CONNSW_ENRGSRC;
1851 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1852 wr32(E1000_CONNSW, connsw);
1854 } else if (connsw & E1000_CONNSW_SERDESD) {
1855 /* already SerDes, no need to enable anything */
1858 netdev_info(adapter->netdev,
1859 "MAS: Unable to configure feature, disabling..\n");
1860 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1865 void igb_reset(struct igb_adapter *adapter)
1867 struct pci_dev *pdev = adapter->pdev;
1868 struct e1000_hw *hw = &adapter->hw;
1869 struct e1000_mac_info *mac = &hw->mac;
1870 struct e1000_fc_info *fc = &hw->fc;
1871 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1873 /* Repartition Pba for greater than 9k mtu
1874 * To take effect CTRL.RST is required.
1876 switch (mac->type) {
1880 pba = rd32(E1000_RXPBS);
1881 pba = igb_rxpbs_adjust_82580(pba);
1884 pba = rd32(E1000_RXPBS);
1885 pba &= E1000_RXPBS_SIZE_MASK_82576;
1891 pba = E1000_PBA_34K;
1895 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1896 (mac->type < e1000_82576)) {
1897 /* adjust PBA for jumbo frames */
1898 wr32(E1000_PBA, pba);
1900 /* To maintain wire speed transmits, the Tx FIFO should be
1901 * large enough to accommodate two full transmit packets,
1902 * rounded up to the next 1KB and expressed in KB. Likewise,
1903 * the Rx FIFO should be large enough to accommodate at least
1904 * one full receive packet and is similarly rounded up and
1907 pba = rd32(E1000_PBA);
1908 /* upper 16 bits has Tx packet buffer allocation size in KB */
1909 tx_space = pba >> 16;
1910 /* lower 16 bits has Rx packet buffer allocation size in KB */
1912 /* the Tx fifo also stores 16 bytes of information about the Tx
1913 * but don't include ethernet FCS because hardware appends it
1915 min_tx_space = (adapter->max_frame_size +
1916 sizeof(union e1000_adv_tx_desc) -
1918 min_tx_space = ALIGN(min_tx_space, 1024);
1919 min_tx_space >>= 10;
1920 /* software strips receive CRC, so leave room for it */
1921 min_rx_space = adapter->max_frame_size;
1922 min_rx_space = ALIGN(min_rx_space, 1024);
1923 min_rx_space >>= 10;
1925 /* If current Tx allocation is less than the min Tx FIFO size,
1926 * and the min Tx FIFO size is less than the current Rx FIFO
1927 * allocation, take space away from current Rx allocation
1929 if (tx_space < min_tx_space &&
1930 ((min_tx_space - tx_space) < pba)) {
1931 pba = pba - (min_tx_space - tx_space);
1933 /* if short on Rx space, Rx wins and must trump Tx
1936 if (pba < min_rx_space)
1939 wr32(E1000_PBA, pba);
1942 /* flow control settings */
1943 /* The high water mark must be low enough to fit one full frame
1944 * (or the size used for early receive) above it in the Rx FIFO.
1945 * Set it to the lower of:
1946 * - 90% of the Rx FIFO size, or
1947 * - the full Rx FIFO size minus one full frame
1949 hwm = min(((pba << 10) * 9 / 10),
1950 ((pba << 10) - 2 * adapter->max_frame_size));
1952 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1953 fc->low_water = fc->high_water - 16;
1954 fc->pause_time = 0xFFFF;
1956 fc->current_mode = fc->requested_mode;
1958 /* disable receive for all VFs and wait one second */
1959 if (adapter->vfs_allocated_count) {
1962 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1963 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1965 /* ping all the active vfs to let them know we are going down */
1966 igb_ping_all_vfs(adapter);
1968 /* disable transmits and receives */
1969 wr32(E1000_VFRE, 0);
1970 wr32(E1000_VFTE, 0);
1973 /* Allow time for pending master requests to run */
1974 hw->mac.ops.reset_hw(hw);
1977 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1978 /* need to resetup here after media swap */
1979 adapter->ei.get_invariants(hw);
1980 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1982 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1983 if (igb_enable_mas(adapter))
1985 "Error enabling Media Auto Sense\n");
1987 if (hw->mac.ops.init_hw(hw))
1988 dev_err(&pdev->dev, "Hardware Error\n");
1990 /* Flow control settings reset on hardware reset, so guarantee flow
1991 * control is off when forcing speed.
1993 if (!hw->mac.autoneg)
1994 igb_force_mac_fc(hw);
1996 igb_init_dmac(adapter, pba);
1997 #ifdef CONFIG_IGB_HWMON
1998 /* Re-initialize the thermal sensor on i350 devices. */
1999 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2000 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2001 /* If present, re-initialize the external thermal sensor
2005 mac->ops.init_thermal_sensor_thresh(hw);
2009 /* Re-establish EEE setting */
2010 if (hw->phy.media_type == e1000_media_type_copper) {
2011 switch (mac->type) {
2015 igb_set_eee_i350(hw, true, true);
2018 igb_set_eee_i354(hw, true, true);
2024 if (!netif_running(adapter->netdev))
2025 igb_power_down_link(adapter);
2027 igb_update_mng_vlan(adapter);
2029 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2030 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2032 /* Re-enable PTP, where applicable. */
2033 igb_ptp_reset(adapter);
2035 igb_get_phy_info(hw);
2038 static netdev_features_t igb_fix_features(struct net_device *netdev,
2039 netdev_features_t features)
2041 /* Since there is no support for separate Rx/Tx vlan accel
2042 * enable/disable make sure Tx flag is always in same state as Rx.
2044 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2045 features |= NETIF_F_HW_VLAN_CTAG_TX;
2047 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2052 static int igb_set_features(struct net_device *netdev,
2053 netdev_features_t features)
2055 netdev_features_t changed = netdev->features ^ features;
2056 struct igb_adapter *adapter = netdev_priv(netdev);
2058 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2059 igb_vlan_mode(netdev, features);
2061 if (!(changed & NETIF_F_RXALL))
2064 netdev->features = features;
2066 if (netif_running(netdev))
2067 igb_reinit_locked(adapter);
2074 static const struct net_device_ops igb_netdev_ops = {
2075 .ndo_open = igb_open,
2076 .ndo_stop = igb_close,
2077 .ndo_start_xmit = igb_xmit_frame,
2078 .ndo_get_stats64 = igb_get_stats64,
2079 .ndo_set_rx_mode = igb_set_rx_mode,
2080 .ndo_set_mac_address = igb_set_mac,
2081 .ndo_change_mtu = igb_change_mtu,
2082 .ndo_do_ioctl = igb_ioctl,
2083 .ndo_tx_timeout = igb_tx_timeout,
2084 .ndo_validate_addr = eth_validate_addr,
2085 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2086 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2087 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2088 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2089 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2090 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2091 .ndo_get_vf_config = igb_ndo_get_vf_config,
2092 #ifdef CONFIG_NET_POLL_CONTROLLER
2093 .ndo_poll_controller = igb_netpoll,
2095 .ndo_fix_features = igb_fix_features,
2096 .ndo_set_features = igb_set_features,
2100 * igb_set_fw_version - Configure version string for ethtool
2101 * @adapter: adapter struct
2103 void igb_set_fw_version(struct igb_adapter *adapter)
2105 struct e1000_hw *hw = &adapter->hw;
2106 struct e1000_fw_version fw;
2108 igb_get_fw_version(hw, &fw);
2110 switch (hw->mac.type) {
2113 if (!(igb_get_flash_presence_i210(hw))) {
2114 snprintf(adapter->fw_version,
2115 sizeof(adapter->fw_version),
2117 fw.invm_major, fw.invm_minor,
2123 /* if option is rom valid, display its version too */
2125 snprintf(adapter->fw_version,
2126 sizeof(adapter->fw_version),
2127 "%d.%d, 0x%08x, %d.%d.%d",
2128 fw.eep_major, fw.eep_minor, fw.etrack_id,
2129 fw.or_major, fw.or_build, fw.or_patch);
2131 } else if (fw.etrack_id != 0X0000) {
2132 snprintf(adapter->fw_version,
2133 sizeof(adapter->fw_version),
2135 fw.eep_major, fw.eep_minor, fw.etrack_id);
2137 snprintf(adapter->fw_version,
2138 sizeof(adapter->fw_version),
2140 fw.eep_major, fw.eep_minor, fw.eep_build);
2147 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2149 * @adapter: adapter struct
2151 static void igb_init_mas(struct igb_adapter *adapter)
2153 struct e1000_hw *hw = &adapter->hw;
2156 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2157 switch (hw->bus.func) {
2159 if (eeprom_data & IGB_MAS_ENABLE_0) {
2160 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2161 netdev_info(adapter->netdev,
2162 "MAS: Enabling Media Autosense for port %d\n",
2167 if (eeprom_data & IGB_MAS_ENABLE_1) {
2168 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2169 netdev_info(adapter->netdev,
2170 "MAS: Enabling Media Autosense for port %d\n",
2175 if (eeprom_data & IGB_MAS_ENABLE_2) {
2176 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2177 netdev_info(adapter->netdev,
2178 "MAS: Enabling Media Autosense for port %d\n",
2183 if (eeprom_data & IGB_MAS_ENABLE_3) {
2184 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2185 netdev_info(adapter->netdev,
2186 "MAS: Enabling Media Autosense for port %d\n",
2191 /* Shouldn't get here */
2192 netdev_err(adapter->netdev,
2193 "MAS: Invalid port configuration, returning\n");
2199 * igb_init_i2c - Init I2C interface
2200 * @adapter: pointer to adapter structure
2202 static s32 igb_init_i2c(struct igb_adapter *adapter)
2206 /* I2C interface supported on i350 devices */
2207 if (adapter->hw.mac.type != e1000_i350)
2210 /* Initialize the i2c bus which is controlled by the registers.
2211 * This bus will use the i2c_algo_bit structue that implements
2212 * the protocol through toggling of the 4 bits in the register.
2214 adapter->i2c_adap.owner = THIS_MODULE;
2215 adapter->i2c_algo = igb_i2c_algo;
2216 adapter->i2c_algo.data = adapter;
2217 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2218 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2219 strlcpy(adapter->i2c_adap.name, "igb BB",
2220 sizeof(adapter->i2c_adap.name));
2221 status = i2c_bit_add_bus(&adapter->i2c_adap);
2226 * igb_probe - Device Initialization Routine
2227 * @pdev: PCI device information struct
2228 * @ent: entry in igb_pci_tbl
2230 * Returns 0 on success, negative on failure
2232 * igb_probe initializes an adapter identified by a pci_dev structure.
2233 * The OS initialization, configuring of the adapter private structure,
2234 * and a hardware reset occur.
2236 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2238 struct net_device *netdev;
2239 struct igb_adapter *adapter;
2240 struct e1000_hw *hw;
2241 u16 eeprom_data = 0;
2243 static int global_quad_port_a; /* global quad port a indication */
2244 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2245 int err, pci_using_dac;
2246 u8 part_str[E1000_PBANUM_LENGTH];
2248 /* Catch broken hardware that put the wrong VF device ID in
2249 * the PCIe SR-IOV capability.
2251 if (pdev->is_virtfn) {
2252 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2253 pci_name(pdev), pdev->vendor, pdev->device);
2257 err = pci_enable_device_mem(pdev);
2262 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2266 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2269 "No usable DMA configuration, aborting\n");
2274 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2280 pci_enable_pcie_error_reporting(pdev);
2282 pci_set_master(pdev);
2283 pci_save_state(pdev);
2286 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2289 goto err_alloc_etherdev;
2291 SET_NETDEV_DEV(netdev, &pdev->dev);
2293 pci_set_drvdata(pdev, netdev);
2294 adapter = netdev_priv(netdev);
2295 adapter->netdev = netdev;
2296 adapter->pdev = pdev;
2299 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2302 hw->hw_addr = pci_iomap(pdev, 0, 0);
2306 netdev->netdev_ops = &igb_netdev_ops;
2307 igb_set_ethtool_ops(netdev);
2308 netdev->watchdog_timeo = 5 * HZ;
2310 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2312 netdev->mem_start = pci_resource_start(pdev, 0);
2313 netdev->mem_end = pci_resource_end(pdev, 0);
2315 /* PCI config space info */
2316 hw->vendor_id = pdev->vendor;
2317 hw->device_id = pdev->device;
2318 hw->revision_id = pdev->revision;
2319 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2320 hw->subsystem_device_id = pdev->subsystem_device;
2322 /* Copy the default MAC, PHY and NVM function pointers */
2323 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2324 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2325 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2326 /* Initialize skew-specific constants */
2327 err = ei->get_invariants(hw);
2331 /* setup the private structure */
2332 err = igb_sw_init(adapter);
2336 igb_get_bus_info_pcie(hw);
2338 hw->phy.autoneg_wait_to_complete = false;
2340 /* Copper options */
2341 if (hw->phy.media_type == e1000_media_type_copper) {
2342 hw->phy.mdix = AUTO_ALL_MODES;
2343 hw->phy.disable_polarity_correction = false;
2344 hw->phy.ms_type = e1000_ms_hw_default;
2347 if (igb_check_reset_block(hw))
2348 dev_info(&pdev->dev,
2349 "PHY reset is blocked due to SOL/IDER session.\n");
2351 /* features is initialized to 0 in allocation, it might have bits
2352 * set by igb_sw_init so we should use an or instead of an
2355 netdev->features |= NETIF_F_SG |
2362 NETIF_F_HW_VLAN_CTAG_RX |
2363 NETIF_F_HW_VLAN_CTAG_TX;
2365 /* copy netdev features into list of user selectable features */
2366 netdev->hw_features |= netdev->features;
2367 netdev->hw_features |= NETIF_F_RXALL;
2369 /* set this bit last since it cannot be part of hw_features */
2370 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2372 netdev->vlan_features |= NETIF_F_TSO |
2378 netdev->priv_flags |= IFF_SUPP_NOFCS;
2380 if (pci_using_dac) {
2381 netdev->features |= NETIF_F_HIGHDMA;
2382 netdev->vlan_features |= NETIF_F_HIGHDMA;
2385 if (hw->mac.type >= e1000_82576) {
2386 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2387 netdev->features |= NETIF_F_SCTP_CSUM;
2390 netdev->priv_flags |= IFF_UNICAST_FLT;
2392 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2394 /* before reading the NVM, reset the controller to put the device in a
2395 * known good starting state
2397 hw->mac.ops.reset_hw(hw);
2399 /* make sure the NVM is good , i211/i210 parts can have special NVM
2400 * that doesn't contain a checksum
2402 switch (hw->mac.type) {
2405 if (igb_get_flash_presence_i210(hw)) {
2406 if (hw->nvm.ops.validate(hw) < 0) {
2408 "The NVM Checksum Is Not Valid\n");
2415 if (hw->nvm.ops.validate(hw) < 0) {
2416 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2423 /* copy the MAC address out of the NVM */
2424 if (hw->mac.ops.read_mac_addr(hw))
2425 dev_err(&pdev->dev, "NVM Read Error\n");
2427 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2429 if (!is_valid_ether_addr(netdev->dev_addr)) {
2430 dev_err(&pdev->dev, "Invalid MAC Address\n");
2435 /* get firmware version for ethtool -i */
2436 igb_set_fw_version(adapter);
2438 /* configure RXPBSIZE and TXPBSIZE */
2439 if (hw->mac.type == e1000_i210) {
2440 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2441 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2444 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2445 (unsigned long) adapter);
2446 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2447 (unsigned long) adapter);
2449 INIT_WORK(&adapter->reset_task, igb_reset_task);
2450 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2452 /* Initialize link properties that are user-changeable */
2453 adapter->fc_autoneg = true;
2454 hw->mac.autoneg = true;
2455 hw->phy.autoneg_advertised = 0x2f;
2457 hw->fc.requested_mode = e1000_fc_default;
2458 hw->fc.current_mode = e1000_fc_default;
2460 igb_validate_mdi_setting(hw);
2462 /* By default, support wake on port A */
2463 if (hw->bus.func == 0)
2464 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2466 /* Check the NVM for wake support on non-port A ports */
2467 if (hw->mac.type >= e1000_82580)
2468 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2469 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2471 else if (hw->bus.func == 1)
2472 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2474 if (eeprom_data & IGB_EEPROM_APME)
2475 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2477 /* now that we have the eeprom settings, apply the special cases where
2478 * the eeprom may be wrong or the board simply won't support wake on
2479 * lan on a particular port
2481 switch (pdev->device) {
2482 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2483 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2485 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2486 case E1000_DEV_ID_82576_FIBER:
2487 case E1000_DEV_ID_82576_SERDES:
2488 /* Wake events only supported on port A for dual fiber
2489 * regardless of eeprom setting
2491 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2492 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2494 case E1000_DEV_ID_82576_QUAD_COPPER:
2495 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2496 /* if quad port adapter, disable WoL on all but port A */
2497 if (global_quad_port_a != 0)
2498 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2500 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2501 /* Reset for multiple quad port adapters */
2502 if (++global_quad_port_a == 4)
2503 global_quad_port_a = 0;
2506 /* If the device can't wake, don't set software support */
2507 if (!device_can_wakeup(&adapter->pdev->dev))
2508 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2511 /* initialize the wol settings based on the eeprom settings */
2512 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2513 adapter->wol |= E1000_WUFC_MAG;
2515 /* Some vendors want WoL disabled by default, but still supported */
2516 if ((hw->mac.type == e1000_i350) &&
2517 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2518 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2522 device_set_wakeup_enable(&adapter->pdev->dev,
2523 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2525 /* reset the hardware with the new settings */
2528 /* Init the I2C interface */
2529 err = igb_init_i2c(adapter);
2531 dev_err(&pdev->dev, "failed to init i2c interface\n");
2535 /* let the f/w know that the h/w is now under the control of the
2538 igb_get_hw_control(adapter);
2540 strcpy(netdev->name, "eth%d");
2541 err = register_netdev(netdev);
2545 /* carrier off reporting is important to ethtool even BEFORE open */
2546 netif_carrier_off(netdev);
2548 #ifdef CONFIG_IGB_DCA
2549 if (dca_add_requester(&pdev->dev) == 0) {
2550 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2551 dev_info(&pdev->dev, "DCA enabled\n");
2552 igb_setup_dca(adapter);
2556 #ifdef CONFIG_IGB_HWMON
2557 /* Initialize the thermal sensor on i350 devices. */
2558 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2561 /* Read the NVM to determine if this i350 device supports an
2562 * external thermal sensor.
2564 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2565 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2566 adapter->ets = true;
2568 adapter->ets = false;
2569 if (igb_sysfs_init(adapter))
2571 "failed to allocate sysfs resources\n");
2573 adapter->ets = false;
2576 /* Check if Media Autosense is enabled */
2578 if (hw->dev_spec._82575.mas_capable)
2579 igb_init_mas(adapter);
2581 /* do hw tstamp init after resetting */
2582 igb_ptp_init(adapter);
2584 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2585 /* print bus type/speed/width info, not applicable to i354 */
2586 if (hw->mac.type != e1000_i354) {
2587 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2589 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2590 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2592 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2594 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2596 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2597 "Width x1" : "unknown"), netdev->dev_addr);
2600 if ((hw->mac.type >= e1000_i210 ||
2601 igb_get_flash_presence_i210(hw))) {
2602 ret_val = igb_read_part_string(hw, part_str,
2603 E1000_PBANUM_LENGTH);
2605 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2609 strcpy(part_str, "Unknown");
2610 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2611 dev_info(&pdev->dev,
2612 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2613 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2614 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2615 adapter->num_rx_queues, adapter->num_tx_queues);
2616 if (hw->phy.media_type == e1000_media_type_copper) {
2617 switch (hw->mac.type) {
2621 /* Enable EEE for internal copper PHY devices */
2622 err = igb_set_eee_i350(hw, true, true);
2624 (!hw->dev_spec._82575.eee_disable)) {
2625 adapter->eee_advert =
2626 MDIO_EEE_100TX | MDIO_EEE_1000T;
2627 adapter->flags |= IGB_FLAG_EEE;
2631 if ((rd32(E1000_CTRL_EXT) &
2632 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2633 err = igb_set_eee_i354(hw, true, true);
2635 (!hw->dev_spec._82575.eee_disable)) {
2636 adapter->eee_advert =
2637 MDIO_EEE_100TX | MDIO_EEE_1000T;
2638 adapter->flags |= IGB_FLAG_EEE;
2646 pm_runtime_put_noidle(&pdev->dev);
2650 igb_release_hw_control(adapter);
2651 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2653 if (!igb_check_reset_block(hw))
2656 if (hw->flash_address)
2657 iounmap(hw->flash_address);
2659 igb_clear_interrupt_scheme(adapter);
2660 pci_iounmap(pdev, hw->hw_addr);
2662 free_netdev(netdev);
2664 pci_release_selected_regions(pdev,
2665 pci_select_bars(pdev, IORESOURCE_MEM));
2668 pci_disable_device(pdev);
2672 #ifdef CONFIG_PCI_IOV
2673 static int igb_disable_sriov(struct pci_dev *pdev)
2675 struct net_device *netdev = pci_get_drvdata(pdev);
2676 struct igb_adapter *adapter = netdev_priv(netdev);
2677 struct e1000_hw *hw = &adapter->hw;
2679 /* reclaim resources allocated to VFs */
2680 if (adapter->vf_data) {
2681 /* disable iov and allow time for transactions to clear */
2682 if (pci_vfs_assigned(pdev)) {
2683 dev_warn(&pdev->dev,
2684 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2687 pci_disable_sriov(pdev);
2691 kfree(adapter->vf_data);
2692 adapter->vf_data = NULL;
2693 adapter->vfs_allocated_count = 0;
2694 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2697 dev_info(&pdev->dev, "IOV Disabled\n");
2699 /* Re-enable DMA Coalescing flag since IOV is turned off */
2700 adapter->flags |= IGB_FLAG_DMAC;
2706 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2708 struct net_device *netdev = pci_get_drvdata(pdev);
2709 struct igb_adapter *adapter = netdev_priv(netdev);
2710 int old_vfs = pci_num_vf(pdev);
2714 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2722 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2724 adapter->vfs_allocated_count = old_vfs;
2726 adapter->vfs_allocated_count = num_vfs;
2728 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2729 sizeof(struct vf_data_storage), GFP_KERNEL);
2731 /* if allocation failed then we do not support SR-IOV */
2732 if (!adapter->vf_data) {
2733 adapter->vfs_allocated_count = 0;
2735 "Unable to allocate memory for VF Data Storage\n");
2740 /* only call pci_enable_sriov() if no VFs are allocated already */
2742 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2746 dev_info(&pdev->dev, "%d VFs allocated\n",
2747 adapter->vfs_allocated_count);
2748 for (i = 0; i < adapter->vfs_allocated_count; i++)
2749 igb_vf_configure(adapter, i);
2751 /* DMA Coalescing is not supported in IOV mode. */
2752 adapter->flags &= ~IGB_FLAG_DMAC;
2756 kfree(adapter->vf_data);
2757 adapter->vf_data = NULL;
2758 adapter->vfs_allocated_count = 0;
2765 * igb_remove_i2c - Cleanup I2C interface
2766 * @adapter: pointer to adapter structure
2768 static void igb_remove_i2c(struct igb_adapter *adapter)
2770 /* free the adapter bus structure */
2771 i2c_del_adapter(&adapter->i2c_adap);
2775 * igb_remove - Device Removal Routine
2776 * @pdev: PCI device information struct
2778 * igb_remove is called by the PCI subsystem to alert the driver
2779 * that it should release a PCI device. The could be caused by a
2780 * Hot-Plug event, or because the driver is going to be removed from
2783 static void igb_remove(struct pci_dev *pdev)
2785 struct net_device *netdev = pci_get_drvdata(pdev);
2786 struct igb_adapter *adapter = netdev_priv(netdev);
2787 struct e1000_hw *hw = &adapter->hw;
2789 pm_runtime_get_noresume(&pdev->dev);
2790 #ifdef CONFIG_IGB_HWMON
2791 igb_sysfs_exit(adapter);
2793 igb_remove_i2c(adapter);
2794 igb_ptp_stop(adapter);
2795 /* The watchdog timer may be rescheduled, so explicitly
2796 * disable watchdog from being rescheduled.
2798 set_bit(__IGB_DOWN, &adapter->state);
2799 del_timer_sync(&adapter->watchdog_timer);
2800 del_timer_sync(&adapter->phy_info_timer);
2802 cancel_work_sync(&adapter->reset_task);
2803 cancel_work_sync(&adapter->watchdog_task);
2805 #ifdef CONFIG_IGB_DCA
2806 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2807 dev_info(&pdev->dev, "DCA disabled\n");
2808 dca_remove_requester(&pdev->dev);
2809 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2810 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2814 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2815 * would have already happened in close and is redundant.
2817 igb_release_hw_control(adapter);
2819 unregister_netdev(netdev);
2821 igb_clear_interrupt_scheme(adapter);
2823 #ifdef CONFIG_PCI_IOV
2824 igb_disable_sriov(pdev);
2827 pci_iounmap(pdev, hw->hw_addr);
2828 if (hw->flash_address)
2829 iounmap(hw->flash_address);
2830 pci_release_selected_regions(pdev,
2831 pci_select_bars(pdev, IORESOURCE_MEM));
2833 kfree(adapter->shadow_vfta);
2834 free_netdev(netdev);
2836 pci_disable_pcie_error_reporting(pdev);
2838 pci_disable_device(pdev);
2842 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2843 * @adapter: board private structure to initialize
2845 * This function initializes the vf specific data storage and then attempts to
2846 * allocate the VFs. The reason for ordering it this way is because it is much
2847 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2848 * the memory for the VFs.
2850 static void igb_probe_vfs(struct igb_adapter *adapter)
2852 #ifdef CONFIG_PCI_IOV
2853 struct pci_dev *pdev = adapter->pdev;
2854 struct e1000_hw *hw = &adapter->hw;
2856 /* Virtualization features not supported on i210 family. */
2857 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2860 pci_sriov_set_totalvfs(pdev, 7);
2861 igb_pci_enable_sriov(pdev, max_vfs);
2863 #endif /* CONFIG_PCI_IOV */
2866 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2868 struct e1000_hw *hw = &adapter->hw;
2871 /* Determine the maximum number of RSS queues supported. */
2872 switch (hw->mac.type) {
2874 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2878 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2881 /* I350 cannot do RSS and SR-IOV at the same time */
2882 if (!!adapter->vfs_allocated_count) {
2888 if (!!adapter->vfs_allocated_count) {
2896 max_rss_queues = IGB_MAX_RX_QUEUES;
2900 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2902 /* Determine if we need to pair queues. */
2903 switch (hw->mac.type) {
2906 /* Device supports enough interrupts without queue pairing. */
2909 /* If VFs are going to be allocated with RSS queues then we
2910 * should pair the queues in order to conserve interrupts due
2911 * to limited supply.
2913 if ((adapter->rss_queues > 1) &&
2914 (adapter->vfs_allocated_count > 6))
2915 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2922 /* If rss_queues > half of max_rss_queues, pair the queues in
2923 * order to conserve interrupts due to limited supply.
2925 if (adapter->rss_queues > (max_rss_queues / 2))
2926 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2932 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2933 * @adapter: board private structure to initialize
2935 * igb_sw_init initializes the Adapter private data structure.
2936 * Fields are initialized based on PCI device information and
2937 * OS network device settings (MTU size).
2939 static int igb_sw_init(struct igb_adapter *adapter)
2941 struct e1000_hw *hw = &adapter->hw;
2942 struct net_device *netdev = adapter->netdev;
2943 struct pci_dev *pdev = adapter->pdev;
2945 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2947 /* set default ring sizes */
2948 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2949 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2951 /* set default ITR values */
2952 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2953 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2955 /* set default work limits */
2956 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2958 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2960 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2962 spin_lock_init(&adapter->stats64_lock);
2963 #ifdef CONFIG_PCI_IOV
2964 switch (hw->mac.type) {
2968 dev_warn(&pdev->dev,
2969 "Maximum of 7 VFs per PF, using max\n");
2970 max_vfs = adapter->vfs_allocated_count = 7;
2972 adapter->vfs_allocated_count = max_vfs;
2973 if (adapter->vfs_allocated_count)
2974 dev_warn(&pdev->dev,
2975 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2980 #endif /* CONFIG_PCI_IOV */
2982 igb_init_queue_configuration(adapter);
2984 /* Setup and initialize a copy of the hw vlan table array */
2985 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2988 /* This call may decrease the number of queues */
2989 if (igb_init_interrupt_scheme(adapter, true)) {
2990 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2994 igb_probe_vfs(adapter);
2996 /* Explicitly disable IRQ since the NIC can be in any state. */
2997 igb_irq_disable(adapter);
2999 if (hw->mac.type >= e1000_i350)
3000 adapter->flags &= ~IGB_FLAG_DMAC;
3002 set_bit(__IGB_DOWN, &adapter->state);
3007 * igb_open - Called when a network interface is made active
3008 * @netdev: network interface device structure
3010 * Returns 0 on success, negative value on failure
3012 * The open entry point is called when a network interface is made
3013 * active by the system (IFF_UP). At this point all resources needed
3014 * for transmit and receive operations are allocated, the interrupt
3015 * handler is registered with the OS, the watchdog timer is started,
3016 * and the stack is notified that the interface is ready.
3018 static int __igb_open(struct net_device *netdev, bool resuming)
3020 struct igb_adapter *adapter = netdev_priv(netdev);
3021 struct e1000_hw *hw = &adapter->hw;
3022 struct pci_dev *pdev = adapter->pdev;
3026 /* disallow open during test */
3027 if (test_bit(__IGB_TESTING, &adapter->state)) {
3033 pm_runtime_get_sync(&pdev->dev);
3035 netif_carrier_off(netdev);
3037 /* allocate transmit descriptors */
3038 err = igb_setup_all_tx_resources(adapter);
3042 /* allocate receive descriptors */
3043 err = igb_setup_all_rx_resources(adapter);
3047 igb_power_up_link(adapter);
3049 /* before we allocate an interrupt, we must be ready to handle it.
3050 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3051 * as soon as we call pci_request_irq, so we have to setup our
3052 * clean_rx handler before we do so.
3054 igb_configure(adapter);
3056 err = igb_request_irq(adapter);
3060 /* Notify the stack of the actual queue counts. */
3061 err = netif_set_real_num_tx_queues(adapter->netdev,
3062 adapter->num_tx_queues);
3064 goto err_set_queues;
3066 err = netif_set_real_num_rx_queues(adapter->netdev,
3067 adapter->num_rx_queues);
3069 goto err_set_queues;
3071 /* From here on the code is the same as igb_up() */
3072 clear_bit(__IGB_DOWN, &adapter->state);
3074 for (i = 0; i < adapter->num_q_vectors; i++)
3075 napi_enable(&(adapter->q_vector[i]->napi));
3077 /* Clear any pending interrupts. */
3080 igb_irq_enable(adapter);
3082 /* notify VFs that reset has been completed */
3083 if (adapter->vfs_allocated_count) {
3084 u32 reg_data = rd32(E1000_CTRL_EXT);
3086 reg_data |= E1000_CTRL_EXT_PFRSTD;
3087 wr32(E1000_CTRL_EXT, reg_data);
3090 netif_tx_start_all_queues(netdev);
3093 pm_runtime_put(&pdev->dev);
3095 /* start the watchdog. */
3096 hw->mac.get_link_status = 1;
3097 schedule_work(&adapter->watchdog_task);
3102 igb_free_irq(adapter);
3104 igb_release_hw_control(adapter);
3105 igb_power_down_link(adapter);
3106 igb_free_all_rx_resources(adapter);
3108 igb_free_all_tx_resources(adapter);
3112 pm_runtime_put(&pdev->dev);
3117 static int igb_open(struct net_device *netdev)
3119 return __igb_open(netdev, false);
3123 * igb_close - Disables a network interface
3124 * @netdev: network interface device structure
3126 * Returns 0, this is not allowed to fail
3128 * The close entry point is called when an interface is de-activated
3129 * by the OS. The hardware is still under the driver's control, but
3130 * needs to be disabled. A global MAC reset is issued to stop the
3131 * hardware, and all transmit and receive resources are freed.
3133 static int __igb_close(struct net_device *netdev, bool suspending)
3135 struct igb_adapter *adapter = netdev_priv(netdev);
3136 struct pci_dev *pdev = adapter->pdev;
3138 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3141 pm_runtime_get_sync(&pdev->dev);
3144 igb_free_irq(adapter);
3146 igb_free_all_tx_resources(adapter);
3147 igb_free_all_rx_resources(adapter);
3150 pm_runtime_put_sync(&pdev->dev);
3154 static int igb_close(struct net_device *netdev)
3156 return __igb_close(netdev, false);
3160 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3161 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3163 * Return 0 on success, negative on failure
3165 int igb_setup_tx_resources(struct igb_ring *tx_ring)
3167 struct device *dev = tx_ring->dev;
3170 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3172 tx_ring->tx_buffer_info = vzalloc(size);
3173 if (!tx_ring->tx_buffer_info)
3176 /* round up to nearest 4K */
3177 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3178 tx_ring->size = ALIGN(tx_ring->size, 4096);
3180 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3181 &tx_ring->dma, GFP_KERNEL);
3185 tx_ring->next_to_use = 0;
3186 tx_ring->next_to_clean = 0;
3191 vfree(tx_ring->tx_buffer_info);
3192 tx_ring->tx_buffer_info = NULL;
3193 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3198 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3199 * (Descriptors) for all queues
3200 * @adapter: board private structure
3202 * Return 0 on success, negative on failure
3204 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3206 struct pci_dev *pdev = adapter->pdev;
3209 for (i = 0; i < adapter->num_tx_queues; i++) {
3210 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3213 "Allocation for Tx Queue %u failed\n", i);
3214 for (i--; i >= 0; i--)
3215 igb_free_tx_resources(adapter->tx_ring[i]);
3224 * igb_setup_tctl - configure the transmit control registers
3225 * @adapter: Board private structure
3227 void igb_setup_tctl(struct igb_adapter *adapter)
3229 struct e1000_hw *hw = &adapter->hw;
3232 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3233 wr32(E1000_TXDCTL(0), 0);
3235 /* Program the Transmit Control Register */
3236 tctl = rd32(E1000_TCTL);
3237 tctl &= ~E1000_TCTL_CT;
3238 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3239 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3241 igb_config_collision_dist(hw);
3243 /* Enable transmits */
3244 tctl |= E1000_TCTL_EN;
3246 wr32(E1000_TCTL, tctl);
3250 * igb_configure_tx_ring - Configure transmit ring after Reset
3251 * @adapter: board private structure
3252 * @ring: tx ring to configure
3254 * Configure a transmit ring after a reset.
3256 void igb_configure_tx_ring(struct igb_adapter *adapter,
3257 struct igb_ring *ring)
3259 struct e1000_hw *hw = &adapter->hw;
3261 u64 tdba = ring->dma;
3262 int reg_idx = ring->reg_idx;
3264 /* disable the queue */
3265 wr32(E1000_TXDCTL(reg_idx), 0);
3269 wr32(E1000_TDLEN(reg_idx),
3270 ring->count * sizeof(union e1000_adv_tx_desc));
3271 wr32(E1000_TDBAL(reg_idx),
3272 tdba & 0x00000000ffffffffULL);
3273 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3275 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3276 wr32(E1000_TDH(reg_idx), 0);
3277 writel(0, ring->tail);
3279 txdctl |= IGB_TX_PTHRESH;
3280 txdctl |= IGB_TX_HTHRESH << 8;
3281 txdctl |= IGB_TX_WTHRESH << 16;
3283 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3284 wr32(E1000_TXDCTL(reg_idx), txdctl);
3288 * igb_configure_tx - Configure transmit Unit after Reset
3289 * @adapter: board private structure
3291 * Configure the Tx unit of the MAC after a reset.
3293 static void igb_configure_tx(struct igb_adapter *adapter)
3297 for (i = 0; i < adapter->num_tx_queues; i++)
3298 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3302 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3303 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3305 * Returns 0 on success, negative on failure
3307 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3309 struct device *dev = rx_ring->dev;
3312 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3314 rx_ring->rx_buffer_info = vzalloc(size);
3315 if (!rx_ring->rx_buffer_info)
3318 /* Round up to nearest 4K */
3319 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3320 rx_ring->size = ALIGN(rx_ring->size, 4096);
3322 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3323 &rx_ring->dma, GFP_KERNEL);
3327 rx_ring->next_to_alloc = 0;
3328 rx_ring->next_to_clean = 0;
3329 rx_ring->next_to_use = 0;
3334 vfree(rx_ring->rx_buffer_info);
3335 rx_ring->rx_buffer_info = NULL;
3336 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3341 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3342 * (Descriptors) for all queues
3343 * @adapter: board private structure
3345 * Return 0 on success, negative on failure
3347 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3349 struct pci_dev *pdev = adapter->pdev;
3352 for (i = 0; i < adapter->num_rx_queues; i++) {
3353 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3356 "Allocation for Rx Queue %u failed\n", i);
3357 for (i--; i >= 0; i--)
3358 igb_free_rx_resources(adapter->rx_ring[i]);
3367 * igb_setup_mrqc - configure the multiple receive queue control registers
3368 * @adapter: Board private structure
3370 static void igb_setup_mrqc(struct igb_adapter *adapter)
3372 struct e1000_hw *hw = &adapter->hw;
3374 u32 j, num_rx_queues;
3377 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3378 for (j = 0; j < 10; j++)
3379 wr32(E1000_RSSRK(j), rss_key[j]);
3381 num_rx_queues = adapter->rss_queues;
3383 switch (hw->mac.type) {
3385 /* 82576 supports 2 RSS queues for SR-IOV */
3386 if (adapter->vfs_allocated_count)
3393 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3394 for (j = 0; j < IGB_RETA_SIZE; j++)
3395 adapter->rss_indir_tbl[j] =
3396 (j * num_rx_queues) / IGB_RETA_SIZE;
3397 adapter->rss_indir_tbl_init = num_rx_queues;
3399 igb_write_rss_indir_tbl(adapter);
3401 /* Disable raw packet checksumming so that RSS hash is placed in
3402 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3403 * offloads as they are enabled by default
3405 rxcsum = rd32(E1000_RXCSUM);
3406 rxcsum |= E1000_RXCSUM_PCSD;
3408 if (adapter->hw.mac.type >= e1000_82576)
3409 /* Enable Receive Checksum Offload for SCTP */
3410 rxcsum |= E1000_RXCSUM_CRCOFL;
3412 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3413 wr32(E1000_RXCSUM, rxcsum);
3415 /* Generate RSS hash based on packet types, TCP/UDP
3416 * port numbers and/or IPv4/v6 src and dst addresses
3418 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3419 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3420 E1000_MRQC_RSS_FIELD_IPV6 |
3421 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3422 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3424 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3425 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3426 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3427 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3429 /* If VMDq is enabled then we set the appropriate mode for that, else
3430 * we default to RSS so that an RSS hash is calculated per packet even
3431 * if we are only using one queue
3433 if (adapter->vfs_allocated_count) {
3434 if (hw->mac.type > e1000_82575) {
3435 /* Set the default pool for the PF's first queue */
3436 u32 vtctl = rd32(E1000_VT_CTL);
3438 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3439 E1000_VT_CTL_DISABLE_DEF_POOL);
3440 vtctl |= adapter->vfs_allocated_count <<
3441 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3442 wr32(E1000_VT_CTL, vtctl);
3444 if (adapter->rss_queues > 1)
3445 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3447 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3449 if (hw->mac.type != e1000_i211)
3450 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3452 igb_vmm_control(adapter);
3454 wr32(E1000_MRQC, mrqc);
3458 * igb_setup_rctl - configure the receive control registers
3459 * @adapter: Board private structure
3461 void igb_setup_rctl(struct igb_adapter *adapter)
3463 struct e1000_hw *hw = &adapter->hw;
3466 rctl = rd32(E1000_RCTL);
3468 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3469 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3471 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3472 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3474 /* enable stripping of CRC. It's unlikely this will break BMC
3475 * redirection as it did with e1000. Newer features require
3476 * that the HW strips the CRC.
3478 rctl |= E1000_RCTL_SECRC;
3480 /* disable store bad packets and clear size bits. */
3481 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3483 /* enable LPE to prevent packets larger than max_frame_size */
3484 rctl |= E1000_RCTL_LPE;
3486 /* disable queue 0 to prevent tail write w/o re-config */
3487 wr32(E1000_RXDCTL(0), 0);
3489 /* Attention!!! For SR-IOV PF driver operations you must enable
3490 * queue drop for all VF and PF queues to prevent head of line blocking
3491 * if an un-trusted VF does not provide descriptors to hardware.
3493 if (adapter->vfs_allocated_count) {
3494 /* set all queue drop enable bits */
3495 wr32(E1000_QDE, ALL_QUEUES);
3498 /* This is useful for sniffing bad packets. */
3499 if (adapter->netdev->features & NETIF_F_RXALL) {
3500 /* UPE and MPE will be handled by normal PROMISC logic
3501 * in e1000e_set_rx_mode
3503 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3504 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3505 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3507 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3508 E1000_RCTL_DPF | /* Allow filtered pause */
3509 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3510 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3511 * and that breaks VLANs.
3515 wr32(E1000_RCTL, rctl);
3518 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3521 struct e1000_hw *hw = &adapter->hw;
3524 /* if it isn't the PF check to see if VFs are enabled and
3525 * increase the size to support vlan tags
3527 if (vfn < adapter->vfs_allocated_count &&
3528 adapter->vf_data[vfn].vlans_enabled)
3529 size += VLAN_TAG_SIZE;
3531 vmolr = rd32(E1000_VMOLR(vfn));
3532 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3533 vmolr |= size | E1000_VMOLR_LPE;
3534 wr32(E1000_VMOLR(vfn), vmolr);
3540 * igb_rlpml_set - set maximum receive packet size
3541 * @adapter: board private structure
3543 * Configure maximum receivable packet size.
3545 static void igb_rlpml_set(struct igb_adapter *adapter)
3547 u32 max_frame_size = adapter->max_frame_size;
3548 struct e1000_hw *hw = &adapter->hw;
3549 u16 pf_id = adapter->vfs_allocated_count;
3552 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3553 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3554 * to our max jumbo frame size, in case we need to enable
3555 * jumbo frames on one of the rings later.
3556 * This will not pass over-length frames into the default
3557 * queue because it's gated by the VMOLR.RLPML.
3559 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3562 wr32(E1000_RLPML, max_frame_size);
3565 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3568 struct e1000_hw *hw = &adapter->hw;
3571 /* This register exists only on 82576 and newer so if we are older then
3572 * we should exit and do nothing
3574 if (hw->mac.type < e1000_82576)
3577 vmolr = rd32(E1000_VMOLR(vfn));
3578 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3579 if (hw->mac.type == e1000_i350) {
3582 dvmolr = rd32(E1000_DVMOLR(vfn));
3583 dvmolr |= E1000_DVMOLR_STRVLAN;
3584 wr32(E1000_DVMOLR(vfn), dvmolr);
3587 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3589 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3591 /* clear all bits that might not be set */
3592 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3594 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3595 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3596 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3599 if (vfn <= adapter->vfs_allocated_count)
3600 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3602 wr32(E1000_VMOLR(vfn), vmolr);
3606 * igb_configure_rx_ring - Configure a receive ring after Reset
3607 * @adapter: board private structure
3608 * @ring: receive ring to be configured
3610 * Configure the Rx unit of the MAC after a reset.
3612 void igb_configure_rx_ring(struct igb_adapter *adapter,
3613 struct igb_ring *ring)
3615 struct e1000_hw *hw = &adapter->hw;
3616 u64 rdba = ring->dma;
3617 int reg_idx = ring->reg_idx;
3618 u32 srrctl = 0, rxdctl = 0;
3620 /* disable the queue */
3621 wr32(E1000_RXDCTL(reg_idx), 0);
3623 /* Set DMA base address registers */
3624 wr32(E1000_RDBAL(reg_idx),
3625 rdba & 0x00000000ffffffffULL);
3626 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3627 wr32(E1000_RDLEN(reg_idx),
3628 ring->count * sizeof(union e1000_adv_rx_desc));
3630 /* initialize head and tail */
3631 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3632 wr32(E1000_RDH(reg_idx), 0);
3633 writel(0, ring->tail);
3635 /* set descriptor configuration */
3636 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3637 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3638 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3639 if (hw->mac.type >= e1000_82580)
3640 srrctl |= E1000_SRRCTL_TIMESTAMP;
3641 /* Only set Drop Enable if we are supporting multiple queues */
3642 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3643 srrctl |= E1000_SRRCTL_DROP_EN;
3645 wr32(E1000_SRRCTL(reg_idx), srrctl);
3647 /* set filtering for VMDQ pools */
3648 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3650 rxdctl |= IGB_RX_PTHRESH;
3651 rxdctl |= IGB_RX_HTHRESH << 8;
3652 rxdctl |= IGB_RX_WTHRESH << 16;
3654 /* enable receive descriptor fetching */
3655 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3656 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3660 * igb_configure_rx - Configure receive Unit after Reset
3661 * @adapter: board private structure
3663 * Configure the Rx unit of the MAC after a reset.
3665 static void igb_configure_rx(struct igb_adapter *adapter)
3669 /* set UTA to appropriate mode */
3670 igb_set_uta(adapter);
3672 /* set the correct pool for the PF default MAC address in entry 0 */
3673 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3674 adapter->vfs_allocated_count);
3676 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3677 * the Base and Length of the Rx Descriptor Ring
3679 for (i = 0; i < adapter->num_rx_queues; i++)
3680 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3684 * igb_free_tx_resources - Free Tx Resources per Queue
3685 * @tx_ring: Tx descriptor ring for a specific queue
3687 * Free all transmit software resources
3689 void igb_free_tx_resources(struct igb_ring *tx_ring)
3691 igb_clean_tx_ring(tx_ring);
3693 vfree(tx_ring->tx_buffer_info);
3694 tx_ring->tx_buffer_info = NULL;
3696 /* if not set, then don't free */
3700 dma_free_coherent(tx_ring->dev, tx_ring->size,
3701 tx_ring->desc, tx_ring->dma);
3703 tx_ring->desc = NULL;
3707 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3708 * @adapter: board private structure
3710 * Free all transmit software resources
3712 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3716 for (i = 0; i < adapter->num_tx_queues; i++)
3717 igb_free_tx_resources(adapter->tx_ring[i]);
3720 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3721 struct igb_tx_buffer *tx_buffer)
3723 if (tx_buffer->skb) {
3724 dev_kfree_skb_any(tx_buffer->skb);
3725 if (dma_unmap_len(tx_buffer, len))
3726 dma_unmap_single(ring->dev,
3727 dma_unmap_addr(tx_buffer, dma),
3728 dma_unmap_len(tx_buffer, len),
3730 } else if (dma_unmap_len(tx_buffer, len)) {
3731 dma_unmap_page(ring->dev,
3732 dma_unmap_addr(tx_buffer, dma),
3733 dma_unmap_len(tx_buffer, len),
3736 tx_buffer->next_to_watch = NULL;
3737 tx_buffer->skb = NULL;
3738 dma_unmap_len_set(tx_buffer, len, 0);
3739 /* buffer_info must be completely set up in the transmit path */
3743 * igb_clean_tx_ring - Free Tx Buffers
3744 * @tx_ring: ring to be cleaned
3746 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3748 struct igb_tx_buffer *buffer_info;
3752 if (!tx_ring->tx_buffer_info)
3754 /* Free all the Tx ring sk_buffs */
3756 for (i = 0; i < tx_ring->count; i++) {
3757 buffer_info = &tx_ring->tx_buffer_info[i];
3758 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3761 netdev_tx_reset_queue(txring_txq(tx_ring));
3763 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3764 memset(tx_ring->tx_buffer_info, 0, size);
3766 /* Zero out the descriptor ring */
3767 memset(tx_ring->desc, 0, tx_ring->size);
3769 tx_ring->next_to_use = 0;
3770 tx_ring->next_to_clean = 0;
3774 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3775 * @adapter: board private structure
3777 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3781 for (i = 0; i < adapter->num_tx_queues; i++)
3782 igb_clean_tx_ring(adapter->tx_ring[i]);
3786 * igb_free_rx_resources - Free Rx Resources
3787 * @rx_ring: ring to clean the resources from
3789 * Free all receive software resources
3791 void igb_free_rx_resources(struct igb_ring *rx_ring)
3793 igb_clean_rx_ring(rx_ring);
3795 vfree(rx_ring->rx_buffer_info);
3796 rx_ring->rx_buffer_info = NULL;
3798 /* if not set, then don't free */
3802 dma_free_coherent(rx_ring->dev, rx_ring->size,
3803 rx_ring->desc, rx_ring->dma);
3805 rx_ring->desc = NULL;
3809 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3810 * @adapter: board private structure
3812 * Free all receive software resources
3814 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3818 for (i = 0; i < adapter->num_rx_queues; i++)
3819 igb_free_rx_resources(adapter->rx_ring[i]);
3823 * igb_clean_rx_ring - Free Rx Buffers per Queue
3824 * @rx_ring: ring to free buffers from
3826 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3832 dev_kfree_skb(rx_ring->skb);
3833 rx_ring->skb = NULL;
3835 if (!rx_ring->rx_buffer_info)
3838 /* Free all the Rx ring sk_buffs */
3839 for (i = 0; i < rx_ring->count; i++) {
3840 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3842 if (!buffer_info->page)
3845 dma_unmap_page(rx_ring->dev,
3849 __free_page(buffer_info->page);
3851 buffer_info->page = NULL;
3854 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3855 memset(rx_ring->rx_buffer_info, 0, size);
3857 /* Zero out the descriptor ring */
3858 memset(rx_ring->desc, 0, rx_ring->size);
3860 rx_ring->next_to_alloc = 0;
3861 rx_ring->next_to_clean = 0;
3862 rx_ring->next_to_use = 0;
3866 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3867 * @adapter: board private structure
3869 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3873 for (i = 0; i < adapter->num_rx_queues; i++)
3874 igb_clean_rx_ring(adapter->rx_ring[i]);
3878 * igb_set_mac - Change the Ethernet Address of the NIC
3879 * @netdev: network interface device structure
3880 * @p: pointer to an address structure
3882 * Returns 0 on success, negative on failure
3884 static int igb_set_mac(struct net_device *netdev, void *p)
3886 struct igb_adapter *adapter = netdev_priv(netdev);
3887 struct e1000_hw *hw = &adapter->hw;
3888 struct sockaddr *addr = p;
3890 if (!is_valid_ether_addr(addr->sa_data))
3891 return -EADDRNOTAVAIL;
3893 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3894 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3896 /* set the correct pool for the new PF MAC address in entry 0 */
3897 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3898 adapter->vfs_allocated_count);
3904 * igb_write_mc_addr_list - write multicast addresses to MTA
3905 * @netdev: network interface device structure
3907 * Writes multicast address list to the MTA hash table.
3908 * Returns: -ENOMEM on failure
3909 * 0 on no addresses written
3910 * X on writing X addresses to MTA
3912 static int igb_write_mc_addr_list(struct net_device *netdev)
3914 struct igb_adapter *adapter = netdev_priv(netdev);
3915 struct e1000_hw *hw = &adapter->hw;
3916 struct netdev_hw_addr *ha;
3920 if (netdev_mc_empty(netdev)) {
3921 /* nothing to program, so clear mc list */
3922 igb_update_mc_addr_list(hw, NULL, 0);
3923 igb_restore_vf_multicasts(adapter);
3927 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3931 /* The shared function expects a packed array of only addresses. */
3933 netdev_for_each_mc_addr(ha, netdev)
3934 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3936 igb_update_mc_addr_list(hw, mta_list, i);
3939 return netdev_mc_count(netdev);
3943 * igb_write_uc_addr_list - write unicast addresses to RAR table
3944 * @netdev: network interface device structure
3946 * Writes unicast address list to the RAR table.
3947 * Returns: -ENOMEM on failure/insufficient address space
3948 * 0 on no addresses written
3949 * X on writing X addresses to the RAR table
3951 static int igb_write_uc_addr_list(struct net_device *netdev)
3953 struct igb_adapter *adapter = netdev_priv(netdev);
3954 struct e1000_hw *hw = &adapter->hw;
3955 unsigned int vfn = adapter->vfs_allocated_count;
3956 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3959 /* return ENOMEM indicating insufficient memory for addresses */
3960 if (netdev_uc_count(netdev) > rar_entries)
3963 if (!netdev_uc_empty(netdev) && rar_entries) {
3964 struct netdev_hw_addr *ha;
3966 netdev_for_each_uc_addr(ha, netdev) {
3969 igb_rar_set_qsel(adapter, ha->addr,
3975 /* write the addresses in reverse order to avoid write combining */
3976 for (; rar_entries > 0 ; rar_entries--) {
3977 wr32(E1000_RAH(rar_entries), 0);
3978 wr32(E1000_RAL(rar_entries), 0);
3986 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3987 * @netdev: network interface device structure
3989 * The set_rx_mode entry point is called whenever the unicast or multicast
3990 * address lists or the network interface flags are updated. This routine is
3991 * responsible for configuring the hardware for proper unicast, multicast,
3992 * promiscuous mode, and all-multi behavior.
3994 static void igb_set_rx_mode(struct net_device *netdev)
3996 struct igb_adapter *adapter = netdev_priv(netdev);
3997 struct e1000_hw *hw = &adapter->hw;
3998 unsigned int vfn = adapter->vfs_allocated_count;
3999 u32 rctl, vmolr = 0;
4002 /* Check for Promiscuous and All Multicast modes */
4003 rctl = rd32(E1000_RCTL);
4005 /* clear the effected bits */
4006 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4008 if (netdev->flags & IFF_PROMISC) {
4009 /* retain VLAN HW filtering if in VT mode */
4010 if (adapter->vfs_allocated_count)
4011 rctl |= E1000_RCTL_VFE;
4012 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4013 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4015 if (netdev->flags & IFF_ALLMULTI) {
4016 rctl |= E1000_RCTL_MPE;
4017 vmolr |= E1000_VMOLR_MPME;
4019 /* Write addresses to the MTA, if the attempt fails
4020 * then we should just turn on promiscuous mode so
4021 * that we can at least receive multicast traffic
4023 count = igb_write_mc_addr_list(netdev);
4025 rctl |= E1000_RCTL_MPE;
4026 vmolr |= E1000_VMOLR_MPME;
4028 vmolr |= E1000_VMOLR_ROMPE;
4031 /* Write addresses to available RAR registers, if there is not
4032 * sufficient space to store all the addresses then enable
4033 * unicast promiscuous mode
4035 count = igb_write_uc_addr_list(netdev);
4037 rctl |= E1000_RCTL_UPE;
4038 vmolr |= E1000_VMOLR_ROPE;
4040 rctl |= E1000_RCTL_VFE;
4042 wr32(E1000_RCTL, rctl);
4044 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4045 * the VMOLR to enable the appropriate modes. Without this workaround
4046 * we will have issues with VLAN tag stripping not being done for frames
4047 * that are only arriving because we are the default pool
4049 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4052 vmolr |= rd32(E1000_VMOLR(vfn)) &
4053 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4054 wr32(E1000_VMOLR(vfn), vmolr);
4055 igb_restore_vf_multicasts(adapter);
4058 static void igb_check_wvbr(struct igb_adapter *adapter)
4060 struct e1000_hw *hw = &adapter->hw;
4063 switch (hw->mac.type) {
4066 wvbr = rd32(E1000_WVBR);
4074 adapter->wvbr |= wvbr;
4077 #define IGB_STAGGERED_QUEUE_OFFSET 8
4079 static void igb_spoof_check(struct igb_adapter *adapter)
4086 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4087 if (adapter->wvbr & (1 << j) ||
4088 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4089 dev_warn(&adapter->pdev->dev,
4090 "Spoof event(s) detected on VF %d\n", j);
4093 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4098 /* Need to wait a few seconds after link up to get diagnostic information from
4101 static void igb_update_phy_info(unsigned long data)
4103 struct igb_adapter *adapter = (struct igb_adapter *) data;
4104 igb_get_phy_info(&adapter->hw);
4108 * igb_has_link - check shared code for link and determine up/down
4109 * @adapter: pointer to driver private info
4111 bool igb_has_link(struct igb_adapter *adapter)
4113 struct e1000_hw *hw = &adapter->hw;
4114 bool link_active = false;
4116 /* get_link_status is set on LSC (link status) interrupt or
4117 * rx sequence error interrupt. get_link_status will stay
4118 * false until the e1000_check_for_link establishes link
4119 * for copper adapters ONLY
4121 switch (hw->phy.media_type) {
4122 case e1000_media_type_copper:
4123 if (!hw->mac.get_link_status)
4125 case e1000_media_type_internal_serdes:
4126 hw->mac.ops.check_for_link(hw);
4127 link_active = !hw->mac.get_link_status;
4130 case e1000_media_type_unknown:
4134 if (((hw->mac.type == e1000_i210) ||
4135 (hw->mac.type == e1000_i211)) &&
4136 (hw->phy.id == I210_I_PHY_ID)) {
4137 if (!netif_carrier_ok(adapter->netdev)) {
4138 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4139 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4140 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4141 adapter->link_check_timeout = jiffies;
4148 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4151 u32 ctrl_ext, thstat;
4153 /* check for thermal sensor event on i350 copper only */
4154 if (hw->mac.type == e1000_i350) {
4155 thstat = rd32(E1000_THSTAT);
4156 ctrl_ext = rd32(E1000_CTRL_EXT);
4158 if ((hw->phy.media_type == e1000_media_type_copper) &&
4159 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4160 ret = !!(thstat & event);
4167 * igb_check_lvmmc - check for malformed packets received
4168 * and indicated in LVMMC register
4169 * @adapter: pointer to adapter
4171 static void igb_check_lvmmc(struct igb_adapter *adapter)
4173 struct e1000_hw *hw = &adapter->hw;
4176 lvmmc = rd32(E1000_LVMMC);
4178 if (unlikely(net_ratelimit())) {
4179 netdev_warn(adapter->netdev,
4180 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4187 * igb_watchdog - Timer Call-back
4188 * @data: pointer to adapter cast into an unsigned long
4190 static void igb_watchdog(unsigned long data)
4192 struct igb_adapter *adapter = (struct igb_adapter *)data;
4193 /* Do the rest outside of interrupt context */
4194 schedule_work(&adapter->watchdog_task);
4197 static void igb_watchdog_task(struct work_struct *work)
4199 struct igb_adapter *adapter = container_of(work,
4202 struct e1000_hw *hw = &adapter->hw;
4203 struct e1000_phy_info *phy = &hw->phy;
4204 struct net_device *netdev = adapter->netdev;
4209 link = igb_has_link(adapter);
4211 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4212 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4213 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4218 /* Force link down if we have fiber to swap to */
4219 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4220 if (hw->phy.media_type == e1000_media_type_copper) {
4221 connsw = rd32(E1000_CONNSW);
4222 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4227 /* Perform a reset if the media type changed. */
4228 if (hw->dev_spec._82575.media_changed) {
4229 hw->dev_spec._82575.media_changed = false;
4230 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4233 /* Cancel scheduled suspend requests. */
4234 pm_runtime_resume(netdev->dev.parent);
4236 if (!netif_carrier_ok(netdev)) {
4239 hw->mac.ops.get_speed_and_duplex(hw,
4240 &adapter->link_speed,
4241 &adapter->link_duplex);
4243 ctrl = rd32(E1000_CTRL);
4244 /* Links status message must follow this format */
4246 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4248 adapter->link_speed,
4249 adapter->link_duplex == FULL_DUPLEX ?
4251 (ctrl & E1000_CTRL_TFCE) &&
4252 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4253 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4254 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
4256 /* disable EEE if enabled */
4257 if ((adapter->flags & IGB_FLAG_EEE) &&
4258 (adapter->link_duplex == HALF_DUPLEX)) {
4259 dev_info(&adapter->pdev->dev,
4260 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4261 adapter->hw.dev_spec._82575.eee_disable = true;
4262 adapter->flags &= ~IGB_FLAG_EEE;
4265 /* check if SmartSpeed worked */
4266 igb_check_downshift(hw);
4267 if (phy->speed_downgraded)
4268 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4270 /* check for thermal sensor event */
4271 if (igb_thermal_sensor_event(hw,
4272 E1000_THSTAT_LINK_THROTTLE))
4273 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4275 /* adjust timeout factor according to speed/duplex */
4276 adapter->tx_timeout_factor = 1;
4277 switch (adapter->link_speed) {
4279 adapter->tx_timeout_factor = 14;
4282 /* maybe add some timeout factor ? */
4286 netif_carrier_on(netdev);
4288 igb_ping_all_vfs(adapter);
4289 igb_check_vf_rate_limit(adapter);
4291 /* link state has changed, schedule phy info update */
4292 if (!test_bit(__IGB_DOWN, &adapter->state))
4293 mod_timer(&adapter->phy_info_timer,
4294 round_jiffies(jiffies + 2 * HZ));
4297 if (netif_carrier_ok(netdev)) {
4298 adapter->link_speed = 0;
4299 adapter->link_duplex = 0;
4301 /* check for thermal sensor event */
4302 if (igb_thermal_sensor_event(hw,
4303 E1000_THSTAT_PWR_DOWN)) {
4304 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4307 /* Links status message must follow this format */
4308 netdev_info(netdev, "igb: %s NIC Link is Down\n",
4310 netif_carrier_off(netdev);
4312 igb_ping_all_vfs(adapter);
4314 /* link state has changed, schedule phy info update */
4315 if (!test_bit(__IGB_DOWN, &adapter->state))
4316 mod_timer(&adapter->phy_info_timer,
4317 round_jiffies(jiffies + 2 * HZ));
4319 /* link is down, time to check for alternate media */
4320 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4321 igb_check_swap_media(adapter);
4322 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4323 schedule_work(&adapter->reset_task);
4324 /* return immediately */
4328 pm_schedule_suspend(netdev->dev.parent,
4331 /* also check for alternate media here */
4332 } else if (!netif_carrier_ok(netdev) &&
4333 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4334 igb_check_swap_media(adapter);
4335 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4336 schedule_work(&adapter->reset_task);
4337 /* return immediately */
4343 spin_lock(&adapter->stats64_lock);
4344 igb_update_stats(adapter, &adapter->stats64);
4345 spin_unlock(&adapter->stats64_lock);
4347 for (i = 0; i < adapter->num_tx_queues; i++) {
4348 struct igb_ring *tx_ring = adapter->tx_ring[i];
4349 if (!netif_carrier_ok(netdev)) {
4350 /* We've lost link, so the controller stops DMA,
4351 * but we've got queued Tx work that's never going
4352 * to get done, so reset controller to flush Tx.
4353 * (Do the reset outside of interrupt context).
4355 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4356 adapter->tx_timeout_count++;
4357 schedule_work(&adapter->reset_task);
4358 /* return immediately since reset is imminent */
4363 /* Force detection of hung controller every watchdog period */
4364 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4367 /* Cause software interrupt to ensure Rx ring is cleaned */
4368 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4371 for (i = 0; i < adapter->num_q_vectors; i++)
4372 eics |= adapter->q_vector[i]->eims_value;
4373 wr32(E1000_EICS, eics);
4375 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4378 igb_spoof_check(adapter);
4379 igb_ptp_rx_hang(adapter);
4381 /* Check LVMMC register on i350/i354 only */
4382 if ((adapter->hw.mac.type == e1000_i350) ||
4383 (adapter->hw.mac.type == e1000_i354))
4384 igb_check_lvmmc(adapter);
4386 /* Reset the timer */
4387 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4388 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4389 mod_timer(&adapter->watchdog_timer,
4390 round_jiffies(jiffies + HZ));
4392 mod_timer(&adapter->watchdog_timer,
4393 round_jiffies(jiffies + 2 * HZ));
4397 enum latency_range {
4401 latency_invalid = 255
4405 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4406 * @q_vector: pointer to q_vector
4408 * Stores a new ITR value based on strictly on packet size. This
4409 * algorithm is less sophisticated than that used in igb_update_itr,
4410 * due to the difficulty of synchronizing statistics across multiple
4411 * receive rings. The divisors and thresholds used by this function
4412 * were determined based on theoretical maximum wire speed and testing
4413 * data, in order to minimize response time while increasing bulk
4415 * This functionality is controlled by ethtool's coalescing settings.
4416 * NOTE: This function is called only when operating in a multiqueue
4417 * receive environment.
4419 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4421 int new_val = q_vector->itr_val;
4422 int avg_wire_size = 0;
4423 struct igb_adapter *adapter = q_vector->adapter;
4424 unsigned int packets;
4426 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4427 * ints/sec - ITR timer value of 120 ticks.
4429 if (adapter->link_speed != SPEED_1000) {
4430 new_val = IGB_4K_ITR;
4434 packets = q_vector->rx.total_packets;
4436 avg_wire_size = q_vector->rx.total_bytes / packets;
4438 packets = q_vector->tx.total_packets;
4440 avg_wire_size = max_t(u32, avg_wire_size,
4441 q_vector->tx.total_bytes / packets);
4443 /* if avg_wire_size isn't set no work was done */
4447 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4448 avg_wire_size += 24;
4450 /* Don't starve jumbo frames */
4451 avg_wire_size = min(avg_wire_size, 3000);
4453 /* Give a little boost to mid-size frames */
4454 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4455 new_val = avg_wire_size / 3;
4457 new_val = avg_wire_size / 2;
4459 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4460 if (new_val < IGB_20K_ITR &&
4461 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4462 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4463 new_val = IGB_20K_ITR;
4466 if (new_val != q_vector->itr_val) {
4467 q_vector->itr_val = new_val;
4468 q_vector->set_itr = 1;
4471 q_vector->rx.total_bytes = 0;
4472 q_vector->rx.total_packets = 0;
4473 q_vector->tx.total_bytes = 0;
4474 q_vector->tx.total_packets = 0;
4478 * igb_update_itr - update the dynamic ITR value based on statistics
4479 * @q_vector: pointer to q_vector
4480 * @ring_container: ring info to update the itr for
4482 * Stores a new ITR value based on packets and byte
4483 * counts during the last interrupt. The advantage of per interrupt
4484 * computation is faster updates and more accurate ITR for the current
4485 * traffic pattern. Constants in this function were computed
4486 * based on theoretical maximum wire speed and thresholds were set based
4487 * on testing data as well as attempting to minimize response time
4488 * while increasing bulk throughput.
4489 * This functionality is controlled by ethtool's coalescing settings.
4490 * NOTE: These calculations are only valid when operating in a single-
4491 * queue environment.
4493 static void igb_update_itr(struct igb_q_vector *q_vector,
4494 struct igb_ring_container *ring_container)
4496 unsigned int packets = ring_container->total_packets;
4497 unsigned int bytes = ring_container->total_bytes;
4498 u8 itrval = ring_container->itr;
4500 /* no packets, exit with status unchanged */
4505 case lowest_latency:
4506 /* handle TSO and jumbo frames */
4507 if (bytes/packets > 8000)
4508 itrval = bulk_latency;
4509 else if ((packets < 5) && (bytes > 512))
4510 itrval = low_latency;
4512 case low_latency: /* 50 usec aka 20000 ints/s */
4513 if (bytes > 10000) {
4514 /* this if handles the TSO accounting */
4515 if (bytes/packets > 8000)
4516 itrval = bulk_latency;
4517 else if ((packets < 10) || ((bytes/packets) > 1200))
4518 itrval = bulk_latency;
4519 else if ((packets > 35))
4520 itrval = lowest_latency;
4521 } else if (bytes/packets > 2000) {
4522 itrval = bulk_latency;
4523 } else if (packets <= 2 && bytes < 512) {
4524 itrval = lowest_latency;
4527 case bulk_latency: /* 250 usec aka 4000 ints/s */
4528 if (bytes > 25000) {
4530 itrval = low_latency;
4531 } else if (bytes < 1500) {
4532 itrval = low_latency;
4537 /* clear work counters since we have the values we need */
4538 ring_container->total_bytes = 0;
4539 ring_container->total_packets = 0;
4541 /* write updated itr to ring container */
4542 ring_container->itr = itrval;
4545 static void igb_set_itr(struct igb_q_vector *q_vector)
4547 struct igb_adapter *adapter = q_vector->adapter;
4548 u32 new_itr = q_vector->itr_val;
4551 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4552 if (adapter->link_speed != SPEED_1000) {
4554 new_itr = IGB_4K_ITR;
4558 igb_update_itr(q_vector, &q_vector->tx);
4559 igb_update_itr(q_vector, &q_vector->rx);
4561 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4563 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4564 if (current_itr == lowest_latency &&
4565 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4566 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4567 current_itr = low_latency;
4569 switch (current_itr) {
4570 /* counts and packets in update_itr are dependent on these numbers */
4571 case lowest_latency:
4572 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4575 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4578 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4585 if (new_itr != q_vector->itr_val) {
4586 /* this attempts to bias the interrupt rate towards Bulk
4587 * by adding intermediate steps when interrupt rate is
4590 new_itr = new_itr > q_vector->itr_val ?
4591 max((new_itr * q_vector->itr_val) /
4592 (new_itr + (q_vector->itr_val >> 2)),
4594 /* Don't write the value here; it resets the adapter's
4595 * internal timer, and causes us to delay far longer than
4596 * we should between interrupts. Instead, we write the ITR
4597 * value at the beginning of the next interrupt so the timing
4598 * ends up being correct.
4600 q_vector->itr_val = new_itr;
4601 q_vector->set_itr = 1;
4605 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4606 u32 type_tucmd, u32 mss_l4len_idx)
4608 struct e1000_adv_tx_context_desc *context_desc;
4609 u16 i = tx_ring->next_to_use;
4611 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4614 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4616 /* set bits to identify this as an advanced context descriptor */
4617 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4619 /* For 82575, context index must be unique per ring. */
4620 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4621 mss_l4len_idx |= tx_ring->reg_idx << 4;
4623 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4624 context_desc->seqnum_seed = 0;
4625 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4626 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4629 static int igb_tso(struct igb_ring *tx_ring,
4630 struct igb_tx_buffer *first,
4633 struct sk_buff *skb = first->skb;
4634 u32 vlan_macip_lens, type_tucmd;
4635 u32 mss_l4len_idx, l4len;
4638 if (skb->ip_summed != CHECKSUM_PARTIAL)
4641 if (!skb_is_gso(skb))
4644 err = skb_cow_head(skb, 0);
4648 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4649 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4651 if (first->protocol == htons(ETH_P_IP)) {
4652 struct iphdr *iph = ip_hdr(skb);
4655 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4659 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4660 first->tx_flags |= IGB_TX_FLAGS_TSO |
4663 } else if (skb_is_gso_v6(skb)) {
4664 ipv6_hdr(skb)->payload_len = 0;
4665 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4666 &ipv6_hdr(skb)->daddr,
4668 first->tx_flags |= IGB_TX_FLAGS_TSO |
4672 /* compute header lengths */
4673 l4len = tcp_hdrlen(skb);
4674 *hdr_len = skb_transport_offset(skb) + l4len;
4676 /* update gso size and bytecount with header size */
4677 first->gso_segs = skb_shinfo(skb)->gso_segs;
4678 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4681 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4682 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4684 /* VLAN MACLEN IPLEN */
4685 vlan_macip_lens = skb_network_header_len(skb);
4686 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4687 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4689 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4694 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4696 struct sk_buff *skb = first->skb;
4697 u32 vlan_macip_lens = 0;
4698 u32 mss_l4len_idx = 0;
4701 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4702 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4707 switch (first->protocol) {
4708 case htons(ETH_P_IP):
4709 vlan_macip_lens |= skb_network_header_len(skb);
4710 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4711 l4_hdr = ip_hdr(skb)->protocol;
4713 case htons(ETH_P_IPV6):
4714 vlan_macip_lens |= skb_network_header_len(skb);
4715 l4_hdr = ipv6_hdr(skb)->nexthdr;
4718 if (unlikely(net_ratelimit())) {
4719 dev_warn(tx_ring->dev,
4720 "partial checksum but proto=%x!\n",
4728 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4729 mss_l4len_idx = tcp_hdrlen(skb) <<
4730 E1000_ADVTXD_L4LEN_SHIFT;
4733 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4734 mss_l4len_idx = sizeof(struct sctphdr) <<
4735 E1000_ADVTXD_L4LEN_SHIFT;
4738 mss_l4len_idx = sizeof(struct udphdr) <<
4739 E1000_ADVTXD_L4LEN_SHIFT;
4742 if (unlikely(net_ratelimit())) {
4743 dev_warn(tx_ring->dev,
4744 "partial checksum but l4 proto=%x!\n",
4750 /* update TX checksum flag */
4751 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4754 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4755 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4757 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4760 #define IGB_SET_FLAG(_input, _flag, _result) \
4761 ((_flag <= _result) ? \
4762 ((u32)(_input & _flag) * (_result / _flag)) : \
4763 ((u32)(_input & _flag) / (_flag / _result)))
4765 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4767 /* set type for advanced descriptor with frame checksum insertion */
4768 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4769 E1000_ADVTXD_DCMD_DEXT |
4770 E1000_ADVTXD_DCMD_IFCS;
4772 /* set HW vlan bit if vlan is present */
4773 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4774 (E1000_ADVTXD_DCMD_VLE));
4776 /* set segmentation bits for TSO */
4777 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4778 (E1000_ADVTXD_DCMD_TSE));
4780 /* set timestamp bit if present */
4781 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4782 (E1000_ADVTXD_MAC_TSTAMP));
4784 /* insert frame checksum */
4785 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4790 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4791 union e1000_adv_tx_desc *tx_desc,
4792 u32 tx_flags, unsigned int paylen)
4794 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4796 /* 82575 requires a unique index per ring */
4797 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4798 olinfo_status |= tx_ring->reg_idx << 4;
4800 /* insert L4 checksum */
4801 olinfo_status |= IGB_SET_FLAG(tx_flags,
4803 (E1000_TXD_POPTS_TXSM << 8));
4805 /* insert IPv4 checksum */
4806 olinfo_status |= IGB_SET_FLAG(tx_flags,
4808 (E1000_TXD_POPTS_IXSM << 8));
4810 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4813 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4815 struct net_device *netdev = tx_ring->netdev;
4817 netif_stop_subqueue(netdev, tx_ring->queue_index);
4819 /* Herbert's original patch had:
4820 * smp_mb__after_netif_stop_queue();
4821 * but since that doesn't exist yet, just open code it.
4825 /* We need to check again in a case another CPU has just
4826 * made room available.
4828 if (igb_desc_unused(tx_ring) < size)
4832 netif_wake_subqueue(netdev, tx_ring->queue_index);
4834 u64_stats_update_begin(&tx_ring->tx_syncp2);
4835 tx_ring->tx_stats.restart_queue2++;
4836 u64_stats_update_end(&tx_ring->tx_syncp2);
4841 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4843 if (igb_desc_unused(tx_ring) >= size)
4845 return __igb_maybe_stop_tx(tx_ring, size);
4848 static void igb_tx_map(struct igb_ring *tx_ring,
4849 struct igb_tx_buffer *first,
4852 struct sk_buff *skb = first->skb;
4853 struct igb_tx_buffer *tx_buffer;
4854 union e1000_adv_tx_desc *tx_desc;
4855 struct skb_frag_struct *frag;
4857 unsigned int data_len, size;
4858 u32 tx_flags = first->tx_flags;
4859 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4860 u16 i = tx_ring->next_to_use;
4862 tx_desc = IGB_TX_DESC(tx_ring, i);
4864 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4866 size = skb_headlen(skb);
4867 data_len = skb->data_len;
4869 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4873 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4874 if (dma_mapping_error(tx_ring->dev, dma))
4877 /* record length, and DMA address */
4878 dma_unmap_len_set(tx_buffer, len, size);
4879 dma_unmap_addr_set(tx_buffer, dma, dma);
4881 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4883 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4884 tx_desc->read.cmd_type_len =
4885 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4889 if (i == tx_ring->count) {
4890 tx_desc = IGB_TX_DESC(tx_ring, 0);
4893 tx_desc->read.olinfo_status = 0;
4895 dma += IGB_MAX_DATA_PER_TXD;
4896 size -= IGB_MAX_DATA_PER_TXD;
4898 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4901 if (likely(!data_len))
4904 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4908 if (i == tx_ring->count) {
4909 tx_desc = IGB_TX_DESC(tx_ring, 0);
4912 tx_desc->read.olinfo_status = 0;
4914 size = skb_frag_size(frag);
4917 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4918 size, DMA_TO_DEVICE);
4920 tx_buffer = &tx_ring->tx_buffer_info[i];
4923 /* write last descriptor with RS and EOP bits */
4924 cmd_type |= size | IGB_TXD_DCMD;
4925 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4927 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4929 /* set the timestamp */
4930 first->time_stamp = jiffies;
4932 /* Force memory writes to complete before letting h/w know there
4933 * are new descriptors to fetch. (Only applicable for weak-ordered
4934 * memory model archs, such as IA-64).
4936 * We also need this memory barrier to make certain all of the
4937 * status bits have been updated before next_to_watch is written.
4941 /* set next_to_watch value indicating a packet is present */
4942 first->next_to_watch = tx_desc;
4945 if (i == tx_ring->count)
4948 tx_ring->next_to_use = i;
4950 /* Make sure there is space in the ring for the next send. */
4951 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4953 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
4954 writel(i, tx_ring->tail);
4956 /* we need this if more than one processor can write to our tail
4957 * at a time, it synchronizes IO on IA64/Altix systems
4964 dev_err(tx_ring->dev, "TX DMA map failed\n");
4966 /* clear dma mappings for failed tx_buffer_info map */
4968 tx_buffer = &tx_ring->tx_buffer_info[i];
4969 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4970 if (tx_buffer == first)
4977 tx_ring->next_to_use = i;
4980 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4981 struct igb_ring *tx_ring)
4983 struct igb_tx_buffer *first;
4986 u16 count = TXD_USE_COUNT(skb_headlen(skb));
4987 __be16 protocol = vlan_get_protocol(skb);
4990 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4991 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4992 * + 2 desc gap to keep tail from touching head,
4993 * + 1 desc for context descriptor,
4994 * otherwise try next time
4996 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4999 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5000 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5002 count += skb_shinfo(skb)->nr_frags;
5005 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5006 /* this is a hard error */
5007 return NETDEV_TX_BUSY;
5010 /* record the location of the first descriptor for this packet */
5011 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5013 first->bytecount = skb->len;
5014 first->gso_segs = 1;
5016 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5017 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5019 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5021 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5022 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5024 adapter->ptp_tx_skb = skb_get(skb);
5025 adapter->ptp_tx_start = jiffies;
5026 if (adapter->hw.mac.type == e1000_82576)
5027 schedule_work(&adapter->ptp_tx_work);
5031 skb_tx_timestamp(skb);
5033 if (vlan_tx_tag_present(skb)) {
5034 tx_flags |= IGB_TX_FLAGS_VLAN;
5035 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5038 /* record initial flags and protocol */
5039 first->tx_flags = tx_flags;
5040 first->protocol = protocol;
5042 tso = igb_tso(tx_ring, first, &hdr_len);
5046 igb_tx_csum(tx_ring, first);
5048 igb_tx_map(tx_ring, first, hdr_len);
5050 return NETDEV_TX_OK;
5053 igb_unmap_and_free_tx_resource(tx_ring, first);
5055 return NETDEV_TX_OK;
5058 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5059 struct sk_buff *skb)
5061 unsigned int r_idx = skb->queue_mapping;
5063 if (r_idx >= adapter->num_tx_queues)
5064 r_idx = r_idx % adapter->num_tx_queues;
5066 return adapter->tx_ring[r_idx];
5069 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5070 struct net_device *netdev)
5072 struct igb_adapter *adapter = netdev_priv(netdev);
5074 if (test_bit(__IGB_DOWN, &adapter->state)) {
5075 dev_kfree_skb_any(skb);
5076 return NETDEV_TX_OK;
5079 if (skb->len <= 0) {
5080 dev_kfree_skb_any(skb);
5081 return NETDEV_TX_OK;
5084 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5085 * in order to meet this minimum size requirement.
5087 if (unlikely(skb->len < 17)) {
5088 if (skb_pad(skb, 17 - skb->len))
5089 return NETDEV_TX_OK;
5091 skb_set_tail_pointer(skb, 17);
5094 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5098 * igb_tx_timeout - Respond to a Tx Hang
5099 * @netdev: network interface device structure
5101 static void igb_tx_timeout(struct net_device *netdev)
5103 struct igb_adapter *adapter = netdev_priv(netdev);
5104 struct e1000_hw *hw = &adapter->hw;
5106 /* Do the reset outside of interrupt context */
5107 adapter->tx_timeout_count++;
5109 if (hw->mac.type >= e1000_82580)
5110 hw->dev_spec._82575.global_device_reset = true;
5112 schedule_work(&adapter->reset_task);
5114 (adapter->eims_enable_mask & ~adapter->eims_other));
5117 static void igb_reset_task(struct work_struct *work)
5119 struct igb_adapter *adapter;
5120 adapter = container_of(work, struct igb_adapter, reset_task);
5123 netdev_err(adapter->netdev, "Reset adapter\n");
5124 igb_reinit_locked(adapter);
5128 * igb_get_stats64 - Get System Network Statistics
5129 * @netdev: network interface device structure
5130 * @stats: rtnl_link_stats64 pointer
5132 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5133 struct rtnl_link_stats64 *stats)
5135 struct igb_adapter *adapter = netdev_priv(netdev);
5137 spin_lock(&adapter->stats64_lock);
5138 igb_update_stats(adapter, &adapter->stats64);
5139 memcpy(stats, &adapter->stats64, sizeof(*stats));
5140 spin_unlock(&adapter->stats64_lock);
5146 * igb_change_mtu - Change the Maximum Transfer Unit
5147 * @netdev: network interface device structure
5148 * @new_mtu: new value for maximum frame size
5150 * Returns 0 on success, negative on failure
5152 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5154 struct igb_adapter *adapter = netdev_priv(netdev);
5155 struct pci_dev *pdev = adapter->pdev;
5156 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5158 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5159 dev_err(&pdev->dev, "Invalid MTU setting\n");
5163 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5164 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5165 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5169 /* adjust max frame to be at least the size of a standard frame */
5170 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5171 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5173 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5174 usleep_range(1000, 2000);
5176 /* igb_down has a dependency on max_frame_size */
5177 adapter->max_frame_size = max_frame;
5179 if (netif_running(netdev))
5182 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5183 netdev->mtu, new_mtu);
5184 netdev->mtu = new_mtu;
5186 if (netif_running(netdev))
5191 clear_bit(__IGB_RESETTING, &adapter->state);
5197 * igb_update_stats - Update the board statistics counters
5198 * @adapter: board private structure
5200 void igb_update_stats(struct igb_adapter *adapter,
5201 struct rtnl_link_stats64 *net_stats)
5203 struct e1000_hw *hw = &adapter->hw;
5204 struct pci_dev *pdev = adapter->pdev;
5209 u64 _bytes, _packets;
5211 /* Prevent stats update while adapter is being reset, or if the pci
5212 * connection is down.
5214 if (adapter->link_speed == 0)
5216 if (pci_channel_offline(pdev))
5223 for (i = 0; i < adapter->num_rx_queues; i++) {
5224 struct igb_ring *ring = adapter->rx_ring[i];
5225 u32 rqdpc = rd32(E1000_RQDPC(i));
5226 if (hw->mac.type >= e1000_i210)
5227 wr32(E1000_RQDPC(i), 0);
5230 ring->rx_stats.drops += rqdpc;
5231 net_stats->rx_fifo_errors += rqdpc;
5235 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5236 _bytes = ring->rx_stats.bytes;
5237 _packets = ring->rx_stats.packets;
5238 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5240 packets += _packets;
5243 net_stats->rx_bytes = bytes;
5244 net_stats->rx_packets = packets;
5248 for (i = 0; i < adapter->num_tx_queues; i++) {
5249 struct igb_ring *ring = adapter->tx_ring[i];
5251 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5252 _bytes = ring->tx_stats.bytes;
5253 _packets = ring->tx_stats.packets;
5254 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5256 packets += _packets;
5258 net_stats->tx_bytes = bytes;
5259 net_stats->tx_packets = packets;
5262 /* read stats registers */
5263 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5264 adapter->stats.gprc += rd32(E1000_GPRC);
5265 adapter->stats.gorc += rd32(E1000_GORCL);
5266 rd32(E1000_GORCH); /* clear GORCL */
5267 adapter->stats.bprc += rd32(E1000_BPRC);
5268 adapter->stats.mprc += rd32(E1000_MPRC);
5269 adapter->stats.roc += rd32(E1000_ROC);
5271 adapter->stats.prc64 += rd32(E1000_PRC64);
5272 adapter->stats.prc127 += rd32(E1000_PRC127);
5273 adapter->stats.prc255 += rd32(E1000_PRC255);
5274 adapter->stats.prc511 += rd32(E1000_PRC511);
5275 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5276 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5277 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5278 adapter->stats.sec += rd32(E1000_SEC);
5280 mpc = rd32(E1000_MPC);
5281 adapter->stats.mpc += mpc;
5282 net_stats->rx_fifo_errors += mpc;
5283 adapter->stats.scc += rd32(E1000_SCC);
5284 adapter->stats.ecol += rd32(E1000_ECOL);
5285 adapter->stats.mcc += rd32(E1000_MCC);
5286 adapter->stats.latecol += rd32(E1000_LATECOL);
5287 adapter->stats.dc += rd32(E1000_DC);
5288 adapter->stats.rlec += rd32(E1000_RLEC);
5289 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5290 adapter->stats.xontxc += rd32(E1000_XONTXC);
5291 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5292 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5293 adapter->stats.fcruc += rd32(E1000_FCRUC);
5294 adapter->stats.gptc += rd32(E1000_GPTC);
5295 adapter->stats.gotc += rd32(E1000_GOTCL);
5296 rd32(E1000_GOTCH); /* clear GOTCL */
5297 adapter->stats.rnbc += rd32(E1000_RNBC);
5298 adapter->stats.ruc += rd32(E1000_RUC);
5299 adapter->stats.rfc += rd32(E1000_RFC);
5300 adapter->stats.rjc += rd32(E1000_RJC);
5301 adapter->stats.tor += rd32(E1000_TORH);
5302 adapter->stats.tot += rd32(E1000_TOTH);
5303 adapter->stats.tpr += rd32(E1000_TPR);
5305 adapter->stats.ptc64 += rd32(E1000_PTC64);
5306 adapter->stats.ptc127 += rd32(E1000_PTC127);
5307 adapter->stats.ptc255 += rd32(E1000_PTC255);
5308 adapter->stats.ptc511 += rd32(E1000_PTC511);
5309 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5310 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5312 adapter->stats.mptc += rd32(E1000_MPTC);
5313 adapter->stats.bptc += rd32(E1000_BPTC);
5315 adapter->stats.tpt += rd32(E1000_TPT);
5316 adapter->stats.colc += rd32(E1000_COLC);
5318 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5319 /* read internal phy specific stats */
5320 reg = rd32(E1000_CTRL_EXT);
5321 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5322 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5324 /* this stat has invalid values on i210/i211 */
5325 if ((hw->mac.type != e1000_i210) &&
5326 (hw->mac.type != e1000_i211))
5327 adapter->stats.tncrs += rd32(E1000_TNCRS);
5330 adapter->stats.tsctc += rd32(E1000_TSCTC);
5331 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5333 adapter->stats.iac += rd32(E1000_IAC);
5334 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5335 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5336 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5337 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5338 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5339 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5340 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5341 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5343 /* Fill out the OS statistics structure */
5344 net_stats->multicast = adapter->stats.mprc;
5345 net_stats->collisions = adapter->stats.colc;
5349 /* RLEC on some newer hardware can be incorrect so build
5350 * our own version based on RUC and ROC
5352 net_stats->rx_errors = adapter->stats.rxerrc +
5353 adapter->stats.crcerrs + adapter->stats.algnerrc +
5354 adapter->stats.ruc + adapter->stats.roc +
5355 adapter->stats.cexterr;
5356 net_stats->rx_length_errors = adapter->stats.ruc +
5358 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5359 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5360 net_stats->rx_missed_errors = adapter->stats.mpc;
5363 net_stats->tx_errors = adapter->stats.ecol +
5364 adapter->stats.latecol;
5365 net_stats->tx_aborted_errors = adapter->stats.ecol;
5366 net_stats->tx_window_errors = adapter->stats.latecol;
5367 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5369 /* Tx Dropped needs to be maintained elsewhere */
5371 /* Management Stats */
5372 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5373 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5374 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5377 reg = rd32(E1000_MANC);
5378 if (reg & E1000_MANC_EN_BMC2OS) {
5379 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5380 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5381 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5382 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5386 static irqreturn_t igb_msix_other(int irq, void *data)
5388 struct igb_adapter *adapter = data;
5389 struct e1000_hw *hw = &adapter->hw;
5390 u32 icr = rd32(E1000_ICR);
5391 /* reading ICR causes bit 31 of EICR to be cleared */
5393 if (icr & E1000_ICR_DRSTA)
5394 schedule_work(&adapter->reset_task);
5396 if (icr & E1000_ICR_DOUTSYNC) {
5397 /* HW is reporting DMA is out of sync */
5398 adapter->stats.doosync++;
5399 /* The DMA Out of Sync is also indication of a spoof event
5400 * in IOV mode. Check the Wrong VM Behavior register to
5401 * see if it is really a spoof event.
5403 igb_check_wvbr(adapter);
5406 /* Check for a mailbox event */
5407 if (icr & E1000_ICR_VMMB)
5408 igb_msg_task(adapter);
5410 if (icr & E1000_ICR_LSC) {
5411 hw->mac.get_link_status = 1;
5412 /* guard against interrupt when we're going down */
5413 if (!test_bit(__IGB_DOWN, &adapter->state))
5414 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5417 if (icr & E1000_ICR_TS) {
5418 u32 tsicr = rd32(E1000_TSICR);
5420 if (tsicr & E1000_TSICR_TXTS) {
5421 /* acknowledge the interrupt */
5422 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5423 /* retrieve hardware timestamp */
5424 schedule_work(&adapter->ptp_tx_work);
5428 wr32(E1000_EIMS, adapter->eims_other);
5433 static void igb_write_itr(struct igb_q_vector *q_vector)
5435 struct igb_adapter *adapter = q_vector->adapter;
5436 u32 itr_val = q_vector->itr_val & 0x7FFC;
5438 if (!q_vector->set_itr)
5444 if (adapter->hw.mac.type == e1000_82575)
5445 itr_val |= itr_val << 16;
5447 itr_val |= E1000_EITR_CNT_IGNR;
5449 writel(itr_val, q_vector->itr_register);
5450 q_vector->set_itr = 0;
5453 static irqreturn_t igb_msix_ring(int irq, void *data)
5455 struct igb_q_vector *q_vector = data;
5457 /* Write the ITR value calculated from the previous interrupt. */
5458 igb_write_itr(q_vector);
5460 napi_schedule(&q_vector->napi);
5465 #ifdef CONFIG_IGB_DCA
5466 static void igb_update_tx_dca(struct igb_adapter *adapter,
5467 struct igb_ring *tx_ring,
5470 struct e1000_hw *hw = &adapter->hw;
5471 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5473 if (hw->mac.type != e1000_82575)
5474 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5476 /* We can enable relaxed ordering for reads, but not writes when
5477 * DCA is enabled. This is due to a known issue in some chipsets
5478 * which will cause the DCA tag to be cleared.
5480 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5481 E1000_DCA_TXCTRL_DATA_RRO_EN |
5482 E1000_DCA_TXCTRL_DESC_DCA_EN;
5484 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5487 static void igb_update_rx_dca(struct igb_adapter *adapter,
5488 struct igb_ring *rx_ring,
5491 struct e1000_hw *hw = &adapter->hw;
5492 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5494 if (hw->mac.type != e1000_82575)
5495 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5497 /* We can enable relaxed ordering for reads, but not writes when
5498 * DCA is enabled. This is due to a known issue in some chipsets
5499 * which will cause the DCA tag to be cleared.
5501 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5502 E1000_DCA_RXCTRL_DESC_DCA_EN;
5504 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5507 static void igb_update_dca(struct igb_q_vector *q_vector)
5509 struct igb_adapter *adapter = q_vector->adapter;
5510 int cpu = get_cpu();
5512 if (q_vector->cpu == cpu)
5515 if (q_vector->tx.ring)
5516 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5518 if (q_vector->rx.ring)
5519 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5521 q_vector->cpu = cpu;
5526 static void igb_setup_dca(struct igb_adapter *adapter)
5528 struct e1000_hw *hw = &adapter->hw;
5531 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5534 /* Always use CB2 mode, difference is masked in the CB driver. */
5535 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5537 for (i = 0; i < adapter->num_q_vectors; i++) {
5538 adapter->q_vector[i]->cpu = -1;
5539 igb_update_dca(adapter->q_vector[i]);
5543 static int __igb_notify_dca(struct device *dev, void *data)
5545 struct net_device *netdev = dev_get_drvdata(dev);
5546 struct igb_adapter *adapter = netdev_priv(netdev);
5547 struct pci_dev *pdev = adapter->pdev;
5548 struct e1000_hw *hw = &adapter->hw;
5549 unsigned long event = *(unsigned long *)data;
5552 case DCA_PROVIDER_ADD:
5553 /* if already enabled, don't do it again */
5554 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5556 if (dca_add_requester(dev) == 0) {
5557 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5558 dev_info(&pdev->dev, "DCA enabled\n");
5559 igb_setup_dca(adapter);
5562 /* Fall Through since DCA is disabled. */
5563 case DCA_PROVIDER_REMOVE:
5564 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5565 /* without this a class_device is left
5566 * hanging around in the sysfs model
5568 dca_remove_requester(dev);
5569 dev_info(&pdev->dev, "DCA disabled\n");
5570 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5571 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5579 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5584 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5587 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5589 #endif /* CONFIG_IGB_DCA */
5591 #ifdef CONFIG_PCI_IOV
5592 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5594 unsigned char mac_addr[ETH_ALEN];
5596 eth_zero_addr(mac_addr);
5597 igb_set_vf_mac(adapter, vf, mac_addr);
5599 /* By default spoof check is enabled for all VFs */
5600 adapter->vf_data[vf].spoofchk_enabled = true;
5606 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5608 struct e1000_hw *hw = &adapter->hw;
5612 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5613 ping = E1000_PF_CONTROL_MSG;
5614 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5615 ping |= E1000_VT_MSGTYPE_CTS;
5616 igb_write_mbx(hw, &ping, 1, i);
5620 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5622 struct e1000_hw *hw = &adapter->hw;
5623 u32 vmolr = rd32(E1000_VMOLR(vf));
5624 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5626 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5627 IGB_VF_FLAG_MULTI_PROMISC);
5628 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5630 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5631 vmolr |= E1000_VMOLR_MPME;
5632 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5633 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5635 /* if we have hashes and we are clearing a multicast promisc
5636 * flag we need to write the hashes to the MTA as this step
5637 * was previously skipped
5639 if (vf_data->num_vf_mc_hashes > 30) {
5640 vmolr |= E1000_VMOLR_MPME;
5641 } else if (vf_data->num_vf_mc_hashes) {
5644 vmolr |= E1000_VMOLR_ROMPE;
5645 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5646 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5650 wr32(E1000_VMOLR(vf), vmolr);
5652 /* there are flags left unprocessed, likely not supported */
5653 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5659 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5660 u32 *msgbuf, u32 vf)
5662 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5663 u16 *hash_list = (u16 *)&msgbuf[1];
5664 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5667 /* salt away the number of multicast addresses assigned
5668 * to this VF for later use to restore when the PF multi cast
5671 vf_data->num_vf_mc_hashes = n;
5673 /* only up to 30 hash values supported */
5677 /* store the hashes for later use */
5678 for (i = 0; i < n; i++)
5679 vf_data->vf_mc_hashes[i] = hash_list[i];
5681 /* Flush and reset the mta with the new values */
5682 igb_set_rx_mode(adapter->netdev);
5687 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5689 struct e1000_hw *hw = &adapter->hw;
5690 struct vf_data_storage *vf_data;
5693 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5694 u32 vmolr = rd32(E1000_VMOLR(i));
5696 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5698 vf_data = &adapter->vf_data[i];
5700 if ((vf_data->num_vf_mc_hashes > 30) ||
5701 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5702 vmolr |= E1000_VMOLR_MPME;
5703 } else if (vf_data->num_vf_mc_hashes) {
5704 vmolr |= E1000_VMOLR_ROMPE;
5705 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5706 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5708 wr32(E1000_VMOLR(i), vmolr);
5712 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5714 struct e1000_hw *hw = &adapter->hw;
5715 u32 pool_mask, reg, vid;
5718 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5720 /* Find the vlan filter for this id */
5721 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5722 reg = rd32(E1000_VLVF(i));
5724 /* remove the vf from the pool */
5727 /* if pool is empty then remove entry from vfta */
5728 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5729 (reg & E1000_VLVF_VLANID_ENABLE)) {
5731 vid = reg & E1000_VLVF_VLANID_MASK;
5732 igb_vfta_set(hw, vid, false);
5735 wr32(E1000_VLVF(i), reg);
5738 adapter->vf_data[vf].vlans_enabled = 0;
5741 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5743 struct e1000_hw *hw = &adapter->hw;
5746 /* The vlvf table only exists on 82576 hardware and newer */
5747 if (hw->mac.type < e1000_82576)
5750 /* we only need to do this if VMDq is enabled */
5751 if (!adapter->vfs_allocated_count)
5754 /* Find the vlan filter for this id */
5755 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5756 reg = rd32(E1000_VLVF(i));
5757 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5758 vid == (reg & E1000_VLVF_VLANID_MASK))
5763 if (i == E1000_VLVF_ARRAY_SIZE) {
5764 /* Did not find a matching VLAN ID entry that was
5765 * enabled. Search for a free filter entry, i.e.
5766 * one without the enable bit set
5768 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5769 reg = rd32(E1000_VLVF(i));
5770 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5774 if (i < E1000_VLVF_ARRAY_SIZE) {
5775 /* Found an enabled/available entry */
5776 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5778 /* if !enabled we need to set this up in vfta */
5779 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5780 /* add VID to filter table */
5781 igb_vfta_set(hw, vid, true);
5782 reg |= E1000_VLVF_VLANID_ENABLE;
5784 reg &= ~E1000_VLVF_VLANID_MASK;
5786 wr32(E1000_VLVF(i), reg);
5788 /* do not modify RLPML for PF devices */
5789 if (vf >= adapter->vfs_allocated_count)
5792 if (!adapter->vf_data[vf].vlans_enabled) {
5795 reg = rd32(E1000_VMOLR(vf));
5796 size = reg & E1000_VMOLR_RLPML_MASK;
5798 reg &= ~E1000_VMOLR_RLPML_MASK;
5800 wr32(E1000_VMOLR(vf), reg);
5803 adapter->vf_data[vf].vlans_enabled++;
5806 if (i < E1000_VLVF_ARRAY_SIZE) {
5807 /* remove vf from the pool */
5808 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5809 /* if pool is empty then remove entry from vfta */
5810 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5812 igb_vfta_set(hw, vid, false);
5814 wr32(E1000_VLVF(i), reg);
5816 /* do not modify RLPML for PF devices */
5817 if (vf >= adapter->vfs_allocated_count)
5820 adapter->vf_data[vf].vlans_enabled--;
5821 if (!adapter->vf_data[vf].vlans_enabled) {
5824 reg = rd32(E1000_VMOLR(vf));
5825 size = reg & E1000_VMOLR_RLPML_MASK;
5827 reg &= ~E1000_VMOLR_RLPML_MASK;
5829 wr32(E1000_VMOLR(vf), reg);
5836 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5838 struct e1000_hw *hw = &adapter->hw;
5841 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5843 wr32(E1000_VMVIR(vf), 0);
5846 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5847 int vf, u16 vlan, u8 qos)
5850 struct igb_adapter *adapter = netdev_priv(netdev);
5852 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5855 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5858 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5859 igb_set_vmolr(adapter, vf, !vlan);
5860 adapter->vf_data[vf].pf_vlan = vlan;
5861 adapter->vf_data[vf].pf_qos = qos;
5862 dev_info(&adapter->pdev->dev,
5863 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5864 if (test_bit(__IGB_DOWN, &adapter->state)) {
5865 dev_warn(&adapter->pdev->dev,
5866 "The VF VLAN has been set, but the PF device is not up.\n");
5867 dev_warn(&adapter->pdev->dev,
5868 "Bring the PF device up before attempting to use the VF device.\n");
5871 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5873 igb_set_vmvir(adapter, vlan, vf);
5874 igb_set_vmolr(adapter, vf, true);
5875 adapter->vf_data[vf].pf_vlan = 0;
5876 adapter->vf_data[vf].pf_qos = 0;
5882 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5884 struct e1000_hw *hw = &adapter->hw;
5888 /* Find the vlan filter for this id */
5889 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5890 reg = rd32(E1000_VLVF(i));
5891 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5892 vid == (reg & E1000_VLVF_VLANID_MASK))
5896 if (i >= E1000_VLVF_ARRAY_SIZE)
5902 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5904 struct e1000_hw *hw = &adapter->hw;
5905 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5906 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5909 /* If in promiscuous mode we need to make sure the PF also has
5910 * the VLAN filter set.
5912 if (add && (adapter->netdev->flags & IFF_PROMISC))
5913 err = igb_vlvf_set(adapter, vid, add,
5914 adapter->vfs_allocated_count);
5918 err = igb_vlvf_set(adapter, vid, add, vf);
5923 /* Go through all the checks to see if the VLAN filter should
5924 * be wiped completely.
5926 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5928 int regndx = igb_find_vlvf_entry(adapter, vid);
5932 /* See if any other pools are set for this VLAN filter
5933 * entry other than the PF.
5935 vlvf = bits = rd32(E1000_VLVF(regndx));
5936 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5937 adapter->vfs_allocated_count);
5938 /* If the filter was removed then ensure PF pool bit
5939 * is cleared if the PF only added itself to the pool
5940 * because the PF is in promiscuous mode.
5942 if ((vlvf & VLAN_VID_MASK) == vid &&
5943 !test_bit(vid, adapter->active_vlans) &&
5945 igb_vlvf_set(adapter, vid, add,
5946 adapter->vfs_allocated_count);
5953 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5955 /* clear flags - except flag that indicates PF has set the MAC */
5956 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5957 adapter->vf_data[vf].last_nack = jiffies;
5959 /* reset offloads to defaults */
5960 igb_set_vmolr(adapter, vf, true);
5962 /* reset vlans for device */
5963 igb_clear_vf_vfta(adapter, vf);
5964 if (adapter->vf_data[vf].pf_vlan)
5965 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5966 adapter->vf_data[vf].pf_vlan,
5967 adapter->vf_data[vf].pf_qos);
5969 igb_clear_vf_vfta(adapter, vf);
5971 /* reset multicast table array for vf */
5972 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5974 /* Flush and reset the mta with the new values */
5975 igb_set_rx_mode(adapter->netdev);
5978 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5980 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5982 /* clear mac address as we were hotplug removed/added */
5983 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5984 eth_zero_addr(vf_mac);
5986 /* process remaining reset events */
5987 igb_vf_reset(adapter, vf);
5990 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5992 struct e1000_hw *hw = &adapter->hw;
5993 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5994 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5996 u8 *addr = (u8 *)(&msgbuf[1]);
5998 /* process all the same items cleared in a function level reset */
5999 igb_vf_reset(adapter, vf);
6001 /* set vf mac address */
6002 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6004 /* enable transmit and receive for vf */
6005 reg = rd32(E1000_VFTE);
6006 wr32(E1000_VFTE, reg | (1 << vf));
6007 reg = rd32(E1000_VFRE);
6008 wr32(E1000_VFRE, reg | (1 << vf));
6010 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6012 /* reply to reset with ack and vf mac address */
6013 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6014 memcpy(addr, vf_mac, ETH_ALEN);
6015 igb_write_mbx(hw, msgbuf, 3, vf);
6018 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6020 /* The VF MAC Address is stored in a packed array of bytes
6021 * starting at the second 32 bit word of the msg array
6023 unsigned char *addr = (char *)&msg[1];
6026 if (is_valid_ether_addr(addr))
6027 err = igb_set_vf_mac(adapter, vf, addr);
6032 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6034 struct e1000_hw *hw = &adapter->hw;
6035 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6036 u32 msg = E1000_VT_MSGTYPE_NACK;
6038 /* if device isn't clear to send it shouldn't be reading either */
6039 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6040 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6041 igb_write_mbx(hw, &msg, 1, vf);
6042 vf_data->last_nack = jiffies;
6046 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6048 struct pci_dev *pdev = adapter->pdev;
6049 u32 msgbuf[E1000_VFMAILBOX_SIZE];
6050 struct e1000_hw *hw = &adapter->hw;
6051 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6054 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6057 /* if receive failed revoke VF CTS stats and restart init */
6058 dev_err(&pdev->dev, "Error receiving message from VF\n");
6059 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6060 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6065 /* this is a message we already processed, do nothing */
6066 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6069 /* until the vf completes a reset it should not be
6070 * allowed to start any configuration.
6072 if (msgbuf[0] == E1000_VF_RESET) {
6073 igb_vf_reset_msg(adapter, vf);
6077 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6078 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6084 switch ((msgbuf[0] & 0xFFFF)) {
6085 case E1000_VF_SET_MAC_ADDR:
6087 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6088 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6090 dev_warn(&pdev->dev,
6091 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6094 case E1000_VF_SET_PROMISC:
6095 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6097 case E1000_VF_SET_MULTICAST:
6098 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6100 case E1000_VF_SET_LPE:
6101 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6103 case E1000_VF_SET_VLAN:
6105 if (vf_data->pf_vlan)
6106 dev_warn(&pdev->dev,
6107 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6110 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
6113 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6118 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6120 /* notify the VF of the results of what it sent us */
6122 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6124 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6126 igb_write_mbx(hw, msgbuf, 1, vf);
6129 static void igb_msg_task(struct igb_adapter *adapter)
6131 struct e1000_hw *hw = &adapter->hw;
6134 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6135 /* process any reset requests */
6136 if (!igb_check_for_rst(hw, vf))
6137 igb_vf_reset_event(adapter, vf);
6139 /* process any messages pending */
6140 if (!igb_check_for_msg(hw, vf))
6141 igb_rcv_msg_from_vf(adapter, vf);
6143 /* process any acks */
6144 if (!igb_check_for_ack(hw, vf))
6145 igb_rcv_ack_from_vf(adapter, vf);
6150 * igb_set_uta - Set unicast filter table address
6151 * @adapter: board private structure
6153 * The unicast table address is a register array of 32-bit registers.
6154 * The table is meant to be used in a way similar to how the MTA is used
6155 * however due to certain limitations in the hardware it is necessary to
6156 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6157 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6159 static void igb_set_uta(struct igb_adapter *adapter)
6161 struct e1000_hw *hw = &adapter->hw;
6164 /* The UTA table only exists on 82576 hardware and newer */
6165 if (hw->mac.type < e1000_82576)
6168 /* we only need to do this if VMDq is enabled */
6169 if (!adapter->vfs_allocated_count)
6172 for (i = 0; i < hw->mac.uta_reg_count; i++)
6173 array_wr32(E1000_UTA, i, ~0);
6177 * igb_intr_msi - Interrupt Handler
6178 * @irq: interrupt number
6179 * @data: pointer to a network interface device structure
6181 static irqreturn_t igb_intr_msi(int irq, void *data)
6183 struct igb_adapter *adapter = data;
6184 struct igb_q_vector *q_vector = adapter->q_vector[0];
6185 struct e1000_hw *hw = &adapter->hw;
6186 /* read ICR disables interrupts using IAM */
6187 u32 icr = rd32(E1000_ICR);
6189 igb_write_itr(q_vector);
6191 if (icr & E1000_ICR_DRSTA)
6192 schedule_work(&adapter->reset_task);
6194 if (icr & E1000_ICR_DOUTSYNC) {
6195 /* HW is reporting DMA is out of sync */
6196 adapter->stats.doosync++;
6199 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6200 hw->mac.get_link_status = 1;
6201 if (!test_bit(__IGB_DOWN, &adapter->state))
6202 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6205 if (icr & E1000_ICR_TS) {
6206 u32 tsicr = rd32(E1000_TSICR);
6208 if (tsicr & E1000_TSICR_TXTS) {
6209 /* acknowledge the interrupt */
6210 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6211 /* retrieve hardware timestamp */
6212 schedule_work(&adapter->ptp_tx_work);
6216 napi_schedule(&q_vector->napi);
6222 * igb_intr - Legacy Interrupt Handler
6223 * @irq: interrupt number
6224 * @data: pointer to a network interface device structure
6226 static irqreturn_t igb_intr(int irq, void *data)
6228 struct igb_adapter *adapter = data;
6229 struct igb_q_vector *q_vector = adapter->q_vector[0];
6230 struct e1000_hw *hw = &adapter->hw;
6231 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6232 * need for the IMC write
6234 u32 icr = rd32(E1000_ICR);
6236 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6237 * not set, then the adapter didn't send an interrupt
6239 if (!(icr & E1000_ICR_INT_ASSERTED))
6242 igb_write_itr(q_vector);
6244 if (icr & E1000_ICR_DRSTA)
6245 schedule_work(&adapter->reset_task);
6247 if (icr & E1000_ICR_DOUTSYNC) {
6248 /* HW is reporting DMA is out of sync */
6249 adapter->stats.doosync++;
6252 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6253 hw->mac.get_link_status = 1;
6254 /* guard against interrupt when we're going down */
6255 if (!test_bit(__IGB_DOWN, &adapter->state))
6256 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6259 if (icr & E1000_ICR_TS) {
6260 u32 tsicr = rd32(E1000_TSICR);
6262 if (tsicr & E1000_TSICR_TXTS) {
6263 /* acknowledge the interrupt */
6264 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6265 /* retrieve hardware timestamp */
6266 schedule_work(&adapter->ptp_tx_work);
6270 napi_schedule(&q_vector->napi);
6275 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6277 struct igb_adapter *adapter = q_vector->adapter;
6278 struct e1000_hw *hw = &adapter->hw;
6280 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6281 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6282 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6283 igb_set_itr(q_vector);
6285 igb_update_ring_itr(q_vector);
6288 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6289 if (adapter->flags & IGB_FLAG_HAS_MSIX)
6290 wr32(E1000_EIMS, q_vector->eims_value);
6292 igb_irq_enable(adapter);
6297 * igb_poll - NAPI Rx polling callback
6298 * @napi: napi polling structure
6299 * @budget: count of how many packets we should handle
6301 static int igb_poll(struct napi_struct *napi, int budget)
6303 struct igb_q_vector *q_vector = container_of(napi,
6304 struct igb_q_vector,
6306 bool clean_complete = true;
6308 #ifdef CONFIG_IGB_DCA
6309 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6310 igb_update_dca(q_vector);
6312 if (q_vector->tx.ring)
6313 clean_complete = igb_clean_tx_irq(q_vector);
6315 if (q_vector->rx.ring)
6316 clean_complete &= igb_clean_rx_irq(q_vector, budget);
6318 /* If all work not completed, return budget and keep polling */
6319 if (!clean_complete)
6322 /* If not enough Rx work done, exit the polling mode */
6323 napi_complete(napi);
6324 igb_ring_irq_enable(q_vector);
6330 * igb_clean_tx_irq - Reclaim resources after transmit completes
6331 * @q_vector: pointer to q_vector containing needed info
6333 * returns true if ring is completely cleaned
6335 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6337 struct igb_adapter *adapter = q_vector->adapter;
6338 struct igb_ring *tx_ring = q_vector->tx.ring;
6339 struct igb_tx_buffer *tx_buffer;
6340 union e1000_adv_tx_desc *tx_desc;
6341 unsigned int total_bytes = 0, total_packets = 0;
6342 unsigned int budget = q_vector->tx.work_limit;
6343 unsigned int i = tx_ring->next_to_clean;
6345 if (test_bit(__IGB_DOWN, &adapter->state))
6348 tx_buffer = &tx_ring->tx_buffer_info[i];
6349 tx_desc = IGB_TX_DESC(tx_ring, i);
6350 i -= tx_ring->count;
6353 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6355 /* if next_to_watch is not set then there is no work pending */
6359 /* prevent any other reads prior to eop_desc */
6360 read_barrier_depends();
6362 /* if DD is not set pending work has not been completed */
6363 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6366 /* clear next_to_watch to prevent false hangs */
6367 tx_buffer->next_to_watch = NULL;
6369 /* update the statistics for this packet */
6370 total_bytes += tx_buffer->bytecount;
6371 total_packets += tx_buffer->gso_segs;
6374 dev_consume_skb_any(tx_buffer->skb);
6376 /* unmap skb header data */
6377 dma_unmap_single(tx_ring->dev,
6378 dma_unmap_addr(tx_buffer, dma),
6379 dma_unmap_len(tx_buffer, len),
6382 /* clear tx_buffer data */
6383 tx_buffer->skb = NULL;
6384 dma_unmap_len_set(tx_buffer, len, 0);
6386 /* clear last DMA location and unmap remaining buffers */
6387 while (tx_desc != eop_desc) {
6392 i -= tx_ring->count;
6393 tx_buffer = tx_ring->tx_buffer_info;
6394 tx_desc = IGB_TX_DESC(tx_ring, 0);
6397 /* unmap any remaining paged data */
6398 if (dma_unmap_len(tx_buffer, len)) {
6399 dma_unmap_page(tx_ring->dev,
6400 dma_unmap_addr(tx_buffer, dma),
6401 dma_unmap_len(tx_buffer, len),
6403 dma_unmap_len_set(tx_buffer, len, 0);
6407 /* move us one more past the eop_desc for start of next pkt */
6412 i -= tx_ring->count;
6413 tx_buffer = tx_ring->tx_buffer_info;
6414 tx_desc = IGB_TX_DESC(tx_ring, 0);
6417 /* issue prefetch for next Tx descriptor */
6420 /* update budget accounting */
6422 } while (likely(budget));
6424 netdev_tx_completed_queue(txring_txq(tx_ring),
6425 total_packets, total_bytes);
6426 i += tx_ring->count;
6427 tx_ring->next_to_clean = i;
6428 u64_stats_update_begin(&tx_ring->tx_syncp);
6429 tx_ring->tx_stats.bytes += total_bytes;
6430 tx_ring->tx_stats.packets += total_packets;
6431 u64_stats_update_end(&tx_ring->tx_syncp);
6432 q_vector->tx.total_bytes += total_bytes;
6433 q_vector->tx.total_packets += total_packets;
6435 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6436 struct e1000_hw *hw = &adapter->hw;
6438 /* Detect a transmit hang in hardware, this serializes the
6439 * check with the clearing of time_stamp and movement of i
6441 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6442 if (tx_buffer->next_to_watch &&
6443 time_after(jiffies, tx_buffer->time_stamp +
6444 (adapter->tx_timeout_factor * HZ)) &&
6445 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6447 /* detected Tx unit hang */
6448 dev_err(tx_ring->dev,
6449 "Detected Tx Unit Hang\n"
6453 " next_to_use <%x>\n"
6454 " next_to_clean <%x>\n"
6455 "buffer_info[next_to_clean]\n"
6456 " time_stamp <%lx>\n"
6457 " next_to_watch <%p>\n"
6459 " desc.status <%x>\n",
6460 tx_ring->queue_index,
6461 rd32(E1000_TDH(tx_ring->reg_idx)),
6462 readl(tx_ring->tail),
6463 tx_ring->next_to_use,
6464 tx_ring->next_to_clean,
6465 tx_buffer->time_stamp,
6466 tx_buffer->next_to_watch,
6468 tx_buffer->next_to_watch->wb.status);
6469 netif_stop_subqueue(tx_ring->netdev,
6470 tx_ring->queue_index);
6472 /* we are about to reset, no point in enabling stuff */
6477 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6478 if (unlikely(total_packets &&
6479 netif_carrier_ok(tx_ring->netdev) &&
6480 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6481 /* Make sure that anybody stopping the queue after this
6482 * sees the new next_to_clean.
6485 if (__netif_subqueue_stopped(tx_ring->netdev,
6486 tx_ring->queue_index) &&
6487 !(test_bit(__IGB_DOWN, &adapter->state))) {
6488 netif_wake_subqueue(tx_ring->netdev,
6489 tx_ring->queue_index);
6491 u64_stats_update_begin(&tx_ring->tx_syncp);
6492 tx_ring->tx_stats.restart_queue++;
6493 u64_stats_update_end(&tx_ring->tx_syncp);
6501 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6502 * @rx_ring: rx descriptor ring to store buffers on
6503 * @old_buff: donor buffer to have page reused
6505 * Synchronizes page for reuse by the adapter
6507 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6508 struct igb_rx_buffer *old_buff)
6510 struct igb_rx_buffer *new_buff;
6511 u16 nta = rx_ring->next_to_alloc;
6513 new_buff = &rx_ring->rx_buffer_info[nta];
6515 /* update, and store next to alloc */
6517 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6519 /* transfer page from old buffer to new buffer */
6520 *new_buff = *old_buff;
6522 /* sync the buffer for use by the device */
6523 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6524 old_buff->page_offset,
6529 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6531 unsigned int truesize)
6533 /* avoid re-using remote pages */
6534 if (unlikely(page_to_nid(page) != numa_node_id()))
6537 if (unlikely(page->pfmemalloc))
6540 #if (PAGE_SIZE < 8192)
6541 /* if we are only owner of page we can reuse it */
6542 if (unlikely(page_count(page) != 1))
6545 /* flip page offset to other buffer */
6546 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6548 /* Even if we own the page, we are not allowed to use atomic_set()
6549 * This would break get_page_unless_zero() users.
6551 atomic_inc(&page->_count);
6553 /* move offset up to the next cache line */
6554 rx_buffer->page_offset += truesize;
6556 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6559 /* bump ref count on page before it is given to the stack */
6567 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6568 * @rx_ring: rx descriptor ring to transact packets on
6569 * @rx_buffer: buffer containing page to add
6570 * @rx_desc: descriptor containing length of buffer written by hardware
6571 * @skb: sk_buff to place the data into
6573 * This function will add the data contained in rx_buffer->page to the skb.
6574 * This is done either through a direct copy if the data in the buffer is
6575 * less than the skb header size, otherwise it will just attach the page as
6576 * a frag to the skb.
6578 * The function will then update the page offset if necessary and return
6579 * true if the buffer can be reused by the adapter.
6581 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6582 struct igb_rx_buffer *rx_buffer,
6583 union e1000_adv_rx_desc *rx_desc,
6584 struct sk_buff *skb)
6586 struct page *page = rx_buffer->page;
6587 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6588 #if (PAGE_SIZE < 8192)
6589 unsigned int truesize = IGB_RX_BUFSZ;
6591 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6594 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6595 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6597 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6598 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6599 va += IGB_TS_HDR_LEN;
6600 size -= IGB_TS_HDR_LEN;
6603 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6605 /* we can reuse buffer as-is, just make sure it is local */
6606 if (likely((page_to_nid(page) == numa_node_id()) &&
6610 /* this page cannot be reused so discard it */
6615 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6616 rx_buffer->page_offset, size, truesize);
6618 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6621 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6622 union e1000_adv_rx_desc *rx_desc,
6623 struct sk_buff *skb)
6625 struct igb_rx_buffer *rx_buffer;
6628 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6630 page = rx_buffer->page;
6634 void *page_addr = page_address(page) +
6635 rx_buffer->page_offset;
6637 /* prefetch first cache line of first page */
6638 prefetch(page_addr);
6639 #if L1_CACHE_BYTES < 128
6640 prefetch(page_addr + L1_CACHE_BYTES);
6643 /* allocate a skb to store the frags */
6644 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6646 if (unlikely(!skb)) {
6647 rx_ring->rx_stats.alloc_failed++;
6651 /* we will be copying header into skb->data in
6652 * pskb_may_pull so it is in our interest to prefetch
6653 * it now to avoid a possible cache miss
6655 prefetchw(skb->data);
6658 /* we are reusing so sync this buffer for CPU use */
6659 dma_sync_single_range_for_cpu(rx_ring->dev,
6661 rx_buffer->page_offset,
6665 /* pull page into skb */
6666 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6667 /* hand second half of page back to the ring */
6668 igb_reuse_rx_page(rx_ring, rx_buffer);
6670 /* we are not reusing the buffer so unmap it */
6671 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6672 PAGE_SIZE, DMA_FROM_DEVICE);
6675 /* clear contents of rx_buffer */
6676 rx_buffer->page = NULL;
6681 static inline void igb_rx_checksum(struct igb_ring *ring,
6682 union e1000_adv_rx_desc *rx_desc,
6683 struct sk_buff *skb)
6685 skb_checksum_none_assert(skb);
6687 /* Ignore Checksum bit is set */
6688 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6691 /* Rx checksum disabled via ethtool */
6692 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6695 /* TCP/UDP checksum error bit is set */
6696 if (igb_test_staterr(rx_desc,
6697 E1000_RXDEXT_STATERR_TCPE |
6698 E1000_RXDEXT_STATERR_IPE)) {
6699 /* work around errata with sctp packets where the TCPE aka
6700 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6701 * packets, (aka let the stack check the crc32c)
6703 if (!((skb->len == 60) &&
6704 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6705 u64_stats_update_begin(&ring->rx_syncp);
6706 ring->rx_stats.csum_err++;
6707 u64_stats_update_end(&ring->rx_syncp);
6709 /* let the stack verify checksum errors */
6712 /* It must be a TCP or UDP packet with a valid checksum */
6713 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6714 E1000_RXD_STAT_UDPCS))
6715 skb->ip_summed = CHECKSUM_UNNECESSARY;
6717 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6718 le32_to_cpu(rx_desc->wb.upper.status_error));
6721 static inline void igb_rx_hash(struct igb_ring *ring,
6722 union e1000_adv_rx_desc *rx_desc,
6723 struct sk_buff *skb)
6725 if (ring->netdev->features & NETIF_F_RXHASH)
6727 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6732 * igb_is_non_eop - process handling of non-EOP buffers
6733 * @rx_ring: Rx ring being processed
6734 * @rx_desc: Rx descriptor for current buffer
6735 * @skb: current socket buffer containing buffer in progress
6737 * This function updates next to clean. If the buffer is an EOP buffer
6738 * this function exits returning false, otherwise it will place the
6739 * sk_buff in the next buffer to be chained and return true indicating
6740 * that this is in fact a non-EOP buffer.
6742 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6743 union e1000_adv_rx_desc *rx_desc)
6745 u32 ntc = rx_ring->next_to_clean + 1;
6747 /* fetch, update, and store next to clean */
6748 ntc = (ntc < rx_ring->count) ? ntc : 0;
6749 rx_ring->next_to_clean = ntc;
6751 prefetch(IGB_RX_DESC(rx_ring, ntc));
6753 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6760 * igb_pull_tail - igb specific version of skb_pull_tail
6761 * @rx_ring: rx descriptor ring packet is being transacted on
6762 * @rx_desc: pointer to the EOP Rx descriptor
6763 * @skb: pointer to current skb being adjusted
6765 * This function is an igb specific version of __pskb_pull_tail. The
6766 * main difference between this version and the original function is that
6767 * this function can make several assumptions about the state of things
6768 * that allow for significant optimizations versus the standard function.
6769 * As a result we can do things like drop a frag and maintain an accurate
6770 * truesize for the skb.
6772 static void igb_pull_tail(struct igb_ring *rx_ring,
6773 union e1000_adv_rx_desc *rx_desc,
6774 struct sk_buff *skb)
6776 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6778 unsigned int pull_len;
6780 /* it is valid to use page_address instead of kmap since we are
6781 * working with pages allocated out of the lomem pool per
6782 * alloc_page(GFP_ATOMIC)
6784 va = skb_frag_address(frag);
6786 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6787 /* retrieve timestamp from buffer */
6788 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6790 /* update pointers to remove timestamp header */
6791 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6792 frag->page_offset += IGB_TS_HDR_LEN;
6793 skb->data_len -= IGB_TS_HDR_LEN;
6794 skb->len -= IGB_TS_HDR_LEN;
6796 /* move va to start of packet data */
6797 va += IGB_TS_HDR_LEN;
6800 /* we need the header to contain the greater of either ETH_HLEN or
6801 * 60 bytes if the skb->len is less than 60 for skb_pad.
6803 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6805 /* align pull length to size of long to optimize memcpy performance */
6806 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6808 /* update all of the pointers */
6809 skb_frag_size_sub(frag, pull_len);
6810 frag->page_offset += pull_len;
6811 skb->data_len -= pull_len;
6812 skb->tail += pull_len;
6816 * igb_cleanup_headers - Correct corrupted or empty headers
6817 * @rx_ring: rx descriptor ring packet is being transacted on
6818 * @rx_desc: pointer to the EOP Rx descriptor
6819 * @skb: pointer to current skb being fixed
6821 * Address the case where we are pulling data in on pages only
6822 * and as such no data is present in the skb header.
6824 * In addition if skb is not at least 60 bytes we need to pad it so that
6825 * it is large enough to qualify as a valid Ethernet frame.
6827 * Returns true if an error was encountered and skb was freed.
6829 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6830 union e1000_adv_rx_desc *rx_desc,
6831 struct sk_buff *skb)
6833 if (unlikely((igb_test_staterr(rx_desc,
6834 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6835 struct net_device *netdev = rx_ring->netdev;
6836 if (!(netdev->features & NETIF_F_RXALL)) {
6837 dev_kfree_skb_any(skb);
6842 /* place header in linear portion of buffer */
6843 if (skb_is_nonlinear(skb))
6844 igb_pull_tail(rx_ring, rx_desc, skb);
6846 /* if skb_pad returns an error the skb was freed */
6847 if (unlikely(skb->len < 60)) {
6848 int pad_len = 60 - skb->len;
6850 if (skb_pad(skb, pad_len))
6852 __skb_put(skb, pad_len);
6859 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6860 * @rx_ring: rx descriptor ring packet is being transacted on
6861 * @rx_desc: pointer to the EOP Rx descriptor
6862 * @skb: pointer to current skb being populated
6864 * This function checks the ring, descriptor, and packet information in
6865 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6866 * other fields within the skb.
6868 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6869 union e1000_adv_rx_desc *rx_desc,
6870 struct sk_buff *skb)
6872 struct net_device *dev = rx_ring->netdev;
6874 igb_rx_hash(rx_ring, rx_desc, skb);
6876 igb_rx_checksum(rx_ring, rx_desc, skb);
6878 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6879 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6880 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
6882 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6883 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6886 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6887 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6888 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6890 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6892 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6895 skb_record_rx_queue(skb, rx_ring->queue_index);
6897 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6900 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6902 struct igb_ring *rx_ring = q_vector->rx.ring;
6903 struct sk_buff *skb = rx_ring->skb;
6904 unsigned int total_bytes = 0, total_packets = 0;
6905 u16 cleaned_count = igb_desc_unused(rx_ring);
6907 while (likely(total_packets < budget)) {
6908 union e1000_adv_rx_desc *rx_desc;
6910 /* return some buffers to hardware, one at a time is too slow */
6911 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6912 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6916 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6918 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6921 /* This memory barrier is needed to keep us from reading
6922 * any other fields out of the rx_desc until we know the
6923 * RXD_STAT_DD bit is set
6927 /* retrieve a buffer from the ring */
6928 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6930 /* exit if we failed to retrieve a buffer */
6936 /* fetch next buffer in frame if non-eop */
6937 if (igb_is_non_eop(rx_ring, rx_desc))
6940 /* verify the packet layout is correct */
6941 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6946 /* probably a little skewed due to removing CRC */
6947 total_bytes += skb->len;
6949 /* populate checksum, timestamp, VLAN, and protocol */
6950 igb_process_skb_fields(rx_ring, rx_desc, skb);
6952 napi_gro_receive(&q_vector->napi, skb);
6954 /* reset skb pointer */
6957 /* update budget accounting */
6961 /* place incomplete frames back on ring for completion */
6964 u64_stats_update_begin(&rx_ring->rx_syncp);
6965 rx_ring->rx_stats.packets += total_packets;
6966 rx_ring->rx_stats.bytes += total_bytes;
6967 u64_stats_update_end(&rx_ring->rx_syncp);
6968 q_vector->rx.total_packets += total_packets;
6969 q_vector->rx.total_bytes += total_bytes;
6972 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6974 return total_packets < budget;
6977 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6978 struct igb_rx_buffer *bi)
6980 struct page *page = bi->page;
6983 /* since we are recycling buffers we should seldom need to alloc */
6987 /* alloc new page for storage */
6988 page = dev_alloc_page();
6989 if (unlikely(!page)) {
6990 rx_ring->rx_stats.alloc_failed++;
6994 /* map page for use */
6995 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6997 /* if mapping failed free memory back to system since
6998 * there isn't much point in holding memory we can't use
7000 if (dma_mapping_error(rx_ring->dev, dma)) {
7003 rx_ring->rx_stats.alloc_failed++;
7009 bi->page_offset = 0;
7015 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7016 * @adapter: address of board private structure
7018 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7020 union e1000_adv_rx_desc *rx_desc;
7021 struct igb_rx_buffer *bi;
7022 u16 i = rx_ring->next_to_use;
7028 rx_desc = IGB_RX_DESC(rx_ring, i);
7029 bi = &rx_ring->rx_buffer_info[i];
7030 i -= rx_ring->count;
7033 if (!igb_alloc_mapped_page(rx_ring, bi))
7036 /* Refresh the desc even if buffer_addrs didn't change
7037 * because each write-back erases this info.
7039 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7045 rx_desc = IGB_RX_DESC(rx_ring, 0);
7046 bi = rx_ring->rx_buffer_info;
7047 i -= rx_ring->count;
7050 /* clear the hdr_addr for the next_to_use descriptor */
7051 rx_desc->read.hdr_addr = 0;
7054 } while (cleaned_count);
7056 i += rx_ring->count;
7058 if (rx_ring->next_to_use != i) {
7059 /* record the next descriptor to use */
7060 rx_ring->next_to_use = i;
7062 /* update next to alloc since we have filled the ring */
7063 rx_ring->next_to_alloc = i;
7065 /* Force memory writes to complete before letting h/w
7066 * know there are new descriptors to fetch. (Only
7067 * applicable for weak-ordered memory model archs,
7071 writel(i, rx_ring->tail);
7081 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7083 struct igb_adapter *adapter = netdev_priv(netdev);
7084 struct mii_ioctl_data *data = if_mii(ifr);
7086 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7091 data->phy_id = adapter->hw.phy.addr;
7094 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7111 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7117 return igb_mii_ioctl(netdev, ifr, cmd);
7119 return igb_ptp_get_ts_config(netdev, ifr);
7121 return igb_ptp_set_ts_config(netdev, ifr);
7127 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7129 struct igb_adapter *adapter = hw->back;
7131 pci_read_config_word(adapter->pdev, reg, value);
7134 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7136 struct igb_adapter *adapter = hw->back;
7138 pci_write_config_word(adapter->pdev, reg, *value);
7141 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7143 struct igb_adapter *adapter = hw->back;
7145 if (pcie_capability_read_word(adapter->pdev, reg, value))
7146 return -E1000_ERR_CONFIG;
7151 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7153 struct igb_adapter *adapter = hw->back;
7155 if (pcie_capability_write_word(adapter->pdev, reg, *value))
7156 return -E1000_ERR_CONFIG;
7161 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7163 struct igb_adapter *adapter = netdev_priv(netdev);
7164 struct e1000_hw *hw = &adapter->hw;
7166 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7169 /* enable VLAN tag insert/strip */
7170 ctrl = rd32(E1000_CTRL);
7171 ctrl |= E1000_CTRL_VME;
7172 wr32(E1000_CTRL, ctrl);
7174 /* Disable CFI check */
7175 rctl = rd32(E1000_RCTL);
7176 rctl &= ~E1000_RCTL_CFIEN;
7177 wr32(E1000_RCTL, rctl);
7179 /* disable VLAN tag insert/strip */
7180 ctrl = rd32(E1000_CTRL);
7181 ctrl &= ~E1000_CTRL_VME;
7182 wr32(E1000_CTRL, ctrl);
7185 igb_rlpml_set(adapter);
7188 static int igb_vlan_rx_add_vid(struct net_device *netdev,
7189 __be16 proto, u16 vid)
7191 struct igb_adapter *adapter = netdev_priv(netdev);
7192 struct e1000_hw *hw = &adapter->hw;
7193 int pf_id = adapter->vfs_allocated_count;
7195 /* attempt to add filter to vlvf array */
7196 igb_vlvf_set(adapter, vid, true, pf_id);
7198 /* add the filter since PF can receive vlans w/o entry in vlvf */
7199 igb_vfta_set(hw, vid, true);
7201 set_bit(vid, adapter->active_vlans);
7206 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7207 __be16 proto, u16 vid)
7209 struct igb_adapter *adapter = netdev_priv(netdev);
7210 struct e1000_hw *hw = &adapter->hw;
7211 int pf_id = adapter->vfs_allocated_count;
7214 /* remove vlan from VLVF table array */
7215 err = igb_vlvf_set(adapter, vid, false, pf_id);
7217 /* if vid was not present in VLVF just remove it from table */
7219 igb_vfta_set(hw, vid, false);
7221 clear_bit(vid, adapter->active_vlans);
7226 static void igb_restore_vlan(struct igb_adapter *adapter)
7230 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7232 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7233 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7236 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7238 struct pci_dev *pdev = adapter->pdev;
7239 struct e1000_mac_info *mac = &adapter->hw.mac;
7243 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7244 * for the switch() below to work
7246 if ((spd & 1) || (dplx & ~1))
7249 /* Fiber NIC's only allow 1000 gbps Full duplex
7250 * and 100Mbps Full duplex for 100baseFx sfp
7252 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7253 switch (spd + dplx) {
7254 case SPEED_10 + DUPLEX_HALF:
7255 case SPEED_10 + DUPLEX_FULL:
7256 case SPEED_100 + DUPLEX_HALF:
7263 switch (spd + dplx) {
7264 case SPEED_10 + DUPLEX_HALF:
7265 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7267 case SPEED_10 + DUPLEX_FULL:
7268 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7270 case SPEED_100 + DUPLEX_HALF:
7271 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7273 case SPEED_100 + DUPLEX_FULL:
7274 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7276 case SPEED_1000 + DUPLEX_FULL:
7278 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7280 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7285 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7286 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7291 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7295 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7298 struct net_device *netdev = pci_get_drvdata(pdev);
7299 struct igb_adapter *adapter = netdev_priv(netdev);
7300 struct e1000_hw *hw = &adapter->hw;
7301 u32 ctrl, rctl, status;
7302 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7307 netif_device_detach(netdev);
7309 if (netif_running(netdev))
7310 __igb_close(netdev, true);
7312 igb_clear_interrupt_scheme(adapter);
7315 retval = pci_save_state(pdev);
7320 status = rd32(E1000_STATUS);
7321 if (status & E1000_STATUS_LU)
7322 wufc &= ~E1000_WUFC_LNKC;
7325 igb_setup_rctl(adapter);
7326 igb_set_rx_mode(netdev);
7328 /* turn on all-multi mode if wake on multicast is enabled */
7329 if (wufc & E1000_WUFC_MC) {
7330 rctl = rd32(E1000_RCTL);
7331 rctl |= E1000_RCTL_MPE;
7332 wr32(E1000_RCTL, rctl);
7335 ctrl = rd32(E1000_CTRL);
7336 /* advertise wake from D3Cold */
7337 #define E1000_CTRL_ADVD3WUC 0x00100000
7338 /* phy power management enable */
7339 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7340 ctrl |= E1000_CTRL_ADVD3WUC;
7341 wr32(E1000_CTRL, ctrl);
7343 /* Allow time for pending master requests to run */
7344 igb_disable_pcie_master(hw);
7346 wr32(E1000_WUC, E1000_WUC_PME_EN);
7347 wr32(E1000_WUFC, wufc);
7350 wr32(E1000_WUFC, 0);
7353 *enable_wake = wufc || adapter->en_mng_pt;
7355 igb_power_down_link(adapter);
7357 igb_power_up_link(adapter);
7359 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7360 * would have already happened in close and is redundant.
7362 igb_release_hw_control(adapter);
7364 pci_disable_device(pdev);
7370 #ifdef CONFIG_PM_SLEEP
7371 static int igb_suspend(struct device *dev)
7375 struct pci_dev *pdev = to_pci_dev(dev);
7377 retval = __igb_shutdown(pdev, &wake, 0);
7382 pci_prepare_to_sleep(pdev);
7384 pci_wake_from_d3(pdev, false);
7385 pci_set_power_state(pdev, PCI_D3hot);
7390 #endif /* CONFIG_PM_SLEEP */
7392 static int igb_resume(struct device *dev)
7394 struct pci_dev *pdev = to_pci_dev(dev);
7395 struct net_device *netdev = pci_get_drvdata(pdev);
7396 struct igb_adapter *adapter = netdev_priv(netdev);
7397 struct e1000_hw *hw = &adapter->hw;
7400 pci_set_power_state(pdev, PCI_D0);
7401 pci_restore_state(pdev);
7402 pci_save_state(pdev);
7404 err = pci_enable_device_mem(pdev);
7407 "igb: Cannot enable PCI device from suspend\n");
7410 pci_set_master(pdev);
7412 pci_enable_wake(pdev, PCI_D3hot, 0);
7413 pci_enable_wake(pdev, PCI_D3cold, 0);
7415 if (igb_init_interrupt_scheme(adapter, true)) {
7416 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7422 /* let the f/w know that the h/w is now under the control of the
7425 igb_get_hw_control(adapter);
7427 wr32(E1000_WUS, ~0);
7429 if (netdev->flags & IFF_UP) {
7431 err = __igb_open(netdev, true);
7437 netif_device_attach(netdev);
7441 #ifdef CONFIG_PM_RUNTIME
7442 static int igb_runtime_idle(struct device *dev)
7444 struct pci_dev *pdev = to_pci_dev(dev);
7445 struct net_device *netdev = pci_get_drvdata(pdev);
7446 struct igb_adapter *adapter = netdev_priv(netdev);
7448 if (!igb_has_link(adapter))
7449 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7454 static int igb_runtime_suspend(struct device *dev)
7456 struct pci_dev *pdev = to_pci_dev(dev);
7460 retval = __igb_shutdown(pdev, &wake, 1);
7465 pci_prepare_to_sleep(pdev);
7467 pci_wake_from_d3(pdev, false);
7468 pci_set_power_state(pdev, PCI_D3hot);
7474 static int igb_runtime_resume(struct device *dev)
7476 return igb_resume(dev);
7478 #endif /* CONFIG_PM_RUNTIME */
7481 static void igb_shutdown(struct pci_dev *pdev)
7485 __igb_shutdown(pdev, &wake, 0);
7487 if (system_state == SYSTEM_POWER_OFF) {
7488 pci_wake_from_d3(pdev, wake);
7489 pci_set_power_state(pdev, PCI_D3hot);
7493 #ifdef CONFIG_PCI_IOV
7494 static int igb_sriov_reinit(struct pci_dev *dev)
7496 struct net_device *netdev = pci_get_drvdata(dev);
7497 struct igb_adapter *adapter = netdev_priv(netdev);
7498 struct pci_dev *pdev = adapter->pdev;
7502 if (netif_running(netdev))
7507 igb_clear_interrupt_scheme(adapter);
7509 igb_init_queue_configuration(adapter);
7511 if (igb_init_interrupt_scheme(adapter, true)) {
7512 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7516 if (netif_running(netdev))
7524 static int igb_pci_disable_sriov(struct pci_dev *dev)
7526 int err = igb_disable_sriov(dev);
7529 err = igb_sriov_reinit(dev);
7534 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7536 int err = igb_enable_sriov(dev, num_vfs);
7541 err = igb_sriov_reinit(dev);
7550 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7552 #ifdef CONFIG_PCI_IOV
7554 return igb_pci_disable_sriov(dev);
7556 return igb_pci_enable_sriov(dev, num_vfs);
7561 #ifdef CONFIG_NET_POLL_CONTROLLER
7562 /* Polling 'interrupt' - used by things like netconsole to send skbs
7563 * without having to re-enable interrupts. It's not called while
7564 * the interrupt routine is executing.
7566 static void igb_netpoll(struct net_device *netdev)
7568 struct igb_adapter *adapter = netdev_priv(netdev);
7569 struct e1000_hw *hw = &adapter->hw;
7570 struct igb_q_vector *q_vector;
7573 for (i = 0; i < adapter->num_q_vectors; i++) {
7574 q_vector = adapter->q_vector[i];
7575 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7576 wr32(E1000_EIMC, q_vector->eims_value);
7578 igb_irq_disable(adapter);
7579 napi_schedule(&q_vector->napi);
7582 #endif /* CONFIG_NET_POLL_CONTROLLER */
7585 * igb_io_error_detected - called when PCI error is detected
7586 * @pdev: Pointer to PCI device
7587 * @state: The current pci connection state
7589 * This function is called after a PCI bus error affecting
7590 * this device has been detected.
7592 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7593 pci_channel_state_t state)
7595 struct net_device *netdev = pci_get_drvdata(pdev);
7596 struct igb_adapter *adapter = netdev_priv(netdev);
7598 netif_device_detach(netdev);
7600 if (state == pci_channel_io_perm_failure)
7601 return PCI_ERS_RESULT_DISCONNECT;
7603 if (netif_running(netdev))
7605 pci_disable_device(pdev);
7607 /* Request a slot slot reset. */
7608 return PCI_ERS_RESULT_NEED_RESET;
7612 * igb_io_slot_reset - called after the pci bus has been reset.
7613 * @pdev: Pointer to PCI device
7615 * Restart the card from scratch, as if from a cold-boot. Implementation
7616 * resembles the first-half of the igb_resume routine.
7618 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7620 struct net_device *netdev = pci_get_drvdata(pdev);
7621 struct igb_adapter *adapter = netdev_priv(netdev);
7622 struct e1000_hw *hw = &adapter->hw;
7623 pci_ers_result_t result;
7626 if (pci_enable_device_mem(pdev)) {
7628 "Cannot re-enable PCI device after reset.\n");
7629 result = PCI_ERS_RESULT_DISCONNECT;
7631 pci_set_master(pdev);
7632 pci_restore_state(pdev);
7633 pci_save_state(pdev);
7635 pci_enable_wake(pdev, PCI_D3hot, 0);
7636 pci_enable_wake(pdev, PCI_D3cold, 0);
7639 wr32(E1000_WUS, ~0);
7640 result = PCI_ERS_RESULT_RECOVERED;
7643 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7646 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7648 /* non-fatal, continue */
7655 * igb_io_resume - called when traffic can start flowing again.
7656 * @pdev: Pointer to PCI device
7658 * This callback is called when the error recovery driver tells us that
7659 * its OK to resume normal operation. Implementation resembles the
7660 * second-half of the igb_resume routine.
7662 static void igb_io_resume(struct pci_dev *pdev)
7664 struct net_device *netdev = pci_get_drvdata(pdev);
7665 struct igb_adapter *adapter = netdev_priv(netdev);
7667 if (netif_running(netdev)) {
7668 if (igb_up(adapter)) {
7669 dev_err(&pdev->dev, "igb_up failed after reset\n");
7674 netif_device_attach(netdev);
7676 /* let the f/w know that the h/w is now under the control of the
7679 igb_get_hw_control(adapter);
7682 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7685 u32 rar_low, rar_high;
7686 struct e1000_hw *hw = &adapter->hw;
7688 /* HW expects these in little endian so we reverse the byte order
7689 * from network order (big endian) to little endian
7691 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7692 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7693 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7695 /* Indicate to hardware the Address is Valid. */
7696 rar_high |= E1000_RAH_AV;
7698 if (hw->mac.type == e1000_82575)
7699 rar_high |= E1000_RAH_POOL_1 * qsel;
7701 rar_high |= E1000_RAH_POOL_1 << qsel;
7703 wr32(E1000_RAL(index), rar_low);
7705 wr32(E1000_RAH(index), rar_high);
7709 static int igb_set_vf_mac(struct igb_adapter *adapter,
7710 int vf, unsigned char *mac_addr)
7712 struct e1000_hw *hw = &adapter->hw;
7713 /* VF MAC addresses start at end of receive addresses and moves
7714 * towards the first, as a result a collision should not be possible
7716 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7718 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7720 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7725 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7727 struct igb_adapter *adapter = netdev_priv(netdev);
7728 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7730 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7731 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7732 dev_info(&adapter->pdev->dev,
7733 "Reload the VF driver to make this change effective.");
7734 if (test_bit(__IGB_DOWN, &adapter->state)) {
7735 dev_warn(&adapter->pdev->dev,
7736 "The VF MAC address has been set, but the PF device is not up.\n");
7737 dev_warn(&adapter->pdev->dev,
7738 "Bring the PF device up before attempting to use the VF device.\n");
7740 return igb_set_vf_mac(adapter, vf, mac);
7743 static int igb_link_mbps(int internal_link_speed)
7745 switch (internal_link_speed) {
7755 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7762 /* Calculate the rate factor values to set */
7763 rf_int = link_speed / tx_rate;
7764 rf_dec = (link_speed - (rf_int * tx_rate));
7765 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7768 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7769 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7770 E1000_RTTBCNRC_RF_INT_MASK);
7771 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7776 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7777 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7778 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7780 wr32(E1000_RTTBCNRM, 0x14);
7781 wr32(E1000_RTTBCNRC, bcnrc_val);
7784 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7786 int actual_link_speed, i;
7787 bool reset_rate = false;
7789 /* VF TX rate limit was not set or not supported */
7790 if ((adapter->vf_rate_link_speed == 0) ||
7791 (adapter->hw.mac.type != e1000_82576))
7794 actual_link_speed = igb_link_mbps(adapter->link_speed);
7795 if (actual_link_speed != adapter->vf_rate_link_speed) {
7797 adapter->vf_rate_link_speed = 0;
7798 dev_info(&adapter->pdev->dev,
7799 "Link speed has been changed. VF Transmit rate is disabled\n");
7802 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7804 adapter->vf_data[i].tx_rate = 0;
7806 igb_set_vf_rate_limit(&adapter->hw, i,
7807 adapter->vf_data[i].tx_rate,
7812 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7813 int min_tx_rate, int max_tx_rate)
7815 struct igb_adapter *adapter = netdev_priv(netdev);
7816 struct e1000_hw *hw = &adapter->hw;
7817 int actual_link_speed;
7819 if (hw->mac.type != e1000_82576)
7825 actual_link_speed = igb_link_mbps(adapter->link_speed);
7826 if ((vf >= adapter->vfs_allocated_count) ||
7827 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7828 (max_tx_rate < 0) ||
7829 (max_tx_rate > actual_link_speed))
7832 adapter->vf_rate_link_speed = actual_link_speed;
7833 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7834 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7839 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7842 struct igb_adapter *adapter = netdev_priv(netdev);
7843 struct e1000_hw *hw = &adapter->hw;
7844 u32 reg_val, reg_offset;
7846 if (!adapter->vfs_allocated_count)
7849 if (vf >= adapter->vfs_allocated_count)
7852 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7853 reg_val = rd32(reg_offset);
7855 reg_val |= ((1 << vf) |
7856 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7858 reg_val &= ~((1 << vf) |
7859 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7860 wr32(reg_offset, reg_val);
7862 adapter->vf_data[vf].spoofchk_enabled = setting;
7866 static int igb_ndo_get_vf_config(struct net_device *netdev,
7867 int vf, struct ifla_vf_info *ivi)
7869 struct igb_adapter *adapter = netdev_priv(netdev);
7870 if (vf >= adapter->vfs_allocated_count)
7873 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7874 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7875 ivi->min_tx_rate = 0;
7876 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7877 ivi->qos = adapter->vf_data[vf].pf_qos;
7878 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7882 static void igb_vmm_control(struct igb_adapter *adapter)
7884 struct e1000_hw *hw = &adapter->hw;
7887 switch (hw->mac.type) {
7893 /* replication is not supported for 82575 */
7896 /* notify HW that the MAC is adding vlan tags */
7897 reg = rd32(E1000_DTXCTL);
7898 reg |= E1000_DTXCTL_VLAN_ADDED;
7899 wr32(E1000_DTXCTL, reg);
7902 /* enable replication vlan tag stripping */
7903 reg = rd32(E1000_RPLOLR);
7904 reg |= E1000_RPLOLR_STRVLAN;
7905 wr32(E1000_RPLOLR, reg);
7908 /* none of the above registers are supported by i350 */
7912 if (adapter->vfs_allocated_count) {
7913 igb_vmdq_set_loopback_pf(hw, true);
7914 igb_vmdq_set_replication_pf(hw, true);
7915 igb_vmdq_set_anti_spoofing_pf(hw, true,
7916 adapter->vfs_allocated_count);
7918 igb_vmdq_set_loopback_pf(hw, false);
7919 igb_vmdq_set_replication_pf(hw, false);
7923 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7925 struct e1000_hw *hw = &adapter->hw;
7929 if (hw->mac.type > e1000_82580) {
7930 if (adapter->flags & IGB_FLAG_DMAC) {
7933 /* force threshold to 0. */
7934 wr32(E1000_DMCTXTH, 0);
7936 /* DMA Coalescing high water mark needs to be greater
7937 * than the Rx threshold. Set hwm to PBA - max frame
7938 * size in 16B units, capping it at PBA - 6KB.
7940 hwm = 64 * pba - adapter->max_frame_size / 16;
7941 if (hwm < 64 * (pba - 6))
7942 hwm = 64 * (pba - 6);
7943 reg = rd32(E1000_FCRTC);
7944 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7945 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7946 & E1000_FCRTC_RTH_COAL_MASK);
7947 wr32(E1000_FCRTC, reg);
7949 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7950 * frame size, capping it at PBA - 10KB.
7952 dmac_thr = pba - adapter->max_frame_size / 512;
7953 if (dmac_thr < pba - 10)
7954 dmac_thr = pba - 10;
7955 reg = rd32(E1000_DMACR);
7956 reg &= ~E1000_DMACR_DMACTHR_MASK;
7957 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7958 & E1000_DMACR_DMACTHR_MASK);
7960 /* transition to L0x or L1 if available..*/
7961 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7963 /* watchdog timer= +-1000 usec in 32usec intervals */
7966 /* Disable BMC-to-OS Watchdog Enable */
7967 if (hw->mac.type != e1000_i354)
7968 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7970 wr32(E1000_DMACR, reg);
7972 /* no lower threshold to disable
7973 * coalescing(smart fifb)-UTRESH=0
7975 wr32(E1000_DMCRTRH, 0);
7977 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7979 wr32(E1000_DMCTLX, reg);
7981 /* free space in tx packet buffer to wake from
7984 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7985 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7987 /* make low power state decision controlled
7990 reg = rd32(E1000_PCIEMISC);
7991 reg &= ~E1000_PCIEMISC_LX_DECISION;
7992 wr32(E1000_PCIEMISC, reg);
7993 } /* endif adapter->dmac is not disabled */
7994 } else if (hw->mac.type == e1000_82580) {
7995 u32 reg = rd32(E1000_PCIEMISC);
7997 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7998 wr32(E1000_DMACR, 0);
8003 * igb_read_i2c_byte - Reads 8 bit word over I2C
8004 * @hw: pointer to hardware structure
8005 * @byte_offset: byte offset to read
8006 * @dev_addr: device address
8009 * Performs byte read operation over I2C interface at
8010 * a specified device address.
8012 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8013 u8 dev_addr, u8 *data)
8015 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8016 struct i2c_client *this_client = adapter->i2c_client;
8021 return E1000_ERR_I2C;
8023 swfw_mask = E1000_SWFW_PHY0_SM;
8025 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8026 return E1000_ERR_SWFW_SYNC;
8028 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8029 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8032 return E1000_ERR_I2C;
8040 * igb_write_i2c_byte - Writes 8 bit word over I2C
8041 * @hw: pointer to hardware structure
8042 * @byte_offset: byte offset to write
8043 * @dev_addr: device address
8044 * @data: value to write
8046 * Performs byte write operation over I2C interface at
8047 * a specified device address.
8049 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8050 u8 dev_addr, u8 data)
8052 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8053 struct i2c_client *this_client = adapter->i2c_client;
8055 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8058 return E1000_ERR_I2C;
8060 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8061 return E1000_ERR_SWFW_SYNC;
8062 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8063 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8066 return E1000_ERR_I2C;
8072 int igb_reinit_queues(struct igb_adapter *adapter)
8074 struct net_device *netdev = adapter->netdev;
8075 struct pci_dev *pdev = adapter->pdev;
8078 if (netif_running(netdev))
8081 igb_reset_interrupt_capability(adapter);
8083 if (igb_init_interrupt_scheme(adapter, true)) {
8084 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8088 if (netif_running(netdev))
8089 err = igb_open(netdev);