1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/bitops.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/cpumask.h>
36 #include <linux/aer.h>
37 #include <linux/if_vlan.h>
39 #ifdef CONFIG_IXGBE_PTP
40 #include <linux/clocksource.h>
41 #include <linux/net_tstamp.h>
42 #include <linux/ptp_clock_kernel.h>
43 #endif /* CONFIG_IXGBE_PTP */
45 #include "ixgbe_type.h"
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb.h"
48 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
50 #include "ixgbe_fcoe.h"
51 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
52 #ifdef CONFIG_IXGBE_DCA
53 #include <linux/dca.h>
56 /* common prefix used by pr_<> macros */
58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
60 /* TX/RX descriptor defines */
61 #define IXGBE_DEFAULT_TXD 512
62 #define IXGBE_DEFAULT_TX_WORK 256
63 #define IXGBE_MAX_TXD 4096
64 #define IXGBE_MIN_TXD 64
66 #define IXGBE_DEFAULT_RXD 512
67 #define IXGBE_MAX_RXD 4096
68 #define IXGBE_MIN_RXD 64
71 #define IXGBE_MIN_FCRTL 0x40
72 #define IXGBE_MAX_FCRTL 0x7FF80
73 #define IXGBE_MIN_FCRTH 0x600
74 #define IXGBE_MAX_FCRTH 0x7FFF0
75 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
76 #define IXGBE_MIN_FCPAUSE 0
77 #define IXGBE_MAX_FCPAUSE 0xFFFF
79 /* Supported Rx Buffer Sizes */
80 #define IXGBE_RXBUFFER_512 512 /* Used for packet split */
81 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
84 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
85 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
86 * this adds up to 512 bytes of extra data meaning the smallest allocation
87 * we could have is 1K.
88 * i.e. RXBUFFER_512 --> size-1024 slab
90 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
92 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
94 /* How many Rx Buffers do we bundle into one write to the hardware ? */
95 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
97 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
98 #define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1)
99 #define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2)
100 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 3)
101 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4)
102 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5)
103 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 6)
104 #define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7)
105 #define IXGBE_TX_FLAGS_TSTAMP (u32)(1 << 8)
106 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
107 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
108 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
109 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
111 #define IXGBE_MAX_VF_MC_ENTRIES 30
112 #define IXGBE_MAX_VF_FUNCTIONS 64
113 #define IXGBE_MAX_VFTA_ENTRIES 128
114 #define MAX_EMULATION_MAC_ADDRS 16
115 #define IXGBE_MAX_PF_MACVLANS 15
116 #define VMDQ_P(p) ((p) + adapter->num_vfs)
117 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
118 #define IXGBE_X540_VF_DEVICE_ID 0x1515
120 struct vf_data_storage {
121 unsigned char vf_mac_addresses[ETH_ALEN];
122 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
123 u16 num_vf_mc_hashes;
124 u16 default_vf_vlan_id;
128 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
133 struct pci_dev *vfdev;
142 u8 vf_macvlan[ETH_ALEN];
145 #define IXGBE_MAX_TXD_PWR 14
146 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
148 /* Tx Descriptors needed, worst case */
149 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
150 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
152 /* wrapper around a pointer to a socket buffer,
153 * so a DMA handle can be stored along with the buffer */
154 struct ixgbe_tx_buffer {
155 union ixgbe_adv_tx_desc *next_to_watch;
156 unsigned long time_stamp;
158 unsigned int bytecount;
159 unsigned short gso_segs;
161 DEFINE_DMA_UNMAP_ADDR(dma);
162 DEFINE_DMA_UNMAP_LEN(len);
166 struct ixgbe_rx_buffer {
170 unsigned int page_offset;
173 struct ixgbe_queue_stats {
178 struct ixgbe_tx_queue_stats {
184 struct ixgbe_rx_queue_stats {
188 u64 alloc_rx_page_failed;
189 u64 alloc_rx_buff_failed;
193 enum ixgbe_ring_state_t {
194 __IXGBE_TX_FDIR_INIT_DONE,
195 __IXGBE_TX_DETECT_HANG,
196 __IXGBE_HANG_CHECK_ARMED,
197 __IXGBE_RX_RSC_ENABLED,
198 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
199 __IXGBE_RX_FCOE_BUFSZ,
202 #define check_for_tx_hang(ring) \
203 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
204 #define set_check_for_tx_hang(ring) \
205 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
206 #define clear_check_for_tx_hang(ring) \
207 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
208 #define ring_is_rsc_enabled(ring) \
209 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
210 #define set_ring_rsc_enabled(ring) \
211 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
212 #define clear_ring_rsc_enabled(ring) \
213 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
215 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
216 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
217 struct net_device *netdev; /* netdev ring belongs to */
218 struct device *dev; /* device for DMA mapping */
219 void *desc; /* descriptor ring memory */
221 struct ixgbe_tx_buffer *tx_buffer_info;
222 struct ixgbe_rx_buffer *rx_buffer_info;
226 dma_addr_t dma; /* phys. address of descriptor ring */
227 unsigned int size; /* length in bytes */
229 u16 count; /* amount of descriptors */
231 u8 queue_index; /* needed for multiqueue queue management */
232 u8 reg_idx; /* holds the special value that gets
233 * the hardware register offset
234 * associated with this ring, which is
235 * different for DCB and RSS modes
249 struct ixgbe_queue_stats stats;
250 struct u64_stats_sync syncp;
252 struct ixgbe_tx_queue_stats tx_stats;
253 struct ixgbe_rx_queue_stats rx_stats;
255 } ____cacheline_internodealigned_in_smp;
257 enum ixgbe_ring_f_enum {
259 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
264 #endif /* IXGBE_FCOE */
266 RING_F_ARRAY_SIZE /* must be last in enum set */
269 #define IXGBE_MAX_RSS_INDICES 16
270 #define IXGBE_MAX_VMDQ_INDICES 64
271 #define IXGBE_MAX_FDIR_INDICES 64
273 #define IXGBE_MAX_FCOE_INDICES 8
274 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
275 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
277 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
278 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
279 #endif /* IXGBE_FCOE */
280 struct ixgbe_ring_feature {
283 } ____cacheline_internodealigned_in_smp;
286 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
287 * this is twice the size of a half page we need to double the page order
288 * for FCoE enabled Rx queues.
290 #if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)
291 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
293 return test_bit(__IXGBE_RX_FCOE_BUFSZ, &ring->state) ? 1 : 0;
296 #define ixgbe_rx_pg_order(_ring) 0
298 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
299 #define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring))
301 struct ixgbe_ring_container {
302 struct ixgbe_ring *ring; /* pointer to linked list of rings */
303 unsigned int total_bytes; /* total bytes processed this int */
304 unsigned int total_packets; /* total packets processed this int */
305 u16 work_limit; /* total work allowed per interrupt */
306 u8 count; /* total number of rings in vector */
307 u8 itr; /* current ITR setting for ring */
310 /* iterator for handling rings in ring container */
311 #define ixgbe_for_each_ring(pos, head) \
312 for (pos = (head).ring; pos != NULL; pos = pos->next)
314 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
316 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
318 /* MAX_MSIX_Q_VECTORS of these are allocated,
319 * but we only use one per queue-specific vector.
321 struct ixgbe_q_vector {
322 struct ixgbe_adapter *adapter;
323 #ifdef CONFIG_IXGBE_DCA
324 int cpu; /* CPU for DCA */
326 u16 v_idx; /* index of q_vector within array, also used for
327 * finding the bit in EICR and friends that
328 * represents the vector for this ring */
329 u16 itr; /* Interrupt throttle rate written to EITR */
330 struct ixgbe_ring_container rx, tx;
332 struct napi_struct napi;
333 cpumask_t affinity_mask;
335 struct rcu_head rcu; /* to avoid race with update stats on free */
336 char name[IFNAMSIZ + 9];
338 /* for dynamic allocation of rings associated with this q_vector */
339 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
341 #ifdef CONFIG_IXGBE_HWMON
343 #define IXGBE_HWMON_TYPE_LOC 0
344 #define IXGBE_HWMON_TYPE_TEMP 1
345 #define IXGBE_HWMON_TYPE_CAUTION 2
346 #define IXGBE_HWMON_TYPE_MAX 3
349 struct device_attribute dev_attr;
351 struct ixgbe_thermal_diode_data *sensor;
356 struct device *device;
357 struct hwmon_attr *hwmon_list;
358 unsigned int n_hwmon;
360 #endif /* CONFIG_IXGBE_HWMON */
363 * microsecond values for various ITR rates shifted by 2 to fit itr register
364 * with the first 3 bits reserved 0
366 #define IXGBE_MIN_RSC_ITR 24
367 #define IXGBE_100K_ITR 40
368 #define IXGBE_20K_ITR 200
369 #define IXGBE_10K_ITR 400
370 #define IXGBE_8K_ITR 500
372 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
373 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
374 const u32 stat_err_bits)
376 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
379 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
381 u16 ntc = ring->next_to_clean;
382 u16 ntu = ring->next_to_use;
384 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
387 #define IXGBE_RX_DESC(R, i) \
388 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
389 #define IXGBE_TX_DESC(R, i) \
390 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
391 #define IXGBE_TX_CTXTDESC(R, i) \
392 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
394 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
396 /* Use 3K as the baby jumbo frame size for FCoE */
397 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
398 #endif /* IXGBE_FCOE */
400 #define OTHER_VECTOR 1
401 #define NON_Q_VECTORS (OTHER_VECTOR)
403 #define MAX_MSIX_VECTORS_82599 64
404 #define MAX_MSIX_Q_VECTORS_82599 64
405 #define MAX_MSIX_VECTORS_82598 18
406 #define MAX_MSIX_Q_VECTORS_82598 16
408 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
409 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
411 #define MIN_MSIX_Q_VECTORS 1
412 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
414 /* default to trying for four seconds */
415 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
417 /* board specific private data structure */
418 struct ixgbe_adapter {
419 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
420 /* OS defined structs */
421 struct net_device *netdev;
422 struct pci_dev *pdev;
426 /* Some features need tri-state capability,
427 * thus the additional *_CAPABLE flags.
430 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
431 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
432 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
433 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
434 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
435 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
436 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
437 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
438 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
439 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
440 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
441 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
442 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
443 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
444 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
445 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
446 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
447 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
448 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
449 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
450 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
451 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
452 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
453 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
454 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
455 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
458 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
459 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
460 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
461 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
462 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
463 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
464 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
465 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
466 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
467 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
468 #define IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED (u32)(1 << 10)
469 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 11)
471 /* Tx fast path data */
476 /* Rx fast path data */
481 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
485 u32 tx_timeout_count;
488 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
489 int num_rx_pools; /* == num_rx_queues in 82598 */
490 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
491 u64 hw_csum_rx_error;
492 u64 hw_rx_no_dma_resources;
496 u32 alloc_rx_page_failed;
497 u32 alloc_rx_buff_failed;
499 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
502 struct ieee_pfc *ixgbe_ieee_pfc;
503 struct ieee_ets *ixgbe_ieee_ets;
504 struct ixgbe_dcb_config dcb_cfg;
505 struct ixgbe_dcb_config temp_dcb_cfg;
508 enum ixgbe_fc_mode last_lfc_mode;
510 int num_msix_vectors;
511 int max_msix_q_vectors; /* true count of q_vectors for device */
512 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
513 struct msix_entry *msix_entries;
516 struct ixgbe_ring test_tx_ring;
517 struct ixgbe_ring test_rx_ring;
519 /* structs defined in ixgbe_hw.h */
522 struct ixgbe_hw_stats stats;
525 unsigned int tx_ring_count;
526 unsigned int rx_ring_count;
530 unsigned long link_check_timeout;
532 struct timer_list service_timer;
533 struct work_struct service_task;
535 struct hlist_head fdir_filter_list;
536 unsigned long fdir_overflow; /* number of times ATR was backed off */
537 union ixgbe_atr_input fdir_mask;
538 int fdir_filter_count;
541 spinlock_t fdir_perfect_lock;
544 struct ixgbe_fcoe fcoe;
545 #endif /* IXGBE_FCOE */
557 #ifdef CONFIG_IXGBE_PTP
558 struct ptp_clock *ptp_clock;
559 struct ptp_clock_info ptp_caps;
560 unsigned long last_overflow_check;
561 spinlock_t tmreg_lock;
562 struct cyclecounter cc;
563 struct timecounter tc;
566 #endif /* CONFIG_IXGBE_PTP */
569 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
570 unsigned int num_vfs;
571 struct vf_data_storage *vfinfo;
572 int vf_rate_link_speed;
573 struct vf_macvlans vf_mvs;
574 struct vf_macvlans *mv_list;
576 u32 timer_event_accumulator;
578 struct kobject *info_kobj;
579 #ifdef CONFIG_IXGBE_HWMON
580 struct hwmon_buff ixgbe_hwmon_buff;
581 #endif /* CONFIG_IXGBE_HWMON */
584 struct ixgbe_fdir_filter {
585 struct hlist_node fdir_node;
586 union ixgbe_atr_input filter;
595 __IXGBE_SERVICE_SCHED,
600 union { /* Union defining head/tail partner */
601 struct sk_buff *head;
602 struct sk_buff *tail;
608 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
616 extern struct ixgbe_info ixgbe_82598_info;
617 extern struct ixgbe_info ixgbe_82599_info;
618 extern struct ixgbe_info ixgbe_X540_info;
619 #ifdef CONFIG_IXGBE_DCB
620 extern const struct dcbnl_rtnl_ops dcbnl_ops;
623 extern char ixgbe_driver_name[];
624 extern const char ixgbe_driver_version[];
626 extern char ixgbe_default_device_descr[];
627 #endif /* IXGBE_FCOE */
629 extern void ixgbe_up(struct ixgbe_adapter *adapter);
630 extern void ixgbe_down(struct ixgbe_adapter *adapter);
631 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
632 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
633 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
634 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
635 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
636 extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
637 extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
638 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
639 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
640 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
641 struct ixgbe_ring *);
642 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
643 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
644 extern int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
646 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
647 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
648 struct ixgbe_adapter *,
649 struct ixgbe_ring *);
650 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
651 struct ixgbe_tx_buffer *);
652 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
653 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
654 extern int ixgbe_poll(struct napi_struct *napi, int budget);
655 extern int ethtool_ioctl(struct ifreq *ifr);
656 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
657 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
658 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
659 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
660 union ixgbe_atr_hash_dword input,
661 union ixgbe_atr_hash_dword common,
663 extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
664 union ixgbe_atr_input *input_mask);
665 extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
666 union ixgbe_atr_input *input,
667 u16 soft_id, u8 queue);
668 extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
669 union ixgbe_atr_input *input,
671 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
672 union ixgbe_atr_input *mask);
673 extern void ixgbe_set_rx_mode(struct net_device *netdev);
674 #ifdef CONFIG_IXGBE_DCB
675 extern void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
676 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
678 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
679 extern void ixgbe_do_reset(struct net_device *netdev);
680 #ifdef CONFIG_IXGBE_HWMON
681 extern void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
682 extern int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
683 #endif /* CONFIG_IXGBE_HWMON */
685 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
686 extern int ixgbe_fso(struct ixgbe_ring *tx_ring,
687 struct ixgbe_tx_buffer *first,
689 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
690 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
691 union ixgbe_adv_rx_desc *rx_desc,
692 struct sk_buff *skb);
693 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
694 struct scatterlist *sgl, unsigned int sgc);
695 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
696 struct scatterlist *sgl, unsigned int sgc);
697 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
698 extern int ixgbe_fcoe_enable(struct net_device *netdev);
699 extern int ixgbe_fcoe_disable(struct net_device *netdev);
700 #ifdef CONFIG_IXGBE_DCB
701 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
702 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
703 #endif /* CONFIG_IXGBE_DCB */
704 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
705 extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
706 struct netdev_fcoe_hbainfo *info);
707 #endif /* IXGBE_FCOE */
709 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
711 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
714 #ifdef CONFIG_IXGBE_PTP
715 extern void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
716 extern void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
717 extern void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
718 extern void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector,
719 struct sk_buff *skb);
720 extern void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector,
721 struct sk_buff *skb);
722 extern int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
723 struct ifreq *ifr, int cmd);
724 extern void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
725 extern void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
726 #endif /* CONFIG_IXGBE_PTP */
728 #endif /* _IXGBE_H_ */