1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
35 #define IXGBE_82598_MAX_TX_QUEUES 32
36 #define IXGBE_82598_MAX_RX_QUEUES 64
37 #define IXGBE_82598_RAR_ENTRIES 16
38 #define IXGBE_82598_MC_TBL_SIZE 128
39 #define IXGBE_82598_VFT_TBL_SIZE 128
40 #define IXGBE_82598_RX_PB_SIZE 512
42 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
43 ixgbe_link_speed speed,
45 bool autoneg_wait_to_complete);
46 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
50 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
51 * @hw: pointer to the HW structure
53 * The defaults for 82598 should be in the range of 50us to 50ms,
54 * however the hardware default for these parts is 500us to 1ms which is less
55 * than the 10ms recommended by the pci-e spec. To address this we need to
56 * increase the value to either 10ms to 250ms for capability version 1 config,
57 * or 16ms to 55ms for version 2.
59 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
61 struct ixgbe_adapter *adapter = hw->back;
62 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
65 /* only take action if timeout value is defaulted to 0 */
66 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
70 * if capababilities version is type 1 we can write the
71 * timeout of 10ms to 250ms through the GCR register
73 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
74 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
79 * for version 2 capabilities we need to write the config space
80 * directly in order to set the completion timeout value for
83 pci_read_config_word(adapter->pdev,
84 IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2);
85 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
86 pci_write_config_word(adapter->pdev,
87 IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
89 /* disable completion timeout resend */
90 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
91 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
94 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
96 struct ixgbe_mac_info *mac = &hw->mac;
98 /* Call PHY identify routine to get the phy type */
99 ixgbe_identify_phy_generic(hw);
101 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
102 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
103 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
104 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
105 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
106 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
112 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
113 * @hw: pointer to hardware structure
115 * Initialize any function pointers that were not able to be
116 * set during get_invariants because the PHY/SFP type was
117 * not known. Perform the SFP init if necessary.
120 static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
122 struct ixgbe_mac_info *mac = &hw->mac;
123 struct ixgbe_phy_info *phy = &hw->phy;
125 u16 list_offset, data_offset;
127 /* Identify the PHY */
128 phy->ops.identify(hw);
130 /* Overwrite the link function pointers if copper PHY */
131 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
132 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
133 mac->ops.get_link_capabilities =
134 &ixgbe_get_copper_link_capabilities_generic;
137 switch (hw->phy.type) {
139 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
140 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
141 phy->ops.get_firmware_version =
142 &ixgbe_get_phy_firmware_version_tnx;
145 phy->ops.reset = &ixgbe_reset_phy_nl;
147 /* Call SFP+ identify routine to get the SFP+ module type */
148 ret_val = phy->ops.identify_sfp(hw);
151 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
152 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
156 /* Check to see if SFP+ module is supported */
157 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
161 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
174 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
175 * @hw: pointer to hardware structure
177 * Starts the hardware using the generic start_hw function.
178 * Disables relaxed ordering Then set pcie completion timeout
181 static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
187 ret_val = ixgbe_start_hw_generic(hw);
189 /* Disable relaxed ordering */
190 for (i = 0; ((i < hw->mac.max_tx_queues) &&
191 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
192 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
193 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
194 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
197 for (i = 0; ((i < hw->mac.max_rx_queues) &&
198 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
199 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
200 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
201 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
202 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
205 hw->mac.rx_pb_size = IXGBE_82598_RX_PB_SIZE;
207 /* set the completion timeout for interface */
209 ixgbe_set_pcie_completion_timeout(hw);
215 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
216 * @hw: pointer to hardware structure
217 * @speed: pointer to link speed
218 * @autoneg: boolean auto-negotiation value
220 * Determines the link capabilities by reading the AUTOC register.
222 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
223 ixgbe_link_speed *speed,
230 * Determine link capabilities based on the stored value of AUTOC,
231 * which represents EEPROM defaults. If AUTOC value has not been
232 * stored, use the current register value.
234 if (hw->mac.orig_link_settings_stored)
235 autoc = hw->mac.orig_autoc;
237 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
239 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
240 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
241 *speed = IXGBE_LINK_SPEED_1GB_FULL;
245 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
246 *speed = IXGBE_LINK_SPEED_10GB_FULL;
250 case IXGBE_AUTOC_LMS_1G_AN:
251 *speed = IXGBE_LINK_SPEED_1GB_FULL;
255 case IXGBE_AUTOC_LMS_KX4_AN:
256 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
257 *speed = IXGBE_LINK_SPEED_UNKNOWN;
258 if (autoc & IXGBE_AUTOC_KX4_SUPP)
259 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
260 if (autoc & IXGBE_AUTOC_KX_SUPP)
261 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
266 status = IXGBE_ERR_LINK_SETUP;
274 * ixgbe_get_media_type_82598 - Determines media type
275 * @hw: pointer to hardware structure
277 * Returns the media type (fiber, copper, backplane)
279 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
281 enum ixgbe_media_type media_type;
283 /* Detect if there is a copper PHY attached. */
284 switch (hw->phy.type) {
285 case ixgbe_phy_cu_unknown:
287 media_type = ixgbe_media_type_copper;
293 /* Media type for I82598 is based on device ID */
294 switch (hw->device_id) {
295 case IXGBE_DEV_ID_82598:
296 case IXGBE_DEV_ID_82598_BX:
297 /* Default device ID is mezzanine card KX/KX4 */
298 media_type = ixgbe_media_type_backplane;
300 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
301 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
302 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
303 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
304 case IXGBE_DEV_ID_82598EB_XF_LR:
305 case IXGBE_DEV_ID_82598EB_SFP_LOM:
306 media_type = ixgbe_media_type_fiber;
308 case IXGBE_DEV_ID_82598EB_CX4:
309 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
310 media_type = ixgbe_media_type_cx4;
312 case IXGBE_DEV_ID_82598AT:
313 case IXGBE_DEV_ID_82598AT2:
314 media_type = ixgbe_media_type_copper;
317 media_type = ixgbe_media_type_unknown;
325 * ixgbe_fc_enable_82598 - Enable flow control
326 * @hw: pointer to hardware structure
327 * @packetbuf_num: packet buffer number (0-7)
329 * Enable flow control according to the current settings.
331 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
341 if (hw->fc.requested_mode == ixgbe_fc_pfc)
344 #endif /* CONFIG_DCB */
346 * On 82598 having Rx FC on causes resets while doing 1G
347 * so if it's on turn it off once we know link_speed. For
348 * more details see 82598 Specification update.
350 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
351 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
352 switch (hw->fc.requested_mode) {
354 hw->fc.requested_mode = ixgbe_fc_tx_pause;
356 case ixgbe_fc_rx_pause:
357 hw->fc.requested_mode = ixgbe_fc_none;
365 /* Negotiate the fc mode to use */
366 ret_val = ixgbe_fc_autoneg(hw);
367 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
370 /* Disable any previous flow control settings */
371 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
372 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
374 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
375 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
378 * The possible values of fc.current_mode are:
379 * 0: Flow control is completely disabled
380 * 1: Rx flow control is enabled (we can receive pause frames,
381 * but not send pause frames).
382 * 2: Tx flow control is enabled (we can send pause frames but
383 * we do not support receiving pause frames).
384 * 3: Both Rx and Tx flow control (symmetric) are enabled.
386 * 4: Priority Flow Control is enabled.
390 switch (hw->fc.current_mode) {
393 * Flow control is disabled by software override or autoneg.
394 * The code below will actually disable it in the HW.
397 case ixgbe_fc_rx_pause:
399 * Rx Flow control is enabled and Tx Flow control is
400 * disabled by software override. Since there really
401 * isn't a way to advertise that we are capable of RX
402 * Pause ONLY, we will advertise that we support both
403 * symmetric and asymmetric Rx PAUSE. Later, we will
404 * disable the adapter's ability to send PAUSE frames.
406 fctrl_reg |= IXGBE_FCTRL_RFCE;
408 case ixgbe_fc_tx_pause:
410 * Tx Flow control is enabled, and Rx Flow control is
411 * disabled by software override.
413 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
416 /* Flow control (both Rx and Tx) is enabled by SW override. */
417 fctrl_reg |= IXGBE_FCTRL_RFCE;
418 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
424 #endif /* CONFIG_DCB */
426 hw_dbg(hw, "Flow control param set incorrectly\n");
427 ret_val = IXGBE_ERR_CONFIG;
432 /* Set 802.3x based flow control settings. */
433 fctrl_reg |= IXGBE_FCTRL_DPF;
434 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
435 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
437 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
438 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
439 reg = hw->fc.low_water << 6;
441 reg |= IXGBE_FCRTL_XONE;
443 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
445 reg = hw->fc.high_water[packetbuf_num] << 6;
446 reg |= IXGBE_FCRTH_FCEN;
448 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
451 /* Configure pause time (2 TCs per register) */
452 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
453 if ((packetbuf_num & 1) == 0)
454 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
456 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
457 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
459 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
466 * ixgbe_start_mac_link_82598 - Configures MAC link settings
467 * @hw: pointer to hardware structure
469 * Configures link settings based on values in the ixgbe_hw struct.
470 * Restarts the link. Performs autonegotiation if needed.
472 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
473 bool autoneg_wait_to_complete)
481 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
482 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
483 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
485 /* Only poll for autoneg to complete if specified to do so */
486 if (autoneg_wait_to_complete) {
487 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
488 IXGBE_AUTOC_LMS_KX4_AN ||
489 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
490 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
491 links_reg = 0; /* Just in case Autoneg time = 0 */
492 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
493 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
494 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
498 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
499 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
500 hw_dbg(hw, "Autonegotiation did not complete.\n");
505 /* Add delay to filter out noises during initial link setup */
512 * ixgbe_validate_link_ready - Function looks for phy link
513 * @hw: pointer to hardware structure
515 * Function indicates success when phy link is available. If phy is not ready
516 * within 5 seconds of MAC indicating link, the function returns error.
518 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
523 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
527 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
528 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
530 if ((an_reg & MDIO_AN_STAT1_COMPLETE) &&
531 (an_reg & MDIO_STAT1_LSTATUS))
537 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
538 hw_dbg(hw, "Link was indicated but link is down\n");
539 return IXGBE_ERR_LINK_SETUP;
546 * ixgbe_check_mac_link_82598 - Get link/speed status
547 * @hw: pointer to hardware structure
548 * @speed: pointer to link speed
549 * @link_up: true is link is up, false otherwise
550 * @link_up_wait_to_complete: bool used to wait for link up or not
552 * Reads the links register to determine if link is up and the current speed
554 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
555 ixgbe_link_speed *speed, bool *link_up,
556 bool link_up_wait_to_complete)
560 u16 link_reg, adapt_comp_reg;
563 * SERDES PHY requires us to read link status from register 0xC79F.
564 * Bit 0 set indicates link is up/ready; clear indicates link down.
565 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
566 * clear indicates active; set indicates inactive.
568 if (hw->phy.type == ixgbe_phy_nl) {
569 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
570 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
571 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
573 if (link_up_wait_to_complete) {
574 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
575 if ((link_reg & 1) &&
576 ((adapt_comp_reg & 1) == 0)) {
583 hw->phy.ops.read_reg(hw, 0xC79F,
586 hw->phy.ops.read_reg(hw, 0xC00C,
591 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
601 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
602 if (link_up_wait_to_complete) {
603 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
604 if (links_reg & IXGBE_LINKS_UP) {
611 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
614 if (links_reg & IXGBE_LINKS_UP)
620 if (links_reg & IXGBE_LINKS_SPEED)
621 *speed = IXGBE_LINK_SPEED_10GB_FULL;
623 *speed = IXGBE_LINK_SPEED_1GB_FULL;
625 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up &&
626 (ixgbe_validate_link_ready(hw) != 0))
634 * ixgbe_setup_mac_link_82598 - Set MAC link speed
635 * @hw: pointer to hardware structure
636 * @speed: new link speed
637 * @autoneg: true if auto-negotiation enabled
638 * @autoneg_wait_to_complete: true when waiting for completion is needed
640 * Set the link speed in the AUTOC register and restarts link.
642 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
643 ixgbe_link_speed speed, bool autoneg,
644 bool autoneg_wait_to_complete)
647 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
648 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
649 u32 autoc = curr_autoc;
650 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
652 /* Check to see if speed passed in is supported. */
653 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
654 speed &= link_capabilities;
656 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
657 status = IXGBE_ERR_LINK_SETUP;
659 /* Set KX4/KX support according to speed requested */
660 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
661 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
662 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
663 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
664 autoc |= IXGBE_AUTOC_KX4_SUPP;
665 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
666 autoc |= IXGBE_AUTOC_KX_SUPP;
667 if (autoc != curr_autoc)
668 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
673 * Setup and restart the link based on the new values in
674 * ixgbe_hw This will write the AUTOC register based on the new
677 status = ixgbe_start_mac_link_82598(hw,
678 autoneg_wait_to_complete);
686 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
687 * @hw: pointer to hardware structure
688 * @speed: new link speed
689 * @autoneg: true if autonegotiation enabled
690 * @autoneg_wait_to_complete: true if waiting is needed to complete
692 * Sets the link speed in the AUTOC register in the MAC and restarts link.
694 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
695 ixgbe_link_speed speed,
697 bool autoneg_wait_to_complete)
701 /* Setup the PHY according to input speed */
702 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
703 autoneg_wait_to_complete);
705 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
711 * ixgbe_reset_hw_82598 - Performs hardware reset
712 * @hw: pointer to hardware structure
714 * Resets the hardware by resetting the transmit and receive units, masks and
715 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
718 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
728 /* Call adapter stop to disable tx/rx and clear interrupts */
729 status = hw->mac.ops.stop_adapter(hw);
734 * Power up the Atlas Tx lanes if they are currently powered down.
735 * Atlas Tx lanes are powered down for MAC loopback tests, but
736 * they are not automatically restored on reset.
738 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
739 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
740 /* Enable Tx Atlas so packets can be transmitted again */
741 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
743 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
744 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
747 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
749 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
750 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
753 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
755 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
756 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
759 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
761 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
762 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
767 if (hw->phy.reset_disable == false) {
768 /* PHY ops must be identified and initialized prior to reset */
770 /* Init PHY and function pointers, perform SFP setup */
771 phy_status = hw->phy.ops.init(hw);
772 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
774 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
777 hw->phy.ops.reset(hw);
782 * Issue global reset to the MAC. This needs to be a SW reset.
783 * If link reset is used, it might reset the MAC when mng is using it
785 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
786 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
787 IXGBE_WRITE_FLUSH(hw);
789 /* Poll for reset bit to self-clear indicating reset is complete */
790 for (i = 0; i < 10; i++) {
792 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
793 if (!(ctrl & IXGBE_CTRL_RST))
796 if (ctrl & IXGBE_CTRL_RST) {
797 status = IXGBE_ERR_RESET_FAILED;
798 hw_dbg(hw, "Reset polling failed to complete.\n");
804 * Double resets are required for recovery from certain error
805 * conditions. Between resets, it is necessary to stall to allow time
806 * for any pending HW events to complete.
808 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
809 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
813 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
814 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
815 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
818 * Store the original AUTOC value if it has not been
819 * stored off yet. Otherwise restore the stored original
820 * AUTOC value since the reset operation sets back to deaults.
822 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
823 if (hw->mac.orig_link_settings_stored == false) {
824 hw->mac.orig_autoc = autoc;
825 hw->mac.orig_link_settings_stored = true;
826 } else if (autoc != hw->mac.orig_autoc) {
827 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
830 /* Store the permanent mac address */
831 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
834 * Store MAC address from RAR0, clear receive address registers, and
835 * clear the multicast table
837 hw->mac.ops.init_rx_addrs(hw);
847 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
848 * @hw: pointer to hardware struct
849 * @rar: receive address register index to associate with a VMDq index
850 * @vmdq: VMDq set index
852 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
855 u32 rar_entries = hw->mac.num_rar_entries;
857 /* Make sure we are using a valid rar index range */
858 if (rar >= rar_entries) {
859 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
860 return IXGBE_ERR_INVALID_ARGUMENT;
863 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
864 rar_high &= ~IXGBE_RAH_VIND_MASK;
865 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
866 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
871 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
872 * @hw: pointer to hardware struct
873 * @rar: receive address register index to associate with a VMDq index
874 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
876 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
879 u32 rar_entries = hw->mac.num_rar_entries;
882 /* Make sure we are using a valid rar index range */
883 if (rar >= rar_entries) {
884 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
885 return IXGBE_ERR_INVALID_ARGUMENT;
888 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
889 if (rar_high & IXGBE_RAH_VIND_MASK) {
890 rar_high &= ~IXGBE_RAH_VIND_MASK;
891 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
898 * ixgbe_set_vfta_82598 - Set VLAN filter table
899 * @hw: pointer to hardware structure
900 * @vlan: VLAN id to write to VLAN filter
901 * @vind: VMDq output index that maps queue to VLAN id in VFTA
902 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
904 * Turn on/off specified VLAN in the VLAN filter table.
906 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
915 return IXGBE_ERR_PARAM;
917 /* Determine 32-bit word position in array */
918 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
920 /* Determine the location of the (VMD) queue index */
921 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
922 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
924 /* Set the nibble for VMD queue index */
925 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
926 bits &= (~(0x0F << bitindex));
927 bits |= (vind << bitindex);
928 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
930 /* Determine the location of the bit for this VLAN id */
931 bitindex = vlan & 0x1F; /* lower five bits */
933 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
935 /* Turn on this VLAN id */
936 bits |= (1 << bitindex);
938 /* Turn off this VLAN id */
939 bits &= ~(1 << bitindex);
940 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
946 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
947 * @hw: pointer to hardware structure
949 * Clears the VLAN filer table, and the VMDq index associated with the filter
951 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
956 for (offset = 0; offset < hw->mac.vft_size; offset++)
957 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
959 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
960 for (offset = 0; offset < hw->mac.vft_size; offset++)
961 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
968 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
969 * @hw: pointer to hardware structure
970 * @reg: analog register to read
973 * Performs read operation to Atlas analog register specified.
975 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
979 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
980 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
981 IXGBE_WRITE_FLUSH(hw);
983 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
984 *val = (u8)atlas_ctl;
990 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
991 * @hw: pointer to hardware structure
992 * @reg: atlas register to write
993 * @val: value to write
995 * Performs write operation to Atlas analog register specified.
997 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1001 atlas_ctl = (reg << 8) | val;
1002 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1003 IXGBE_WRITE_FLUSH(hw);
1010 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1011 * @hw: pointer to hardware structure
1012 * @byte_offset: EEPROM byte offset to read
1013 * @eeprom_data: value read
1015 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1017 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1026 if (hw->phy.type == ixgbe_phy_nl) {
1028 * phy SDA/SCL registers are at addresses 0xC30A to
1029 * 0xC30D. These registers are used to talk to the SFP+
1030 * module's EEPROM through the SDA/SCL (I2C) interface.
1032 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1033 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1034 hw->phy.ops.write_reg(hw,
1035 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1040 for (i = 0; i < 100; i++) {
1041 hw->phy.ops.read_reg(hw,
1042 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1045 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1046 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1048 usleep_range(10000, 20000);
1051 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1052 hw_dbg(hw, "EEPROM read did not pass.\n");
1053 status = IXGBE_ERR_SFP_NOT_PRESENT;
1058 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1059 MDIO_MMD_PMAPMD, &sfp_data);
1061 *eeprom_data = (u8)(sfp_data >> 8);
1063 status = IXGBE_ERR_PHY;
1072 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1073 * @hw: pointer to hardware structure
1075 * Determines physical layer capabilities of the current configuration.
1077 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1079 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1080 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1081 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1082 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1083 u16 ext_ability = 0;
1085 hw->phy.ops.identify(hw);
1087 /* Copper PHY must be checked before AUTOC LMS to determine correct
1088 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1089 switch (hw->phy.type) {
1091 case ixgbe_phy_cu_unknown:
1092 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE,
1093 MDIO_MMD_PMAPMD, &ext_ability);
1094 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1095 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1096 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1097 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1098 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1099 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1105 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1106 case IXGBE_AUTOC_LMS_1G_AN:
1107 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1108 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1109 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1111 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1113 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1114 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1115 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1116 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1117 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1119 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1121 case IXGBE_AUTOC_LMS_KX4_AN:
1122 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1123 if (autoc & IXGBE_AUTOC_KX_SUPP)
1124 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1125 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1126 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1132 if (hw->phy.type == ixgbe_phy_nl) {
1133 hw->phy.ops.identify_sfp(hw);
1135 switch (hw->phy.sfp_type) {
1136 case ixgbe_sfp_type_da_cu:
1137 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1139 case ixgbe_sfp_type_sr:
1140 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1142 case ixgbe_sfp_type_lr:
1143 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1146 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1151 switch (hw->device_id) {
1152 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1153 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1155 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1156 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1157 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1158 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1160 case IXGBE_DEV_ID_82598EB_XF_LR:
1161 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1168 return physical_layer;
1172 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1174 * @hw: pointer to the HW structure
1176 * Calls common function and corrects issue with some single port devices
1177 * that enable LAN1 but not LAN0.
1179 static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1181 struct ixgbe_bus_info *bus = &hw->bus;
1185 ixgbe_set_lan_id_multi_port_pcie(hw);
1187 /* check if LAN0 is disabled */
1188 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1189 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1191 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1193 /* if LAN0 is completely disabled force function to 0 */
1194 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1195 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1196 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1204 * ixgbe_set_rxpba_82598 - Configure packet buffers
1205 * @hw: pointer to hardware structure
1206 * @dcb_config: pointer to ixgbe_dcb_config structure
1208 * Configure packet buffers.
1210 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, u32 headroom,
1213 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1219 /* Setup Rx packet buffer sizes */
1221 case PBA_STRATEGY_WEIGHTED:
1222 /* Setup the first four at 80KB */
1223 rxpktsize = IXGBE_RXPBSIZE_80KB;
1225 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1226 /* Setup the last four at 48KB...don't re-init i */
1227 rxpktsize = IXGBE_RXPBSIZE_48KB;
1229 case PBA_STRATEGY_EQUAL:
1231 /* Divide the remaining Rx packet buffer evenly among the TCs */
1232 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1233 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1237 /* Setup Tx packet buffer sizes */
1238 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1239 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1244 static struct ixgbe_mac_operations mac_ops_82598 = {
1245 .init_hw = &ixgbe_init_hw_generic,
1246 .reset_hw = &ixgbe_reset_hw_82598,
1247 .start_hw = &ixgbe_start_hw_82598,
1248 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1249 .get_media_type = &ixgbe_get_media_type_82598,
1250 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1251 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
1252 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1253 .stop_adapter = &ixgbe_stop_adapter_generic,
1254 .get_bus_info = &ixgbe_get_bus_info_generic,
1255 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598,
1256 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1257 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1258 .setup_link = &ixgbe_setup_mac_link_82598,
1259 .set_rxpba = &ixgbe_set_rxpba_82598,
1260 .check_link = &ixgbe_check_mac_link_82598,
1261 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1262 .led_on = &ixgbe_led_on_generic,
1263 .led_off = &ixgbe_led_off_generic,
1264 .blink_led_start = &ixgbe_blink_led_start_generic,
1265 .blink_led_stop = &ixgbe_blink_led_stop_generic,
1266 .set_rar = &ixgbe_set_rar_generic,
1267 .clear_rar = &ixgbe_clear_rar_generic,
1268 .set_vmdq = &ixgbe_set_vmdq_82598,
1269 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1270 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1271 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1272 .enable_mc = &ixgbe_enable_mc_generic,
1273 .disable_mc = &ixgbe_disable_mc_generic,
1274 .clear_vfta = &ixgbe_clear_vfta_82598,
1275 .set_vfta = &ixgbe_set_vfta_82598,
1276 .fc_enable = &ixgbe_fc_enable_82598,
1277 .set_fw_drv_ver = NULL,
1278 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
1279 .release_swfw_sync = &ixgbe_release_swfw_sync,
1280 .get_thermal_sensor_data = NULL,
1281 .init_thermal_sensor_thresh = NULL,
1284 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1285 .init_params = &ixgbe_init_eeprom_params_generic,
1286 .read = &ixgbe_read_eerd_generic,
1287 .write = &ixgbe_write_eeprom_generic,
1288 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
1289 .read_buffer = &ixgbe_read_eerd_buffer_generic,
1290 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
1291 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1292 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1295 static struct ixgbe_phy_operations phy_ops_82598 = {
1296 .identify = &ixgbe_identify_phy_generic,
1297 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1298 .init = &ixgbe_init_phy_ops_82598,
1299 .reset = &ixgbe_reset_phy_generic,
1300 .read_reg = &ixgbe_read_phy_reg_generic,
1301 .write_reg = &ixgbe_write_phy_reg_generic,
1302 .setup_link = &ixgbe_setup_phy_link_generic,
1303 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1304 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
1305 .check_overtemp = &ixgbe_tn_check_overtemp,
1308 struct ixgbe_info ixgbe_82598_info = {
1309 .mac = ixgbe_mac_82598EB,
1310 .get_invariants = &ixgbe_get_invariants_82598,
1311 .mac_ops = &mac_ops_82598,
1312 .eeprom_ops = &eeprom_ops_82598,
1313 .phy_ops = &phy_ops_82598,