1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg_wait_to_complete);
52 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
53 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg_wait_to_complete);
58 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
59 ixgbe_link_speed speed,
60 bool autoneg_wait_to_complete);
61 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
62 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
63 u8 dev_addr, u8 *data);
64 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
65 u8 dev_addr, u8 data);
67 static bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
69 u32 fwsm, manc, factps;
71 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
72 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
75 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
76 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
79 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
80 if (factps & IXGBE_FACTPS_MNGCG)
86 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
88 struct ixgbe_mac_info *mac = &hw->mac;
90 /* enable the laser control functions for SFP+ fiber
93 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
94 !hw->mng_fw_enabled) {
95 mac->ops.disable_tx_laser =
96 &ixgbe_disable_tx_laser_multispeed_fiber;
97 mac->ops.enable_tx_laser =
98 &ixgbe_enable_tx_laser_multispeed_fiber;
99 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
101 mac->ops.disable_tx_laser = NULL;
102 mac->ops.enable_tx_laser = NULL;
103 mac->ops.flap_tx_laser = NULL;
106 if (hw->phy.multispeed_fiber) {
107 /* Set up dual speed SFP+ support */
108 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
110 if ((mac->ops.get_media_type(hw) ==
111 ixgbe_media_type_backplane) &&
112 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
113 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
114 !ixgbe_verify_lesm_fw_enabled_82599(hw))
115 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
117 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
121 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
124 u16 list_offset, data_offset, data_value;
125 bool got_lock = false;
127 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
128 ixgbe_init_mac_link_ops_82599(hw);
130 hw->phy.ops.reset = NULL;
132 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
137 /* PHY config will finish before releasing the semaphore */
138 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
139 IXGBE_GSSR_MAC_CSR_SM);
141 ret_val = IXGBE_ERR_SWFW_SYNC;
145 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
147 while (data_value != 0xffff) {
148 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
149 IXGBE_WRITE_FLUSH(hw);
150 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
154 /* Release the semaphore */
155 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
157 * Delay obtaining semaphore again to allow FW access,
158 * semaphore_delay is in ms usleep_range needs us.
160 usleep_range(hw->eeprom.semaphore_delay * 1000,
161 hw->eeprom.semaphore_delay * 2000);
163 /* Need SW/FW semaphore around AUTOC writes if LESM on,
164 * likewise reset_pipeline requires lock as it also writes
167 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
168 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
169 IXGBE_GSSR_MAC_CSR_SM);
176 /* Restart DSP and set SFI mode */
177 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((hw->mac.orig_autoc) |
178 IXGBE_AUTOC_LMS_10G_SERIAL));
179 hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
180 ret_val = ixgbe_reset_pipeline_82599(hw);
183 hw->mac.ops.release_swfw_sync(hw,
184 IXGBE_GSSR_MAC_CSR_SM);
189 hw_dbg(hw, " sfp module setup not complete\n");
190 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
199 /* Release the semaphore */
200 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
201 /* Delay obtaining semaphore again to allow FW access,
202 * semaphore_delay is in ms usleep_range needs us.
204 usleep_range(hw->eeprom.semaphore_delay * 1000,
205 hw->eeprom.semaphore_delay * 2000);
206 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
207 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
210 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
212 struct ixgbe_mac_info *mac = &hw->mac;
214 ixgbe_init_mac_link_ops_82599(hw);
216 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
217 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
218 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
219 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
220 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
221 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
227 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
228 * @hw: pointer to hardware structure
230 * Initialize any function pointers that were not able to be
231 * set during get_invariants because the PHY/SFP type was
232 * not known. Perform the SFP init if necessary.
235 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
237 struct ixgbe_mac_info *mac = &hw->mac;
238 struct ixgbe_phy_info *phy = &hw->phy;
242 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
243 /* Store flag indicating I2C bus access control unit. */
244 hw->phy.qsfp_shared_i2c_bus = true;
246 /* Initialize access to QSFP+ I2C bus */
247 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
248 esdp |= IXGBE_ESDP_SDP0_DIR;
249 esdp &= ~IXGBE_ESDP_SDP1_DIR;
250 esdp &= ~IXGBE_ESDP_SDP0;
251 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
252 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
253 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
254 IXGBE_WRITE_FLUSH(hw);
256 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;
257 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;
260 /* Identify the PHY or SFP module */
261 ret_val = phy->ops.identify(hw);
263 /* Setup function pointers based on detected SFP module and speeds */
264 ixgbe_init_mac_link_ops_82599(hw);
266 /* If copper media, overwrite with copper function pointers */
267 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
268 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
269 mac->ops.get_link_capabilities =
270 &ixgbe_get_copper_link_capabilities_generic;
273 /* Set necessary function pointers based on phy type */
274 switch (hw->phy.type) {
276 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
277 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
278 phy->ops.get_firmware_version =
279 &ixgbe_get_phy_firmware_version_tnx;
289 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
290 * @hw: pointer to hardware structure
291 * @speed: pointer to link speed
292 * @autoneg: true when autoneg or autotry is enabled
294 * Determines the link capabilities by reading the AUTOC register.
296 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
297 ixgbe_link_speed *speed,
303 /* Determine 1G link capabilities off of SFP+ type */
304 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
305 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
306 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
307 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
308 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
309 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
310 *speed = IXGBE_LINK_SPEED_1GB_FULL;
316 * Determine link capabilities based on the stored value of AUTOC,
317 * which represents EEPROM defaults. If AUTOC value has not been
318 * stored, use the current register value.
320 if (hw->mac.orig_link_settings_stored)
321 autoc = hw->mac.orig_autoc;
323 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
325 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
326 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
327 *speed = IXGBE_LINK_SPEED_1GB_FULL;
331 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
332 *speed = IXGBE_LINK_SPEED_10GB_FULL;
336 case IXGBE_AUTOC_LMS_1G_AN:
337 *speed = IXGBE_LINK_SPEED_1GB_FULL;
341 case IXGBE_AUTOC_LMS_10G_SERIAL:
342 *speed = IXGBE_LINK_SPEED_10GB_FULL;
346 case IXGBE_AUTOC_LMS_KX4_KX_KR:
347 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
348 *speed = IXGBE_LINK_SPEED_UNKNOWN;
349 if (autoc & IXGBE_AUTOC_KR_SUPP)
350 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
351 if (autoc & IXGBE_AUTOC_KX4_SUPP)
352 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
353 if (autoc & IXGBE_AUTOC_KX_SUPP)
354 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
358 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
359 *speed = IXGBE_LINK_SPEED_100_FULL;
360 if (autoc & IXGBE_AUTOC_KR_SUPP)
361 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
362 if (autoc & IXGBE_AUTOC_KX4_SUPP)
363 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
364 if (autoc & IXGBE_AUTOC_KX_SUPP)
365 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
369 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
370 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
375 status = IXGBE_ERR_LINK_SETUP;
380 if (hw->phy.multispeed_fiber) {
381 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
382 IXGBE_LINK_SPEED_1GB_FULL;
384 /* QSFP must not enable auto-negotiation */
385 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
396 * ixgbe_get_media_type_82599 - Get media type
397 * @hw: pointer to hardware structure
399 * Returns the media type (fiber, copper, backplane)
401 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
403 enum ixgbe_media_type media_type;
405 /* Detect if there is a copper PHY attached. */
406 switch (hw->phy.type) {
407 case ixgbe_phy_cu_unknown:
409 media_type = ixgbe_media_type_copper;
415 switch (hw->device_id) {
416 case IXGBE_DEV_ID_82599_KX4:
417 case IXGBE_DEV_ID_82599_KX4_MEZZ:
418 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
419 case IXGBE_DEV_ID_82599_KR:
420 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
421 case IXGBE_DEV_ID_82599_XAUI_LOM:
422 /* Default device ID is mezzanine card KX/KX4 */
423 media_type = ixgbe_media_type_backplane;
425 case IXGBE_DEV_ID_82599_SFP:
426 case IXGBE_DEV_ID_82599_SFP_FCOE:
427 case IXGBE_DEV_ID_82599_SFP_EM:
428 case IXGBE_DEV_ID_82599_SFP_SF2:
429 case IXGBE_DEV_ID_82599_SFP_SF_QP:
430 case IXGBE_DEV_ID_82599EN_SFP:
431 media_type = ixgbe_media_type_fiber;
433 case IXGBE_DEV_ID_82599_CX4:
434 media_type = ixgbe_media_type_cx4;
436 case IXGBE_DEV_ID_82599_T3_LOM:
437 media_type = ixgbe_media_type_copper;
439 case IXGBE_DEV_ID_82599_LS:
440 media_type = ixgbe_media_type_fiber_lco;
442 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
443 media_type = ixgbe_media_type_fiber_qsfp;
446 media_type = ixgbe_media_type_unknown;
454 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
455 * @hw: pointer to hardware structure
457 * Disables link, should be called during D3 power down sequence.
460 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
464 if (!hw->mng_fw_enabled && !hw->wol_enabled) {
465 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
466 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
467 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
472 * ixgbe_start_mac_link_82599 - Setup MAC link settings
473 * @hw: pointer to hardware structure
474 * @autoneg_wait_to_complete: true when waiting for completion is needed
476 * Configures link settings based on values in the ixgbe_hw struct.
477 * Restarts the link. Performs autonegotiation if needed.
479 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
480 bool autoneg_wait_to_complete)
486 bool got_lock = false;
488 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
489 status = hw->mac.ops.acquire_swfw_sync(hw,
490 IXGBE_GSSR_MAC_CSR_SM);
498 ixgbe_reset_pipeline_82599(hw);
501 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
503 /* Only poll for autoneg to complete if specified to do so */
504 if (autoneg_wait_to_complete) {
505 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
506 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
507 IXGBE_AUTOC_LMS_KX4_KX_KR ||
508 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
509 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
510 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
511 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
512 links_reg = 0; /* Just in case Autoneg time = 0 */
513 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
514 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
515 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
519 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
520 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
521 hw_dbg(hw, "Autoneg did not complete.\n");
526 /* Add delay to filter out noises during initial link setup */
534 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
535 * @hw: pointer to hardware structure
537 * The base drivers may require better control over SFP+ module
538 * PHY states. This includes selectively shutting down the Tx
539 * laser on the PHY, effectively halting physical link.
541 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
543 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
545 /* Disable tx laser; allow 100us to go dark per spec */
546 esdp_reg |= IXGBE_ESDP_SDP3;
547 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
548 IXGBE_WRITE_FLUSH(hw);
553 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
554 * @hw: pointer to hardware structure
556 * The base drivers may require better control over SFP+ module
557 * PHY states. This includes selectively turning on the Tx
558 * laser on the PHY, effectively starting physical link.
560 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
562 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
564 /* Enable tx laser; allow 100ms to light up */
565 esdp_reg &= ~IXGBE_ESDP_SDP3;
566 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
567 IXGBE_WRITE_FLUSH(hw);
572 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
573 * @hw: pointer to hardware structure
575 * When the driver changes the link speeds that it can support,
576 * it sets autotry_restart to true to indicate that we need to
577 * initiate a new autotry session with the link partner. To do
578 * so, we set the speed then disable and re-enable the tx laser, to
579 * alert the link partner that it also needs to restart autotry on its
580 * end. This is consistent with true clause 37 autoneg, which also
581 * involves a loss of signal.
583 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
585 if (hw->mac.autotry_restart) {
586 ixgbe_disable_tx_laser_multispeed_fiber(hw);
587 ixgbe_enable_tx_laser_multispeed_fiber(hw);
588 hw->mac.autotry_restart = false;
593 * ixgbe_set_fiber_fixed_speed - Set module link speed for fixed fiber
594 * @hw: pointer to hardware structure
595 * @speed: link speed to set
597 * We set the module speed differently for fixed fiber. For other
598 * multi-speed devices we don't have an error value so here if we
599 * detect an error we just log it and exit.
601 static void ixgbe_set_fiber_fixed_speed(struct ixgbe_hw *hw,
602 ixgbe_link_speed speed)
608 case IXGBE_LINK_SPEED_10GB_FULL:
609 /* one bit mask same as setting on */
610 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
612 case IXGBE_LINK_SPEED_1GB_FULL:
613 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
616 hw_dbg(hw, "Invalid fixed module speed\n");
621 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
622 IXGBE_I2C_EEPROM_DEV_ADDR2,
625 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n");
629 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
631 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
632 IXGBE_I2C_EEPROM_DEV_ADDR2,
635 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n");
640 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
641 IXGBE_I2C_EEPROM_DEV_ADDR2,
644 hw_dbg(hw, "Failed to read Rx Rate Select RS1\n");
648 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
650 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
651 IXGBE_I2C_EEPROM_DEV_ADDR2,
654 hw_dbg(hw, "Failed to write Rx Rate Select RS1\n");
662 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
663 * @hw: pointer to hardware structure
664 * @speed: new link speed
665 * @autoneg_wait_to_complete: true when waiting for completion is needed
667 * Set the link speed in the AUTOC register and restarts link.
669 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
670 ixgbe_link_speed speed,
671 bool autoneg_wait_to_complete)
674 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
675 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
677 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
679 bool link_up = false;
680 bool autoneg = false;
682 /* Mask off requested but non-supported speeds */
683 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
691 * Try each speed one by one, highest priority first. We do this in
692 * software because 10gb fiber doesn't support speed autonegotiation.
694 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
696 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
698 /* If we already have link at this speed, just jump out */
699 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
704 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
707 /* Set the module link speed */
708 switch (hw->phy.media_type) {
709 case ixgbe_media_type_fiber:
710 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
711 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
712 IXGBE_WRITE_FLUSH(hw);
714 case ixgbe_media_type_fiber_qsfp:
715 /* QSFP module automatically detects MAC link speed */
718 hw_dbg(hw, "Unexpected media type.\n");
722 /* Allow module to change analog characteristics (1G->10G) */
725 status = ixgbe_setup_mac_link_82599(hw,
726 IXGBE_LINK_SPEED_10GB_FULL,
727 autoneg_wait_to_complete);
731 /* Flap the tx laser if it has not already been done */
732 if (hw->mac.ops.flap_tx_laser)
733 hw->mac.ops.flap_tx_laser(hw);
736 * Wait for the controller to acquire link. Per IEEE 802.3ap,
737 * Section 73.10.2, we may have to wait up to 500ms if KR is
738 * attempted. 82599 uses the same timing for 10g SFI.
740 for (i = 0; i < 5; i++) {
741 /* Wait for the link partner to also set speed */
744 /* If we have link, just jump out */
745 status = hw->mac.ops.check_link(hw, &link_speed,
755 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
757 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
758 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
760 /* If we already have link at this speed, just jump out */
761 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
766 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
769 /* Set the module link speed */
770 switch (hw->phy.media_type) {
771 case ixgbe_media_type_fiber_fixed:
772 ixgbe_set_fiber_fixed_speed(hw,
773 IXGBE_LINK_SPEED_1GB_FULL);
775 case ixgbe_media_type_fiber:
776 esdp_reg &= ~IXGBE_ESDP_SDP5;
777 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
778 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
779 IXGBE_WRITE_FLUSH(hw);
781 case ixgbe_media_type_fiber_qsfp:
782 /* QSFP module automatically detects MAC link speed */
785 hw_dbg(hw, "Unexpected media type.\n");
789 /* Allow module to change analog characteristics (10G->1G) */
792 status = ixgbe_setup_mac_link_82599(hw,
793 IXGBE_LINK_SPEED_1GB_FULL,
794 autoneg_wait_to_complete);
798 /* Flap the tx laser if it has not already been done */
799 if (hw->mac.ops.flap_tx_laser)
800 hw->mac.ops.flap_tx_laser(hw);
802 /* Wait for the link partner to also set speed */
805 /* If we have link, just jump out */
806 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
816 * We didn't get link. Configure back to the highest speed we tried,
817 * (if there was more than one). We call ourselves back with just the
818 * single highest speed that the user requested.
821 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
823 autoneg_wait_to_complete);
826 /* Set autoneg_advertised value based on input link speed */
827 hw->phy.autoneg_advertised = 0;
829 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
830 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
832 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
833 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
839 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
840 * @hw: pointer to hardware structure
841 * @speed: new link speed
842 * @autoneg_wait_to_complete: true when waiting for completion is needed
844 * Implements the Intel SmartSpeed algorithm.
846 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
847 ixgbe_link_speed speed,
848 bool autoneg_wait_to_complete)
851 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
853 bool link_up = false;
854 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
856 /* Set autoneg_advertised value based on input link speed */
857 hw->phy.autoneg_advertised = 0;
859 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
860 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
862 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
863 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
865 if (speed & IXGBE_LINK_SPEED_100_FULL)
866 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
869 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
870 * autoneg advertisement if link is unable to be established at the
871 * highest negotiated rate. This can sometimes happen due to integrity
872 * issues with the physical media connection.
875 /* First, try to get link with full advertisement */
876 hw->phy.smart_speed_active = false;
877 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
878 status = ixgbe_setup_mac_link_82599(hw, speed,
879 autoneg_wait_to_complete);
884 * Wait for the controller to acquire link. Per IEEE 802.3ap,
885 * Section 73.10.2, we may have to wait up to 500ms if KR is
886 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
887 * Table 9 in the AN MAS.
889 for (i = 0; i < 5; i++) {
892 /* If we have link, just jump out */
893 status = hw->mac.ops.check_link(hw, &link_speed,
904 * We didn't get link. If we advertised KR plus one of KX4/KX
905 * (or BX4/BX), then disable KR and try again.
907 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
908 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
911 /* Turn SmartSpeed on to disable KR support */
912 hw->phy.smart_speed_active = true;
913 status = ixgbe_setup_mac_link_82599(hw, speed,
914 autoneg_wait_to_complete);
919 * Wait for the controller to acquire link. 600ms will allow for
920 * the AN link_fail_inhibit_timer as well for multiple cycles of
921 * parallel detect, both 10g and 1g. This allows for the maximum
922 * connect attempts as defined in the AN MAS table 73-7.
924 for (i = 0; i < 6; i++) {
927 /* If we have link, just jump out */
928 status = hw->mac.ops.check_link(hw, &link_speed,
937 /* We didn't get link. Turn SmartSpeed back off. */
938 hw->phy.smart_speed_active = false;
939 status = ixgbe_setup_mac_link_82599(hw, speed,
940 autoneg_wait_to_complete);
943 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
944 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
945 "the maximum advertised\n");
950 * ixgbe_setup_mac_link_82599 - Set MAC link speed
951 * @hw: pointer to hardware structure
952 * @speed: new link speed
953 * @autoneg_wait_to_complete: true when waiting for completion is needed
955 * Set the link speed in the AUTOC register and restarts link.
957 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
958 ixgbe_link_speed speed,
959 bool autoneg_wait_to_complete)
962 u32 autoc, pma_pmd_1g, link_mode, start_autoc;
963 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
965 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
968 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
969 bool got_lock = false;
970 bool autoneg = false;
972 /* Check to see if speed passed in is supported. */
973 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
978 speed &= link_capabilities;
980 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
981 status = IXGBE_ERR_LINK_SETUP;
985 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
986 if (hw->mac.orig_link_settings_stored)
987 autoc = hw->mac.orig_autoc;
989 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
992 start_autoc = hw->mac.cached_autoc;
993 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
994 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
996 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
997 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
998 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
999 /* Set KX4/KX/KR support according to speed requested */
1000 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
1001 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1002 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
1003 autoc |= IXGBE_AUTOC_KX4_SUPP;
1004 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
1005 (hw->phy.smart_speed_active == false))
1006 autoc |= IXGBE_AUTOC_KR_SUPP;
1008 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1009 autoc |= IXGBE_AUTOC_KX_SUPP;
1010 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
1011 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
1012 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
1013 /* Switch from 1G SFI to 10G SFI if requested */
1014 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
1015 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
1016 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1017 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
1019 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
1020 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
1021 /* Switch from 10G SFI to 1G SFI if requested */
1022 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1023 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
1024 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1026 autoc |= IXGBE_AUTOC_LMS_1G_AN;
1028 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1032 if (autoc != start_autoc) {
1033 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
1034 * likewise reset_pipeline requires us to hold this lock as
1035 * it also writes to AUTOC.
1037 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1038 status = hw->mac.ops.acquire_swfw_sync(hw,
1039 IXGBE_GSSR_MAC_CSR_SM);
1047 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
1048 hw->mac.cached_autoc = autoc;
1049 ixgbe_reset_pipeline_82599(hw);
1052 hw->mac.ops.release_swfw_sync(hw,
1053 IXGBE_GSSR_MAC_CSR_SM);
1055 /* Only poll for autoneg to complete if specified to do so */
1056 if (autoneg_wait_to_complete) {
1057 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1058 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1059 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1060 links_reg = 0; /*Just in case Autoneg time=0*/
1061 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1063 IXGBE_READ_REG(hw, IXGBE_LINKS);
1064 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1068 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1070 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1071 hw_dbg(hw, "Autoneg did not "
1077 /* Add delay to filter out noises during initial link setup */
1086 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1087 * @hw: pointer to hardware structure
1088 * @speed: new link speed
1089 * @autoneg_wait_to_complete: true if waiting is needed to complete
1091 * Restarts link on PHY and MAC based on settings passed in.
1093 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1094 ixgbe_link_speed speed,
1095 bool autoneg_wait_to_complete)
1099 /* Setup the PHY according to input speed */
1100 status = hw->phy.ops.setup_link_speed(hw, speed,
1101 autoneg_wait_to_complete);
1103 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1109 * ixgbe_reset_hw_82599 - Perform hardware reset
1110 * @hw: pointer to hardware structure
1112 * Resets the hardware by resetting the transmit and receive units, masks
1113 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1116 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1118 ixgbe_link_speed link_speed;
1120 u32 ctrl, i, autoc2;
1122 bool link_up = false;
1124 /* Call adapter stop to disable tx/rx and clear interrupts */
1125 status = hw->mac.ops.stop_adapter(hw);
1129 /* flush pending Tx transactions */
1130 ixgbe_clear_tx_pending(hw);
1132 /* PHY ops must be identified and initialized prior to reset */
1134 /* Identify PHY and related function pointers */
1135 status = hw->phy.ops.init(hw);
1137 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1140 /* Setup SFP module if there is one present. */
1141 if (hw->phy.sfp_setup_needed) {
1142 status = hw->mac.ops.setup_sfp(hw);
1143 hw->phy.sfp_setup_needed = false;
1146 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1150 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1151 hw->phy.ops.reset(hw);
1153 /* remember AUTOC from before we reset */
1154 if (hw->mac.cached_autoc)
1155 curr_lms = hw->mac.cached_autoc & IXGBE_AUTOC_LMS_MASK;
1157 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) &
1158 IXGBE_AUTOC_LMS_MASK;
1162 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1163 * If link reset is used when link is up, it might reset the PHY when
1164 * mng is using it. If link is down or the flag to force full link
1165 * reset is set, then perform link reset.
1167 ctrl = IXGBE_CTRL_LNK_RST;
1168 if (!hw->force_full_reset) {
1169 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1171 ctrl = IXGBE_CTRL_RST;
1174 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1175 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1176 IXGBE_WRITE_FLUSH(hw);
1178 /* Poll for reset bit to self-clear indicating reset is complete */
1179 for (i = 0; i < 10; i++) {
1181 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1182 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1186 if (ctrl & IXGBE_CTRL_RST_MASK) {
1187 status = IXGBE_ERR_RESET_FAILED;
1188 hw_dbg(hw, "Reset polling failed to complete.\n");
1194 * Double resets are required for recovery from certain error
1195 * conditions. Between resets, it is necessary to stall to allow time
1196 * for any pending HW events to complete.
1198 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1199 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1204 * Store the original AUTOC/AUTOC2 values if they have not been
1205 * stored off yet. Otherwise restore the stored original
1206 * values since the reset operation sets back to defaults.
1208 hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1209 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1211 /* Enable link if disabled in NVM */
1212 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1213 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1214 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1215 IXGBE_WRITE_FLUSH(hw);
1218 if (hw->mac.orig_link_settings_stored == false) {
1219 hw->mac.orig_autoc = hw->mac.cached_autoc;
1220 hw->mac.orig_autoc2 = autoc2;
1221 hw->mac.orig_link_settings_stored = true;
1224 /* If MNG FW is running on a multi-speed device that
1225 * doesn't autoneg with out driver support we need to
1226 * leave LMS in the state it was before we MAC reset.
1227 * Likewise if we support WoL we don't want change the
1230 if ((hw->phy.multispeed_fiber && hw->mng_fw_enabled) ||
1232 hw->mac.orig_autoc =
1233 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1236 if (hw->mac.cached_autoc != hw->mac.orig_autoc) {
1237 /* Need SW/FW semaphore around AUTOC writes if LESM is
1238 * on, likewise reset_pipeline requires us to hold
1239 * this lock as it also writes to AUTOC.
1241 bool got_lock = false;
1242 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1243 status = hw->mac.ops.acquire_swfw_sync(hw,
1244 IXGBE_GSSR_MAC_CSR_SM);
1251 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1252 hw->mac.cached_autoc = hw->mac.orig_autoc;
1253 ixgbe_reset_pipeline_82599(hw);
1256 hw->mac.ops.release_swfw_sync(hw,
1257 IXGBE_GSSR_MAC_CSR_SM);
1260 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1261 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1262 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1263 autoc2 |= (hw->mac.orig_autoc2 &
1264 IXGBE_AUTOC2_UPPER_MASK);
1265 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1269 /* Store the permanent mac address */
1270 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1273 * Store MAC address from RAR0, clear receive address registers, and
1274 * clear the multicast table. Also reset num_rar_entries to 128,
1275 * since we modify this value when programming the SAN MAC address.
1277 hw->mac.num_rar_entries = 128;
1278 hw->mac.ops.init_rx_addrs(hw);
1280 /* Store the permanent SAN mac address */
1281 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1283 /* Add the SAN MAC address to the RAR only if it's a valid address */
1284 if (is_valid_ether_addr(hw->mac.san_addr)) {
1285 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1286 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1288 /* Save the SAN MAC RAR index */
1289 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1291 /* Reserve the last RAR for the SAN MAC address */
1292 hw->mac.num_rar_entries--;
1295 /* Store the alternative WWNN/WWPN prefix */
1296 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1297 &hw->mac.wwpn_prefix);
1304 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1305 * @hw: pointer to hardware structure
1307 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1310 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1311 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1314 * Before starting reinitialization process,
1315 * FDIRCMD.CMD must be zero.
1317 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1318 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1319 IXGBE_FDIRCMD_CMD_MASK))
1323 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1324 hw_dbg(hw, "Flow Director previous command isn't complete, "
1325 "aborting table re-initialization.\n");
1326 return IXGBE_ERR_FDIR_REINIT_FAILED;
1329 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1330 IXGBE_WRITE_FLUSH(hw);
1332 * 82599 adapters flow director init flow cannot be restarted,
1333 * Workaround 82599 silicon errata by performing the following steps
1334 * before re-writing the FDIRCTRL control register with the same value.
1335 * - write 1 to bit 8 of FDIRCMD register &
1336 * - write 0 to bit 8 of FDIRCMD register
1338 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1339 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1340 IXGBE_FDIRCMD_CLEARHT));
1341 IXGBE_WRITE_FLUSH(hw);
1342 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1343 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1344 ~IXGBE_FDIRCMD_CLEARHT));
1345 IXGBE_WRITE_FLUSH(hw);
1347 * Clear FDIR Hash register to clear any leftover hashes
1348 * waiting to be programmed.
1350 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1351 IXGBE_WRITE_FLUSH(hw);
1353 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1354 IXGBE_WRITE_FLUSH(hw);
1356 /* Poll init-done after we write FDIRCTRL register */
1357 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1358 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1359 IXGBE_FDIRCTRL_INIT_DONE)
1361 usleep_range(1000, 2000);
1363 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1364 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1365 return IXGBE_ERR_FDIR_REINIT_FAILED;
1368 /* Clear FDIR statistics registers (read to clear) */
1369 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1370 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1371 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1372 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1373 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1379 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1380 * @hw: pointer to hardware structure
1381 * @fdirctrl: value to write to flow director control register
1383 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1387 /* Prime the keys for hashing */
1388 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1389 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1392 * Poll init-done after we write the register. Estimated times:
1393 * 10G: PBALLOC = 11b, timing is 60us
1394 * 1G: PBALLOC = 11b, timing is 600us
1395 * 100M: PBALLOC = 11b, timing is 6ms
1397 * Multiple these timings by 4 if under full Rx load
1399 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1400 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1401 * this might not finish in our poll time, but we can live with that
1404 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1405 IXGBE_WRITE_FLUSH(hw);
1406 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1407 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1408 IXGBE_FDIRCTRL_INIT_DONE)
1410 usleep_range(1000, 2000);
1413 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1414 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1418 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1419 * @hw: pointer to hardware structure
1420 * @fdirctrl: value to write to flow director control register, initially
1421 * contains just the value of the Rx packet buffer allocation
1423 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1426 * Continue setup of fdirctrl register bits:
1427 * Move the flexible bytes to use the ethertype - shift 6 words
1428 * Set the maximum length per hash bucket to 0xA filters
1429 * Send interrupt when 64 filters are left
1431 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1432 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1433 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1435 /* write hashes and fdirctrl register, poll for completion */
1436 ixgbe_fdir_enable_82599(hw, fdirctrl);
1442 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1443 * @hw: pointer to hardware structure
1444 * @fdirctrl: value to write to flow director control register, initially
1445 * contains just the value of the Rx packet buffer allocation
1447 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1450 * Continue setup of fdirctrl register bits:
1451 * Turn perfect match filtering on
1452 * Report hash in RSS field of Rx wb descriptor
1453 * Initialize the drop queue
1454 * Move the flexible bytes to use the ethertype - shift 6 words
1455 * Set the maximum length per hash bucket to 0xA filters
1456 * Send interrupt when 64 (0x4 * 16) filters are left
1458 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1459 IXGBE_FDIRCTRL_REPORT_STATUS |
1460 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1461 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1462 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1463 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1465 /* write hashes and fdirctrl register, poll for completion */
1466 ixgbe_fdir_enable_82599(hw, fdirctrl);
1472 * These defines allow us to quickly generate all of the necessary instructions
1473 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1474 * for values 0 through 15
1476 #define IXGBE_ATR_COMMON_HASH_KEY \
1477 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1478 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1481 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1482 common_hash ^= lo_hash_dword >> n; \
1483 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1484 bucket_hash ^= lo_hash_dword >> n; \
1485 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1486 sig_hash ^= lo_hash_dword << (16 - n); \
1487 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1488 common_hash ^= hi_hash_dword >> n; \
1489 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1490 bucket_hash ^= hi_hash_dword >> n; \
1491 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1492 sig_hash ^= hi_hash_dword << (16 - n); \
1496 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1497 * @stream: input bitstream to compute the hash on
1499 * This function is almost identical to the function above but contains
1500 * several optomizations such as unwinding all of the loops, letting the
1501 * compiler work out all of the conditional ifs since the keys are static
1502 * defines, and computing two keys at once since the hashed dword stream
1503 * will be the same for both keys.
1505 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1506 union ixgbe_atr_hash_dword common)
1508 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1509 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1511 /* record the flow_vm_vlan bits as they are a key part to the hash */
1512 flow_vm_vlan = ntohl(input.dword);
1514 /* generate common hash dword */
1515 hi_hash_dword = ntohl(common.dword);
1517 /* low dword is word swapped version of common */
1518 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1520 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1521 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1523 /* Process bits 0 and 16 */
1524 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1527 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1528 * delay this because bit 0 of the stream should not be processed
1529 * so we do not add the vlan until after bit 0 was processed
1531 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1533 /* Process remaining 30 bit of the key */
1534 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1535 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1536 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1537 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1538 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1539 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1540 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1541 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1542 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1543 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1544 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1545 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1546 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1547 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1548 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1550 /* combine common_hash result with signature and bucket hashes */
1551 bucket_hash ^= common_hash;
1552 bucket_hash &= IXGBE_ATR_HASH_MASK;
1554 sig_hash ^= common_hash << 16;
1555 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1557 /* return completed signature hash */
1558 return sig_hash ^ bucket_hash;
1562 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1563 * @hw: pointer to hardware structure
1564 * @input: unique input dword
1565 * @common: compressed common input dword
1566 * @queue: queue index to direct traffic to
1568 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1569 union ixgbe_atr_hash_dword input,
1570 union ixgbe_atr_hash_dword common,
1577 * Get the flow_type in order to program FDIRCMD properly
1578 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1580 switch (input.formatted.flow_type) {
1581 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1582 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1583 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1584 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1585 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1586 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1589 hw_dbg(hw, " Error on flow type input\n");
1590 return IXGBE_ERR_CONFIG;
1593 /* configure FDIRCMD register */
1594 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1595 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1596 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1597 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1600 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1601 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1603 fdirhashcmd = (u64)fdircmd << 32;
1604 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1605 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1607 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1612 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1615 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1616 bucket_hash ^= lo_hash_dword >> n; \
1617 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1618 bucket_hash ^= hi_hash_dword >> n; \
1622 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1623 * @atr_input: input bitstream to compute the hash on
1624 * @input_mask: mask for the input bitstream
1626 * This function serves two main purposes. First it applys the input_mask
1627 * to the atr_input resulting in a cleaned up atr_input data stream.
1628 * Secondly it computes the hash and stores it in the bkt_hash field at
1629 * the end of the input byte stream. This way it will be available for
1630 * future use without needing to recompute the hash.
1632 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1633 union ixgbe_atr_input *input_mask)
1636 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1637 u32 bucket_hash = 0;
1639 /* Apply masks to input data */
1640 input->dword_stream[0] &= input_mask->dword_stream[0];
1641 input->dword_stream[1] &= input_mask->dword_stream[1];
1642 input->dword_stream[2] &= input_mask->dword_stream[2];
1643 input->dword_stream[3] &= input_mask->dword_stream[3];
1644 input->dword_stream[4] &= input_mask->dword_stream[4];
1645 input->dword_stream[5] &= input_mask->dword_stream[5];
1646 input->dword_stream[6] &= input_mask->dword_stream[6];
1647 input->dword_stream[7] &= input_mask->dword_stream[7];
1648 input->dword_stream[8] &= input_mask->dword_stream[8];
1649 input->dword_stream[9] &= input_mask->dword_stream[9];
1650 input->dword_stream[10] &= input_mask->dword_stream[10];
1652 /* record the flow_vm_vlan bits as they are a key part to the hash */
1653 flow_vm_vlan = ntohl(input->dword_stream[0]);
1655 /* generate common hash dword */
1656 hi_hash_dword = ntohl(input->dword_stream[1] ^
1657 input->dword_stream[2] ^
1658 input->dword_stream[3] ^
1659 input->dword_stream[4] ^
1660 input->dword_stream[5] ^
1661 input->dword_stream[6] ^
1662 input->dword_stream[7] ^
1663 input->dword_stream[8] ^
1664 input->dword_stream[9] ^
1665 input->dword_stream[10]);
1667 /* low dword is word swapped version of common */
1668 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1670 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1671 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1673 /* Process bits 0 and 16 */
1674 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1677 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1678 * delay this because bit 0 of the stream should not be processed
1679 * so we do not add the vlan until after bit 0 was processed
1681 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1683 /* Process remaining 30 bit of the key */
1684 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1685 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1686 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1687 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1688 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1689 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1690 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1691 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1692 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1693 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1694 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1695 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1696 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1697 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1698 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1701 * Limit hash to 13 bits since max bucket count is 8K.
1702 * Store result at the end of the input stream.
1704 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1708 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1709 * @input_mask: mask to be bit swapped
1711 * The source and destination port masks for flow director are bit swapped
1712 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1713 * generate a correctly swapped value we need to bit swap the mask and that
1714 * is what is accomplished by this function.
1716 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1718 u32 mask = ntohs(input_mask->formatted.dst_port);
1719 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1720 mask |= ntohs(input_mask->formatted.src_port);
1721 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1722 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1723 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1724 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1728 * These two macros are meant to address the fact that we have registers
1729 * that are either all or in part big-endian. As a result on big-endian
1730 * systems we will end up byte swapping the value to little-endian before
1731 * it is byte swapped again and written to the hardware in the original
1732 * big-endian format.
1734 #define IXGBE_STORE_AS_BE32(_value) \
1735 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1736 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1738 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1739 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1741 #define IXGBE_STORE_AS_BE16(_value) \
1742 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1744 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1745 union ixgbe_atr_input *input_mask)
1747 /* mask IPv6 since it is currently not supported */
1748 u32 fdirm = IXGBE_FDIRM_DIPv6;
1752 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1753 * are zero, then assume a full mask for that field. Also assume that
1754 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1755 * cannot be masked out in this implementation.
1757 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1761 /* verify bucket hash is cleared on hash generation */
1762 if (input_mask->formatted.bkt_hash)
1763 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1765 /* Program FDIRM and verify partial masks */
1766 switch (input_mask->formatted.vm_pool & 0x7F) {
1768 fdirm |= IXGBE_FDIRM_POOL;
1772 hw_dbg(hw, " Error on vm pool mask\n");
1773 return IXGBE_ERR_CONFIG;
1776 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1778 fdirm |= IXGBE_FDIRM_L4P;
1779 if (input_mask->formatted.dst_port ||
1780 input_mask->formatted.src_port) {
1781 hw_dbg(hw, " Error on src/dst port mask\n");
1782 return IXGBE_ERR_CONFIG;
1784 case IXGBE_ATR_L4TYPE_MASK:
1787 hw_dbg(hw, " Error on flow type mask\n");
1788 return IXGBE_ERR_CONFIG;
1791 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1793 /* mask VLAN ID, fall through to mask VLAN priority */
1794 fdirm |= IXGBE_FDIRM_VLANID;
1796 /* mask VLAN priority */
1797 fdirm |= IXGBE_FDIRM_VLANP;
1800 /* mask VLAN ID only, fall through */
1801 fdirm |= IXGBE_FDIRM_VLANID;
1803 /* no VLAN fields masked */
1806 hw_dbg(hw, " Error on VLAN mask\n");
1807 return IXGBE_ERR_CONFIG;
1810 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1812 /* Mask Flex Bytes, fall through */
1813 fdirm |= IXGBE_FDIRM_FLEX;
1817 hw_dbg(hw, " Error on flexible byte mask\n");
1818 return IXGBE_ERR_CONFIG;
1821 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1822 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1824 /* store the TCP/UDP port masks, bit reversed from port layout */
1825 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1827 /* write both the same so that UDP and TCP use the same mask */
1828 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1829 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1831 /* store source and destination IP masks (big-enian) */
1832 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1833 ~input_mask->formatted.src_ip[0]);
1834 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1835 ~input_mask->formatted.dst_ip[0]);
1840 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1841 union ixgbe_atr_input *input,
1842 u16 soft_id, u8 queue)
1844 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1846 /* currently IPv6 is not supported, must be programmed with 0 */
1847 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1848 input->formatted.src_ip[0]);
1849 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1850 input->formatted.src_ip[1]);
1851 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1852 input->formatted.src_ip[2]);
1854 /* record the source address (big-endian) */
1855 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1857 /* record the first 32 bits of the destination address (big-endian) */
1858 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1860 /* record source and destination port (little-endian)*/
1861 fdirport = ntohs(input->formatted.dst_port);
1862 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1863 fdirport |= ntohs(input->formatted.src_port);
1864 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1866 /* record vlan (little-endian) and flex_bytes(big-endian) */
1867 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1868 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1869 fdirvlan |= ntohs(input->formatted.vlan_id);
1870 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1872 /* configure FDIRHASH register */
1873 fdirhash = input->formatted.bkt_hash;
1874 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1875 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1878 * flush all previous writes to make certain registers are
1879 * programmed prior to issuing the command
1881 IXGBE_WRITE_FLUSH(hw);
1883 /* configure FDIRCMD register */
1884 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1885 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1886 if (queue == IXGBE_FDIR_DROP_QUEUE)
1887 fdircmd |= IXGBE_FDIRCMD_DROP;
1888 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1889 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1890 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1892 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1897 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1898 union ixgbe_atr_input *input,
1906 /* configure FDIRHASH register */
1907 fdirhash = input->formatted.bkt_hash;
1908 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1909 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1911 /* flush hash to HW */
1912 IXGBE_WRITE_FLUSH(hw);
1914 /* Query if filter is present */
1915 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1917 for (retry_count = 10; retry_count; retry_count--) {
1918 /* allow 10us for query to process */
1920 /* verify query completed successfully */
1921 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1922 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1927 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1929 /* if filter exists in hardware then remove it */
1930 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1931 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1932 IXGBE_WRITE_FLUSH(hw);
1933 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1934 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1941 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1942 * @hw: pointer to hardware structure
1943 * @reg: analog register to read
1946 * Performs read operation to Omer analog register specified.
1948 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1952 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1954 IXGBE_WRITE_FLUSH(hw);
1956 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1957 *val = (u8)core_ctl;
1963 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1964 * @hw: pointer to hardware structure
1965 * @reg: atlas register to write
1966 * @val: value to write
1968 * Performs write operation to Omer analog register specified.
1970 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1974 core_ctl = (reg << 8) | val;
1975 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1976 IXGBE_WRITE_FLUSH(hw);
1983 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1984 * @hw: pointer to hardware structure
1986 * Starts the hardware using the generic start_hw function
1987 * and the generation start_hw function.
1988 * Then performs revision-specific operations, if any.
1990 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1994 ret_val = ixgbe_start_hw_generic(hw);
1998 ret_val = ixgbe_start_hw_gen2(hw);
2002 /* We need to run link autotry after the driver loads */
2003 hw->mac.autotry_restart = true;
2004 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
2007 ret_val = ixgbe_verify_fw_version_82599(hw);
2013 * ixgbe_identify_phy_82599 - Get physical layer module
2014 * @hw: pointer to hardware structure
2016 * Determines the physical layer module found on the current adapter.
2017 * If PHY already detected, maintains current PHY type in hw struct,
2018 * otherwise executes the PHY detection routine.
2020 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2022 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2024 /* Detect PHY if not unknown - returns success if already detected. */
2025 status = ixgbe_identify_phy_generic(hw);
2027 /* 82599 10GBASE-T requires an external PHY */
2028 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2031 status = ixgbe_identify_module_generic(hw);
2034 /* Set PHY type none if no PHY detected */
2035 if (hw->phy.type == ixgbe_phy_unknown) {
2036 hw->phy.type = ixgbe_phy_none;
2040 /* Return error if SFP module has been detected but is not supported */
2041 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2042 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
2049 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2050 * @hw: pointer to hardware structure
2052 * Determines physical layer capabilities of the current configuration.
2054 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2056 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2057 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2058 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2059 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2060 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2061 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2062 u16 ext_ability = 0;
2063 u8 comp_codes_10g = 0;
2064 u8 comp_codes_1g = 0;
2066 hw->phy.ops.identify(hw);
2068 switch (hw->phy.type) {
2070 case ixgbe_phy_cu_unknown:
2071 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2073 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
2074 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2075 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
2076 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2077 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
2078 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2084 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2085 case IXGBE_AUTOC_LMS_1G_AN:
2086 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2087 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2088 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2089 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2092 /* SFI mode so read SFP module */
2095 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2096 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2097 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2098 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2099 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2100 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2101 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2104 case IXGBE_AUTOC_LMS_10G_SERIAL:
2105 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2106 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2108 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2111 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2112 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2113 if (autoc & IXGBE_AUTOC_KX_SUPP)
2114 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2115 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2116 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2117 if (autoc & IXGBE_AUTOC_KR_SUPP)
2118 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2127 /* SFP check must be done last since DA modules are sometimes used to
2128 * test KR mode - we need to id KR mode correctly before SFP module.
2129 * Call identify_sfp because the pluggable module may have changed */
2130 hw->phy.ops.identify_sfp(hw);
2131 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2134 switch (hw->phy.type) {
2135 case ixgbe_phy_sfp_passive_tyco:
2136 case ixgbe_phy_sfp_passive_unknown:
2137 case ixgbe_phy_qsfp_passive_unknown:
2138 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2140 case ixgbe_phy_sfp_ftl_active:
2141 case ixgbe_phy_sfp_active_unknown:
2142 case ixgbe_phy_qsfp_active_unknown:
2143 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2145 case ixgbe_phy_sfp_avago:
2146 case ixgbe_phy_sfp_ftl:
2147 case ixgbe_phy_sfp_intel:
2148 case ixgbe_phy_sfp_unknown:
2149 hw->phy.ops.read_i2c_eeprom(hw,
2150 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2151 hw->phy.ops.read_i2c_eeprom(hw,
2152 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2153 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2154 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2155 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2156 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2157 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2158 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2160 case ixgbe_phy_qsfp_intel:
2161 case ixgbe_phy_qsfp_unknown:
2162 hw->phy.ops.read_i2c_eeprom(hw,
2163 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
2164 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2165 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2166 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2167 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2174 return physical_layer;
2178 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2179 * @hw: pointer to hardware structure
2180 * @regval: register value to write to RXCTRL
2182 * Enables the Rx DMA unit for 82599
2184 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2187 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2188 * If traffic is incoming before we enable the Rx unit, it could hang
2189 * the Rx DMA unit. Therefore, make sure the security engine is
2190 * completely disabled prior to enabling the Rx unit.
2192 hw->mac.ops.disable_rx_buff(hw);
2194 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2196 hw->mac.ops.enable_rx_buff(hw);
2202 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2203 * @hw: pointer to hardware structure
2205 * Verifies that installed the firmware version is 0.6 or higher
2206 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2208 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2209 * if the FW version is not supported.
2211 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2213 s32 status = IXGBE_ERR_EEPROM_VERSION;
2214 u16 fw_offset, fw_ptp_cfg_offset;
2218 /* firmware check is only necessary for SFI devices */
2219 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2221 goto fw_version_out;
2224 /* get the offset to the Firmware Module block */
2225 offset = IXGBE_FW_PTR;
2226 if (hw->eeprom.ops.read(hw, offset, &fw_offset))
2227 goto fw_version_err;
2229 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2230 goto fw_version_out;
2232 /* get the offset to the Pass Through Patch Configuration block */
2233 offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR;
2234 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset))
2235 goto fw_version_err;
2237 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2238 goto fw_version_out;
2240 /* get the firmware version */
2241 offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4;
2242 if (hw->eeprom.ops.read(hw, offset, &fw_version))
2243 goto fw_version_err;
2245 if (fw_version > 0x5)
2252 hw_err(hw, "eeprom read at offset %d failed\n", offset);
2253 return IXGBE_ERR_EEPROM_VERSION;
2257 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2258 * @hw: pointer to hardware structure
2260 * Returns true if the LESM FW module is present and enabled. Otherwise
2261 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2263 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2265 bool lesm_enabled = false;
2266 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2269 /* get the offset to the Firmware Module block */
2270 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2272 if ((status != 0) ||
2273 (fw_offset == 0) || (fw_offset == 0xFFFF))
2276 /* get the offset to the LESM Parameters block */
2277 status = hw->eeprom.ops.read(hw, (fw_offset +
2278 IXGBE_FW_LESM_PARAMETERS_PTR),
2279 &fw_lesm_param_offset);
2281 if ((status != 0) ||
2282 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2285 /* get the lesm state word */
2286 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2287 IXGBE_FW_LESM_STATE_1),
2290 if ((status == 0) &&
2291 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2292 lesm_enabled = true;
2295 return lesm_enabled;
2299 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2300 * fastest available method
2302 * @hw: pointer to hardware structure
2303 * @offset: offset of word in EEPROM to read
2304 * @words: number of words
2305 * @data: word(s) read from the EEPROM
2307 * Retrieves 16 bit word(s) read from EEPROM
2309 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2310 u16 words, u16 *data)
2312 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2313 s32 ret_val = IXGBE_ERR_CONFIG;
2316 * If EEPROM is detected and can be addressed using 14 bits,
2317 * use EERD otherwise use bit bang
2319 if ((eeprom->type == ixgbe_eeprom_spi) &&
2320 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2321 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2324 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2332 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2333 * fastest available method
2335 * @hw: pointer to hardware structure
2336 * @offset: offset of word in the EEPROM to read
2337 * @data: word read from the EEPROM
2339 * Reads a 16 bit word from the EEPROM
2341 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2342 u16 offset, u16 *data)
2344 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2345 s32 ret_val = IXGBE_ERR_CONFIG;
2348 * If EEPROM is detected and can be addressed using 14 bits,
2349 * use EERD otherwise use bit bang
2351 if ((eeprom->type == ixgbe_eeprom_spi) &&
2352 (offset <= IXGBE_EERD_MAX_ADDR))
2353 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2355 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2361 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2363 * @hw: pointer to hardware structure
2365 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2366 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2367 * to AUTOC, so this function assumes the semaphore is held.
2369 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2373 u32 i, autoc_reg, autoc2_reg;
2375 /* Enable link if disabled in NVM */
2376 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2377 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2378 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2379 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2380 IXGBE_WRITE_FLUSH(hw);
2383 autoc_reg = hw->mac.cached_autoc;
2384 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2386 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2387 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2389 /* Wait for AN to leave state 0 */
2390 for (i = 0; i < 10; i++) {
2391 usleep_range(4000, 8000);
2392 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2393 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2397 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2398 hw_dbg(hw, "auto negotiation not completed\n");
2399 ret_val = IXGBE_ERR_RESET_FAILED;
2400 goto reset_pipeline_out;
2406 /* Write AUTOC register with original LMS field and Restart_AN */
2407 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2408 IXGBE_WRITE_FLUSH(hw);
2414 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2415 * @hw: pointer to hardware structure
2416 * @byte_offset: byte offset to read
2419 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2420 * a specified device address.
2422 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2423 u8 dev_addr, u8 *data)
2429 if (hw->phy.qsfp_shared_i2c_bus == true) {
2430 /* Acquire I2C bus ownership. */
2431 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2432 esdp |= IXGBE_ESDP_SDP0;
2433 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2434 IXGBE_WRITE_FLUSH(hw);
2437 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2438 if (esdp & IXGBE_ESDP_SDP1)
2441 usleep_range(5000, 10000);
2446 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");
2447 status = IXGBE_ERR_I2C;
2448 goto release_i2c_access;
2452 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2455 if (hw->phy.qsfp_shared_i2c_bus == true) {
2456 /* Release I2C bus ownership. */
2457 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2458 esdp &= ~IXGBE_ESDP_SDP0;
2459 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2460 IXGBE_WRITE_FLUSH(hw);
2467 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2468 * @hw: pointer to hardware structure
2469 * @byte_offset: byte offset to write
2470 * @data: value to write
2472 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2473 * a specified device address.
2475 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2476 u8 dev_addr, u8 data)
2482 if (hw->phy.qsfp_shared_i2c_bus == true) {
2483 /* Acquire I2C bus ownership. */
2484 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2485 esdp |= IXGBE_ESDP_SDP0;
2486 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2487 IXGBE_WRITE_FLUSH(hw);
2490 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2491 if (esdp & IXGBE_ESDP_SDP1)
2494 usleep_range(5000, 10000);
2499 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");
2500 status = IXGBE_ERR_I2C;
2501 goto release_i2c_access;
2505 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2508 if (hw->phy.qsfp_shared_i2c_bus == true) {
2509 /* Release I2C bus ownership. */
2510 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2511 esdp &= ~IXGBE_ESDP_SDP0;
2512 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2513 IXGBE_WRITE_FLUSH(hw);
2519 static struct ixgbe_mac_operations mac_ops_82599 = {
2520 .init_hw = &ixgbe_init_hw_generic,
2521 .reset_hw = &ixgbe_reset_hw_82599,
2522 .start_hw = &ixgbe_start_hw_82599,
2523 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2524 .get_media_type = &ixgbe_get_media_type_82599,
2525 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2526 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2527 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
2528 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
2529 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2530 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2531 .get_device_caps = &ixgbe_get_device_caps_generic,
2532 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2533 .stop_adapter = &ixgbe_stop_adapter_generic,
2534 .get_bus_info = &ixgbe_get_bus_info_generic,
2535 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2536 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2537 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2538 .stop_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599,
2539 .setup_link = &ixgbe_setup_mac_link_82599,
2540 .set_rxpba = &ixgbe_set_rxpba_generic,
2541 .check_link = &ixgbe_check_mac_link_generic,
2542 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2543 .led_on = &ixgbe_led_on_generic,
2544 .led_off = &ixgbe_led_off_generic,
2545 .blink_led_start = &ixgbe_blink_led_start_generic,
2546 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2547 .set_rar = &ixgbe_set_rar_generic,
2548 .clear_rar = &ixgbe_clear_rar_generic,
2549 .set_vmdq = &ixgbe_set_vmdq_generic,
2550 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
2551 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2552 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2553 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2554 .enable_mc = &ixgbe_enable_mc_generic,
2555 .disable_mc = &ixgbe_disable_mc_generic,
2556 .clear_vfta = &ixgbe_clear_vfta_generic,
2557 .set_vfta = &ixgbe_set_vfta_generic,
2558 .fc_enable = &ixgbe_fc_enable_generic,
2559 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2560 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2561 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2562 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2563 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2564 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2565 .release_swfw_sync = &ixgbe_release_swfw_sync,
2566 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic,
2567 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,
2568 .mng_fw_enabled = &ixgbe_mng_enabled,
2571 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2572 .init_params = &ixgbe_init_eeprom_params_generic,
2573 .read = &ixgbe_read_eeprom_82599,
2574 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2575 .write = &ixgbe_write_eeprom_generic,
2576 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2577 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2578 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2579 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2582 static struct ixgbe_phy_operations phy_ops_82599 = {
2583 .identify = &ixgbe_identify_phy_82599,
2584 .identify_sfp = &ixgbe_identify_module_generic,
2585 .init = &ixgbe_init_phy_ops_82599,
2586 .reset = &ixgbe_reset_phy_generic,
2587 .read_reg = &ixgbe_read_phy_reg_generic,
2588 .write_reg = &ixgbe_write_phy_reg_generic,
2589 .setup_link = &ixgbe_setup_phy_link_generic,
2590 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2591 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2592 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2593 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
2594 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2595 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2596 .check_overtemp = &ixgbe_tn_check_overtemp,
2599 struct ixgbe_info ixgbe_82599_info = {
2600 .mac = ixgbe_mac_82599EB,
2601 .get_invariants = &ixgbe_get_invariants_82599,
2602 .mac_ops = &mac_ops_82599,
2603 .eeprom_ops = &eeprom_ops_82599,
2604 .phy_ops = &phy_ops_82599,
2605 .mbx_ops = &mbx_ops_generic,