1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 #include <linux/netdevice.h>
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
37 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
38 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
40 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
44 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
49 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
50 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
51 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
52 u16 words, u16 *data);
53 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
54 u16 words, u16 *data);
55 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
57 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
60 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
62 * @hw: pointer to hardware structure
64 * There are several phys that do not support autoneg flow control. This
65 * function check the device id to see if the associated phy supports
66 * autoneg flow control.
68 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
71 switch (hw->device_id) {
72 case IXGBE_DEV_ID_X540T:
74 case IXGBE_DEV_ID_82599_T3_LOM:
77 return IXGBE_ERR_FC_NOT_SUPPORTED;
82 * ixgbe_setup_fc - Set up flow control
83 * @hw: pointer to hardware structure
85 * Called at init time to set up flow control.
87 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
90 u32 reg = 0, reg_bp = 0;
94 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
95 hw->fc.current_mode = hw->fc.requested_mode;
99 #endif /* CONFIG_DCB */
100 /* Validate the packetbuf configuration */
101 if (packetbuf_num < 0 || packetbuf_num > 7) {
102 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is 0-7\n",
104 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
109 * Validate the water mark configuration. Zero water marks are invalid
110 * because it causes the controller to just blast out fc packets.
112 if (!hw->fc.low_water ||
113 !hw->fc.high_water[packetbuf_num] ||
114 !hw->fc.pause_time) {
115 hw_dbg(hw, "Invalid water mark configuration\n");
116 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
121 * Validate the requested mode. Strict IEEE mode does not allow
122 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
124 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
125 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
126 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
131 * 10gig parts do not have a word in the EEPROM to determine the
132 * default flow control setting, so we explicitly set it to full.
134 if (hw->fc.requested_mode == ixgbe_fc_default)
135 hw->fc.requested_mode = ixgbe_fc_full;
138 * Set up the 1G and 10G flow control advertisement registers so the
139 * HW will be able to do fc autoneg once the cable is plugged in. If
140 * we link at 10G, the 1G advertisement is harmless and vice versa.
143 switch (hw->phy.media_type) {
144 case ixgbe_media_type_fiber:
145 case ixgbe_media_type_backplane:
146 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
147 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
150 case ixgbe_media_type_copper:
151 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
152 MDIO_MMD_AN, ®_cu);
160 * The possible values of fc.requested_mode are:
161 * 0: Flow control is completely disabled
162 * 1: Rx flow control is enabled (we can receive pause frames,
163 * but not send pause frames).
164 * 2: Tx flow control is enabled (we can send pause frames but
165 * we do not support receiving pause frames).
166 * 3: Both Rx and Tx flow control (symmetric) are enabled.
168 * 4: Priority Flow Control is enabled.
172 switch (hw->fc.requested_mode) {
174 /* Flow control completely disabled by software override. */
175 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
176 if (hw->phy.media_type == ixgbe_media_type_backplane)
177 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
178 IXGBE_AUTOC_ASM_PAUSE);
179 else if (hw->phy.media_type == ixgbe_media_type_copper)
180 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
182 case ixgbe_fc_rx_pause:
184 * Rx Flow control is enabled and Tx Flow control is
185 * disabled by software override. Since there really
186 * isn't a way to advertise that we are capable of RX
187 * Pause ONLY, we will advertise that we support both
188 * symmetric and asymmetric Rx PAUSE. Later, we will
189 * disable the adapter's ability to send PAUSE frames.
191 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
192 if (hw->phy.media_type == ixgbe_media_type_backplane)
193 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
194 IXGBE_AUTOC_ASM_PAUSE);
195 else if (hw->phy.media_type == ixgbe_media_type_copper)
196 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
198 case ixgbe_fc_tx_pause:
200 * Tx Flow control is enabled, and Rx Flow control is
201 * disabled by software override.
203 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
204 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
205 if (hw->phy.media_type == ixgbe_media_type_backplane) {
206 reg_bp |= (IXGBE_AUTOC_ASM_PAUSE);
207 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE);
208 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
209 reg_cu |= (IXGBE_TAF_ASM_PAUSE);
210 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE);
214 /* Flow control (both Rx and Tx) is enabled by SW override. */
215 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
216 if (hw->phy.media_type == ixgbe_media_type_backplane)
217 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
218 IXGBE_AUTOC_ASM_PAUSE);
219 else if (hw->phy.media_type == ixgbe_media_type_copper)
220 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
226 #endif /* CONFIG_DCB */
228 hw_dbg(hw, "Flow control param set incorrectly\n");
229 ret_val = IXGBE_ERR_CONFIG;
234 if (hw->mac.type != ixgbe_mac_X540) {
236 * Enable auto-negotiation between the MAC & PHY;
237 * the MAC will advertise clause 37 flow control.
239 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
240 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
242 /* Disable AN timeout */
243 if (hw->fc.strict_ieee)
244 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
246 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
247 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
251 * AUTOC restart handles negotiation of 1G and 10G on backplane
252 * and copper. There is no need to set the PCS1GCTL register.
255 if (hw->phy.media_type == ixgbe_media_type_backplane) {
256 reg_bp |= IXGBE_AUTOC_AN_RESTART;
257 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
258 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
259 (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
260 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
261 MDIO_MMD_AN, reg_cu);
264 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
270 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
271 * @hw: pointer to hardware structure
273 * Starts the hardware by filling the bus info structure and media type, clears
274 * all on chip counters, initializes receive address registers, multicast
275 * table, VLAN filter table, calls routine to set up link and flow control
276 * settings, and leaves transmit and receive units disabled and uninitialized
278 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
282 /* Set the media type */
283 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
285 /* Identify the PHY */
286 hw->phy.ops.identify(hw);
288 /* Clear the VLAN filter table */
289 hw->mac.ops.clear_vfta(hw);
291 /* Clear statistics registers */
292 hw->mac.ops.clear_hw_cntrs(hw);
294 /* Set No Snoop Disable */
295 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
296 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
297 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
298 IXGBE_WRITE_FLUSH(hw);
300 /* Setup flow control */
301 ixgbe_setup_fc(hw, 0);
303 /* Clear adapter stopped flag */
304 hw->adapter_stopped = false;
310 * ixgbe_start_hw_gen2 - Init sequence for common device family
311 * @hw: pointer to hw structure
313 * Performs the init sequence common to the second generation
315 * Devices in the second generation:
319 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
324 /* Clear the rate limiters */
325 for (i = 0; i < hw->mac.max_tx_queues; i++) {
326 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
327 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
329 IXGBE_WRITE_FLUSH(hw);
331 /* Disable relaxed ordering */
332 for (i = 0; i < hw->mac.max_tx_queues; i++) {
333 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
334 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
335 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
338 for (i = 0; i < hw->mac.max_rx_queues; i++) {
339 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
340 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
341 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
342 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
349 * ixgbe_init_hw_generic - Generic hardware initialization
350 * @hw: pointer to hardware structure
352 * Initialize the hardware by resetting the hardware, filling the bus info
353 * structure and media type, clears all on chip counters, initializes receive
354 * address registers, multicast table, VLAN filter table, calls routine to set
355 * up link and flow control settings, and leaves transmit and receive units
356 * disabled and uninitialized
358 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
362 /* Reset the hardware */
363 status = hw->mac.ops.reset_hw(hw);
367 status = hw->mac.ops.start_hw(hw);
374 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
375 * @hw: pointer to hardware structure
377 * Clears all hardware statistics counters by reading them from the hardware
378 * Statistics counters are clear on read.
380 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
384 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
385 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
386 IXGBE_READ_REG(hw, IXGBE_ERRBC);
387 IXGBE_READ_REG(hw, IXGBE_MSPDC);
388 for (i = 0; i < 8; i++)
389 IXGBE_READ_REG(hw, IXGBE_MPC(i));
391 IXGBE_READ_REG(hw, IXGBE_MLFC);
392 IXGBE_READ_REG(hw, IXGBE_MRFC);
393 IXGBE_READ_REG(hw, IXGBE_RLEC);
394 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
395 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
396 if (hw->mac.type >= ixgbe_mac_82599EB) {
397 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
398 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
400 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
401 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
404 for (i = 0; i < 8; i++) {
405 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
406 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
407 if (hw->mac.type >= ixgbe_mac_82599EB) {
408 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
409 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
411 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
412 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
415 if (hw->mac.type >= ixgbe_mac_82599EB)
416 for (i = 0; i < 8; i++)
417 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
418 IXGBE_READ_REG(hw, IXGBE_PRC64);
419 IXGBE_READ_REG(hw, IXGBE_PRC127);
420 IXGBE_READ_REG(hw, IXGBE_PRC255);
421 IXGBE_READ_REG(hw, IXGBE_PRC511);
422 IXGBE_READ_REG(hw, IXGBE_PRC1023);
423 IXGBE_READ_REG(hw, IXGBE_PRC1522);
424 IXGBE_READ_REG(hw, IXGBE_GPRC);
425 IXGBE_READ_REG(hw, IXGBE_BPRC);
426 IXGBE_READ_REG(hw, IXGBE_MPRC);
427 IXGBE_READ_REG(hw, IXGBE_GPTC);
428 IXGBE_READ_REG(hw, IXGBE_GORCL);
429 IXGBE_READ_REG(hw, IXGBE_GORCH);
430 IXGBE_READ_REG(hw, IXGBE_GOTCL);
431 IXGBE_READ_REG(hw, IXGBE_GOTCH);
432 if (hw->mac.type == ixgbe_mac_82598EB)
433 for (i = 0; i < 8; i++)
434 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
435 IXGBE_READ_REG(hw, IXGBE_RUC);
436 IXGBE_READ_REG(hw, IXGBE_RFC);
437 IXGBE_READ_REG(hw, IXGBE_ROC);
438 IXGBE_READ_REG(hw, IXGBE_RJC);
439 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
440 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
441 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
442 IXGBE_READ_REG(hw, IXGBE_TORL);
443 IXGBE_READ_REG(hw, IXGBE_TORH);
444 IXGBE_READ_REG(hw, IXGBE_TPR);
445 IXGBE_READ_REG(hw, IXGBE_TPT);
446 IXGBE_READ_REG(hw, IXGBE_PTC64);
447 IXGBE_READ_REG(hw, IXGBE_PTC127);
448 IXGBE_READ_REG(hw, IXGBE_PTC255);
449 IXGBE_READ_REG(hw, IXGBE_PTC511);
450 IXGBE_READ_REG(hw, IXGBE_PTC1023);
451 IXGBE_READ_REG(hw, IXGBE_PTC1522);
452 IXGBE_READ_REG(hw, IXGBE_MPTC);
453 IXGBE_READ_REG(hw, IXGBE_BPTC);
454 for (i = 0; i < 16; i++) {
455 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
456 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
457 if (hw->mac.type >= ixgbe_mac_82599EB) {
458 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
459 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
460 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
461 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
462 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
464 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
465 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
469 if (hw->mac.type == ixgbe_mac_X540) {
471 hw->phy.ops.identify(hw);
472 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
473 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
474 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
475 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
482 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
483 * @hw: pointer to hardware structure
484 * @pba_num: stores the part number string from the EEPROM
485 * @pba_num_size: part number string buffer length
487 * Reads the part number string from the EEPROM.
489 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
498 if (pba_num == NULL) {
499 hw_dbg(hw, "PBA string buffer was null\n");
500 return IXGBE_ERR_INVALID_ARGUMENT;
503 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
505 hw_dbg(hw, "NVM Read Error\n");
509 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
511 hw_dbg(hw, "NVM Read Error\n");
516 * if data is not ptr guard the PBA must be in legacy format which
517 * means pba_ptr is actually our second data word for the PBA number
518 * and we can decode it into an ascii string
520 if (data != IXGBE_PBANUM_PTR_GUARD) {
521 hw_dbg(hw, "NVM PBA number is not stored as string\n");
523 /* we will need 11 characters to store the PBA */
524 if (pba_num_size < 11) {
525 hw_dbg(hw, "PBA string buffer too small\n");
526 return IXGBE_ERR_NO_SPACE;
529 /* extract hex string from data and pba_ptr */
530 pba_num[0] = (data >> 12) & 0xF;
531 pba_num[1] = (data >> 8) & 0xF;
532 pba_num[2] = (data >> 4) & 0xF;
533 pba_num[3] = data & 0xF;
534 pba_num[4] = (pba_ptr >> 12) & 0xF;
535 pba_num[5] = (pba_ptr >> 8) & 0xF;
538 pba_num[8] = (pba_ptr >> 4) & 0xF;
539 pba_num[9] = pba_ptr & 0xF;
541 /* put a null character on the end of our string */
544 /* switch all the data but the '-' to hex char */
545 for (offset = 0; offset < 10; offset++) {
546 if (pba_num[offset] < 0xA)
547 pba_num[offset] += '0';
548 else if (pba_num[offset] < 0x10)
549 pba_num[offset] += 'A' - 0xA;
555 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
557 hw_dbg(hw, "NVM Read Error\n");
561 if (length == 0xFFFF || length == 0) {
562 hw_dbg(hw, "NVM PBA number section invalid length\n");
563 return IXGBE_ERR_PBA_SECTION;
566 /* check if pba_num buffer is big enough */
567 if (pba_num_size < (((u32)length * 2) - 1)) {
568 hw_dbg(hw, "PBA string buffer too small\n");
569 return IXGBE_ERR_NO_SPACE;
572 /* trim pba length from start of string */
576 for (offset = 0; offset < length; offset++) {
577 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
579 hw_dbg(hw, "NVM Read Error\n");
582 pba_num[offset * 2] = (u8)(data >> 8);
583 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
585 pba_num[offset * 2] = '\0';
591 * ixgbe_get_mac_addr_generic - Generic get MAC address
592 * @hw: pointer to hardware structure
593 * @mac_addr: Adapter MAC address
595 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
596 * A reset of the adapter must be performed prior to calling this function
597 * in order for the MAC address to have been loaded from the EEPROM into RAR0
599 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
605 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
606 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
608 for (i = 0; i < 4; i++)
609 mac_addr[i] = (u8)(rar_low >> (i*8));
611 for (i = 0; i < 2; i++)
612 mac_addr[i+4] = (u8)(rar_high >> (i*8));
618 * ixgbe_get_bus_info_generic - Generic set PCI bus info
619 * @hw: pointer to hardware structure
621 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
623 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
625 struct ixgbe_adapter *adapter = hw->back;
626 struct ixgbe_mac_info *mac = &hw->mac;
629 hw->bus.type = ixgbe_bus_type_pci_express;
631 /* Get the negotiated link width and speed from PCI config space */
632 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
635 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
636 case IXGBE_PCI_LINK_WIDTH_1:
637 hw->bus.width = ixgbe_bus_width_pcie_x1;
639 case IXGBE_PCI_LINK_WIDTH_2:
640 hw->bus.width = ixgbe_bus_width_pcie_x2;
642 case IXGBE_PCI_LINK_WIDTH_4:
643 hw->bus.width = ixgbe_bus_width_pcie_x4;
645 case IXGBE_PCI_LINK_WIDTH_8:
646 hw->bus.width = ixgbe_bus_width_pcie_x8;
649 hw->bus.width = ixgbe_bus_width_unknown;
653 switch (link_status & IXGBE_PCI_LINK_SPEED) {
654 case IXGBE_PCI_LINK_SPEED_2500:
655 hw->bus.speed = ixgbe_bus_speed_2500;
657 case IXGBE_PCI_LINK_SPEED_5000:
658 hw->bus.speed = ixgbe_bus_speed_5000;
661 hw->bus.speed = ixgbe_bus_speed_unknown;
665 mac->ops.set_lan_id(hw);
671 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
672 * @hw: pointer to the HW structure
674 * Determines the LAN function id by reading memory-mapped registers
675 * and swaps the port value if requested.
677 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
679 struct ixgbe_bus_info *bus = &hw->bus;
682 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
683 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
684 bus->lan_id = bus->func;
686 /* check for a port swap */
687 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
688 if (reg & IXGBE_FACTPS_LFS)
693 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
694 * @hw: pointer to hardware structure
696 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
697 * disables transmit and receive units. The adapter_stopped flag is used by
698 * the shared code and drivers to determine if the adapter is in a stopped
699 * state and should not touch the hardware.
701 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
707 * Set the adapter_stopped flag so other driver functions stop touching
710 hw->adapter_stopped = true;
712 /* Disable the receive unit */
713 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
715 /* Clear interrupt mask to stop interrupts from being generated */
716 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
718 /* Clear any pending interrupts, flush previous writes */
719 IXGBE_READ_REG(hw, IXGBE_EICR);
721 /* Disable the transmit unit. Each queue must be disabled. */
722 for (i = 0; i < hw->mac.max_tx_queues; i++)
723 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
725 /* Disable the receive unit by stopping each queue */
726 for (i = 0; i < hw->mac.max_rx_queues; i++) {
727 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
728 reg_val &= ~IXGBE_RXDCTL_ENABLE;
729 reg_val |= IXGBE_RXDCTL_SWFLSH;
730 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
733 /* flush all queues disables */
734 IXGBE_WRITE_FLUSH(hw);
735 usleep_range(1000, 2000);
738 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
739 * access and verify no pending requests
741 return ixgbe_disable_pcie_master(hw);
745 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
746 * @hw: pointer to hardware structure
747 * @index: led number to turn on
749 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
751 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
753 /* To turn on the LED, set mode to ON. */
754 led_reg &= ~IXGBE_LED_MODE_MASK(index);
755 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
756 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
757 IXGBE_WRITE_FLUSH(hw);
763 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
764 * @hw: pointer to hardware structure
765 * @index: led number to turn off
767 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
769 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
771 /* To turn off the LED, set mode to OFF. */
772 led_reg &= ~IXGBE_LED_MODE_MASK(index);
773 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
774 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
775 IXGBE_WRITE_FLUSH(hw);
781 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
782 * @hw: pointer to hardware structure
784 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
785 * ixgbe_hw struct in order to set up EEPROM access.
787 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
789 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
793 if (eeprom->type == ixgbe_eeprom_uninitialized) {
794 eeprom->type = ixgbe_eeprom_none;
795 /* Set default semaphore delay to 10ms which is a well
797 eeprom->semaphore_delay = 10;
798 /* Clear EEPROM page size, it will be initialized as needed */
799 eeprom->word_page_size = 0;
802 * Check for EEPROM present first.
803 * If not present leave as none
805 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
806 if (eec & IXGBE_EEC_PRES) {
807 eeprom->type = ixgbe_eeprom_spi;
810 * SPI EEPROM is assumed here. This code would need to
811 * change if a future EEPROM is not SPI.
813 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
814 IXGBE_EEC_SIZE_SHIFT);
815 eeprom->word_size = 1 << (eeprom_size +
816 IXGBE_EEPROM_WORD_SIZE_SHIFT);
819 if (eec & IXGBE_EEC_ADDR_SIZE)
820 eeprom->address_bits = 16;
822 eeprom->address_bits = 8;
823 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
824 "%d\n", eeprom->type, eeprom->word_size,
825 eeprom->address_bits);
832 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
833 * @hw: pointer to hardware structure
834 * @offset: offset within the EEPROM to write
835 * @words: number of words
836 * @data: 16 bit word(s) to write to EEPROM
838 * Reads 16 bit word(s) from EEPROM through bit-bang method
840 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
841 u16 words, u16 *data)
846 hw->eeprom.ops.init_params(hw);
849 status = IXGBE_ERR_INVALID_ARGUMENT;
853 if (offset + words > hw->eeprom.word_size) {
854 status = IXGBE_ERR_EEPROM;
859 * The EEPROM page size cannot be queried from the chip. We do lazy
860 * initialization. It is worth to do that when we write large buffer.
862 if ((hw->eeprom.word_page_size == 0) &&
863 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
864 ixgbe_detect_eeprom_page_size_generic(hw, offset);
867 * We cannot hold synchronization semaphores for too long
868 * to avoid other entity starvation. However it is more efficient
869 * to read in bursts than synchronizing access for each word.
871 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
872 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
873 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
874 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
886 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
887 * @hw: pointer to hardware structure
888 * @offset: offset within the EEPROM to be written to
889 * @words: number of word(s)
890 * @data: 16 bit word(s) to be written to the EEPROM
892 * If ixgbe_eeprom_update_checksum is not called after this function, the
893 * EEPROM will most likely contain an invalid checksum.
895 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
896 u16 words, u16 *data)
902 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
904 /* Prepare the EEPROM for writing */
905 status = ixgbe_acquire_eeprom(hw);
908 if (ixgbe_ready_eeprom(hw) != 0) {
909 ixgbe_release_eeprom(hw);
910 status = IXGBE_ERR_EEPROM;
915 for (i = 0; i < words; i++) {
916 ixgbe_standby_eeprom(hw);
918 /* Send the WRITE ENABLE command (8 bit opcode ) */
919 ixgbe_shift_out_eeprom_bits(hw,
920 IXGBE_EEPROM_WREN_OPCODE_SPI,
921 IXGBE_EEPROM_OPCODE_BITS);
923 ixgbe_standby_eeprom(hw);
926 * Some SPI eeproms use the 8th address bit embedded
929 if ((hw->eeprom.address_bits == 8) &&
930 ((offset + i) >= 128))
931 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
933 /* Send the Write command (8-bit opcode + addr) */
934 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
935 IXGBE_EEPROM_OPCODE_BITS);
936 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
937 hw->eeprom.address_bits);
939 page_size = hw->eeprom.word_page_size;
941 /* Send the data in burst via SPI*/
944 word = (word >> 8) | (word << 8);
945 ixgbe_shift_out_eeprom_bits(hw, word, 16);
950 /* do not wrap around page */
951 if (((offset + i) & (page_size - 1)) ==
954 } while (++i < words);
956 ixgbe_standby_eeprom(hw);
957 usleep_range(10000, 20000);
959 /* Done with writing - release the EEPROM */
960 ixgbe_release_eeprom(hw);
967 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
968 * @hw: pointer to hardware structure
969 * @offset: offset within the EEPROM to be written to
970 * @data: 16 bit word to be written to the EEPROM
972 * If ixgbe_eeprom_update_checksum is not called after this function, the
973 * EEPROM will most likely contain an invalid checksum.
975 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
979 hw->eeprom.ops.init_params(hw);
981 if (offset >= hw->eeprom.word_size) {
982 status = IXGBE_ERR_EEPROM;
986 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
993 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
994 * @hw: pointer to hardware structure
995 * @offset: offset within the EEPROM to be read
996 * @words: number of word(s)
997 * @data: read 16 bit words(s) from EEPROM
999 * Reads 16 bit word(s) from EEPROM through bit-bang method
1001 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1002 u16 words, u16 *data)
1007 hw->eeprom.ops.init_params(hw);
1010 status = IXGBE_ERR_INVALID_ARGUMENT;
1014 if (offset + words > hw->eeprom.word_size) {
1015 status = IXGBE_ERR_EEPROM;
1020 * We cannot hold synchronization semaphores for too long
1021 * to avoid other entity starvation. However it is more efficient
1022 * to read in bursts than synchronizing access for each word.
1024 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1025 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1026 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1028 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1040 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1041 * @hw: pointer to hardware structure
1042 * @offset: offset within the EEPROM to be read
1043 * @words: number of word(s)
1044 * @data: read 16 bit word(s) from EEPROM
1046 * Reads 16 bit word(s) from EEPROM through bit-bang method
1048 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1049 u16 words, u16 *data)
1053 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1056 /* Prepare the EEPROM for reading */
1057 status = ixgbe_acquire_eeprom(hw);
1060 if (ixgbe_ready_eeprom(hw) != 0) {
1061 ixgbe_release_eeprom(hw);
1062 status = IXGBE_ERR_EEPROM;
1067 for (i = 0; i < words; i++) {
1068 ixgbe_standby_eeprom(hw);
1070 * Some SPI eeproms use the 8th address bit embedded
1073 if ((hw->eeprom.address_bits == 8) &&
1074 ((offset + i) >= 128))
1075 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1077 /* Send the READ command (opcode + addr) */
1078 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1079 IXGBE_EEPROM_OPCODE_BITS);
1080 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1081 hw->eeprom.address_bits);
1083 /* Read the data. */
1084 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1085 data[i] = (word_in >> 8) | (word_in << 8);
1088 /* End this read operation */
1089 ixgbe_release_eeprom(hw);
1096 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1097 * @hw: pointer to hardware structure
1098 * @offset: offset within the EEPROM to be read
1099 * @data: read 16 bit value from EEPROM
1101 * Reads 16 bit value from EEPROM through bit-bang method
1103 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1108 hw->eeprom.ops.init_params(hw);
1110 if (offset >= hw->eeprom.word_size) {
1111 status = IXGBE_ERR_EEPROM;
1115 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1122 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1123 * @hw: pointer to hardware structure
1124 * @offset: offset of word in the EEPROM to read
1125 * @words: number of word(s)
1126 * @data: 16 bit word(s) from the EEPROM
1128 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1130 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1131 u16 words, u16 *data)
1137 hw->eeprom.ops.init_params(hw);
1140 status = IXGBE_ERR_INVALID_ARGUMENT;
1144 if (offset >= hw->eeprom.word_size) {
1145 status = IXGBE_ERR_EEPROM;
1149 for (i = 0; i < words; i++) {
1150 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
1151 IXGBE_EEPROM_RW_REG_START;
1153 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1154 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1157 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1158 IXGBE_EEPROM_RW_REG_DATA);
1160 hw_dbg(hw, "Eeprom read timed out\n");
1169 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1170 * @hw: pointer to hardware structure
1171 * @offset: offset within the EEPROM to be used as a scratch pad
1173 * Discover EEPROM page size by writing marching data at given offset.
1174 * This function is called only when we are writing a new large buffer
1175 * at given offset so the data would be overwritten anyway.
1177 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1180 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1184 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1187 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1188 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1189 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1190 hw->eeprom.word_page_size = 0;
1194 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1199 * When writing in burst more than the actual page size
1200 * EEPROM address wraps around current page.
1202 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1204 hw_dbg(hw, "Detected EEPROM page size = %d words.",
1205 hw->eeprom.word_page_size);
1211 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1212 * @hw: pointer to hardware structure
1213 * @offset: offset of word in the EEPROM to read
1214 * @data: word read from the EEPROM
1216 * Reads a 16 bit word from the EEPROM using the EERD register.
1218 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1220 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1224 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1225 * @hw: pointer to hardware structure
1226 * @offset: offset of word in the EEPROM to write
1227 * @words: number of words
1228 * @data: word(s) write to the EEPROM
1230 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1232 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1233 u16 words, u16 *data)
1239 hw->eeprom.ops.init_params(hw);
1242 status = IXGBE_ERR_INVALID_ARGUMENT;
1246 if (offset >= hw->eeprom.word_size) {
1247 status = IXGBE_ERR_EEPROM;
1251 for (i = 0; i < words; i++) {
1252 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1253 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1254 IXGBE_EEPROM_RW_REG_START;
1256 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1258 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1262 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1264 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1266 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1276 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1277 * @hw: pointer to hardware structure
1278 * @offset: offset of word in the EEPROM to write
1279 * @data: word write to the EEPROM
1281 * Write a 16 bit word to the EEPROM using the EEWR register.
1283 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1285 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1289 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1290 * @hw: pointer to hardware structure
1291 * @ee_reg: EEPROM flag for polling
1293 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1294 * read or write is done respectively.
1296 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1300 s32 status = IXGBE_ERR_EEPROM;
1302 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1303 if (ee_reg == IXGBE_NVM_POLL_READ)
1304 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1306 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1308 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1318 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1319 * @hw: pointer to hardware structure
1321 * Prepares EEPROM for access using bit-bang method. This function should
1322 * be called before issuing a command to the EEPROM.
1324 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1330 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
1331 status = IXGBE_ERR_SWFW_SYNC;
1334 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1336 /* Request EEPROM Access */
1337 eec |= IXGBE_EEC_REQ;
1338 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1340 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1341 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1342 if (eec & IXGBE_EEC_GNT)
1347 /* Release if grant not acquired */
1348 if (!(eec & IXGBE_EEC_GNT)) {
1349 eec &= ~IXGBE_EEC_REQ;
1350 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1351 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1353 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1354 status = IXGBE_ERR_EEPROM;
1357 /* Setup EEPROM for Read/Write */
1359 /* Clear CS and SK */
1360 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1361 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1362 IXGBE_WRITE_FLUSH(hw);
1370 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1371 * @hw: pointer to hardware structure
1373 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1375 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1377 s32 status = IXGBE_ERR_EEPROM;
1382 /* Get SMBI software semaphore between device drivers first */
1383 for (i = 0; i < timeout; i++) {
1385 * If the SMBI bit is 0 when we read it, then the bit will be
1386 * set and we have the semaphore
1388 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1389 if (!(swsm & IXGBE_SWSM_SMBI)) {
1397 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1400 * this release is particularly important because our attempts
1401 * above to get the semaphore may have succeeded, and if there
1402 * was a timeout, we should unconditionally clear the semaphore
1403 * bits to free the driver to make progress
1405 ixgbe_release_eeprom_semaphore(hw);
1410 * If the SMBI bit is 0 when we read it, then the bit will be
1411 * set and we have the semaphore
1413 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1414 if (!(swsm & IXGBE_SWSM_SMBI))
1418 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1420 for (i = 0; i < timeout; i++) {
1421 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1423 /* Set the SW EEPROM semaphore bit to request access */
1424 swsm |= IXGBE_SWSM_SWESMBI;
1425 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1428 * If we set the bit successfully then we got the
1431 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1432 if (swsm & IXGBE_SWSM_SWESMBI)
1439 * Release semaphores and return error if SW EEPROM semaphore
1440 * was not granted because we don't have access to the EEPROM
1443 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
1445 ixgbe_release_eeprom_semaphore(hw);
1446 status = IXGBE_ERR_EEPROM;
1449 hw_dbg(hw, "Software semaphore SMBI between device drivers "
1457 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1458 * @hw: pointer to hardware structure
1460 * This function clears hardware semaphore bits.
1462 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1466 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1468 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1469 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1470 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1471 IXGBE_WRITE_FLUSH(hw);
1475 * ixgbe_ready_eeprom - Polls for EEPROM ready
1476 * @hw: pointer to hardware structure
1478 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1485 * Read "Status Register" repeatedly until the LSB is cleared. The
1486 * EEPROM will signal that the command has been completed by clearing
1487 * bit 0 of the internal status register. If it's not cleared within
1488 * 5 milliseconds, then error out.
1490 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1491 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1492 IXGBE_EEPROM_OPCODE_BITS);
1493 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1494 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1498 ixgbe_standby_eeprom(hw);
1502 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1503 * devices (and only 0-5mSec on 5V devices)
1505 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1506 hw_dbg(hw, "SPI EEPROM Status error\n");
1507 status = IXGBE_ERR_EEPROM;
1514 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1515 * @hw: pointer to hardware structure
1517 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1521 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1523 /* Toggle CS to flush commands */
1524 eec |= IXGBE_EEC_CS;
1525 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1526 IXGBE_WRITE_FLUSH(hw);
1528 eec &= ~IXGBE_EEC_CS;
1529 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1530 IXGBE_WRITE_FLUSH(hw);
1535 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1536 * @hw: pointer to hardware structure
1537 * @data: data to send to the EEPROM
1538 * @count: number of bits to shift out
1540 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1547 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1550 * Mask is used to shift "count" bits of "data" out to the EEPROM
1551 * one bit at a time. Determine the starting bit based on count
1553 mask = 0x01 << (count - 1);
1555 for (i = 0; i < count; i++) {
1557 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1558 * "1", and then raising and then lowering the clock (the SK
1559 * bit controls the clock input to the EEPROM). A "0" is
1560 * shifted out to the EEPROM by setting "DI" to "0" and then
1561 * raising and then lowering the clock.
1564 eec |= IXGBE_EEC_DI;
1566 eec &= ~IXGBE_EEC_DI;
1568 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1569 IXGBE_WRITE_FLUSH(hw);
1573 ixgbe_raise_eeprom_clk(hw, &eec);
1574 ixgbe_lower_eeprom_clk(hw, &eec);
1577 * Shift mask to signify next bit of data to shift in to the
1583 /* We leave the "DI" bit set to "0" when we leave this routine. */
1584 eec &= ~IXGBE_EEC_DI;
1585 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1586 IXGBE_WRITE_FLUSH(hw);
1590 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1591 * @hw: pointer to hardware structure
1593 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1600 * In order to read a register from the EEPROM, we need to shift
1601 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1602 * the clock input to the EEPROM (setting the SK bit), and then reading
1603 * the value of the "DO" bit. During this "shifting in" process the
1604 * "DI" bit should always be clear.
1606 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1608 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1610 for (i = 0; i < count; i++) {
1612 ixgbe_raise_eeprom_clk(hw, &eec);
1614 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1616 eec &= ~(IXGBE_EEC_DI);
1617 if (eec & IXGBE_EEC_DO)
1620 ixgbe_lower_eeprom_clk(hw, &eec);
1627 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1628 * @hw: pointer to hardware structure
1629 * @eec: EEC register's current value
1631 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1634 * Raise the clock input to the EEPROM
1635 * (setting the SK bit), then delay
1637 *eec = *eec | IXGBE_EEC_SK;
1638 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1639 IXGBE_WRITE_FLUSH(hw);
1644 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1645 * @hw: pointer to hardware structure
1646 * @eecd: EECD's current value
1648 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1651 * Lower the clock input to the EEPROM (clearing the SK bit), then
1654 *eec = *eec & ~IXGBE_EEC_SK;
1655 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1656 IXGBE_WRITE_FLUSH(hw);
1661 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1662 * @hw: pointer to hardware structure
1664 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1668 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1670 eec |= IXGBE_EEC_CS; /* Pull CS high */
1671 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1673 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1674 IXGBE_WRITE_FLUSH(hw);
1678 /* Stop requesting EEPROM access */
1679 eec &= ~IXGBE_EEC_REQ;
1680 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1682 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1685 * Delay before attempt to obtain semaphore again to allow FW
1686 * access. semaphore_delay is in ms we need us for usleep_range
1688 usleep_range(hw->eeprom.semaphore_delay * 1000,
1689 hw->eeprom.semaphore_delay * 2000);
1693 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1694 * @hw: pointer to hardware structure
1696 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1705 /* Include 0x0-0x3F in the checksum */
1706 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1707 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1708 hw_dbg(hw, "EEPROM read failed\n");
1714 /* Include all data from pointers except for the fw pointer */
1715 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1716 hw->eeprom.ops.read(hw, i, &pointer);
1718 /* Make sure the pointer seems valid */
1719 if (pointer != 0xFFFF && pointer != 0) {
1720 hw->eeprom.ops.read(hw, pointer, &length);
1722 if (length != 0xFFFF && length != 0) {
1723 for (j = pointer+1; j <= pointer+length; j++) {
1724 hw->eeprom.ops.read(hw, j, &word);
1731 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1737 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1738 * @hw: pointer to hardware structure
1739 * @checksum_val: calculated checksum
1741 * Performs checksum calculation and validates the EEPROM checksum. If the
1742 * caller does not need checksum_val, the value can be NULL.
1744 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1749 u16 read_checksum = 0;
1752 * Read the first word from the EEPROM. If this times out or fails, do
1753 * not continue or we could be in for a very long wait while every
1756 status = hw->eeprom.ops.read(hw, 0, &checksum);
1759 checksum = hw->eeprom.ops.calc_checksum(hw);
1761 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1764 * Verify read checksum from EEPROM is the same as
1765 * calculated checksum
1767 if (read_checksum != checksum)
1768 status = IXGBE_ERR_EEPROM_CHECKSUM;
1770 /* If the user cares, return the calculated checksum */
1772 *checksum_val = checksum;
1774 hw_dbg(hw, "EEPROM read failed\n");
1781 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1782 * @hw: pointer to hardware structure
1784 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1790 * Read the first word from the EEPROM. If this times out or fails, do
1791 * not continue or we could be in for a very long wait while every
1794 status = hw->eeprom.ops.read(hw, 0, &checksum);
1797 checksum = hw->eeprom.ops.calc_checksum(hw);
1798 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1801 hw_dbg(hw, "EEPROM read failed\n");
1808 * ixgbe_validate_mac_addr - Validate MAC address
1809 * @mac_addr: pointer to MAC address.
1811 * Tests a MAC address to ensure it is a valid Individual Address
1813 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1817 /* Make sure it is not a multicast address */
1818 if (IXGBE_IS_MULTICAST(mac_addr))
1819 status = IXGBE_ERR_INVALID_MAC_ADDR;
1820 /* Not a broadcast address */
1821 else if (IXGBE_IS_BROADCAST(mac_addr))
1822 status = IXGBE_ERR_INVALID_MAC_ADDR;
1823 /* Reject the zero address */
1824 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1825 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
1826 status = IXGBE_ERR_INVALID_MAC_ADDR;
1832 * ixgbe_set_rar_generic - Set Rx address register
1833 * @hw: pointer to hardware structure
1834 * @index: Receive address register to write
1835 * @addr: Address to put into receive address register
1836 * @vmdq: VMDq "set" or "pool" index
1837 * @enable_addr: set flag that address is active
1839 * Puts an ethernet address into a receive address register.
1841 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1844 u32 rar_low, rar_high;
1845 u32 rar_entries = hw->mac.num_rar_entries;
1847 /* Make sure we are using a valid rar index range */
1848 if (index >= rar_entries) {
1849 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1850 return IXGBE_ERR_INVALID_ARGUMENT;
1853 /* setup VMDq pool selection before this RAR gets enabled */
1854 hw->mac.ops.set_vmdq(hw, index, vmdq);
1857 * HW expects these in little endian so we reverse the byte
1858 * order from network order (big endian) to little endian
1860 rar_low = ((u32)addr[0] |
1861 ((u32)addr[1] << 8) |
1862 ((u32)addr[2] << 16) |
1863 ((u32)addr[3] << 24));
1865 * Some parts put the VMDq setting in the extra RAH bits,
1866 * so save everything except the lower 16 bits that hold part
1867 * of the address and the address valid bit.
1869 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1870 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1871 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1873 if (enable_addr != 0)
1874 rar_high |= IXGBE_RAH_AV;
1876 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1877 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1883 * ixgbe_clear_rar_generic - Remove Rx address register
1884 * @hw: pointer to hardware structure
1885 * @index: Receive address register to write
1887 * Clears an ethernet address from a receive address register.
1889 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1892 u32 rar_entries = hw->mac.num_rar_entries;
1894 /* Make sure we are using a valid rar index range */
1895 if (index >= rar_entries) {
1896 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1897 return IXGBE_ERR_INVALID_ARGUMENT;
1901 * Some parts put the VMDq setting in the extra RAH bits,
1902 * so save everything except the lower 16 bits that hold part
1903 * of the address and the address valid bit.
1905 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1906 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1908 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1909 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1911 /* clear VMDq pool/queue selection for this RAR */
1912 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1918 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1919 * @hw: pointer to hardware structure
1921 * Places the MAC address in receive address register 0 and clears the rest
1922 * of the receive address registers. Clears the multicast table. Assumes
1923 * the receiver is in reset when the routine is called.
1925 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1928 u32 rar_entries = hw->mac.num_rar_entries;
1931 * If the current mac address is valid, assume it is a software override
1932 * to the permanent address.
1933 * Otherwise, use the permanent address from the eeprom.
1935 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1936 IXGBE_ERR_INVALID_MAC_ADDR) {
1937 /* Get the MAC address from the RAR0 for later reference */
1938 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1940 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
1942 /* Setup the receive address. */
1943 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1944 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
1946 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1948 /* clear VMDq pool/queue selection for RAR 0 */
1949 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1951 hw->addr_ctrl.overflow_promisc = 0;
1953 hw->addr_ctrl.rar_used_count = 1;
1955 /* Zero out the other receive addresses. */
1956 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1957 for (i = 1; i < rar_entries; i++) {
1958 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1959 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1963 hw->addr_ctrl.mta_in_use = 0;
1964 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1966 hw_dbg(hw, " Clearing MTA\n");
1967 for (i = 0; i < hw->mac.mcft_size; i++)
1968 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1970 if (hw->mac.ops.init_uta_tables)
1971 hw->mac.ops.init_uta_tables(hw);
1977 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1978 * @hw: pointer to hardware structure
1979 * @mc_addr: the multicast address
1981 * Extracts the 12 bits, from a multicast address, to determine which
1982 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1983 * incoming rx multicast addresses, to determine the bit-vector to check in
1984 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1985 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1986 * to mc_filter_type.
1988 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1992 switch (hw->mac.mc_filter_type) {
1993 case 0: /* use bits [47:36] of the address */
1994 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1996 case 1: /* use bits [46:35] of the address */
1997 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1999 case 2: /* use bits [45:34] of the address */
2000 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2002 case 3: /* use bits [43:32] of the address */
2003 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2005 default: /* Invalid mc_filter_type */
2006 hw_dbg(hw, "MC filter type param set incorrectly\n");
2010 /* vector can only be 12-bits or boundary will be exceeded */
2016 * ixgbe_set_mta - Set bit-vector in multicast table
2017 * @hw: pointer to hardware structure
2018 * @hash_value: Multicast address hash value
2020 * Sets the bit-vector in the multicast table.
2022 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2028 hw->addr_ctrl.mta_in_use++;
2030 vector = ixgbe_mta_vector(hw, mc_addr);
2031 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
2034 * The MTA is a register array of 128 32-bit registers. It is treated
2035 * like an array of 4096 bits. We want to set bit
2036 * BitArray[vector_value]. So we figure out what register the bit is
2037 * in, read it, OR in the new bit, then write back the new value. The
2038 * register is determined by the upper 7 bits of the vector value and
2039 * the bit within that register are determined by the lower 5 bits of
2042 vector_reg = (vector >> 5) & 0x7F;
2043 vector_bit = vector & 0x1F;
2044 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2048 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2049 * @hw: pointer to hardware structure
2050 * @netdev: pointer to net device structure
2052 * The given list replaces any existing list. Clears the MC addrs from receive
2053 * address registers and the multicast table. Uses unused receive address
2054 * registers for the first multicast addresses, and hashes the rest into the
2057 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
2058 struct net_device *netdev)
2060 struct netdev_hw_addr *ha;
2064 * Set the new number of MC addresses that we are being requested to
2067 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
2068 hw->addr_ctrl.mta_in_use = 0;
2070 /* Clear mta_shadow */
2071 hw_dbg(hw, " Clearing MTA\n");
2072 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2074 /* Update mta shadow */
2075 netdev_for_each_mc_addr(ha, netdev) {
2076 hw_dbg(hw, " Adding the multicast addresses:\n");
2077 ixgbe_set_mta(hw, ha->addr);
2081 for (i = 0; i < hw->mac.mcft_size; i++)
2082 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2083 hw->mac.mta_shadow[i]);
2085 if (hw->addr_ctrl.mta_in_use > 0)
2086 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2087 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2089 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
2094 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2095 * @hw: pointer to hardware structure
2097 * Enables multicast address in RAR and the use of the multicast hash table.
2099 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2101 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2103 if (a->mta_in_use > 0)
2104 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2105 hw->mac.mc_filter_type);
2111 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2112 * @hw: pointer to hardware structure
2114 * Disables multicast address in RAR and the use of the multicast hash table.
2116 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2118 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2120 if (a->mta_in_use > 0)
2121 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2127 * ixgbe_fc_enable_generic - Enable flow control
2128 * @hw: pointer to hardware structure
2129 * @packetbuf_num: packet buffer number (0-7)
2131 * Enable flow control according to the current settings.
2133 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
2136 u32 mflcn_reg, fccfg_reg;
2141 if (hw->fc.requested_mode == ixgbe_fc_pfc)
2144 #endif /* CONFIG_DCB */
2145 /* Negotiate the fc mode to use */
2146 ixgbe_fc_autoneg(hw);
2148 /* Disable any previous flow control settings */
2149 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2150 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
2152 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2153 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2156 * The possible values of fc.current_mode are:
2157 * 0: Flow control is completely disabled
2158 * 1: Rx flow control is enabled (we can receive pause frames,
2159 * but not send pause frames).
2160 * 2: Tx flow control is enabled (we can send pause frames but
2161 * we do not support receiving pause frames).
2162 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2164 * 4: Priority Flow Control is enabled.
2168 switch (hw->fc.current_mode) {
2171 * Flow control is disabled by software override or autoneg.
2172 * The code below will actually disable it in the HW.
2175 case ixgbe_fc_rx_pause:
2177 * Rx Flow control is enabled and Tx Flow control is
2178 * disabled by software override. Since there really
2179 * isn't a way to advertise that we are capable of RX
2180 * Pause ONLY, we will advertise that we support both
2181 * symmetric and asymmetric Rx PAUSE. Later, we will
2182 * disable the adapter's ability to send PAUSE frames.
2184 mflcn_reg |= IXGBE_MFLCN_RFCE;
2186 case ixgbe_fc_tx_pause:
2188 * Tx Flow control is enabled, and Rx Flow control is
2189 * disabled by software override.
2191 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2194 /* Flow control (both Rx and Tx) is enabled by SW override. */
2195 mflcn_reg |= IXGBE_MFLCN_RFCE;
2196 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2202 #endif /* CONFIG_DCB */
2204 hw_dbg(hw, "Flow control param set incorrectly\n");
2205 ret_val = IXGBE_ERR_CONFIG;
2210 /* Set 802.3x based flow control settings. */
2211 mflcn_reg |= IXGBE_MFLCN_DPF;
2212 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2213 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2215 fcrtl = hw->fc.low_water << 10;
2217 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2218 fcrth = hw->fc.high_water[packetbuf_num] << 10;
2219 fcrth |= IXGBE_FCRTH_FCEN;
2220 if (hw->fc.send_xon)
2221 fcrtl |= IXGBE_FCRTL_XONE;
2224 * If Tx flow control is disabled, set our high water mark
2225 * to Rx FIFO size minus 32 in order prevent Tx switch
2226 * loopback from stalling on DMA.
2228 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)) - 32;
2231 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
2232 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
2234 /* Configure pause time (2 TCs per register) */
2235 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
2236 if ((packetbuf_num & 1) == 0)
2237 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
2239 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
2240 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
2242 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
2249 * ixgbe_negotiate_fc - Negotiate flow control
2250 * @hw: pointer to hardware structure
2251 * @adv_reg: flow control advertised settings
2252 * @lp_reg: link partner's flow control settings
2253 * @adv_sym: symmetric pause bit in advertisement
2254 * @adv_asm: asymmetric pause bit in advertisement
2255 * @lp_sym: symmetric pause bit in link partner advertisement
2256 * @lp_asm: asymmetric pause bit in link partner advertisement
2258 * Find the intersection between advertised settings and link partner's
2259 * advertised settings
2261 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2262 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2264 if ((!(adv_reg)) || (!(lp_reg)))
2265 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2267 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2269 * Now we need to check if the user selected Rx ONLY
2270 * of pause frames. In this case, we had to advertise
2271 * FULL flow control because we could not advertise RX
2272 * ONLY. Hence, we must now check to see if we need to
2273 * turn OFF the TRANSMISSION of PAUSE frames.
2275 if (hw->fc.requested_mode == ixgbe_fc_full) {
2276 hw->fc.current_mode = ixgbe_fc_full;
2277 hw_dbg(hw, "Flow Control = FULL.\n");
2279 hw->fc.current_mode = ixgbe_fc_rx_pause;
2280 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2282 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2283 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2284 hw->fc.current_mode = ixgbe_fc_tx_pause;
2285 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2286 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2287 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2288 hw->fc.current_mode = ixgbe_fc_rx_pause;
2289 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2291 hw->fc.current_mode = ixgbe_fc_none;
2292 hw_dbg(hw, "Flow Control = NONE.\n");
2298 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2299 * @hw: pointer to hardware structure
2301 * Enable flow control according on 1 gig fiber.
2303 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2305 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2306 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2309 * On multispeed fiber at 1g, bail out if
2310 * - link is up but AN did not complete, or if
2311 * - link is up and AN completed but timed out
2314 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2315 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2316 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2319 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2320 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2322 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2323 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2324 IXGBE_PCS1GANA_ASM_PAUSE,
2325 IXGBE_PCS1GANA_SYM_PAUSE,
2326 IXGBE_PCS1GANA_ASM_PAUSE);
2333 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2334 * @hw: pointer to hardware structure
2336 * Enable flow control according to IEEE clause 37.
2338 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2340 u32 links2, anlp1_reg, autoc_reg, links;
2341 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2344 * On backplane, bail out if
2345 * - backplane autoneg was not completed, or if
2346 * - we are 82599 and link partner is not AN enabled
2348 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2349 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2352 if (hw->mac.type == ixgbe_mac_82599EB) {
2353 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2354 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2358 * Read the 10g AN autoc and LP ability registers and resolve
2359 * local flow control settings accordingly
2361 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2362 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2364 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2365 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2366 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2373 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2374 * @hw: pointer to hardware structure
2376 * Enable flow control according to IEEE clause 37.
2378 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2380 u16 technology_ability_reg = 0;
2381 u16 lp_technology_ability_reg = 0;
2383 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2385 &technology_ability_reg);
2386 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2388 &lp_technology_ability_reg);
2390 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2391 (u32)lp_technology_ability_reg,
2392 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2393 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2397 * ixgbe_fc_autoneg - Configure flow control
2398 * @hw: pointer to hardware structure
2400 * Compares our advertised flow control capabilities to those advertised by
2401 * our link partner, and determines the proper flow control mode to use.
2403 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2405 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2406 ixgbe_link_speed speed;
2410 * AN should have completed when the cable was plugged in.
2411 * Look for reasons to bail out. Bail out if:
2412 * - FC autoneg is disabled, or if
2415 * Since we're being called from an LSC, link is already known to be up.
2416 * So use link_up_wait_to_complete=false.
2418 if (hw->fc.disable_fc_autoneg)
2421 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2425 switch (hw->phy.media_type) {
2426 /* Autoneg flow control on fiber adapters */
2427 case ixgbe_media_type_fiber:
2428 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2429 ret_val = ixgbe_fc_autoneg_fiber(hw);
2432 /* Autoneg flow control on backplane adapters */
2433 case ixgbe_media_type_backplane:
2434 ret_val = ixgbe_fc_autoneg_backplane(hw);
2437 /* Autoneg flow control on copper adapters */
2438 case ixgbe_media_type_copper:
2439 if (ixgbe_device_supports_autoneg_fc(hw) == 0)
2440 ret_val = ixgbe_fc_autoneg_copper(hw);
2449 hw->fc.fc_was_autonegged = true;
2451 hw->fc.fc_was_autonegged = false;
2452 hw->fc.current_mode = hw->fc.requested_mode;
2457 * ixgbe_disable_pcie_master - Disable PCI-express master access
2458 * @hw: pointer to hardware structure
2460 * Disables PCI-Express master access and verifies there are no pending
2461 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2462 * bit hasn't caused the master requests to be disabled, else 0
2463 * is returned signifying master requests disabled.
2465 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2467 struct ixgbe_adapter *adapter = hw->back;
2472 /* Always set this bit to ensure any future transactions are blocked */
2473 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2475 /* Exit if master requests are blocked */
2476 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2479 /* Poll for master request bit to clear */
2480 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2482 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2487 * Two consecutive resets are required via CTRL.RST per datasheet
2488 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2489 * of this need. The first reset prevents new master requests from
2490 * being issued by our device. We then must wait 1usec or more for any
2491 * remaining completions from the PCIe bus to trickle in, and then reset
2492 * again to clear out any effects they may have had on our device.
2494 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2495 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2498 * Before proceeding, make sure that the PCIe block does not have
2499 * transactions pending.
2501 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2503 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
2505 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2509 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2510 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2517 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2518 * @hw: pointer to hardware structure
2519 * @mask: Mask to specify which semaphore to acquire
2521 * Acquires the SWFW semaphore through the GSSR register for the specified
2522 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2524 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2528 u32 fwmask = mask << 5;
2533 * SW EEPROM semaphore bit is used for access to all
2534 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2536 if (ixgbe_get_eeprom_semaphore(hw))
2537 return IXGBE_ERR_SWFW_SYNC;
2539 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2540 if (!(gssr & (fwmask | swmask)))
2544 * Firmware currently using resource (fwmask) or other software
2545 * thread currently using resource (swmask)
2547 ixgbe_release_eeprom_semaphore(hw);
2548 usleep_range(5000, 10000);
2553 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
2554 return IXGBE_ERR_SWFW_SYNC;
2558 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2560 ixgbe_release_eeprom_semaphore(hw);
2565 * ixgbe_release_swfw_sync - Release SWFW semaphore
2566 * @hw: pointer to hardware structure
2567 * @mask: Mask to specify which semaphore to release
2569 * Releases the SWFW semaphore through the GSSR register for the specified
2570 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2572 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2577 ixgbe_get_eeprom_semaphore(hw);
2579 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2581 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2583 ixgbe_release_eeprom_semaphore(hw);
2587 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2588 * @hw: pointer to hardware structure
2590 * Stops the receive data path and waits for the HW to internally
2591 * empty the Rx security block.
2593 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2595 #define IXGBE_MAX_SECRX_POLL 40
2599 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2600 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2601 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2602 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2603 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2604 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2607 /* Use interrupt-safe sleep just in case */
2611 /* For informational purposes only */
2612 if (i >= IXGBE_MAX_SECRX_POLL)
2613 hw_dbg(hw, "Rx unit being enabled before security "
2614 "path fully disabled. Continuing with init.\n");
2621 * ixgbe_enable_rx_buff - Enables the receive data path
2622 * @hw: pointer to hardware structure
2624 * Enables the receive data path
2626 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2630 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2631 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2632 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2633 IXGBE_WRITE_FLUSH(hw);
2639 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2640 * @hw: pointer to hardware structure
2641 * @regval: register value to write to RXCTRL
2643 * Enables the Rx DMA unit
2645 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2647 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2653 * ixgbe_blink_led_start_generic - Blink LED based on index.
2654 * @hw: pointer to hardware structure
2655 * @index: led number to blink
2657 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2659 ixgbe_link_speed speed = 0;
2660 bool link_up = false;
2661 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2662 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2665 * Link must be up to auto-blink the LEDs;
2666 * Force it if link is down.
2668 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2671 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2672 autoc_reg |= IXGBE_AUTOC_FLU;
2673 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2674 IXGBE_WRITE_FLUSH(hw);
2675 usleep_range(10000, 20000);
2678 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2679 led_reg |= IXGBE_LED_BLINK(index);
2680 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2681 IXGBE_WRITE_FLUSH(hw);
2687 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2688 * @hw: pointer to hardware structure
2689 * @index: led number to stop blinking
2691 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2693 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2694 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2696 autoc_reg &= ~IXGBE_AUTOC_FLU;
2697 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2698 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2700 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2701 led_reg &= ~IXGBE_LED_BLINK(index);
2702 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2703 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2704 IXGBE_WRITE_FLUSH(hw);
2710 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2711 * @hw: pointer to hardware structure
2712 * @san_mac_offset: SAN MAC address offset
2714 * This function will read the EEPROM location for the SAN MAC address
2715 * pointer, and returns the value at that location. This is used in both
2716 * get and set mac_addr routines.
2718 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2719 u16 *san_mac_offset)
2722 * First read the EEPROM pointer to see if the MAC addresses are
2725 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2731 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2732 * @hw: pointer to hardware structure
2733 * @san_mac_addr: SAN MAC address
2735 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2736 * per-port, so set_lan_id() must be called before reading the addresses.
2737 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2738 * upon for non-SFP connections, so we must call it here.
2740 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2742 u16 san_mac_data, san_mac_offset;
2746 * First read the EEPROM pointer to see if the MAC addresses are
2747 * available. If they're not, no point in calling set_lan_id() here.
2749 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2751 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2753 * No addresses available in this EEPROM. It's not an
2754 * error though, so just wipe the local address and return.
2756 for (i = 0; i < 6; i++)
2757 san_mac_addr[i] = 0xFF;
2759 goto san_mac_addr_out;
2762 /* make sure we know which port we need to program */
2763 hw->mac.ops.set_lan_id(hw);
2764 /* apply the port offset to the address offset */
2765 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2766 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2767 for (i = 0; i < 3; i++) {
2768 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2769 san_mac_addr[i * 2] = (u8)(san_mac_data);
2770 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2779 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2780 * @hw: pointer to hardware structure
2782 * Read PCIe configuration space, and get the MSI-X vector count from
2783 * the capabilities table.
2785 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2787 struct ixgbe_adapter *adapter = hw->back;
2792 switch (hw->mac.type) {
2793 case ixgbe_mac_82598EB:
2794 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2795 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2797 case ixgbe_mac_82599EB:
2798 case ixgbe_mac_X540:
2799 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2800 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2806 pci_read_config_word(adapter->pdev, pcie_offset, &msix_count);
2807 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2809 /* MSI-X count is zero-based in HW */
2812 if (msix_count > max_msix_count)
2813 msix_count = max_msix_count;
2819 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2820 * @hw: pointer to hardware struct
2821 * @rar: receive address register index to disassociate
2822 * @vmdq: VMDq pool index to remove from the rar
2824 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2826 u32 mpsar_lo, mpsar_hi;
2827 u32 rar_entries = hw->mac.num_rar_entries;
2829 /* Make sure we are using a valid rar index range */
2830 if (rar >= rar_entries) {
2831 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2832 return IXGBE_ERR_INVALID_ARGUMENT;
2835 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2836 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2838 if (!mpsar_lo && !mpsar_hi)
2841 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2843 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2847 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2850 } else if (vmdq < 32) {
2851 mpsar_lo &= ~(1 << vmdq);
2852 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2854 mpsar_hi &= ~(1 << (vmdq - 32));
2855 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2858 /* was that the last pool using this rar? */
2859 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2860 hw->mac.ops.clear_rar(hw, rar);
2866 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2867 * @hw: pointer to hardware struct
2868 * @rar: receive address register index to associate with a VMDq index
2869 * @vmdq: VMDq pool index
2871 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2874 u32 rar_entries = hw->mac.num_rar_entries;
2876 /* Make sure we are using a valid rar index range */
2877 if (rar >= rar_entries) {
2878 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2879 return IXGBE_ERR_INVALID_ARGUMENT;
2883 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2885 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2887 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2888 mpsar |= 1 << (vmdq - 32);
2889 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2895 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2896 * @hw: pointer to hardware structure
2898 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2902 for (i = 0; i < 128; i++)
2903 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2909 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2910 * @hw: pointer to hardware structure
2911 * @vlan: VLAN id to write to VLAN filter
2913 * return the VLVF index where this VLAN id should be placed
2916 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
2919 u32 first_empty_slot = 0;
2922 /* short cut the special case */
2927 * Search for the vlan id in the VLVF entries. Save off the first empty
2928 * slot found along the way
2930 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2931 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2932 if (!bits && !(first_empty_slot))
2933 first_empty_slot = regindex;
2934 else if ((bits & 0x0FFF) == vlan)
2939 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2940 * in the VLVF. Else use the first empty VLVF register for this
2943 if (regindex >= IXGBE_VLVF_ENTRIES) {
2944 if (first_empty_slot)
2945 regindex = first_empty_slot;
2947 hw_dbg(hw, "No space in VLVF.\n");
2948 regindex = IXGBE_ERR_NO_SPACE;
2956 * ixgbe_set_vfta_generic - Set VLAN filter table
2957 * @hw: pointer to hardware structure
2958 * @vlan: VLAN id to write to VLAN filter
2959 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2960 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2962 * Turn on/off specified VLAN in the VLAN filter table.
2964 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2973 bool vfta_changed = false;
2976 return IXGBE_ERR_PARAM;
2979 * this is a 2 part operation - first the VFTA, then the
2980 * VLVF and VLVFB if VT Mode is set
2981 * We don't write the VFTA until we know the VLVF part succeeded.
2985 * The VFTA is a bitstring made up of 128 32-bit registers
2986 * that enable the particular VLAN id, much like the MTA:
2987 * bits[11-5]: which register
2988 * bits[4-0]: which bit in the register
2990 regindex = (vlan >> 5) & 0x7F;
2991 bitindex = vlan & 0x1F;
2992 targetbit = (1 << bitindex);
2993 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2996 if (!(vfta & targetbit)) {
2998 vfta_changed = true;
3001 if ((vfta & targetbit)) {
3003 vfta_changed = true;
3010 * make sure the vlan is in VLVF
3011 * set the vind bit in the matching VLVFB
3013 * clear the pool bit and possibly the vind
3015 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3016 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3019 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3024 /* set the pool bit */
3026 bits = IXGBE_READ_REG(hw,
3027 IXGBE_VLVFB(vlvf_index*2));
3028 bits |= (1 << vind);
3030 IXGBE_VLVFB(vlvf_index*2),
3033 bits = IXGBE_READ_REG(hw,
3034 IXGBE_VLVFB((vlvf_index*2)+1));
3035 bits |= (1 << (vind-32));
3037 IXGBE_VLVFB((vlvf_index*2)+1),
3041 /* clear the pool bit */
3043 bits = IXGBE_READ_REG(hw,
3044 IXGBE_VLVFB(vlvf_index*2));
3045 bits &= ~(1 << vind);
3047 IXGBE_VLVFB(vlvf_index*2),
3049 bits |= IXGBE_READ_REG(hw,
3050 IXGBE_VLVFB((vlvf_index*2)+1));
3052 bits = IXGBE_READ_REG(hw,
3053 IXGBE_VLVFB((vlvf_index*2)+1));
3054 bits &= ~(1 << (vind-32));
3056 IXGBE_VLVFB((vlvf_index*2)+1),
3058 bits |= IXGBE_READ_REG(hw,
3059 IXGBE_VLVFB(vlvf_index*2));
3064 * If there are still bits set in the VLVFB registers
3065 * for the VLAN ID indicated we need to see if the
3066 * caller is requesting that we clear the VFTA entry bit.
3067 * If the caller has requested that we clear the VFTA
3068 * entry bit but there are still pools/VFs using this VLAN
3069 * ID entry then ignore the request. We're not worried
3070 * about the case where we're turning the VFTA VLAN ID
3071 * entry bit on, only when requested to turn it off as
3072 * there may be multiple pools and/or VFs using the
3073 * VLAN ID entry. In that case we cannot clear the
3074 * VFTA bit until all pools/VFs using that VLAN ID have also
3075 * been cleared. This will be indicated by "bits" being
3079 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3080 (IXGBE_VLVF_VIEN | vlan));
3082 /* someone wants to clear the vfta entry
3083 * but some pools/VFs are still using it.
3085 vfta_changed = false;
3089 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3093 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3099 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3100 * @hw: pointer to hardware structure
3102 * Clears the VLAN filer table, and the VMDq index associated with the filter
3104 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3108 for (offset = 0; offset < hw->mac.vft_size; offset++)
3109 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3111 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3112 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3113 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3114 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3121 * ixgbe_check_mac_link_generic - Determine link and speed status
3122 * @hw: pointer to hardware structure
3123 * @speed: pointer to link speed
3124 * @link_up: true when link is up
3125 * @link_up_wait_to_complete: bool used to wait for link up or not
3127 * Reads the links register to determine if link is up and the current speed
3129 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3130 bool *link_up, bool link_up_wait_to_complete)
3132 u32 links_reg, links_orig;
3135 /* clear the old state */
3136 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3138 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3140 if (links_orig != links_reg) {
3141 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3142 links_orig, links_reg);
3145 if (link_up_wait_to_complete) {
3146 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3147 if (links_reg & IXGBE_LINKS_UP) {
3154 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3157 if (links_reg & IXGBE_LINKS_UP)
3163 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3164 IXGBE_LINKS_SPEED_10G_82599)
3165 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3166 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3167 IXGBE_LINKS_SPEED_1G_82599)
3168 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3169 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3170 IXGBE_LINKS_SPEED_100_82599)
3171 *speed = IXGBE_LINK_SPEED_100_FULL;
3173 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3179 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
3181 * @hw: pointer to hardware structure
3182 * @wwnn_prefix: the alternative WWNN prefix
3183 * @wwpn_prefix: the alternative WWPN prefix
3185 * This function will read the EEPROM from the alternative SAN MAC address
3186 * block to check the support for the alternative WWNN/WWPN prefix support.
3188 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3192 u16 alt_san_mac_blk_offset;
3194 /* clear output first */
3195 *wwnn_prefix = 0xFFFF;
3196 *wwpn_prefix = 0xFFFF;
3198 /* check if alternative SAN MAC is supported */
3199 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3200 &alt_san_mac_blk_offset);
3202 if ((alt_san_mac_blk_offset == 0) ||
3203 (alt_san_mac_blk_offset == 0xFFFF))
3204 goto wwn_prefix_out;
3206 /* check capability in alternative san mac address block */
3207 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3208 hw->eeprom.ops.read(hw, offset, &caps);
3209 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3210 goto wwn_prefix_out;
3212 /* get the corresponding prefix for WWNN/WWPN */
3213 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3214 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3216 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3217 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3224 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3225 * @hw: pointer to hardware structure
3226 * @enable: enable or disable switch for anti-spoofing
3227 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3230 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3233 int pf_target_reg = pf >> 3;
3234 int pf_target_shift = pf % 8;
3237 if (hw->mac.type == ixgbe_mac_82598EB)
3241 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3244 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3245 * MAC anti-spoof enables in each register array element.
3247 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3248 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3250 /* If not enabling anti-spoofing then done */
3255 * The PF should be allowed to spoof so that it can support
3256 * emulation mode NICs. Reset the bit assigned to the PF
3258 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
3259 pfvfspoof ^= (1 << pf_target_shift);
3260 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
3264 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3265 * @hw: pointer to hardware structure
3266 * @enable: enable or disable switch for VLAN anti-spoofing
3267 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3270 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3272 int vf_target_reg = vf >> 3;
3273 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3276 if (hw->mac.type == ixgbe_mac_82598EB)
3279 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3281 pfvfspoof |= (1 << vf_target_shift);
3283 pfvfspoof &= ~(1 << vf_target_shift);
3284 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3288 * ixgbe_get_device_caps_generic - Get additional device capabilities
3289 * @hw: pointer to hardware structure
3290 * @device_caps: the EEPROM word with the extra device capabilities
3292 * This function will read the EEPROM location for the device capabilities,
3293 * and return the word through device_caps.
3295 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3297 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3303 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3304 * @hw: pointer to hardware structure
3305 * @num_pb: number of packet buffers to allocate
3306 * @headroom: reserve n KB of headroom
3307 * @strategy: packet buffer allocation strategy
3309 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3314 u32 pbsize = hw->mac.rx_pb_size;
3316 u32 rxpktsize, txpktsize, txpbthresh;
3318 /* Reserve headroom */
3324 /* Divide remaining packet buffer space amongst the number
3325 * of packet buffers requested using supplied strategy.
3328 case (PBA_STRATEGY_WEIGHTED):
3329 /* pba_80_48 strategy weight first half of packet buffer with
3330 * 5/8 of the packet buffer space.
3332 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3333 pbsize -= rxpktsize * (num_pb / 2);
3334 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3335 for (; i < (num_pb / 2); i++)
3336 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3337 /* Fall through to configure remaining packet buffers */
3338 case (PBA_STRATEGY_EQUAL):
3339 /* Divide the remaining Rx packet buffer evenly among the TCs */
3340 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3341 for (; i < num_pb; i++)
3342 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3349 * Setup Tx packet buffer and threshold equally for all TCs
3350 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3351 * 10 since the largest packet we support is just over 9K.
3353 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3354 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3355 for (i = 0; i < num_pb; i++) {
3356 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3357 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3360 /* Clear unused TCs, if any, to zero buffer size*/
3361 for (; i < IXGBE_MAX_PB; i++) {
3362 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3363 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3364 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3369 * ixgbe_calculate_checksum - Calculate checksum for buffer
3370 * @buffer: pointer to EEPROM
3371 * @length: size of EEPROM to calculate a checksum for
3372 * Calculates the checksum for some buffer on a specified length. The
3373 * checksum calculated is returned.
3375 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3383 for (i = 0; i < length; i++)
3386 return (u8) (0 - sum);
3390 * ixgbe_host_interface_command - Issue command to manageability block
3391 * @hw: pointer to the HW structure
3392 * @buffer: contains the command to write and where the return status will
3394 * @length: length of buffer, must be multiple of 4 bytes
3396 * Communicates with the manageability block. On success return 0
3397 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3399 static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3403 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3404 u8 buf_len, dword_len;
3408 if (length == 0 || length & 0x3 ||
3409 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3410 hw_dbg(hw, "Buffer length failure.\n");
3411 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3415 /* Check that the host interface is enabled. */
3416 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3417 if ((hicr & IXGBE_HICR_EN) == 0) {
3418 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3419 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3423 /* Calculate length in DWORDs */
3424 dword_len = length >> 2;
3427 * The device driver writes the relevant command block
3428 * into the ram area.
3430 for (i = 0; i < dword_len; i++)
3431 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3432 i, cpu_to_le32(buffer[i]));
3434 /* Setting this bit tells the ARC that a new command is pending. */
3435 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3437 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3438 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3439 if (!(hicr & IXGBE_HICR_C))
3441 usleep_range(1000, 2000);
3444 /* Check command successful completion. */
3445 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3446 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3447 hw_dbg(hw, "Command has failed with no status valid.\n");
3448 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3452 /* Calculate length in DWORDs */
3453 dword_len = hdr_size >> 2;
3455 /* first pull in the header so we know the buffer length */
3456 for (bi = 0; bi < dword_len; bi++) {
3457 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3458 le32_to_cpus(&buffer[bi]);
3461 /* If there is any thing in data position pull it in */
3462 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3466 if (length < (buf_len + hdr_size)) {
3467 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3468 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3472 /* Calculate length in DWORDs, add 3 for odd lengths */
3473 dword_len = (buf_len + 3) >> 2;
3475 /* Pull in the rest of the buffer (bi is where we left off)*/
3476 for (; bi <= dword_len; bi++) {
3477 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3478 le32_to_cpus(&buffer[bi]);
3486 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3487 * @hw: pointer to the HW structure
3488 * @maj: driver version major number
3489 * @min: driver version minor number
3490 * @build: driver version build number
3491 * @sub: driver version sub build number
3493 * Sends driver version number to firmware through the manageability
3494 * block. On success return 0
3495 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3496 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3498 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3501 struct ixgbe_hic_drv_info fw_cmd;
3505 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) {
3506 ret_val = IXGBE_ERR_SWFW_SYNC;
3510 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3511 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3512 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3513 fw_cmd.port_num = (u8)hw->bus.func;
3514 fw_cmd.ver_maj = maj;
3515 fw_cmd.ver_min = min;
3516 fw_cmd.ver_build = build;
3517 fw_cmd.ver_sub = sub;
3518 fw_cmd.hdr.checksum = 0;
3519 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3520 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3524 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3525 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3530 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3531 FW_CEM_RESP_STATUS_SUCCESS)
3534 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3539 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3545 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3546 * @hw: pointer to the hardware structure
3548 * The 82599 and x540 MACs can experience issues if TX work is still pending
3549 * when a reset occurs. This function prevents this by flushing the PCIe
3550 * buffers on the system.
3552 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3554 u32 gcr_ext, hlreg0;
3557 * If double reset is not requested then all transactions should
3558 * already be clear and as such there is no work to do
3560 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3564 * Set loopback enable to prevent any transmits from being sent
3565 * should the link come up. This assumes that the RXCTRL.RXEN bit
3566 * has already been cleared.
3568 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3569 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3571 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3572 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3573 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3574 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3576 /* Flush all writes and allow 20usec for all transactions to clear */
3577 IXGBE_WRITE_FLUSH(hw);
3580 /* restore previous register values */
3581 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3582 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3585 static const u8 ixgbe_emc_temp_data[4] = {
3586 IXGBE_EMC_INTERNAL_DATA,
3587 IXGBE_EMC_DIODE1_DATA,
3588 IXGBE_EMC_DIODE2_DATA,
3589 IXGBE_EMC_DIODE3_DATA
3591 static const u8 ixgbe_emc_therm_limit[4] = {
3592 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3593 IXGBE_EMC_DIODE1_THERM_LIMIT,
3594 IXGBE_EMC_DIODE2_THERM_LIMIT,
3595 IXGBE_EMC_DIODE3_THERM_LIMIT
3599 * ixgbe_get_ets_data - Extracts the ETS bit data
3600 * @hw: pointer to hardware structure
3601 * @ets_cfg: extected ETS data
3602 * @ets_offset: offset of ETS data
3604 * Returns error code.
3606 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3611 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3615 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) {
3616 status = IXGBE_NOT_IMPLEMENTED;
3620 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3624 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) {
3625 status = IXGBE_NOT_IMPLEMENTED;
3634 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3635 * @hw: pointer to hardware structure
3637 * Returns the thermal sensor data structure
3639 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3647 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3649 /* Only support thermal sensors attached to physical port 0 */
3650 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
3651 status = IXGBE_NOT_IMPLEMENTED;
3655 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3659 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3660 if (num_sensors > IXGBE_MAX_SENSORS)
3661 num_sensors = IXGBE_MAX_SENSORS;
3663 for (i = 0; i < num_sensors; i++) {
3667 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3672 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3673 IXGBE_ETS_DATA_INDEX_SHIFT);
3674 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3675 IXGBE_ETS_DATA_LOC_SHIFT);
3677 if (sensor_location != 0) {
3678 status = hw->phy.ops.read_i2c_byte(hw,
3679 ixgbe_emc_temp_data[sensor_index],
3680 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3681 &data->sensor[i].temp);
3691 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3692 * @hw: pointer to hardware structure
3694 * Inits the thermal sensor thresholds according to the NVM map
3695 * and save off the threshold and location values into mac.thermal_sensor_data
3697 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3703 u8 low_thresh_delta;
3707 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3709 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3711 /* Only support thermal sensors attached to physical port 0 */
3712 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
3713 status = IXGBE_NOT_IMPLEMENTED;
3717 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3721 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3722 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3723 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3724 if (num_sensors > IXGBE_MAX_SENSORS)
3725 num_sensors = IXGBE_MAX_SENSORS;
3727 for (i = 0; i < num_sensors; i++) {
3731 hw->eeprom.ops.read(hw, (ets_offset + 1 + i), &ets_sensor);
3732 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3733 IXGBE_ETS_DATA_INDEX_SHIFT);
3734 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3735 IXGBE_ETS_DATA_LOC_SHIFT);
3736 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3738 hw->phy.ops.write_i2c_byte(hw,
3739 ixgbe_emc_therm_limit[sensor_index],
3740 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3742 if (sensor_location == 0)
3745 data->sensor[i].location = sensor_location;
3746 data->sensor[i].caution_thresh = therm_limit;
3747 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;