1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
29 #include "ixgbe_type.h"
30 #include "ixgbe_dcb.h"
31 #include "ixgbe_dcb_82599.h"
34 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
35 * @hw: pointer to hardware structure
36 * @refill: refill credits index by traffic class
37 * @max: max credits index by traffic class
38 * @bwg_id: bandwidth grouping indexed by traffic class
39 * @prio_type: priority type indexed by traffic class
41 * Configure Rx Packet Arbiter and credits for each traffic class.
43 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
51 u32 credit_refill = 0;
56 * Disable the arbiter before changing parameters
57 * (always enable recycle mode; WSP)
59 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
60 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
62 /* Map all traffic classes to their UP */
64 for (i = 0; i < MAX_USER_PRIORITY; i++)
65 reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
66 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
68 /* Configure traffic class credits and priority */
69 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
70 credit_refill = refill[i];
72 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
74 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
76 if (prio_type[i] == prio_link)
77 reg |= IXGBE_RTRPT4C_LSP;
79 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
83 * Configure Rx packet plane (recycle mode; WSP) and
86 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
87 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
93 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
94 * @hw: pointer to hardware structure
95 * @refill: refill credits index by traffic class
96 * @max: max credits index by traffic class
97 * @bwg_id: bandwidth grouping indexed by traffic class
98 * @prio_type: priority type indexed by traffic class
100 * Configure Tx Descriptor Arbiter and credits for each traffic class.
102 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
108 u32 reg, max_credits;
111 /* Clear the per-Tx queue credits; we use per-TC instead */
112 for (i = 0; i < 128; i++) {
113 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
114 IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
117 /* Configure traffic class credits and priority */
118 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
119 max_credits = max[i];
120 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
122 reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
124 if (prio_type[i] == prio_group)
125 reg |= IXGBE_RTTDT2C_GSP;
127 if (prio_type[i] == prio_link)
128 reg |= IXGBE_RTTDT2C_LSP;
130 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
134 * Configure Tx descriptor plane (recycle mode; WSP) and
137 reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
138 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
144 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
145 * @hw: pointer to hardware structure
146 * @refill: refill credits index by traffic class
147 * @max: max credits index by traffic class
148 * @bwg_id: bandwidth grouping indexed by traffic class
149 * @prio_type: priority type indexed by traffic class
151 * Configure Tx Packet Arbiter and credits for each traffic class.
153 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
164 * Disable the arbiter before changing parameters
165 * (always enable recycle mode; SP; arb delay)
167 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
168 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
170 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
172 /* Map all traffic classes to their UP */
174 for (i = 0; i < MAX_USER_PRIORITY; i++)
175 reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
176 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
178 /* Configure traffic class credits and priority */
179 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
181 reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
182 reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
184 if (prio_type[i] == prio_group)
185 reg |= IXGBE_RTTPT2C_GSP;
187 if (prio_type[i] == prio_link)
188 reg |= IXGBE_RTTPT2C_LSP;
190 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
194 * Configure Tx packet plane (recycle mode; SP; arb delay) and
197 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
198 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
199 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
205 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
206 * @hw: pointer to hardware structure
207 * @pfc_en: enabled pfc bitmask
208 * @prio_tc: priority to tc assignments indexed by priority
210 * Configure Priority Flow Control (PFC) for each traffic class.
212 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
217 for (i = 0; i < MAX_USER_PRIORITY; i++)
218 if (prio_tc[i] > max_tc)
221 /* Configure PFC Tx thresholds per TC */
222 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
227 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
228 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
232 for (j = 0; j < MAX_USER_PRIORITY; j++) {
233 if ((prio_tc[j] == i) && (pfc_en & (1 << j))) {
239 reg = hw->fc.low_water << 10;
242 reg |= IXGBE_FCRTL_XONE;
243 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
245 reg = hw->fc.high_water[i] << 10;
247 reg |= IXGBE_FCRTH_FCEN;
248 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
252 /* Configure pause time (2 TCs per register) */
253 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
254 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
255 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
257 /* Configure flow control refresh threshold value */
258 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
261 reg = IXGBE_FCCFG_TFCE_PRIORITY;
262 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
265 * 82599 will always honor XOFF frames we receive when
266 * we are in PFC mode however X540 only honors enabled
269 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
270 reg &= ~IXGBE_MFLCN_RFCE;
271 reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
273 if (hw->mac.type == ixgbe_mac_X540) {
274 reg &= ~IXGBE_MFLCN_RPFCE_MASK;
275 reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
278 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
281 /* X540 devices have a RX bit that should be cleared
282 * if PFC is disabled on all TCs but PFC features is
285 if (hw->mac.type == ixgbe_mac_X540) {
286 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
287 reg &= ~IXGBE_MFLCN_RPFCE_MASK;
288 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
291 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
292 hw->mac.ops.fc_enable(hw, i);
299 * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
300 * @hw: pointer to hardware structure
302 * Configure queue statistics registers, all queues belonging to same traffic
303 * class uses a single set of queue statistics counters.
305 static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
311 * Receive Queues stats setting
312 * 32 RQSMR registers, each configuring 4 queues.
313 * Set all 16 queues of each TC to the same stat
314 * with TC 'n' going to stat 'n'.
316 for (i = 0; i < 32; i++) {
317 reg = 0x01010101 * (i / 4);
318 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
321 * Transmit Queues stats setting
322 * 32 TQSM registers, each controlling 4 queues.
323 * Set all queues of each TC to the same stat
324 * with TC 'n' going to stat 'n'.
325 * Tx queues are allocated non-uniformly to TCs:
326 * 32, 32, 16, 16, 8, 8, 8, 8.
328 for (i = 0; i < 32; i++) {
345 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
352 * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
353 * @hw: pointer to hardware structure
354 * @refill: refill credits index by traffic class
355 * @max: max credits index by traffic class
356 * @bwg_id: bandwidth grouping indexed by traffic class
357 * @prio_type: priority type indexed by traffic class
358 * @pfc_en: enabled pfc bitmask
360 * Configure dcb settings and enable dcb mode.
362 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
363 u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc)
365 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
367 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
369 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
370 bwg_id, prio_type, prio_tc);
371 ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
372 ixgbe_dcb_config_tc_stats_82599(hw);