drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for ixgbe */
  29
  30 #include <linux/interrupt.h>
  31 #include <linux/types.h>
  32 #include <linux/module.h>
  33 #include <linux/slab.h>
  34 #include <linux/pci.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/vmalloc.h>
  38 #include <linux/highmem.h>
  39 #include <linux/uaccess.h>
  40
  41 #include "ixgbe.h"
  42 #include "ixgbe_phy.h"
  43
  44
  45 #define IXGBE_ALL_RAR_ENTRIES 16
  46
  47 enum {NETDEV_STATS, IXGBE_STATS};
  48
  49 struct ixgbe_stats {
  50         char stat_string[ETH_GSTRING_LEN];
  51         int type;
  52         int sizeof_stat;
  53         int stat_offset;
  54 };
  55
  56 #define IXGBE_STAT(m)           IXGBE_STATS, \
  57                                 sizeof(((struct ixgbe_adapter *)0)->m), \
  58                                 offsetof(struct ixgbe_adapter, m)
  59 #define IXGBE_NETDEV_STAT(m)    NETDEV_STATS, \
  60                                 sizeof(((struct rtnl_link_stats64 *)0)->m), \
  61                                 offsetof(struct rtnl_link_stats64, m)
  62
  63 static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
  64         {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
  65         {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
  66         {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
  67         {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
  68         {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
  69         {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
  70         {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
  71         {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
  72         {"lsc_int", IXGBE_STAT(lsc_int)},
  73         {"tx_busy", IXGBE_STAT(tx_busy)},
  74         {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
  75         {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
  76         {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
  77         {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
  78         {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
  79         {"multicast", IXGBE_NETDEV_STAT(multicast)},
  80         {"broadcast", IXGBE_STAT(stats.bprc)},
  81         {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
  82         {"collisions", IXGBE_NETDEV_STAT(collisions)},
  83         {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
  84         {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
  85         {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
  86         {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
  87         {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
  88         {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
  89         {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
  90         {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
  91         {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
  92         {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
  93         {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
  94         {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
  95         {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
  96         {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
  97         {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
  98         {"tx_restart_queue", IXGBE_STAT(restart_queue)},
  99         {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
 100         {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
 101         {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
 102         {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
 103         {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
 104         {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
 105         {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
 106         {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
 107         {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
 108         {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
 109         {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
 110         {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
 111         {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
 112         {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
 113 #ifdef IXGBE_FCOE
 114         {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
 115         {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
 116         {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
 117         {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
 118         {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
 119         {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
 120         {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
 121         {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
 122 #endif /* IXGBE_FCOE */
 123 };
 124
 125 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
 126  * we set the num_rx_queues to evaluate to num_tx_queues. This is
 127  * used because we do not have a good way to get the max number of
 128  * rx queues with CONFIG_RPS disabled.
 129  */
 130 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
 131
 132 #define IXGBE_QUEUE_STATS_LEN ( \
 133         (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
 134         (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
 135 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
 136 #define IXGBE_PB_STATS_LEN ( \
 137                         (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
 138                          sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
 139                          sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
 140                          sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
 141                         / sizeof(u64))
 142 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
 143                          IXGBE_PB_STATS_LEN + \
 144                          IXGBE_QUEUE_STATS_LEN)
 145
 146 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
 147         "Register test  (offline)", "Eeprom test    (offline)",
 148         "Interrupt test (offline)", "Loopback test  (offline)",
 149         "Link test   (on/offline)"
 150 };
 151 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
 152
 153 static int ixgbe_get_settings(struct net_device *netdev,
 154                               struct ethtool_cmd *ecmd)
 155 {
 156         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 157         struct ixgbe_hw *hw = &adapter->hw;
 158         ixgbe_link_speed supported_link;
 159         u32 link_speed = 0;
 160         bool autoneg = false;
 161         bool link_up;
 162
 163         /* SFP type is needed for get_link_capabilities */
 164         if (hw->phy.media_type & (ixgbe_media_type_fiber |
 165                                   ixgbe_media_type_fiber_qsfp)) {
 166                 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
 167                                 hw->phy.ops.identify_sfp(hw);
 168         }
 169
 170         hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
 171
 172         /* set the supported link speeds */
 173         if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
 174                 ecmd->supported |= SUPPORTED_10000baseT_Full;
 175         if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
 176                 ecmd->supported |= SUPPORTED_1000baseT_Full;
 177         if (supported_link & IXGBE_LINK_SPEED_100_FULL)
 178                 ecmd->supported |= SUPPORTED_100baseT_Full;
 179
 180         /* set the advertised speeds */
 181         if (hw->phy.autoneg_advertised) {
 182                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 183                         ecmd->advertising |= ADVERTISED_100baseT_Full;
 184                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 185                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
 186                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 187                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
 188         } else {
 189                 /* default modes in case phy.autoneg_advertised isn't set */
 190                 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
 191                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
 192                 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
 193                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
 194                 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
 195                         ecmd->advertising |= ADVERTISED_100baseT_Full;
 196
 197                 if (hw->phy.multispeed_fiber && !autoneg) {
 198                         if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
 199                                 ecmd->advertising = ADVERTISED_10000baseT_Full;
 200                 }
 201         }
 202
 203         if (autoneg) {
 204                 ecmd->supported |= SUPPORTED_Autoneg;
 205                 ecmd->advertising |= ADVERTISED_Autoneg;
 206                 ecmd->autoneg = AUTONEG_ENABLE;
 207         } else
 208                 ecmd->autoneg = AUTONEG_DISABLE;
 209
 210         ecmd->transceiver = XCVR_EXTERNAL;
 211
 212         /* Determine the remaining settings based on the PHY type. */
 213         switch (adapter->hw.phy.type) {
 214         case ixgbe_phy_tn:
 215         case ixgbe_phy_aq:
 216         case ixgbe_phy_cu_unknown:
 217                 ecmd->supported |= SUPPORTED_TP;
 218                 ecmd->advertising |= ADVERTISED_TP;
 219                 ecmd->port = PORT_TP;
 220                 break;
 221         case ixgbe_phy_qt:
 222                 ecmd->supported |= SUPPORTED_FIBRE;
 223                 ecmd->advertising |= ADVERTISED_FIBRE;
 224                 ecmd->port = PORT_FIBRE;
 225                 break;
 226         case ixgbe_phy_nl:
 227         case ixgbe_phy_sfp_passive_tyco:
 228         case ixgbe_phy_sfp_passive_unknown:
 229         case ixgbe_phy_sfp_ftl:
 230         case ixgbe_phy_sfp_avago:
 231         case ixgbe_phy_sfp_intel:
 232         case ixgbe_phy_sfp_unknown:
 233                 /* SFP+ devices, further checking needed */
 234                 switch (adapter->hw.phy.sfp_type) {
 235                 case ixgbe_sfp_type_da_cu:
 236                 case ixgbe_sfp_type_da_cu_core0:
 237                 case ixgbe_sfp_type_da_cu_core1:
 238                         ecmd->supported |= SUPPORTED_FIBRE;
 239                         ecmd->advertising |= ADVERTISED_FIBRE;
 240                         ecmd->port = PORT_DA;
 241                         break;
 242                 case ixgbe_sfp_type_sr:
 243                 case ixgbe_sfp_type_lr:
 244                 case ixgbe_sfp_type_srlr_core0:
 245                 case ixgbe_sfp_type_srlr_core1:
 246                 case ixgbe_sfp_type_1g_sx_core0:
 247                 case ixgbe_sfp_type_1g_sx_core1:
 248                 case ixgbe_sfp_type_1g_lx_core0:
 249                 case ixgbe_sfp_type_1g_lx_core1:
 250                         ecmd->supported |= SUPPORTED_FIBRE;
 251                         ecmd->advertising |= ADVERTISED_FIBRE;
 252                         ecmd->port = PORT_FIBRE;
 253                         break;
 254                 case ixgbe_sfp_type_not_present:
 255                         ecmd->supported |= SUPPORTED_FIBRE;
 256                         ecmd->advertising |= ADVERTISED_FIBRE;
 257                         ecmd->port = PORT_NONE;
 258                         break;
 259                 case ixgbe_sfp_type_1g_cu_core0:
 260                 case ixgbe_sfp_type_1g_cu_core1:
 261                         ecmd->supported |= SUPPORTED_TP;
 262                         ecmd->advertising |= ADVERTISED_TP;
 263                         ecmd->port = PORT_TP;
 264                         break;
 265                 case ixgbe_sfp_type_unknown:
 266                 default:
 267                         ecmd->supported |= SUPPORTED_FIBRE;
 268                         ecmd->advertising |= ADVERTISED_FIBRE;
 269                         ecmd->port = PORT_OTHER;
 270                         break;
 271                 }
 272                 break;
 273         case ixgbe_phy_xaui:
 274                 ecmd->supported |= SUPPORTED_FIBRE;
 275                 ecmd->advertising |= ADVERTISED_FIBRE;
 276                 ecmd->port = PORT_NONE;
 277                 break;
 278         case ixgbe_phy_unknown:
 279         case ixgbe_phy_generic:
 280         case ixgbe_phy_sfp_unsupported:
 281         default:
 282                 ecmd->supported |= SUPPORTED_FIBRE;
 283                 ecmd->advertising |= ADVERTISED_FIBRE;
 284                 ecmd->port = PORT_OTHER;
 285                 break;
 286         }
 287
 288         hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
 289         if (link_up) {
 290                 switch (link_speed) {
 291                 case IXGBE_LINK_SPEED_10GB_FULL:
 292                         ethtool_cmd_speed_set(ecmd, SPEED_10000);
 293                         break;
 294                 case IXGBE_LINK_SPEED_1GB_FULL:
 295                         ethtool_cmd_speed_set(ecmd, SPEED_1000);
 296                         break;
 297                 case IXGBE_LINK_SPEED_100_FULL:
 298                         ethtool_cmd_speed_set(ecmd, SPEED_100);
 299                         break;
 300                 default:
 301                         break;
 302                 }
 303                 ecmd->duplex = DUPLEX_FULL;
 304         } else {
 305                 ethtool_cmd_speed_set(ecmd, -1);
 306                 ecmd->duplex = -1;
 307         }
 308
 309         return 0;
 310 }
 311
 312 static int ixgbe_set_settings(struct net_device *netdev,
 313                               struct ethtool_cmd *ecmd)
 314 {
 315         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 316         struct ixgbe_hw *hw = &adapter->hw;
 317         u32 advertised, old;
 318         s32 err = 0;
 319
 320         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
 321             (hw->phy.multispeed_fiber)) {
 322                 /*
 323                  * this function does not support duplex forcing, but can
 324                  * limit the advertising of the adapter to the specified speed
 325                  */
 326                 if (ecmd->advertising & ~ecmd->supported)
 327                         return -EINVAL;
 328
 329                 /* only allow one speed at a time if no autoneg */
 330                 if (!ecmd->autoneg && hw->phy.multispeed_fiber) {
 331                         if (ecmd->advertising ==
 332                             (ADVERTISED_10000baseT_Full |
 333                              ADVERTISED_1000baseT_Full))
 334                                 return -EINVAL;
 335                 }
 336
 337                 old = hw->phy.autoneg_advertised;
 338                 advertised = 0;
 339                 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
 340                         advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 341
 342                 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
 343                         advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 344
 345                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
 346                         advertised |= IXGBE_LINK_SPEED_100_FULL;
 347
 348                 if (old == advertised)
 349                         return err;
 350                 /* this sets the link speed and restarts auto-neg */
 351                 hw->mac.autotry_restart = true;
 352                 err = hw->mac.ops.setup_link(hw, advertised, true);
 353                 if (err) {
 354                         e_info(probe, "setup link failed with code %d\n", err);
 355                         hw->mac.ops.setup_link(hw, old, true);
 356                 }
 357         } else {
 358                 /* in this case we currently only support 10Gb/FULL */
 359                 u32 speed = ethtool_cmd_speed(ecmd);
 360                 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
 361                     (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
 362                     (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
 363                         return -EINVAL;
 364         }
 365
 366         return err;
 367 }
 368
 369 static void ixgbe_get_pauseparam(struct net_device *netdev,
 370                                  struct ethtool_pauseparam *pause)
 371 {
 372         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 373         struct ixgbe_hw *hw = &adapter->hw;
 374
 375         if (ixgbe_device_supports_autoneg_fc(hw) &&
 376             !hw->fc.disable_fc_autoneg)
 377                 pause->autoneg = 1;
 378         else
 379                 pause->autoneg = 0;
 380
 381         if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
 382                 pause->rx_pause = 1;
 383         } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
 384                 pause->tx_pause = 1;
 385         } else if (hw->fc.current_mode == ixgbe_fc_full) {
 386                 pause->rx_pause = 1;
 387                 pause->tx_pause = 1;
 388         }
 389 }
 390
 391 static int ixgbe_set_pauseparam(struct net_device *netdev,
 392                                 struct ethtool_pauseparam *pause)
 393 {
 394         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 395         struct ixgbe_hw *hw = &adapter->hw;
 396         struct ixgbe_fc_info fc = hw->fc;
 397
 398         /* 82598 does no support link flow control with DCB enabled */
 399         if ((hw->mac.type == ixgbe_mac_82598EB) &&
 400             (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
 401                 return -EINVAL;
 402
 403         /* some devices do not support autoneg of link flow control */
 404         if ((pause->autoneg == AUTONEG_ENABLE) &&
 405             !ixgbe_device_supports_autoneg_fc(hw))
 406                 return -EINVAL;
 407
 408         fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
 409
 410         if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
 411                 fc.requested_mode = ixgbe_fc_full;
 412         else if (pause->rx_pause && !pause->tx_pause)
 413                 fc.requested_mode = ixgbe_fc_rx_pause;
 414         else if (!pause->rx_pause && pause->tx_pause)
 415                 fc.requested_mode = ixgbe_fc_tx_pause;
 416         else
 417                 fc.requested_mode = ixgbe_fc_none;
 418
 419         /* if the thing changed then we'll update and use new autoneg */
 420         if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
 421                 hw->fc = fc;
 422                 if (netif_running(netdev))
 423                         ixgbe_reinit_locked(adapter);
 424                 else
 425                         ixgbe_reset(adapter);
 426         }
 427
 428         return 0;
 429 }
 430
 431 static u32 ixgbe_get_msglevel(struct net_device *netdev)
 432 {
 433         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 434         return adapter->msg_enable;
 435 }
 436
 437 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
 438 {
 439         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 440         adapter->msg_enable = data;
 441 }
 442
 443 static int ixgbe_get_regs_len(struct net_device *netdev)
 444 {
 445 #define IXGBE_REGS_LEN  1129
 446         return IXGBE_REGS_LEN * sizeof(u32);
 447 }
 448
 449 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
 450
 451 static void ixgbe_get_regs(struct net_device *netdev,
 452                            struct ethtool_regs *regs, void *p)
 453 {
 454         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 455         struct ixgbe_hw *hw = &adapter->hw;
 456         u32 *regs_buff = p;
 457         u8 i;
 458
 459         memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
 460
 461         regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
 462                         hw->device_id;
 463
 464         /* General Registers */
 465         regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
 466         regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
 467         regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 468         regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
 469         regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
 470         regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 471         regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
 472         regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
 473
 474         /* NVM Register */
 475         regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
 476         regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
 477         regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
 478         regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
 479         regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
 480         regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
 481         regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
 482         regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
 483         regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
 484         regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
 485
 486         /* Interrupt */
 487         /* don't read EICR because it can clear interrupt causes, instead
 488          * read EICS which is a shadow but doesn't clear EICR */
 489         regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
 490         regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
 491         regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
 492         regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
 493         regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
 494         regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
 495         regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
 496         regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
 497         regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
 498         regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
 499         regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
 500         regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
 501
 502         /* Flow Control */
 503         regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
 504         regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
 505         regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
 506         regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
 507         regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
 508         for (i = 0; i < 8; i++) {
 509                 switch (hw->mac.type) {
 510                 case ixgbe_mac_82598EB:
 511                         regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
 512                         regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
 513                         break;
 514                 case ixgbe_mac_82599EB:
 515                 case ixgbe_mac_X540:
 516                         regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
 517                         regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
 518                         break;
 519                 default:
 520                         break;
 521                 }
 522         }
 523         regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
 524         regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
 525
 526         /* Receive DMA */
 527         for (i = 0; i < 64; i++)
 528                 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 529         for (i = 0; i < 64; i++)
 530                 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 531         for (i = 0; i < 64; i++)
 532                 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 533         for (i = 0; i < 64; i++)
 534                 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 535         for (i = 0; i < 64; i++)
 536                 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 537         for (i = 0; i < 64; i++)
 538                 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 539         for (i = 0; i < 16; i++)
 540                 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 541         for (i = 0; i < 16; i++)
 542                 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 543         regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 544         for (i = 0; i < 8; i++)
 545                 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
 546         regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 547         regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
 548
 549         /* Receive */
 550         regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
 551         regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
 552         for (i = 0; i < 16; i++)
 553                 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
 554         for (i = 0; i < 16; i++)
 555                 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
 556         regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
 557         regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 558         regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 559         regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
 560         regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
 561         regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
 562         for (i = 0; i < 8; i++)
 563                 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
 564         for (i = 0; i < 8; i++)
 565                 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
 566         regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
 567
 568         /* Transmit */
 569         for (i = 0; i < 32; i++)
 570                 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 571         for (i = 0; i < 32; i++)
 572                 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 573         for (i = 0; i < 32; i++)
 574                 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 575         for (i = 0; i < 32; i++)
 576                 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 577         for (i = 0; i < 32; i++)
 578                 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 579         for (i = 0; i < 32; i++)
 580                 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 581         for (i = 0; i < 32; i++)
 582                 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
 583         for (i = 0; i < 32; i++)
 584                 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
 585         regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
 586         for (i = 0; i < 16; i++)
 587                 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
 588         regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
 589         for (i = 0; i < 8; i++)
 590                 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
 591         regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
 592
 593         /* Wake Up */
 594         regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
 595         regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
 596         regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
 597         regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
 598         regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
 599         regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
 600         regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
 601         regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
 602         regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
 603
 604         /* DCB */
 605         regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
 606         regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
 607         regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
 608         regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
 609         for (i = 0; i < 8; i++)
 610                 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
 611         for (i = 0; i < 8; i++)
 612                 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
 613         for (i = 0; i < 8; i++)
 614                 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
 615         for (i = 0; i < 8; i++)
 616                 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
 617         for (i = 0; i < 8; i++)
 618                 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
 619         for (i = 0; i < 8; i++)
 620                 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
 621
 622         /* Statistics */
 623         regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
 624         regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
 625         regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
 626         regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
 627         for (i = 0; i < 8; i++)
 628                 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
 629         regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
 630         regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
 631         regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
 632         regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
 633         regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
 634         regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
 635         regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
 636         for (i = 0; i < 8; i++)
 637                 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
 638         for (i = 0; i < 8; i++)
 639                 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
 640         for (i = 0; i < 8; i++)
 641                 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
 642         for (i = 0; i < 8; i++)
 643                 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
 644         regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
 645         regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
 646         regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
 647         regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
 648         regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
 649         regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
 650         regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
 651         regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
 652         regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
 653         regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
 654         regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
 655         regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
 656         for (i = 0; i < 8; i++)
 657                 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
 658         regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
 659         regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
 660         regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
 661         regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
 662         regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
 663         regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
 664         regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
 665         regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
 666         regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
 667         regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
 668         regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
 669         regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
 670         regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
 671         regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
 672         regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
 673         regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
 674         regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
 675         regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
 676         regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
 677         for (i = 0; i < 16; i++)
 678                 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
 679         for (i = 0; i < 16; i++)
 680                 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
 681         for (i = 0; i < 16; i++)
 682                 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
 683         for (i = 0; i < 16; i++)
 684                 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
 685
 686         /* MAC */
 687         regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
 688         regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
 689         regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
 690         regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
 691         regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
 692         regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
 693         regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
 694         regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
 695         regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
 696         regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
 697         regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
 698         regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
 699         regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
 700         regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
 701         regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
 702         regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
 703         regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
 704         regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 705         regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
 706         regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
 707         regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
 708         regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
 709         regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
 710         regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
 711         regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
 712         regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
 713         regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 714         regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
 715         regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 716         regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
 717         regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
 718         regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
 719         regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 720
 721         /* Diagnostic */
 722         regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
 723         for (i = 0; i < 8; i++)
 724                 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
 725         regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
 726         for (i = 0; i < 4; i++)
 727                 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
 728         regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
 729         regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
 730         for (i = 0; i < 8; i++)
 731                 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
 732         regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
 733         for (i = 0; i < 4; i++)
 734                 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
 735         regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
 736         regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
 737         regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
 738         regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
 739         regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
 740         regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
 741         regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
 742         regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
 743         regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
 744         regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
 745         regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
 746         for (i = 0; i < 8; i++)
 747                 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
 748         regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
 749         regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
 750         regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
 751         regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
 752         regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
 753         regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
 754         regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
 755         regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
 756         regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
 757
 758         /* 82599 X540 specific registers  */
 759         regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
 760 }
 761
 762 static int ixgbe_get_eeprom_len(struct net_device *netdev)
 763 {
 764         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 765         return adapter->hw.eeprom.word_size * 2;
 766 }
 767
 768 static int ixgbe_get_eeprom(struct net_device *netdev,
 769                             struct ethtool_eeprom *eeprom, u8 *bytes)
 770 {
 771         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 772         struct ixgbe_hw *hw = &adapter->hw;
 773         u16 *eeprom_buff;
 774         int first_word, last_word, eeprom_len;
 775         int ret_val = 0;
 776         u16 i;
 777
 778         if (eeprom->len == 0)
 779                 return -EINVAL;
 780
 781         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 782
 783         first_word = eeprom->offset >> 1;
 784         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 785         eeprom_len = last_word - first_word + 1;
 786
 787         eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
 788         if (!eeprom_buff)
 789                 return -ENOMEM;
 790
 791         ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
 792                                              eeprom_buff);
 793
 794         /* Device's eeprom is always little-endian, word addressable */
 795         for (i = 0; i < eeprom_len; i++)
 796                 le16_to_cpus(&eeprom_buff[i]);
 797
 798         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
 799         kfree(eeprom_buff);
 800
 801         return ret_val;
 802 }
 803
 804 static int ixgbe_set_eeprom(struct net_device *netdev,
 805                             struct ethtool_eeprom *eeprom, u8 *bytes)
 806 {
 807         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 808         struct ixgbe_hw *hw = &adapter->hw;
 809         u16 *eeprom_buff;
 810         void *ptr;
 811         int max_len, first_word, last_word, ret_val = 0;
 812         u16 i;
 813
 814         if (eeprom->len == 0)
 815                 return -EINVAL;
 816
 817         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 818                 return -EINVAL;
 819
 820         max_len = hw->eeprom.word_size * 2;
 821
 822         first_word = eeprom->offset >> 1;
 823         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 824         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 825         if (!eeprom_buff)
 826                 return -ENOMEM;
 827
 828         ptr = eeprom_buff;
 829
 830         if (eeprom->offset & 1) {
 831                 /*
 832                  * need read/modify/write of first changed EEPROM word
 833                  * only the second byte of the word is being modified
 834                  */
 835                 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
 836                 if (ret_val)
 837                         goto err;
 838
 839                 ptr++;
 840         }
 841         if ((eeprom->offset + eeprom->len) & 1) {
 842                 /*
 843                  * need read/modify/write of last changed EEPROM word
 844                  * only the first byte of the word is being modified
 845                  */
 846                 ret_val = hw->eeprom.ops.read(hw, last_word,
 847                                           &eeprom_buff[last_word - first_word]);
 848                 if (ret_val)
 849                         goto err;
 850         }
 851
 852         /* Device's eeprom is always little-endian, word addressable */
 853         for (i = 0; i < last_word - first_word + 1; i++)
 854                 le16_to_cpus(&eeprom_buff[i]);
 855
 856         memcpy(ptr, bytes, eeprom->len);
 857
 858         for (i = 0; i < last_word - first_word + 1; i++)
 859                 cpu_to_le16s(&eeprom_buff[i]);
 860
 861         ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
 862                                               last_word - first_word + 1,
 863                                               eeprom_buff);
 864
 865         /* Update the checksum */
 866         if (ret_val == 0)
 867                 hw->eeprom.ops.update_checksum(hw);
 868
 869 err:
 870         kfree(eeprom_buff);
 871         return ret_val;
 872 }
 873
 874 static void ixgbe_get_drvinfo(struct net_device *netdev,
 875                               struct ethtool_drvinfo *drvinfo)
 876 {
 877         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 878         u32 nvm_track_id;
 879
 880         strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
 881         strlcpy(drvinfo->version, ixgbe_driver_version,
 882                 sizeof(drvinfo->version));
 883
 884         nvm_track_id = (adapter->eeprom_verh << 16) |
 885                         adapter->eeprom_verl;
 886         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
 887                  nvm_track_id);
 888
 889         strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
 890                 sizeof(drvinfo->bus_info));
 891         drvinfo->n_stats = IXGBE_STATS_LEN;
 892         drvinfo->testinfo_len = IXGBE_TEST_LEN;
 893         drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
 894 }
 895
 896 static void ixgbe_get_ringparam(struct net_device *netdev,
 897                                 struct ethtool_ringparam *ring)
 898 {
 899         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 900         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
 901         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
 902
 903         ring->rx_max_pending = IXGBE_MAX_RXD;
 904         ring->tx_max_pending = IXGBE_MAX_TXD;
 905         ring->rx_pending = rx_ring->count;
 906         ring->tx_pending = tx_ring->count;
 907 }
 908
 909 static int ixgbe_set_ringparam(struct net_device *netdev,
 910                                struct ethtool_ringparam *ring)
 911 {
 912         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 913         struct ixgbe_ring *temp_ring;
 914         int i, err = 0;
 915         u32 new_rx_count, new_tx_count;
 916
 917         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 918                 return -EINVAL;
 919
 920         new_tx_count = clamp_t(u32, ring->tx_pending,
 921                                IXGBE_MIN_TXD, IXGBE_MAX_TXD);
 922         new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
 923
 924         new_rx_count = clamp_t(u32, ring->rx_pending,
 925                                IXGBE_MIN_RXD, IXGBE_MAX_RXD);
 926         new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
 927
 928         if ((new_tx_count == adapter->tx_ring_count) &&
 929             (new_rx_count == adapter->rx_ring_count)) {
 930                 /* nothing to do */
 931                 return 0;
 932         }
 933
 934         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
 935                 usleep_range(1000, 2000);
 936
 937         if (!netif_running(adapter->netdev)) {
 938                 for (i = 0; i < adapter->num_tx_queues; i++)
 939                         adapter->tx_ring[i]->count = new_tx_count;
 940                 for (i = 0; i < adapter->num_rx_queues; i++)
 941                         adapter->rx_ring[i]->count = new_rx_count;
 942                 adapter->tx_ring_count = new_tx_count;
 943                 adapter->rx_ring_count = new_rx_count;
 944                 goto clear_reset;
 945         }
 946
 947         /* allocate temporary buffer to store rings in */
 948         i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
 949         temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
 950
 951         if (!temp_ring) {
 952                 err = -ENOMEM;
 953                 goto clear_reset;
 954         }
 955
 956         ixgbe_down(adapter);
 957
 958         /*
 959          * Setup new Tx resources and free the old Tx resources in that order.
 960          * We can then assign the new resources to the rings via a memcpy.
 961          * The advantage to this approach is that we are guaranteed to still
 962          * have resources even in the case of an allocation failure.
 963          */
 964         if (new_tx_count != adapter->tx_ring_count) {
 965                 for (i = 0; i < adapter->num_tx_queues; i++) {
 966                         memcpy(&temp_ring[i], adapter->tx_ring[i],
 967                                sizeof(struct ixgbe_ring));
 968
 969                         temp_ring[i].count = new_tx_count;
 970                         err = ixgbe_setup_tx_resources(&temp_ring[i]);
 971                         if (err) {
 972                                 while (i) {
 973                                         i--;
 974                                         ixgbe_free_tx_resources(&temp_ring[i]);
 975                                 }
 976                                 goto err_setup;
 977                         }
 978                 }
 979
 980                 for (i = 0; i < adapter->num_tx_queues; i++) {
 981                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
 982
 983                         memcpy(adapter->tx_ring[i], &temp_ring[i],
 984                                sizeof(struct ixgbe_ring));
 985                 }
 986
 987                 adapter->tx_ring_count = new_tx_count;
 988         }
 989
 990         /* Repeat the process for the Rx rings if needed */
 991         if (new_rx_count != adapter->rx_ring_count) {
 992                 for (i = 0; i < adapter->num_rx_queues; i++) {
 993                         memcpy(&temp_ring[i], adapter->rx_ring[i],
 994                                sizeof(struct ixgbe_ring));
 995
 996                         temp_ring[i].count = new_rx_count;
 997                         err = ixgbe_setup_rx_resources(&temp_ring[i]);
 998                         if (err) {
 999                                 while (i) {
1000                                         i--;
1001                                         ixgbe_free_rx_resources(&temp_ring[i]);
1002                                 }
1003                                 goto err_setup;
1004                         }
1005
1006                 }
1007
1008                 for (i = 0; i < adapter->num_rx_queues; i++) {
1009                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
1010
1011                         memcpy(adapter->rx_ring[i], &temp_ring[i],
1012                                sizeof(struct ixgbe_ring));
1013                 }
1014
1015                 adapter->rx_ring_count = new_rx_count;
1016         }
1017
1018 err_setup:
1019         ixgbe_up(adapter);
1020         vfree(temp_ring);
1021 clear_reset:
1022         clear_bit(__IXGBE_RESETTING, &adapter->state);
1023         return err;
1024 }
1025
1026 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
1027 {
1028         switch (sset) {
1029         case ETH_SS_TEST:
1030                 return IXGBE_TEST_LEN;
1031         case ETH_SS_STATS:
1032                 return IXGBE_STATS_LEN;
1033         default:
1034                 return -EOPNOTSUPP;
1035         }
1036 }
1037
1038 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
1039                                     struct ethtool_stats *stats, u64 *data)
1040 {
1041         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1042         struct rtnl_link_stats64 temp;
1043         const struct rtnl_link_stats64 *net_stats;
1044         unsigned int start;
1045         struct ixgbe_ring *ring;
1046         int i, j;
1047         char *p = NULL;
1048
1049         ixgbe_update_stats(adapter);
1050         net_stats = dev_get_stats(netdev, &temp);
1051         for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1052                 switch (ixgbe_gstrings_stats[i].type) {
1053                 case NETDEV_STATS:
1054                         p = (char *) net_stats +
1055                                         ixgbe_gstrings_stats[i].stat_offset;
1056                         break;
1057                 case IXGBE_STATS:
1058                         p = (char *) adapter +
1059                                         ixgbe_gstrings_stats[i].stat_offset;
1060                         break;
1061                 default:
1062                         data[i] = 0;
1063                         continue;
1064                 }
1065
1066                 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1067                            sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1068         }
1069         for (j = 0; j < netdev->num_tx_queues; j++) {
1070                 ring = adapter->tx_ring[j];
1071                 if (!ring) {
1072                         data[i] = 0;
1073                         data[i+1] = 0;
1074                         i += 2;
1075 #ifdef LL_EXTENDED_STATS
1076                         data[i] = 0;
1077                         data[i+1] = 0;
1078                         data[i+2] = 0;
1079                         i += 3;
1080 #endif
1081                         continue;
1082                 }
1083
1084                 do {
1085                         start = u64_stats_fetch_begin_bh(&ring->syncp);
1086                         data[i]   = ring->stats.packets;
1087                         data[i+1] = ring->stats.bytes;
1088                 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1089                 i += 2;
1090 #ifdef LL_EXTENDED_STATS
1091                 data[i] = ring->stats.yields;
1092                 data[i+1] = ring->stats.misses;
1093                 data[i+2] = ring->stats.cleaned;
1094                 i += 3;
1095 #endif
1096         }
1097         for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
1098                 ring = adapter->rx_ring[j];
1099                 if (!ring) {
1100                         data[i] = 0;
1101                         data[i+1] = 0;
1102                         i += 2;
1103 #ifdef LL_EXTENDED_STATS
1104                         data[i] = 0;
1105                         data[i+1] = 0;
1106                         data[i+2] = 0;
1107                         i += 3;
1108 #endif
1109                         continue;
1110                 }
1111
1112                 do {
1113                         start = u64_stats_fetch_begin_bh(&ring->syncp);
1114                         data[i]   = ring->stats.packets;
1115                         data[i+1] = ring->stats.bytes;
1116                 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1117                 i += 2;
1118 #ifdef LL_EXTENDED_STATS
1119                 data[i] = ring->stats.yields;
1120                 data[i+1] = ring->stats.misses;
1121                 data[i+2] = ring->stats.cleaned;
1122                 i += 3;
1123 #endif
1124         }
1125
1126         for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1127                 data[i++] = adapter->stats.pxontxc[j];
1128                 data[i++] = adapter->stats.pxofftxc[j];
1129         }
1130         for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1131                 data[i++] = adapter->stats.pxonrxc[j];
1132                 data[i++] = adapter->stats.pxoffrxc[j];
1133         }
1134 }
1135
1136 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1137                               u8 *data)
1138 {
1139         char *p = (char *)data;
1140         int i;
1141
1142         switch (stringset) {
1143         case ETH_SS_TEST:
1144                 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1145                         memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1146                         data += ETH_GSTRING_LEN;
1147                 }
1148                 break;
1149         case ETH_SS_STATS:
1150                 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1151                         memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1152                                ETH_GSTRING_LEN);
1153                         p += ETH_GSTRING_LEN;
1154                 }
1155                 for (i = 0; i < netdev->num_tx_queues; i++) {
1156                         sprintf(p, "tx_queue_%u_packets", i);
1157                         p += ETH_GSTRING_LEN;
1158                         sprintf(p, "tx_queue_%u_bytes", i);
1159                         p += ETH_GSTRING_LEN;
1160 #ifdef LL_EXTENDED_STATS
1161                         sprintf(p, "tx_queue_%u_ll_napi_yield", i);
1162                         p += ETH_GSTRING_LEN;
1163                         sprintf(p, "tx_queue_%u_ll_misses", i);
1164                         p += ETH_GSTRING_LEN;
1165                         sprintf(p, "tx_queue_%u_ll_cleaned", i);
1166                         p += ETH_GSTRING_LEN;
1167 #endif /* LL_EXTENDED_STATS */
1168                 }
1169                 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
1170                         sprintf(p, "rx_queue_%u_packets", i);
1171                         p += ETH_GSTRING_LEN;
1172                         sprintf(p, "rx_queue_%u_bytes", i);
1173                         p += ETH_GSTRING_LEN;
1174 #ifdef LL_EXTENDED_STATS
1175                         sprintf(p, "rx_queue_%u_ll_poll_yield", i);
1176                         p += ETH_GSTRING_LEN;
1177                         sprintf(p, "rx_queue_%u_ll_misses", i);
1178                         p += ETH_GSTRING_LEN;
1179                         sprintf(p, "rx_queue_%u_ll_cleaned", i);
1180                         p += ETH_GSTRING_LEN;
1181 #endif /* LL_EXTENDED_STATS */
1182                 }
1183                 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1184                         sprintf(p, "tx_pb_%u_pxon", i);
1185                         p += ETH_GSTRING_LEN;
1186                         sprintf(p, "tx_pb_%u_pxoff", i);
1187                         p += ETH_GSTRING_LEN;
1188                 }
1189                 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1190                         sprintf(p, "rx_pb_%u_pxon", i);
1191                         p += ETH_GSTRING_LEN;
1192                         sprintf(p, "rx_pb_%u_pxoff", i);
1193                         p += ETH_GSTRING_LEN;
1194                 }
1195                 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1196                 break;
1197         }
1198 }
1199
1200 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1201 {
1202         struct ixgbe_hw *hw = &adapter->hw;
1203         bool link_up;
1204         u32 link_speed = 0;
1205         *data = 0;
1206
1207         hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1208         if (link_up)
1209                 return *data;
1210         else
1211                 *data = 1;
1212         return *data;
1213 }
1214
1215 /* ethtool register test data */
1216 struct ixgbe_reg_test {
1217         u16 reg;
1218         u8  array_len;
1219         u8  test_type;
1220         u32 mask;
1221         u32 write;
1222 };
1223
1224 /* In the hardware, registers are laid out either singly, in arrays
1225  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
1226  * most tests take place on arrays or single registers (handled
1227  * as a single-element array) and special-case the tables.
1228  * Table tests are always pattern tests.
1229  *
1230  * We also make provision for some required setup steps by specifying
1231  * registers to be written without any read-back testing.
1232  */
1233
1234 #define PATTERN_TEST    1
1235 #define SET_READ_TEST   2
1236 #define WRITE_NO_TEST   3
1237 #define TABLE32_TEST    4
1238 #define TABLE64_TEST_LO 5
1239 #define TABLE64_TEST_HI 6
1240
1241 /* default 82599 register test */
1242 static const struct ixgbe_reg_test reg_test_82599[] = {
1243         { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1244         { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1245         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1246         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1247         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1248         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1249         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1250         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1251         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1252         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1253         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1254         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1255         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1256         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1257         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1258         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1259         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1260         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1261         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1262         { 0, 0, 0, 0 }
1263 };
1264
1265 /* default 82598 register test */
1266 static const struct ixgbe_reg_test reg_test_82598[] = {
1267         { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1268         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1269         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1270         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1271         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1272         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1273         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1274         /* Enable all four RX queues before testing. */
1275         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1276         /* RDH is read-only for 82598, only test RDT. */
1277         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1278         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1279         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1280         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1281         { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1282         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1283         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1284         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1285         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1286         { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1287         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1288         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1289         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1290         { 0, 0, 0, 0 }
1291 };
1292
1293 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1294                              u32 mask, u32 write)
1295 {
1296         u32 pat, val, before;
1297         static const u32 test_pattern[] = {
1298                 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1299
1300         for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1301                 before = readl(adapter->hw.hw_addr + reg);
1302                 writel((test_pattern[pat] & write),
1303                        (adapter->hw.hw_addr + reg));
1304                 val = readl(adapter->hw.hw_addr + reg);
1305                 if (val != (test_pattern[pat] & write & mask)) {
1306                         e_err(drv, "pattern test reg %04X failed: got "
1307                               "0x%08X expected 0x%08X\n",
1308                               reg, val, (test_pattern[pat] & write & mask));
1309                         *data = reg;
1310                         writel(before, adapter->hw.hw_addr + reg);
1311                         return 1;
1312                 }
1313                 writel(before, adapter->hw.hw_addr + reg);
1314         }
1315         return 0;
1316 }
1317
1318 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1319                               u32 mask, u32 write)
1320 {
1321         u32 val, before;
1322         before = readl(adapter->hw.hw_addr + reg);
1323         writel((write & mask), (adapter->hw.hw_addr + reg));
1324         val = readl(adapter->hw.hw_addr + reg);
1325         if ((write & mask) != (val & mask)) {
1326                 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1327                       "expected 0x%08X\n", reg, (val & mask), (write & mask));
1328                 *data = reg;
1329                 writel(before, (adapter->hw.hw_addr + reg));
1330                 return 1;
1331         }
1332         writel(before, (adapter->hw.hw_addr + reg));
1333         return 0;
1334 }
1335
1336 #define REG_PATTERN_TEST(reg, mask, write)                                    \
1337         do {                                                                  \
1338                 if (reg_pattern_test(adapter, data, reg, mask, write))        \
1339                         return 1;                                             \
1340         } while (0)                                                           \
1341
1342
1343 #define REG_SET_AND_CHECK(reg, mask, write)                                   \
1344         do {                                                                  \
1345                 if (reg_set_and_check(adapter, data, reg, mask, write))       \
1346                         return 1;                                             \
1347         } while (0)                                                           \
1348
1349 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1350 {
1351         const struct ixgbe_reg_test *test;
1352         u32 value, before, after;
1353         u32 i, toggle;
1354
1355         switch (adapter->hw.mac.type) {
1356         case ixgbe_mac_82598EB:
1357                 toggle = 0x7FFFF3FF;
1358                 test = reg_test_82598;
1359                 break;
1360         case ixgbe_mac_82599EB:
1361         case ixgbe_mac_X540:
1362                 toggle = 0x7FFFF30F;
1363                 test = reg_test_82599;
1364                 break;
1365         default:
1366                 *data = 1;
1367                 return 1;
1368                 break;
1369         }
1370
1371         /*
1372          * Because the status register is such a special case,
1373          * we handle it separately from the rest of the register
1374          * tests.  Some bits are read-only, some toggle, and some
1375          * are writeable on newer MACs.
1376          */
1377         before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1378         value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1379         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1380         after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1381         if (value != after) {
1382                 e_err(drv, "failed STATUS register test got: 0x%08X "
1383                       "expected: 0x%08X\n", after, value);
1384                 *data = 1;
1385                 return 1;
1386         }
1387         /* restore previous status */
1388         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1389
1390         /*
1391          * Perform the remainder of the register test, looping through
1392          * the test table until we either fail or reach the null entry.
1393          */
1394         while (test->reg) {
1395                 for (i = 0; i < test->array_len; i++) {
1396                         switch (test->test_type) {
1397                         case PATTERN_TEST:
1398                                 REG_PATTERN_TEST(test->reg + (i * 0x40),
1399                                                  test->mask,
1400                                                  test->write);
1401                                 break;
1402                         case SET_READ_TEST:
1403                                 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1404                                                   test->mask,
1405                                                   test->write);
1406                                 break;
1407                         case WRITE_NO_TEST:
1408                                 writel(test->write,
1409                                        (adapter->hw.hw_addr + test->reg)
1410                                        + (i * 0x40));
1411                                 break;
1412                         case TABLE32_TEST:
1413                                 REG_PATTERN_TEST(test->reg + (i * 4),
1414                                                  test->mask,
1415                                                  test->write);
1416                                 break;
1417                         case TABLE64_TEST_LO:
1418                                 REG_PATTERN_TEST(test->reg + (i * 8),
1419                                                  test->mask,
1420                                                  test->write);
1421                                 break;
1422                         case TABLE64_TEST_HI:
1423                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1424                                                  test->mask,
1425                                                  test->write);
1426                                 break;
1427                         }
1428                 }
1429                 test++;
1430         }
1431
1432         *data = 0;
1433         return 0;
1434 }
1435
1436 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1437 {
1438         struct ixgbe_hw *hw = &adapter->hw;
1439         if (hw->eeprom.ops.validate_checksum(hw, NULL))
1440                 *data = 1;
1441         else
1442                 *data = 0;
1443         return *data;
1444 }
1445
1446 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1447 {
1448         struct net_device *netdev = (struct net_device *) data;
1449         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1450
1451         adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1452
1453         return IRQ_HANDLED;
1454 }
1455
1456 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1457 {
1458         struct net_device *netdev = adapter->netdev;
1459         u32 mask, i = 0, shared_int = true;
1460         u32 irq = adapter->pdev->irq;
1461
1462         *data = 0;
1463
1464         /* Hook up test interrupt handler just for this test */
1465         if (adapter->msix_entries) {
1466                 /* NOTE: we don't test MSI-X interrupts here, yet */
1467                 return 0;
1468         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1469                 shared_int = false;
1470                 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1471                                 netdev)) {
1472                         *data = 1;
1473                         return -1;
1474                 }
1475         } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1476                                 netdev->name, netdev)) {
1477                 shared_int = false;
1478         } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1479                                netdev->name, netdev)) {
1480                 *data = 1;
1481                 return -1;
1482         }
1483         e_info(hw, "testing %s interrupt\n", shared_int ?
1484                "shared" : "unshared");
1485
1486         /* Disable all the interrupts */
1487         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1488         IXGBE_WRITE_FLUSH(&adapter->hw);
1489         usleep_range(10000, 20000);
1490
1491         /* Test each interrupt */
1492         for (; i < 10; i++) {
1493                 /* Interrupt to test */
1494                 mask = 1 << i;
1495
1496                 if (!shared_int) {
1497                         /*
1498                          * Disable the interrupts to be reported in
1499                          * the cause register and then force the same
1500                          * interrupt and see if one gets posted.  If
1501                          * an interrupt was posted to the bus, the
1502                          * test failed.
1503                          */
1504                         adapter->test_icr = 0;
1505                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1506                                         ~mask & 0x00007FFF);
1507                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1508                                         ~mask & 0x00007FFF);
1509                         IXGBE_WRITE_FLUSH(&adapter->hw);
1510                         usleep_range(10000, 20000);
1511
1512                         if (adapter->test_icr & mask) {
1513                                 *data = 3;
1514                                 break;
1515                         }
1516                 }
1517
1518                 /*
1519                  * Enable the interrupt to be reported in the cause
1520                  * register and then force the same interrupt and see
1521                  * if one gets posted.  If an interrupt was not posted
1522                  * to the bus, the test failed.
1523                  */
1524                 adapter->test_icr = 0;
1525                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1526                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1527                 IXGBE_WRITE_FLUSH(&adapter->hw);
1528                 usleep_range(10000, 20000);
1529
1530                 if (!(adapter->test_icr &mask)) {
1531                         *data = 4;
1532                         break;
1533                 }
1534
1535                 if (!shared_int) {
1536                         /*
1537                          * Disable the other interrupts to be reported in
1538                          * the cause register and then force the other
1539                          * interrupts and see if any get posted.  If
1540                          * an interrupt was posted to the bus, the
1541                          * test failed.
1542                          */
1543                         adapter->test_icr = 0;
1544                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1545                                         ~mask & 0x00007FFF);
1546                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1547                                         ~mask & 0x00007FFF);
1548                         IXGBE_WRITE_FLUSH(&adapter->hw);
1549                         usleep_range(10000, 20000);
1550
1551                         if (adapter->test_icr) {
1552                                 *data = 5;
1553                                 break;
1554                         }
1555                 }
1556         }
1557
1558         /* Disable all the interrupts */
1559         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1560         IXGBE_WRITE_FLUSH(&adapter->hw);
1561         usleep_range(10000, 20000);
1562
1563         /* Unhook test interrupt handler */
1564         free_irq(irq, netdev);
1565
1566         return *data;
1567 }
1568
1569 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1570 {
1571         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1572         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1573         struct ixgbe_hw *hw = &adapter->hw;
1574         u32 reg_ctl;
1575
1576         /* shut down the DMA engines now so they can be reinitialized later */
1577
1578         /* first Rx */
1579         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1580         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1581         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1582         ixgbe_disable_rx_queue(adapter, rx_ring);
1583
1584         /* now Tx */
1585         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
1586         reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1587         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1588
1589         switch (hw->mac.type) {
1590         case ixgbe_mac_82599EB:
1591         case ixgbe_mac_X540:
1592                 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1593                 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1594                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1595                 break;
1596         default:
1597                 break;
1598         }
1599
1600         ixgbe_reset(adapter);
1601
1602         ixgbe_free_tx_resources(&adapter->test_tx_ring);
1603         ixgbe_free_rx_resources(&adapter->test_rx_ring);
1604 }
1605
1606 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1607 {
1608         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1609         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1610         u32 rctl, reg_data;
1611         int ret_val;
1612         int err;
1613
1614         /* Setup Tx descriptor ring and Tx buffers */
1615         tx_ring->count = IXGBE_DEFAULT_TXD;
1616         tx_ring->queue_index = 0;
1617         tx_ring->dev = &adapter->pdev->dev;
1618         tx_ring->netdev = adapter->netdev;
1619         tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1620
1621         err = ixgbe_setup_tx_resources(tx_ring);
1622         if (err)
1623                 return 1;
1624
1625         switch (adapter->hw.mac.type) {
1626         case ixgbe_mac_82599EB:
1627         case ixgbe_mac_X540:
1628                 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1629                 reg_data |= IXGBE_DMATXCTL_TE;
1630                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1631                 break;
1632         default:
1633                 break;
1634         }
1635
1636         ixgbe_configure_tx_ring(adapter, tx_ring);
1637
1638         /* Setup Rx Descriptor ring and Rx buffers */
1639         rx_ring->count = IXGBE_DEFAULT_RXD;
1640         rx_ring->queue_index = 0;
1641         rx_ring->dev = &adapter->pdev->dev;
1642         rx_ring->netdev = adapter->netdev;
1643         rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1644
1645         err = ixgbe_setup_rx_resources(rx_ring);
1646         if (err) {
1647                 ret_val = 4;
1648                 goto err_nomem;
1649         }
1650
1651         rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1652         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1653
1654         ixgbe_configure_rx_ring(adapter, rx_ring);
1655
1656         rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1657         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1658
1659         return 0;
1660
1661 err_nomem:
1662         ixgbe_free_desc_rings(adapter);
1663         return ret_val;
1664 }
1665
1666 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1667 {
1668         struct ixgbe_hw *hw = &adapter->hw;
1669         u32 reg_data;
1670
1671
1672         /* Setup MAC loopback */
1673         reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1674         reg_data |= IXGBE_HLREG0_LPBK;
1675         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
1676
1677         reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1678         reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1679         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
1680
1681         /* X540 needs to set the MACC.FLU bit to force link up */
1682         if (adapter->hw.mac.type == ixgbe_mac_X540) {
1683                 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1684                 reg_data |= IXGBE_MACC_FLU;
1685                 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1686         } else {
1687                 if (hw->mac.orig_autoc) {
1688                         reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1689                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1690                 } else {
1691                         return 10;
1692                 }
1693         }
1694         IXGBE_WRITE_FLUSH(hw);
1695         usleep_range(10000, 20000);
1696
1697         /* Disable Atlas Tx lanes; re-enabled in reset path */
1698         if (hw->mac.type == ixgbe_mac_82598EB) {
1699                 u8 atlas;
1700
1701                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1702                 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1703                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1704
1705                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1706                 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1707                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1708
1709                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1710                 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1711                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1712
1713                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1714                 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1715                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1716         }
1717
1718         return 0;
1719 }
1720
1721 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1722 {
1723         u32 reg_data;
1724
1725         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1726         reg_data &= ~IXGBE_HLREG0_LPBK;
1727         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1728 }
1729
1730 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1731                                       unsigned int frame_size)
1732 {
1733         memset(skb->data, 0xFF, frame_size);
1734         frame_size >>= 1;
1735         memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1736         memset(&skb->data[frame_size + 10], 0xBE, 1);
1737         memset(&skb->data[frame_size + 12], 0xAF, 1);
1738 }
1739
1740 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1741                                      unsigned int frame_size)
1742 {
1743         unsigned char *data;
1744         bool match = true;
1745
1746         frame_size >>= 1;
1747
1748         data = kmap(rx_buffer->page) + rx_buffer->page_offset;
1749
1750         if (data[3] != 0xFF ||
1751             data[frame_size + 10] != 0xBE ||
1752             data[frame_size + 12] != 0xAF)
1753                 match = false;
1754
1755         kunmap(rx_buffer->page);
1756
1757         return match;
1758 }
1759
1760 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
1761                                   struct ixgbe_ring *tx_ring,
1762                                   unsigned int size)
1763 {
1764         union ixgbe_adv_rx_desc *rx_desc;
1765         struct ixgbe_rx_buffer *rx_buffer;
1766         struct ixgbe_tx_buffer *tx_buffer;
1767         u16 rx_ntc, tx_ntc, count = 0;
1768
1769         /* initialize next to clean and descriptor values */
1770         rx_ntc = rx_ring->next_to_clean;
1771         tx_ntc = tx_ring->next_to_clean;
1772         rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1773
1774         while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
1775                 /* check Rx buffer */
1776                 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
1777
1778                 /* sync Rx buffer for CPU read */
1779                 dma_sync_single_for_cpu(rx_ring->dev,
1780                                         rx_buffer->dma,
1781                                         ixgbe_rx_bufsz(rx_ring),
1782                                         DMA_FROM_DEVICE);
1783
1784                 /* verify contents of skb */
1785                 if (ixgbe_check_lbtest_frame(rx_buffer, size))
1786                         count++;
1787
1788                 /* sync Rx buffer for device write */
1789                 dma_sync_single_for_device(rx_ring->dev,
1790                                            rx_buffer->dma,
1791                                            ixgbe_rx_bufsz(rx_ring),
1792                                            DMA_FROM_DEVICE);
1793
1794                 /* unmap buffer on Tx side */
1795                 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1796                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
1797
1798                 /* increment Rx/Tx next to clean counters */
1799                 rx_ntc++;
1800                 if (rx_ntc == rx_ring->count)
1801                         rx_ntc = 0;
1802                 tx_ntc++;
1803                 if (tx_ntc == tx_ring->count)
1804                         tx_ntc = 0;
1805
1806                 /* fetch next descriptor */
1807                 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1808         }
1809
1810         netdev_tx_reset_queue(txring_txq(tx_ring));
1811
1812         /* re-map buffers to ring, store next to clean values */
1813         ixgbe_alloc_rx_buffers(rx_ring, count);
1814         rx_ring->next_to_clean = rx_ntc;
1815         tx_ring->next_to_clean = tx_ntc;
1816
1817         return count;
1818 }
1819
1820 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1821 {
1822         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1823         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1824         int i, j, lc, good_cnt, ret_val = 0;
1825         unsigned int size = 1024;
1826         netdev_tx_t tx_ret_val;
1827         struct sk_buff *skb;
1828         u32 flags_orig = adapter->flags;
1829
1830         /* DCB can modify the frames on Tx */
1831         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
1832
1833         /* allocate test skb */
1834         skb = alloc_skb(size, GFP_KERNEL);
1835         if (!skb)
1836                 return 11;
1837
1838         /* place data into test skb */
1839         ixgbe_create_lbtest_frame(skb, size);
1840         skb_put(skb, size);
1841
1842         /*
1843          * Calculate the loop count based on the largest descriptor ring
1844          * The idea is to wrap the largest ring a number of times using 64
1845          * send/receive pairs during each loop
1846          */
1847
1848         if (rx_ring->count <= tx_ring->count)
1849                 lc = ((tx_ring->count / 64) * 2) + 1;
1850         else
1851                 lc = ((rx_ring->count / 64) * 2) + 1;
1852
1853         for (j = 0; j <= lc; j++) {
1854                 /* reset count of good packets */
1855                 good_cnt = 0;
1856
1857                 /* place 64 packets on the transmit queue*/
1858                 for (i = 0; i < 64; i++) {
1859                         skb_get(skb);
1860                         tx_ret_val = ixgbe_xmit_frame_ring(skb,
1861                                                            adapter,
1862                                                            tx_ring);
1863                         if (tx_ret_val == NETDEV_TX_OK)
1864                                 good_cnt++;
1865                 }
1866
1867                 if (good_cnt != 64) {
1868                         ret_val = 12;
1869                         break;
1870                 }
1871
1872                 /* allow 200 milliseconds for packets to go from Tx to Rx */
1873                 msleep(200);
1874
1875                 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
1876                 if (good_cnt != 64) {
1877                         ret_val = 13;
1878                         break;
1879                 }
1880         }
1881
1882         /* free the original skb */
1883         kfree_skb(skb);
1884         adapter->flags = flags_orig;
1885
1886         return ret_val;
1887 }
1888
1889 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1890 {
1891         *data = ixgbe_setup_desc_rings(adapter);
1892         if (*data)
1893                 goto out;
1894         *data = ixgbe_setup_loopback_test(adapter);
1895         if (*data)
1896                 goto err_loopback;
1897         *data = ixgbe_run_loopback_test(adapter);
1898         ixgbe_loopback_cleanup(adapter);
1899
1900 err_loopback:
1901         ixgbe_free_desc_rings(adapter);
1902 out:
1903         return *data;
1904 }
1905
1906 static void ixgbe_diag_test(struct net_device *netdev,
1907                             struct ethtool_test *eth_test, u64 *data)
1908 {
1909         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1910         bool if_running = netif_running(netdev);
1911
1912         set_bit(__IXGBE_TESTING, &adapter->state);
1913         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1914                 struct ixgbe_hw *hw = &adapter->hw;
1915
1916                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1917                         int i;
1918                         for (i = 0; i < adapter->num_vfs; i++) {
1919                                 if (adapter->vfinfo[i].clear_to_send) {
1920                                         netdev_warn(netdev, "%s",
1921                                                     "offline diagnostic is not "
1922                                                     "supported when VFs are "
1923                                                     "present\n");
1924                                         data[0] = 1;
1925                                         data[1] = 1;
1926                                         data[2] = 1;
1927                                         data[3] = 1;
1928                                         eth_test->flags |= ETH_TEST_FL_FAILED;
1929                                         clear_bit(__IXGBE_TESTING,
1930                                                   &adapter->state);
1931                                         goto skip_ol_tests;
1932                                 }
1933                         }
1934                 }
1935
1936                 /* Offline tests */
1937                 e_info(hw, "offline testing starting\n");
1938
1939                 /* Link test performed before hardware reset so autoneg doesn't
1940                  * interfere with test result
1941                  */
1942                 if (ixgbe_link_test(adapter, &data[4]))
1943                         eth_test->flags |= ETH_TEST_FL_FAILED;
1944
1945                 if (if_running)
1946                         /* indicate we're in test mode */
1947                         dev_close(netdev);
1948                 else
1949                         ixgbe_reset(adapter);
1950
1951                 e_info(hw, "register testing starting\n");
1952                 if (ixgbe_reg_test(adapter, &data[0]))
1953                         eth_test->flags |= ETH_TEST_FL_FAILED;
1954
1955                 ixgbe_reset(adapter);
1956                 e_info(hw, "eeprom testing starting\n");
1957                 if (ixgbe_eeprom_test(adapter, &data[1]))
1958                         eth_test->flags |= ETH_TEST_FL_FAILED;
1959
1960                 ixgbe_reset(adapter);
1961                 e_info(hw, "interrupt testing starting\n");
1962                 if (ixgbe_intr_test(adapter, &data[2]))
1963                         eth_test->flags |= ETH_TEST_FL_FAILED;
1964
1965                 /* If SRIOV or VMDq is enabled then skip MAC
1966                  * loopback diagnostic. */
1967                 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1968                                       IXGBE_FLAG_VMDQ_ENABLED)) {
1969                         e_info(hw, "Skip MAC loopback diagnostic in VT "
1970                                "mode\n");
1971                         data[3] = 0;
1972                         goto skip_loopback;
1973                 }
1974
1975                 ixgbe_reset(adapter);
1976                 e_info(hw, "loopback testing starting\n");
1977                 if (ixgbe_loopback_test(adapter, &data[3]))
1978                         eth_test->flags |= ETH_TEST_FL_FAILED;
1979
1980 skip_loopback:
1981                 ixgbe_reset(adapter);
1982
1983                 /* clear testing bit and return adapter to previous state */
1984                 clear_bit(__IXGBE_TESTING, &adapter->state);
1985                 if (if_running)
1986                         dev_open(netdev);
1987                 else if (hw->mac.ops.disable_tx_laser)
1988                         hw->mac.ops.disable_tx_laser(hw);
1989         } else {
1990                 e_info(hw, "online testing starting\n");
1991
1992                 /* Online tests */
1993                 if (ixgbe_link_test(adapter, &data[4]))
1994                         eth_test->flags |= ETH_TEST_FL_FAILED;
1995
1996                 /* Offline tests aren't run; pass by default */
1997                 data[0] = 0;
1998                 data[1] = 0;
1999                 data[2] = 0;
2000                 data[3] = 0;
2001
2002                 clear_bit(__IXGBE_TESTING, &adapter->state);
2003         }
2004
2005 skip_ol_tests:
2006         msleep_interruptible(4 * 1000);
2007 }
2008
2009 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
2010                                struct ethtool_wolinfo *wol)
2011 {
2012         struct ixgbe_hw *hw = &adapter->hw;
2013         int retval = 0;
2014
2015         /* WOL not supported for all devices */
2016         if (!ixgbe_wol_supported(adapter, hw->device_id,
2017                                  hw->subsystem_device_id)) {
2018                 retval = 1;
2019                 wol->supported = 0;
2020         }
2021
2022         return retval;
2023 }
2024
2025 static void ixgbe_get_wol(struct net_device *netdev,
2026                           struct ethtool_wolinfo *wol)
2027 {
2028         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2029
2030         wol->supported = WAKE_UCAST | WAKE_MCAST |
2031                          WAKE_BCAST | WAKE_MAGIC;
2032         wol->wolopts = 0;
2033
2034         if (ixgbe_wol_exclusion(adapter, wol) ||
2035             !device_can_wakeup(&adapter->pdev->dev))
2036                 return;
2037
2038         if (adapter->wol & IXGBE_WUFC_EX)
2039                 wol->wolopts |= WAKE_UCAST;
2040         if (adapter->wol & IXGBE_WUFC_MC)
2041                 wol->wolopts |= WAKE_MCAST;
2042         if (adapter->wol & IXGBE_WUFC_BC)
2043                 wol->wolopts |= WAKE_BCAST;
2044         if (adapter->wol & IXGBE_WUFC_MAG)
2045                 wol->wolopts |= WAKE_MAGIC;
2046 }
2047
2048 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2049 {
2050         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2051
2052         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2053                 return -EOPNOTSUPP;
2054
2055         if (ixgbe_wol_exclusion(adapter, wol))
2056                 return wol->wolopts ? -EOPNOTSUPP : 0;
2057
2058         adapter->wol = 0;
2059
2060         if (wol->wolopts & WAKE_UCAST)
2061                 adapter->wol |= IXGBE_WUFC_EX;
2062         if (wol->wolopts & WAKE_MCAST)
2063                 adapter->wol |= IXGBE_WUFC_MC;
2064         if (wol->wolopts & WAKE_BCAST)
2065                 adapter->wol |= IXGBE_WUFC_BC;
2066         if (wol->wolopts & WAKE_MAGIC)
2067                 adapter->wol |= IXGBE_WUFC_MAG;
2068
2069         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2070
2071         return 0;
2072 }
2073
2074 static int ixgbe_nway_reset(struct net_device *netdev)
2075 {
2076         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2077
2078         if (netif_running(netdev))
2079                 ixgbe_reinit_locked(adapter);
2080
2081         return 0;
2082 }
2083
2084 static int ixgbe_set_phys_id(struct net_device *netdev,
2085                              enum ethtool_phys_id_state state)
2086 {
2087         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2088         struct ixgbe_hw *hw = &adapter->hw;
2089
2090         switch (state) {
2091         case ETHTOOL_ID_ACTIVE:
2092                 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2093                 return 2;
2094
2095         case ETHTOOL_ID_ON:
2096                 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
2097                 break;
2098
2099         case ETHTOOL_ID_OFF:
2100                 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
2101                 break;
2102
2103         case ETHTOOL_ID_INACTIVE:
2104                 /* Restore LED settings */
2105                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2106                 break;
2107         }
2108
2109         return 0;
2110 }
2111
2112 static int ixgbe_get_coalesce(struct net_device *netdev,
2113                               struct ethtool_coalesce *ec)
2114 {
2115         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2116
2117         /* only valid if in constant ITR mode */
2118         if (adapter->rx_itr_setting <= 1)
2119                 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2120         else
2121                 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2122
2123         /* if in mixed tx/rx queues per vector mode, report only rx settings */
2124         if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2125                 return 0;
2126
2127         /* only valid if in constant ITR mode */
2128         if (adapter->tx_itr_setting <= 1)
2129                 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2130         else
2131                 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2132
2133         return 0;
2134 }
2135
2136 /*
2137  * this function must be called before setting the new value of
2138  * rx_itr_setting
2139  */
2140 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
2141 {
2142         struct net_device *netdev = adapter->netdev;
2143
2144         /* nothing to do if LRO or RSC are not enabled */
2145         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2146             !(netdev->features & NETIF_F_LRO))
2147                 return false;
2148
2149         /* check the feature flag value and enable RSC if necessary */
2150         if (adapter->rx_itr_setting == 1 ||
2151             adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2152                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2153                         adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2154                         e_info(probe, "rx-usecs value high enough "
2155                                       "to re-enable RSC\n");
2156                         return true;
2157                 }
2158         /* if interrupt rate is too high then disable RSC */
2159         } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2160                 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2161                 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2162                 return true;
2163         }
2164         return false;
2165 }
2166
2167 static int ixgbe_set_coalesce(struct net_device *netdev,
2168                               struct ethtool_coalesce *ec)
2169 {
2170         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2171         struct ixgbe_q_vector *q_vector;
2172         int i;
2173         u16 tx_itr_param, rx_itr_param, tx_itr_prev;
2174         bool need_reset = false;
2175
2176         if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2177                 /* reject Tx specific changes in case of mixed RxTx vectors */
2178                 if (ec->tx_coalesce_usecs)
2179                         return -EINVAL;
2180                 tx_itr_prev = adapter->rx_itr_setting;
2181         } else {
2182                 tx_itr_prev = adapter->tx_itr_setting;
2183         }
2184
2185         if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2186             (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2187                 return -EINVAL;
2188
2189         if (ec->rx_coalesce_usecs > 1)
2190                 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2191         else
2192                 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2193
2194         if (adapter->rx_itr_setting == 1)
2195                 rx_itr_param = IXGBE_20K_ITR;
2196         else
2197                 rx_itr_param = adapter->rx_itr_setting;
2198
2199         if (ec->tx_coalesce_usecs > 1)
2200                 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2201         else
2202                 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2203
2204         if (adapter->tx_itr_setting == 1)
2205                 tx_itr_param = IXGBE_10K_ITR;
2206         else
2207                 tx_itr_param = adapter->tx_itr_setting;
2208
2209         /* mixed Rx/Tx */
2210         if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2211                 adapter->tx_itr_setting = adapter->rx_itr_setting;
2212
2213 #if IS_ENABLED(CONFIG_BQL)
2214         /* detect ITR changes that require update of TXDCTL.WTHRESH */
2215         if ((adapter->tx_itr_setting > 1) &&
2216             (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2217                 if ((tx_itr_prev == 1) ||
2218                     (tx_itr_prev > IXGBE_100K_ITR))
2219                         need_reset = true;
2220         } else {
2221                 if ((tx_itr_prev > 1) &&
2222                     (tx_itr_prev < IXGBE_100K_ITR))
2223                         need_reset = true;
2224         }
2225 #endif
2226         /* check the old value and enable RSC if necessary */
2227         need_reset |= ixgbe_update_rsc(adapter);
2228
2229         for (i = 0; i < adapter->num_q_vectors; i++) {
2230                 q_vector = adapter->q_vector[i];
2231                 if (q_vector->tx.count && !q_vector->rx.count)
2232                         /* tx only */
2233                         q_vector->itr = tx_itr_param;
2234                 else
2235                         /* rx only or mixed */
2236                         q_vector->itr = rx_itr_param;
2237                 ixgbe_write_eitr(q_vector);
2238         }
2239
2240         /*
2241          * do reset here at the end to make sure EITR==0 case is handled
2242          * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2243          * also locks in RSC enable/disable which requires reset
2244          */
2245         if (need_reset)
2246                 ixgbe_do_reset(netdev);
2247
2248         return 0;
2249 }
2250
2251 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2252                                         struct ethtool_rxnfc *cmd)
2253 {
2254         union ixgbe_atr_input *mask = &adapter->fdir_mask;
2255         struct ethtool_rx_flow_spec *fsp =
2256                 (struct ethtool_rx_flow_spec *)&cmd->fs;
2257         struct hlist_node *node2;
2258         struct ixgbe_fdir_filter *rule = NULL;
2259
2260         /* report total rule count */
2261         cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2262
2263         hlist_for_each_entry_safe(rule, node2,
2264                                   &adapter->fdir_filter_list, fdir_node) {
2265                 if (fsp->location <= rule->sw_idx)
2266                         break;
2267         }
2268
2269         if (!rule || fsp->location != rule->sw_idx)
2270                 return -EINVAL;
2271
2272         /* fill out the flow spec entry */
2273
2274         /* set flow type field */
2275         switch (rule->filter.formatted.flow_type) {
2276         case IXGBE_ATR_FLOW_TYPE_TCPV4:
2277                 fsp->flow_type = TCP_V4_FLOW;
2278                 break;
2279         case IXGBE_ATR_FLOW_TYPE_UDPV4:
2280                 fsp->flow_type = UDP_V4_FLOW;
2281                 break;
2282         case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2283                 fsp->flow_type = SCTP_V4_FLOW;
2284                 break;
2285         case IXGBE_ATR_FLOW_TYPE_IPV4:
2286                 fsp->flow_type = IP_USER_FLOW;
2287                 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2288                 fsp->h_u.usr_ip4_spec.proto = 0;
2289                 fsp->m_u.usr_ip4_spec.proto = 0;
2290                 break;
2291         default:
2292                 return -EINVAL;
2293         }
2294
2295         fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2296         fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2297         fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2298         fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2299         fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2300         fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2301         fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2302         fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2303         fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2304         fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2305         fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2306         fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2307         fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2308         fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2309         fsp->flow_type |= FLOW_EXT;
2310
2311         /* record action */
2312         if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2313                 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2314         else
2315                 fsp->ring_cookie = rule->action;
2316
2317         return 0;
2318 }
2319
2320 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2321                                       struct ethtool_rxnfc *cmd,
2322                                       u32 *rule_locs)
2323 {
2324         struct hlist_node *node2;
2325         struct ixgbe_fdir_filter *rule;
2326         int cnt = 0;
2327
2328         /* report total rule count */
2329         cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2330
2331         hlist_for_each_entry_safe(rule, node2,
2332                                   &adapter->fdir_filter_list, fdir_node) {
2333                 if (cnt == cmd->rule_cnt)
2334                         return -EMSGSIZE;
2335                 rule_locs[cnt] = rule->sw_idx;
2336                 cnt++;
2337         }
2338
2339         cmd->rule_cnt = cnt;
2340
2341         return 0;
2342 }
2343
2344 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2345                                    struct ethtool_rxnfc *cmd)
2346 {
2347         cmd->data = 0;
2348
2349         /* Report default options for RSS on ixgbe */
2350         switch (cmd->flow_type) {
2351         case TCP_V4_FLOW:
2352                 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2353         case UDP_V4_FLOW:
2354                 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2355                         cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2356         case SCTP_V4_FLOW:
2357         case AH_ESP_V4_FLOW:
2358         case AH_V4_FLOW:
2359         case ESP_V4_FLOW:
2360         case IPV4_FLOW:
2361                 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2362                 break;
2363         case TCP_V6_FLOW:
2364                 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2365         case UDP_V6_FLOW:
2366                 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2367                         cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2368         case SCTP_V6_FLOW:
2369         case AH_ESP_V6_FLOW:
2370         case AH_V6_FLOW:
2371         case ESP_V6_FLOW:
2372         case IPV6_FLOW:
2373                 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2374                 break;
2375         default:
2376                 return -EINVAL;
2377         }
2378
2379         return 0;
2380 }
2381
2382 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2383                            u32 *rule_locs)
2384 {
2385         struct ixgbe_adapter *adapter = netdev_priv(dev);
2386         int ret = -EOPNOTSUPP;
2387
2388         switch (cmd->cmd) {
2389         case ETHTOOL_GRXRINGS:
2390                 cmd->data = adapter->num_rx_queues;
2391                 ret = 0;
2392                 break;
2393         case ETHTOOL_GRXCLSRLCNT:
2394                 cmd->rule_cnt = adapter->fdir_filter_count;
2395                 ret = 0;
2396                 break;
2397         case ETHTOOL_GRXCLSRULE:
2398                 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2399                 break;
2400         case ETHTOOL_GRXCLSRLALL:
2401                 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
2402                 break;
2403         case ETHTOOL_GRXFH:
2404                 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2405                 break;
2406         default:
2407                 break;
2408         }
2409
2410         return ret;
2411 }
2412
2413 static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2414                                            struct ixgbe_fdir_filter *input,
2415                                            u16 sw_idx)
2416 {
2417         struct ixgbe_hw *hw = &adapter->hw;
2418         struct hlist_node *node2;
2419         struct ixgbe_fdir_filter *rule, *parent;
2420         int err = -EINVAL;
2421
2422         parent = NULL;
2423         rule = NULL;
2424
2425         hlist_for_each_entry_safe(rule, node2,
2426                                   &adapter->fdir_filter_list, fdir_node) {
2427                 /* hash found, or no matching entry */
2428                 if (rule->sw_idx >= sw_idx)
2429                         break;
2430                 parent = rule;
2431         }
2432
2433         /* if there is an old rule occupying our place remove it */
2434         if (rule && (rule->sw_idx == sw_idx)) {
2435                 if (!input || (rule->filter.formatted.bkt_hash !=
2436                                input->filter.formatted.bkt_hash)) {
2437                         err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2438                                                                 &rule->filter,
2439                                                                 sw_idx);
2440                 }
2441
2442                 hlist_del(&rule->fdir_node);
2443                 kfree(rule);
2444                 adapter->fdir_filter_count--;
2445         }
2446
2447         /*
2448          * If no input this was a delete, err should be 0 if a rule was
2449          * successfully found and removed from the list else -EINVAL
2450          */
2451         if (!input)
2452                 return err;
2453
2454         /* initialize node and set software index */
2455         INIT_HLIST_NODE(&input->fdir_node);
2456
2457         /* add filter to the list */
2458         if (parent)
2459                 hlist_add_after(&parent->fdir_node, &input->fdir_node);
2460         else
2461                 hlist_add_head(&input->fdir_node,
2462                                &adapter->fdir_filter_list);
2463
2464         /* update counts */
2465         adapter->fdir_filter_count++;
2466
2467         return 0;
2468 }
2469
2470 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2471                                        u8 *flow_type)
2472 {
2473         switch (fsp->flow_type & ~FLOW_EXT) {
2474         case TCP_V4_FLOW:
2475                 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2476                 break;
2477         case UDP_V4_FLOW:
2478                 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2479                 break;
2480         case SCTP_V4_FLOW:
2481                 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2482                 break;
2483         case IP_USER_FLOW:
2484                 switch (fsp->h_u.usr_ip4_spec.proto) {
2485                 case IPPROTO_TCP:
2486                         *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2487                         break;
2488                 case IPPROTO_UDP:
2489                         *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2490                         break;
2491                 case IPPROTO_SCTP:
2492                         *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2493                         break;
2494                 case 0:
2495                         if (!fsp->m_u.usr_ip4_spec.proto) {
2496                                 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2497                                 break;
2498                         }
2499                 default:
2500                         return 0;
2501                 }
2502                 break;
2503         default:
2504                 return 0;
2505         }
2506
2507         return 1;
2508 }
2509
2510 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2511                                         struct ethtool_rxnfc *cmd)
2512 {
2513         struct ethtool_rx_flow_spec *fsp =
2514                 (struct ethtool_rx_flow_spec *)&cmd->fs;
2515         struct ixgbe_hw *hw = &adapter->hw;
2516         struct ixgbe_fdir_filter *input;
2517         union ixgbe_atr_input mask;
2518         int err;
2519
2520         if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2521                 return -EOPNOTSUPP;
2522
2523         /*
2524          * Don't allow programming if the action is a queue greater than
2525          * the number of online Rx queues.
2526          */
2527         if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2528             (fsp->ring_cookie >= adapter->num_rx_queues))
2529                 return -EINVAL;
2530
2531         /* Don't allow indexes to exist outside of available space */
2532         if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2533                 e_err(drv, "Location out of range\n");
2534                 return -EINVAL;
2535         }
2536
2537         input = kzalloc(sizeof(*input), GFP_ATOMIC);
2538         if (!input)
2539                 return -ENOMEM;
2540
2541         memset(&mask, 0, sizeof(union ixgbe_atr_input));
2542
2543         /* set SW index */
2544         input->sw_idx = fsp->location;
2545
2546         /* record flow type */
2547         if (!ixgbe_flowspec_to_flow_type(fsp,
2548                                          &input->filter.formatted.flow_type)) {
2549                 e_err(drv, "Unrecognized flow type\n");
2550                 goto err_out;
2551         }
2552
2553         mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2554                                    IXGBE_ATR_L4TYPE_MASK;
2555
2556         if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2557                 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2558
2559         /* Copy input into formatted structures */
2560         input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2561         mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2562         input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2563         mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2564         input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2565         mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2566         input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2567         mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2568
2569         if (fsp->flow_type & FLOW_EXT) {
2570                 input->filter.formatted.vm_pool =
2571                                 (unsigned char)ntohl(fsp->h_ext.data[1]);
2572                 mask.formatted.vm_pool =
2573                                 (unsigned char)ntohl(fsp->m_ext.data[1]);
2574                 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2575                 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2576                 input->filter.formatted.flex_bytes =
2577                                                 fsp->h_ext.vlan_etype;
2578                 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2579         }
2580
2581         /* determine if we need to drop or route the packet */
2582         if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2583                 input->action = IXGBE_FDIR_DROP_QUEUE;
2584         else
2585                 input->action = fsp->ring_cookie;
2586
2587         spin_lock(&adapter->fdir_perfect_lock);
2588
2589         if (hlist_empty(&adapter->fdir_filter_list)) {
2590                 /* save mask and program input mask into HW */
2591                 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2592                 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2593                 if (err) {
2594                         e_err(drv, "Error writing mask\n");
2595                         goto err_out_w_lock;
2596                 }
2597         } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2598                 e_err(drv, "Only one mask supported per port\n");
2599                 goto err_out_w_lock;
2600         }
2601
2602         /* apply mask and compute/store hash */
2603         ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2604
2605         /* program filters to filter memory */
2606         err = ixgbe_fdir_write_perfect_filter_82599(hw,
2607                                 &input->filter, input->sw_idx,
2608                                 (input->action == IXGBE_FDIR_DROP_QUEUE) ?
2609                                 IXGBE_FDIR_DROP_QUEUE :
2610                                 adapter->rx_ring[input->action]->reg_idx);
2611         if (err)
2612                 goto err_out_w_lock;
2613
2614         ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2615
2616         spin_unlock(&adapter->fdir_perfect_lock);
2617
2618         return err;
2619 err_out_w_lock:
2620         spin_unlock(&adapter->fdir_perfect_lock);
2621 err_out:
2622         kfree(input);
2623         return -EINVAL;
2624 }
2625
2626 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2627                                         struct ethtool_rxnfc *cmd)
2628 {
2629         struct ethtool_rx_flow_spec *fsp =
2630                 (struct ethtool_rx_flow_spec *)&cmd->fs;
2631         int err;
2632
2633         spin_lock(&adapter->fdir_perfect_lock);
2634         err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2635         spin_unlock(&adapter->fdir_perfect_lock);
2636
2637         return err;
2638 }
2639
2640 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2641                        IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2642 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2643                                   struct ethtool_rxnfc *nfc)
2644 {
2645         u32 flags2 = adapter->flags2;
2646
2647         /*
2648          * RSS does not support anything other than hashing
2649          * to queues on src and dst IPs and ports
2650          */
2651         if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2652                           RXH_L4_B_0_1 | RXH_L4_B_2_3))
2653                 return -EINVAL;
2654
2655         switch (nfc->flow_type) {
2656         case TCP_V4_FLOW:
2657         case TCP_V6_FLOW:
2658                 if (!(nfc->data & RXH_IP_SRC) ||
2659                     !(nfc->data & RXH_IP_DST) ||
2660                     !(nfc->data & RXH_L4_B_0_1) ||
2661                     !(nfc->data & RXH_L4_B_2_3))
2662                         return -EINVAL;
2663                 break;
2664         case UDP_V4_FLOW:
2665                 if (!(nfc->data & RXH_IP_SRC) ||
2666                     !(nfc->data & RXH_IP_DST))
2667                         return -EINVAL;
2668                 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2669                 case 0:
2670                         flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2671                         break;
2672                 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2673                         flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2674                         break;
2675                 default:
2676                         return -EINVAL;
2677                 }
2678                 break;
2679         case UDP_V6_FLOW:
2680                 if (!(nfc->data & RXH_IP_SRC) ||
2681                     !(nfc->data & RXH_IP_DST))
2682                         return -EINVAL;
2683                 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2684                 case 0:
2685                         flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2686                         break;
2687                 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2688                         flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2689                         break;
2690                 default:
2691                         return -EINVAL;
2692                 }
2693                 break;
2694         case AH_ESP_V4_FLOW:
2695         case AH_V4_FLOW:
2696         case ESP_V4_FLOW:
2697         case SCTP_V4_FLOW:
2698         case AH_ESP_V6_FLOW:
2699         case AH_V6_FLOW:
2700         case ESP_V6_FLOW:
2701         case SCTP_V6_FLOW:
2702                 if (!(nfc->data & RXH_IP_SRC) ||
2703                     !(nfc->data & RXH_IP_DST) ||
2704                     (nfc->data & RXH_L4_B_0_1) ||
2705                     (nfc->data & RXH_L4_B_2_3))
2706                         return -EINVAL;
2707                 break;
2708         default:
2709                 return -EINVAL;
2710         }
2711
2712         /* if we changed something we need to update flags */
2713         if (flags2 != adapter->flags2) {
2714                 struct ixgbe_hw *hw = &adapter->hw;
2715                 u32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2716
2717                 if ((flags2 & UDP_RSS_FLAGS) &&
2718                     !(adapter->flags2 & UDP_RSS_FLAGS))
2719                         e_warn(drv, "enabling UDP RSS: fragmented packets"
2720                                " may arrive out of order to the stack above\n");
2721
2722                 adapter->flags2 = flags2;
2723
2724                 /* Perform hash on these packet types */
2725                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2726                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2727                       | IXGBE_MRQC_RSS_FIELD_IPV6
2728                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2729
2730                 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2731                           IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2732
2733                 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2734                         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2735
2736                 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2737                         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2738
2739                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2740         }
2741
2742         return 0;
2743 }
2744
2745 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2746 {
2747         struct ixgbe_adapter *adapter = netdev_priv(dev);
2748         int ret = -EOPNOTSUPP;
2749
2750         switch (cmd->cmd) {
2751         case ETHTOOL_SRXCLSRLINS:
2752                 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2753                 break;
2754         case ETHTOOL_SRXCLSRLDEL:
2755                 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2756                 break;
2757         case ETHTOOL_SRXFH:
2758                 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2759                 break;
2760         default:
2761                 break;
2762         }
2763
2764         return ret;
2765 }
2766
2767 static int ixgbe_get_ts_info(struct net_device *dev,
2768                              struct ethtool_ts_info *info)
2769 {
2770         struct ixgbe_adapter *adapter = netdev_priv(dev);
2771
2772         switch (adapter->hw.mac.type) {
2773         case ixgbe_mac_X540:
2774         case ixgbe_mac_82599EB:
2775                 info->so_timestamping =
2776                         SOF_TIMESTAMPING_TX_SOFTWARE |
2777                         SOF_TIMESTAMPING_RX_SOFTWARE |
2778                         SOF_TIMESTAMPING_SOFTWARE |
2779                         SOF_TIMESTAMPING_TX_HARDWARE |
2780                         SOF_TIMESTAMPING_RX_HARDWARE |
2781                         SOF_TIMESTAMPING_RAW_HARDWARE;
2782
2783                 if (adapter->ptp_clock)
2784                         info->phc_index = ptp_clock_index(adapter->ptp_clock);
2785                 else
2786                         info->phc_index = -1;
2787
2788                 info->tx_types =
2789                         (1 << HWTSTAMP_TX_OFF) |
2790                         (1 << HWTSTAMP_TX_ON);
2791
2792                 info->rx_filters =
2793                         (1 << HWTSTAMP_FILTER_NONE) |
2794                         (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2795                         (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2796                         (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2797                         (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2798                         (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
2799                         (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2800                         (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2801                         (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2802                         (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2803                         (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2804                         (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2805                 break;
2806         default:
2807                 return ethtool_op_get_ts_info(dev, info);
2808                 break;
2809         }
2810         return 0;
2811 }
2812
2813 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
2814 {
2815         unsigned int max_combined;
2816         u8 tcs = netdev_get_num_tc(adapter->netdev);
2817
2818         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2819                 /* We only support one q_vector without MSI-X */
2820                 max_combined = 1;
2821         } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2822                 /* SR-IOV currently only allows one queue on the PF */
2823                 max_combined = 1;
2824         } else if (tcs > 1) {
2825                 /* For DCB report channels per traffic class */
2826                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2827                         /* 8 TC w/ 4 queues per TC */
2828                         max_combined = 4;
2829                 } else if (tcs > 4) {
2830                         /* 8 TC w/ 8 queues per TC */
2831                         max_combined = 8;
2832                 } else {
2833                         /* 4 TC w/ 16 queues per TC */
2834                         max_combined = 16;
2835                 }
2836         } else if (adapter->atr_sample_rate) {
2837                 /* support up to 64 queues with ATR */
2838                 max_combined = IXGBE_MAX_FDIR_INDICES;
2839         } else {
2840                 /* support up to 16 queues with RSS */
2841                 max_combined = IXGBE_MAX_RSS_INDICES;
2842         }
2843
2844         return max_combined;
2845 }
2846
2847 static void ixgbe_get_channels(struct net_device *dev,
2848                                struct ethtool_channels *ch)
2849 {
2850         struct ixgbe_adapter *adapter = netdev_priv(dev);
2851
2852         /* report maximum channels */
2853         ch->max_combined = ixgbe_max_channels(adapter);
2854
2855         /* report info for other vector */
2856         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2857                 ch->max_other = NON_Q_VECTORS;
2858                 ch->other_count = NON_Q_VECTORS;
2859         }
2860
2861         /* record RSS queues */
2862         ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
2863
2864         /* nothing else to report if RSS is disabled */
2865         if (ch->combined_count == 1)
2866                 return;
2867
2868         /* we do not support ATR queueing if SR-IOV is enabled */
2869         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
2870                 return;
2871
2872         /* same thing goes for being DCB enabled */
2873         if (netdev_get_num_tc(dev) > 1)
2874                 return;
2875
2876         /* if ATR is disabled we can exit */
2877         if (!adapter->atr_sample_rate)
2878                 return;
2879
2880         /* report flow director queues as maximum channels */
2881         ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
2882 }
2883
2884 static int ixgbe_set_channels(struct net_device *dev,
2885                               struct ethtool_channels *ch)
2886 {
2887         struct ixgbe_adapter *adapter = netdev_priv(dev);
2888         unsigned int count = ch->combined_count;
2889
2890         /* verify they are not requesting separate vectors */
2891         if (!count || ch->rx_count || ch->tx_count)
2892                 return -EINVAL;
2893
2894         /* verify other_count has not changed */
2895         if (ch->other_count != NON_Q_VECTORS)
2896                 return -EINVAL;
2897
2898         /* verify the number of channels does not exceed hardware limits */
2899         if (count > ixgbe_max_channels(adapter))
2900                 return -EINVAL;
2901
2902         /* update feature limits from largest to smallest supported values */
2903         adapter->ring_feature[RING_F_FDIR].limit = count;
2904
2905         /* cap RSS limit at 16 */
2906         if (count > IXGBE_MAX_RSS_INDICES)
2907                 count = IXGBE_MAX_RSS_INDICES;
2908         adapter->ring_feature[RING_F_RSS].limit = count;
2909
2910 #ifdef IXGBE_FCOE
2911         /* cap FCoE limit at 8 */
2912         if (count > IXGBE_FCRETA_SIZE)
2913                 count = IXGBE_FCRETA_SIZE;
2914         adapter->ring_feature[RING_F_FCOE].limit = count;
2915
2916 #endif
2917         /* use setup TC to update any traffic class queue mapping */
2918         return ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
2919 }
2920
2921 static int ixgbe_get_module_info(struct net_device *dev,
2922                                        struct ethtool_modinfo *modinfo)
2923 {
2924         struct ixgbe_adapter *adapter = netdev_priv(dev);
2925         struct ixgbe_hw *hw = &adapter->hw;
2926         u32 status;
2927         u8 sff8472_rev, addr_mode;
2928         bool page_swap = false;
2929
2930         /* Check whether we support SFF-8472 or not */
2931         status = hw->phy.ops.read_i2c_eeprom(hw,
2932                                              IXGBE_SFF_SFF_8472_COMP,
2933                                              &sff8472_rev);
2934         if (status != 0)
2935                 return -EIO;
2936
2937         /* addressing mode is not supported */
2938         status = hw->phy.ops.read_i2c_eeprom(hw,
2939                                              IXGBE_SFF_SFF_8472_SWAP,
2940                                              &addr_mode);
2941         if (status != 0)
2942                 return -EIO;
2943
2944         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
2945                 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2946                 page_swap = true;
2947         }
2948
2949         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
2950                 /* We have a SFP, but it does not support SFF-8472 */
2951                 modinfo->type = ETH_MODULE_SFF_8079;
2952                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2953         } else {
2954                 /* We have a SFP which supports a revision of SFF-8472. */
2955                 modinfo->type = ETH_MODULE_SFF_8472;
2956                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2957         }
2958
2959         return 0;
2960 }
2961
2962 static int ixgbe_get_module_eeprom(struct net_device *dev,
2963                                          struct ethtool_eeprom *ee,
2964                                          u8 *data)
2965 {
2966         struct ixgbe_adapter *adapter = netdev_priv(dev);
2967         struct ixgbe_hw *hw = &adapter->hw;
2968         u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2969         u8 databyte = 0xFF;
2970         int i = 0;
2971
2972         if (ee->len == 0)
2973                 return -EINVAL;
2974
2975         for (i = ee->offset; i < ee->offset + ee->len; i++) {
2976                 /* I2C reads can take long time */
2977                 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
2978                         return -EBUSY;
2979
2980                 if (i < ETH_MODULE_SFF_8079_LEN)
2981                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
2982                 else
2983                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
2984
2985                 if (status != 0)
2986                         return -EIO;
2987
2988                 data[i - ee->offset] = databyte;
2989         }
2990
2991         return 0;
2992 }
2993
2994 static const struct ethtool_ops ixgbe_ethtool_ops = {
2995         .get_settings           = ixgbe_get_settings,
2996         .set_settings           = ixgbe_set_settings,
2997         .get_drvinfo            = ixgbe_get_drvinfo,
2998         .get_regs_len           = ixgbe_get_regs_len,
2999         .get_regs               = ixgbe_get_regs,
3000         .get_wol                = ixgbe_get_wol,
3001         .set_wol                = ixgbe_set_wol,
3002         .nway_reset             = ixgbe_nway_reset,
3003         .get_link               = ethtool_op_get_link,
3004         .get_eeprom_len         = ixgbe_get_eeprom_len,
3005         .get_eeprom             = ixgbe_get_eeprom,
3006         .set_eeprom             = ixgbe_set_eeprom,
3007         .get_ringparam          = ixgbe_get_ringparam,
3008         .set_ringparam          = ixgbe_set_ringparam,
3009         .get_pauseparam         = ixgbe_get_pauseparam,
3010         .set_pauseparam         = ixgbe_set_pauseparam,
3011         .get_msglevel           = ixgbe_get_msglevel,
3012         .set_msglevel           = ixgbe_set_msglevel,
3013         .self_test              = ixgbe_diag_test,
3014         .get_strings            = ixgbe_get_strings,
3015         .set_phys_id            = ixgbe_set_phys_id,
3016         .get_sset_count         = ixgbe_get_sset_count,
3017         .get_ethtool_stats      = ixgbe_get_ethtool_stats,
3018         .get_coalesce           = ixgbe_get_coalesce,
3019         .set_coalesce           = ixgbe_set_coalesce,
3020         .get_rxnfc              = ixgbe_get_rxnfc,
3021         .set_rxnfc              = ixgbe_set_rxnfc,
3022         .get_channels           = ixgbe_get_channels,
3023         .set_channels           = ixgbe_set_channels,
3024         .get_ts_info            = ixgbe_get_ts_info,
3025         .get_module_info        = ixgbe_get_module_info,
3026         .get_module_eeprom      = ixgbe_get_module_eeprom,
3027 };
3028
3029 void ixgbe_set_ethtool_ops(struct net_device *netdev)
3030 {
3031         SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
3032 }