drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2014 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #include <linux/pci.h>
  30 #include <linux/delay.h>
  31 #include <linux/sched.h>
  32
  33 #include "ixgbe.h"
  34 #include "ixgbe_phy.h"
  35
  36 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  37 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  38 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  39 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  40 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  41 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  42 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  43 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  44 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  45 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  46 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  47 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  50 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
  51
  52 /**
  53  *  ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  *  @hw: pointer to the hardware structure
  55  *  @byte: byte to send
  56  *
  57  *  Returns an error code on error.
  58  **/
  59 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  *  ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  *  @hw: pointer to the hardware structure
  72  *  @byte: pointer to a u8 to receive the byte
  73  *
  74  *  Returns an error code on error.
  75  **/
  76 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  *  ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  *  @add1: addend 1
  90  *  @add2: addend 2
  91  *
  92  *  Returns one's complement 8-bit sum.
  93  **/
  94 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  *  ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  *  @hw: pointer to the hardware structure
 105  *  @addr: I2C bus address to read from
 106  *  @reg: I2C device register to read from
 107  *  @val: pointer to location to receive read value
 108  *  @lock: true if to take and release semaphore
 109  *
 110  *  Returns an error code on error.
 111  */
 112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
 113                                         u16 reg, u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 125         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 126         csum = ~csum;
 127         do {
 128                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 129                         return IXGBE_ERR_SWFW_SYNC;
 130                 ixgbe_i2c_start(hw);
 131                 /* Device Address and write indication */
 132                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 133                         goto fail;
 134                 /* Write bits 14:8 */
 135                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 136                         goto fail;
 137                 /* Write bits 7:0 */
 138                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 139                         goto fail;
 140                 /* Write csum */
 141                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 142                         goto fail;
 143                 /* Re-start condition */
 144                 ixgbe_i2c_start(hw);
 145                 /* Device Address and read indication */
 146                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 147                         goto fail;
 148                 /* Get upper bits */
 149                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 150                         goto fail;
 151                 /* Get low bits */
 152                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 153                         goto fail;
 154                 /* Get csum */
 155                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 156                         goto fail;
 157                 /* NACK */
 158                 if (ixgbe_clock_out_i2c_bit(hw, false))
 159                         goto fail;
 160                 ixgbe_i2c_stop(hw);
 161                 if (lock)
 162                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 163                 *val = (high_bits << 8) | low_bits;
 164                 return 0;
 165
 166 fail:
 167                 ixgbe_i2c_bus_clear(hw);
 168                 if (lock)
 169                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 170                 retry++;
 171                 if (retry < max_retry)
 172                         hw_dbg(hw, "I2C byte read combined error - Retry.\n");
 173                 else
 174                         hw_dbg(hw, "I2C byte read combined error.\n");
 175         } while (retry < max_retry);
 176
 177         return IXGBE_ERR_I2C;
 178 }
 179
 180 /**
 181  *  ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 182  *  @hw: pointer to the hardware structure
 183  *  @addr: I2C bus address to write to
 184  *  @reg: I2C device register to write to
 185  *  @val: value to write
 186  *  @lock: true if to take and release semaphore
 187  *
 188  *  Returns an error code on error.
 189  */
 190 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
 191                                          u16 reg, u16 val, bool lock)
 192 {
 193         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 194         int max_retry = 1;
 195         int retry = 0;
 196         u8 reg_high;
 197         u8 csum;
 198
 199         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 200         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 201         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 202         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 203         csum = ~csum;
 204         do {
 205                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 206                         return IXGBE_ERR_SWFW_SYNC;
 207                 ixgbe_i2c_start(hw);
 208                 /* Device Address and write indication */
 209                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 210                         goto fail;
 211                 /* Write bits 14:8 */
 212                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 213                         goto fail;
 214                 /* Write bits 7:0 */
 215                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 216                         goto fail;
 217                 /* Write data 15:8 */
 218                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 219                         goto fail;
 220                 /* Write data 7:0 */
 221                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 222                         goto fail;
 223                 /* Write csum */
 224                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 225                         goto fail;
 226                 ixgbe_i2c_stop(hw);
 227                 if (lock)
 228                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 229                 return 0;
 230
 231 fail:
 232                 ixgbe_i2c_bus_clear(hw);
 233                 if (lock)
 234                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 235                 retry++;
 236                 if (retry < max_retry)
 237                         hw_dbg(hw, "I2C byte write combined error - Retry.\n");
 238                 else
 239                         hw_dbg(hw, "I2C byte write combined error.\n");
 240         } while (retry < max_retry);
 241
 242         return IXGBE_ERR_I2C;
 243 }
 244
 245 /**
 246  *  ixgbe_probe_phy - Probe a single address for a PHY
 247  *  @hw: pointer to hardware structure
 248  *  @phy_addr: PHY address to probe
 249  *
 250  *  Returns true if PHY found
 251  **/
 252 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 253 {
 254         u16 ext_ability = 0;
 255
 256         hw->phy.mdio.prtad = phy_addr;
 257         if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
 258                 return false;
 259
 260         if (ixgbe_get_phy_id(hw))
 261                 return false;
 262
 263         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 264
 265         if (hw->phy.type == ixgbe_phy_unknown) {
 266                 hw->phy.ops.read_reg(hw,
 267                                      MDIO_PMA_EXTABLE,
 268                                      MDIO_MMD_PMAPMD,
 269                                      &ext_ability);
 270                 if (ext_ability &
 271                     (MDIO_PMA_EXTABLE_10GBT |
 272                      MDIO_PMA_EXTABLE_1000BT))
 273                         hw->phy.type = ixgbe_phy_cu_unknown;
 274                 else
 275                         hw->phy.type = ixgbe_phy_generic;
 276         }
 277
 278         return true;
 279 }
 280
 281 /**
 282  *  ixgbe_identify_phy_generic - Get physical layer module
 283  *  @hw: pointer to hardware structure
 284  *
 285  *  Determines the physical layer module found on the current adapter.
 286  **/
 287 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 288 {
 289         u32 phy_addr;
 290         u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 291
 292         if (!hw->phy.phy_semaphore_mask) {
 293                 if (hw->bus.lan_id)
 294                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 295                 else
 296                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 297         }
 298
 299         if (hw->phy.type != ixgbe_phy_unknown)
 300                 return 0;
 301
 302         if (hw->phy.nw_mng_if_sel) {
 303                 phy_addr = (hw->phy.nw_mng_if_sel &
 304                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 305                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 306                 if (ixgbe_probe_phy(hw, phy_addr))
 307                         return 0;
 308                 else
 309                         return IXGBE_ERR_PHY_ADDR_INVALID;
 310         }
 311
 312         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 313                 if (ixgbe_probe_phy(hw, phy_addr)) {
 314                         status = 0;
 315                         break;
 316                 }
 317         }
 318
 319         /* Certain media types do not have a phy so an address will not
 320          * be found and the code will take this path.  Caller has to
 321          * decide if it is an error or not.
 322          */
 323         if (status)
 324                 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
 325
 326         return status;
 327 }
 328
 329 /**
 330  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 331  * @hw: pointer to the hardware structure
 332  *
 333  * This function checks the MMNGC.MNG_VETO bit to see if there are
 334  * any constraints on link from manageability.  For MAC's that don't
 335  * have this bit just return false since the link can not be blocked
 336  * via this method.
 337  **/
 338 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 339 {
 340         u32 mmngc;
 341
 342         /* If we don't have this bit, it can't be blocking */
 343         if (hw->mac.type == ixgbe_mac_82598EB)
 344                 return false;
 345
 346         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 347         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 348                 hw_dbg(hw, "MNG_VETO bit detected.\n");
 349                 return true;
 350         }
 351
 352         return false;
 353 }
 354
 355 /**
 356  *  ixgbe_get_phy_id - Get the phy type
 357  *  @hw: pointer to hardware structure
 358  *
 359  **/
 360 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 361 {
 362         s32 status;
 363         u16 phy_id_high = 0;
 364         u16 phy_id_low = 0;
 365
 366         status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
 367                                       &phy_id_high);
 368
 369         if (!status) {
 370                 hw->phy.id = (u32)(phy_id_high << 16);
 371                 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
 372                                               &phy_id_low);
 373                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 374                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 375         }
 376         return status;
 377 }
 378
 379 /**
 380  *  ixgbe_get_phy_type_from_id - Get the phy type
 381  *  @hw: pointer to hardware structure
 382  *
 383  **/
 384 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 385 {
 386         enum ixgbe_phy_type phy_type;
 387
 388         switch (phy_id) {
 389         case TN1010_PHY_ID:
 390                 phy_type = ixgbe_phy_tn;
 391                 break;
 392         case X550_PHY_ID2:
 393         case X550_PHY_ID3:
 394         case X540_PHY_ID:
 395                 phy_type = ixgbe_phy_aq;
 396                 break;
 397         case QT2022_PHY_ID:
 398                 phy_type = ixgbe_phy_qt;
 399                 break;
 400         case ATH_PHY_ID:
 401                 phy_type = ixgbe_phy_nl;
 402                 break;
 403         case X557_PHY_ID:
 404         case X557_PHY_ID2:
 405                 phy_type = ixgbe_phy_x550em_ext_t;
 406                 break;
 407         default:
 408                 phy_type = ixgbe_phy_unknown;
 409                 break;
 410         }
 411
 412         return phy_type;
 413 }
 414
 415 /**
 416  *  ixgbe_reset_phy_generic - Performs a PHY reset
 417  *  @hw: pointer to hardware structure
 418  **/
 419 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 420 {
 421         u32 i;
 422         u16 ctrl = 0;
 423         s32 status = 0;
 424
 425         if (hw->phy.type == ixgbe_phy_unknown)
 426                 status = ixgbe_identify_phy_generic(hw);
 427
 428         if (status != 0 || hw->phy.type == ixgbe_phy_none)
 429                 return status;
 430
 431         /* Don't reset PHY if it's shut down due to overtemp. */
 432         if (!hw->phy.reset_if_overtemp &&
 433             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 434                 return 0;
 435
 436         /* Blocked by MNG FW so bail */
 437         if (ixgbe_check_reset_blocked(hw))
 438                 return 0;
 439
 440         /*
 441          * Perform soft PHY reset to the PHY_XS.
 442          * This will cause a soft reset to the PHY
 443          */
 444         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 445                               MDIO_MMD_PHYXS,
 446                               MDIO_CTRL1_RESET);
 447
 448         /*
 449          * Poll for reset bit to self-clear indicating reset is complete.
 450          * Some PHYs could take up to 3 seconds to complete and need about
 451          * 1.7 usec delay after the reset is complete.
 452          */
 453         for (i = 0; i < 30; i++) {
 454                 msleep(100);
 455                 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &ctrl);
 456                 if (!(ctrl & MDIO_CTRL1_RESET)) {
 457                         udelay(2);
 458                         break;
 459                 }
 460         }
 461
 462         if (ctrl & MDIO_CTRL1_RESET) {
 463                 hw_dbg(hw, "PHY reset polling failed to complete.\n");
 464                 return IXGBE_ERR_RESET_FAILED;
 465         }
 466
 467         return 0;
 468 }
 469
 470 /**
 471  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 472  *  the SWFW lock
 473  *  @hw: pointer to hardware structure
 474  *  @reg_addr: 32 bit address of PHY register to read
 475  *  @phy_data: Pointer to read data from PHY register
 476  **/
 477 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 478                        u16 *phy_data)
 479 {
 480         u32 i, data, command;
 481
 482         /* Setup and write the address cycle command */
 483         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 484                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 485                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 486                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 487
 488         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 489
 490         /* Check every 10 usec to see if the address cycle completed.
 491          * The MDI Command bit will clear when the operation is
 492          * complete
 493          */
 494         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 495                 udelay(10);
 496
 497                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 498                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 499                                 break;
 500         }
 501
 502
 503         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 504                 hw_dbg(hw, "PHY address command did not complete.\n");
 505                 return IXGBE_ERR_PHY;
 506         }
 507
 508         /* Address cycle complete, setup and write the read
 509          * command
 510          */
 511         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 512                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 513                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 514                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 515
 516         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 517
 518         /* Check every 10 usec to see if the address cycle
 519          * completed. The MDI Command bit will clear when the
 520          * operation is complete
 521          */
 522         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 523                 udelay(10);
 524
 525                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 526                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 527                         break;
 528         }
 529
 530         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 531                 hw_dbg(hw, "PHY read command didn't complete\n");
 532                 return IXGBE_ERR_PHY;
 533         }
 534
 535         /* Read operation is complete.  Get the data
 536          * from MSRWD
 537          */
 538         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 539         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 540         *phy_data = (u16)(data);
 541
 542         return 0;
 543 }
 544
 545 /**
 546  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 547  *  using the SWFW lock - this function is needed in most cases
 548  *  @hw: pointer to hardware structure
 549  *  @reg_addr: 32 bit address of PHY register to read
 550  *  @phy_data: Pointer to read data from PHY register
 551  **/
 552 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 553                                u32 device_type, u16 *phy_data)
 554 {
 555         s32 status;
 556         u32 gssr = hw->phy.phy_semaphore_mask;
 557
 558         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 559                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 560                                                 phy_data);
 561                 hw->mac.ops.release_swfw_sync(hw, gssr);
 562         } else {
 563                 return IXGBE_ERR_SWFW_SYNC;
 564         }
 565
 566         return status;
 567 }
 568
 569 /**
 570  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 571  *  without SWFW lock
 572  *  @hw: pointer to hardware structure
 573  *  @reg_addr: 32 bit PHY register to write
 574  *  @device_type: 5 bit device type
 575  *  @phy_data: Data to write to the PHY register
 576  **/
 577 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 578                                 u32 device_type, u16 phy_data)
 579 {
 580         u32 i, command;
 581
 582         /* Put the data in the MDI single read and write data register*/
 583         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 584
 585         /* Setup and write the address cycle command */
 586         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 587                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 588                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 589                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 590
 591         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 592
 593         /*
 594          * Check every 10 usec to see if the address cycle completed.
 595          * The MDI Command bit will clear when the operation is
 596          * complete
 597          */
 598         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 599                 udelay(10);
 600
 601                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 602                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 603                         break;
 604         }
 605
 606         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 607                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 608                 return IXGBE_ERR_PHY;
 609         }
 610
 611         /*
 612          * Address cycle complete, setup and write the write
 613          * command
 614          */
 615         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 616                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 617                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 618                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 619
 620         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 621
 622         /* Check every 10 usec to see if the address cycle
 623          * completed. The MDI Command bit will clear when the
 624          * operation is complete
 625          */
 626         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 627                 udelay(10);
 628
 629                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 630                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 631                         break;
 632         }
 633
 634         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 635                 hw_dbg(hw, "PHY write cmd didn't complete\n");
 636                 return IXGBE_ERR_PHY;
 637         }
 638
 639         return 0;
 640 }
 641
 642 /**
 643  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 644  *  using SWFW lock- this function is needed in most cases
 645  *  @hw: pointer to hardware structure
 646  *  @reg_addr: 32 bit PHY register to write
 647  *  @device_type: 5 bit device type
 648  *  @phy_data: Data to write to the PHY register
 649  **/
 650 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 651                                 u32 device_type, u16 phy_data)
 652 {
 653         s32 status;
 654         u32 gssr = hw->phy.phy_semaphore_mask;
 655
 656         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 657                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 658                                                  phy_data);
 659                 hw->mac.ops.release_swfw_sync(hw, gssr);
 660         } else {
 661                 return IXGBE_ERR_SWFW_SYNC;
 662         }
 663
 664         return status;
 665 }
 666
 667 /**
 668  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 669  *  @hw: pointer to hardware structure
 670  *
 671  *  Restart autonegotiation and PHY and waits for completion.
 672  **/
 673 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 674 {
 675         s32 status = 0;
 676         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 677         bool autoneg = false;
 678         ixgbe_link_speed speed;
 679
 680         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 681
 682         /* Set or unset auto-negotiation 10G advertisement */
 683         hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
 684
 685         autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 686         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 687             (speed & IXGBE_LINK_SPEED_10GB_FULL))
 688                 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 689
 690         hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
 691
 692         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 693                              MDIO_MMD_AN, &autoneg_reg);
 694
 695         if (hw->mac.type == ixgbe_mac_X550) {
 696                 /* Set or unset auto-negotiation 5G advertisement */
 697                 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 698                 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 699                     (speed & IXGBE_LINK_SPEED_5GB_FULL))
 700                         autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 701
 702                 /* Set or unset auto-negotiation 2.5G advertisement */
 703                 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 704                 if ((hw->phy.autoneg_advertised &
 705                      IXGBE_LINK_SPEED_2_5GB_FULL) &&
 706                     (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 707                         autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 708         }
 709
 710         /* Set or unset auto-negotiation 1G advertisement */
 711         autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 712         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 713             (speed & IXGBE_LINK_SPEED_1GB_FULL))
 714                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 715
 716         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 717                               MDIO_MMD_AN, autoneg_reg);
 718
 719         /* Set or unset auto-negotiation 100M advertisement */
 720         hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
 721
 722         autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
 723         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 724             (speed & IXGBE_LINK_SPEED_100_FULL))
 725                 autoneg_reg |= ADVERTISE_100FULL;
 726
 727         hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
 728
 729         /* Blocked by MNG FW so don't reset PHY */
 730         if (ixgbe_check_reset_blocked(hw))
 731                 return 0;
 732
 733         /* Restart PHY autonegotiation and wait for completion */
 734         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 735                              MDIO_MMD_AN, &autoneg_reg);
 736
 737         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 738
 739         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 740                               MDIO_MMD_AN, autoneg_reg);
 741
 742         return status;
 743 }
 744
 745 /**
 746  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 747  *  @hw: pointer to hardware structure
 748  *  @speed: new link speed
 749  **/
 750 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 751                                        ixgbe_link_speed speed,
 752                                        bool autoneg_wait_to_complete)
 753 {
 754
 755         /*
 756          * Clear autoneg_advertised and set new values based on input link
 757          * speed.
 758          */
 759         hw->phy.autoneg_advertised = 0;
 760
 761         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 762                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 763
 764         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 765                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 766
 767         if (speed & IXGBE_LINK_SPEED_100_FULL)
 768                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 769
 770         /* Setup link based on the new speed settings */
 771         hw->phy.ops.setup_link(hw);
 772
 773         return 0;
 774 }
 775
 776 /**
 777  * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
 778  * @hw: pointer to hardware structure
 779  *
 780  * Determines the supported link capabilities by reading the PHY auto
 781  * negotiation register.
 782  */
 783 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 784 {
 785         u16 speed_ability;
 786         s32 status;
 787
 788         status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
 789                                       &speed_ability);
 790         if (status)
 791                 return status;
 792
 793         if (speed_ability & MDIO_SPEED_10G)
 794                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 795         if (speed_ability & MDIO_PMA_SPEED_1000)
 796                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 797         if (speed_ability & MDIO_PMA_SPEED_100)
 798                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 799
 800         switch (hw->mac.type) {
 801         case ixgbe_mac_X550:
 802                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 803                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 804                 break;
 805         case ixgbe_mac_X550EM_x:
 806         case ixgbe_mac_x550em_a:
 807                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 808                 break;
 809         default:
 810                 break;
 811         }
 812
 813         return 0;
 814 }
 815
 816 /**
 817  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 818  * @hw: pointer to hardware structure
 819  * @speed: pointer to link speed
 820  * @autoneg: boolean auto-negotiation value
 821  */
 822 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 823                                                ixgbe_link_speed *speed,
 824                                                bool *autoneg)
 825 {
 826         s32 status = 0;
 827
 828         *autoneg = true;
 829         if (!hw->phy.speeds_supported)
 830                 status = ixgbe_get_copper_speeds_supported(hw);
 831
 832         *speed = hw->phy.speeds_supported;
 833         return status;
 834 }
 835
 836 /**
 837  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 838  *  @hw: pointer to hardware structure
 839  *
 840  *  Reads the VS1 register to determine if link is up and the current speed for
 841  *  the PHY.
 842  **/
 843 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 844                              bool *link_up)
 845 {
 846         s32 status;
 847         u32 time_out;
 848         u32 max_time_out = 10;
 849         u16 phy_link = 0;
 850         u16 phy_speed = 0;
 851         u16 phy_data = 0;
 852
 853         /* Initialize speed and link to default case */
 854         *link_up = false;
 855         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 856
 857         /*
 858          * Check current speed and link status of the PHY register.
 859          * This is a vendor specific register and may have to
 860          * be changed for other copper PHYs.
 861          */
 862         for (time_out = 0; time_out < max_time_out; time_out++) {
 863                 udelay(10);
 864                 status = hw->phy.ops.read_reg(hw,
 865                                               MDIO_STAT1,
 866                                               MDIO_MMD_VEND1,
 867                                               &phy_data);
 868                 phy_link = phy_data &
 869                             IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 870                 phy_speed = phy_data &
 871                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 872                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 873                         *link_up = true;
 874                         if (phy_speed ==
 875                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 876                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 877                         break;
 878                 }
 879         }
 880
 881         return status;
 882 }
 883
 884 /**
 885  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 886  *      @hw: pointer to hardware structure
 887  *
 888  *      Restart autonegotiation and PHY and waits for completion.
 889  *      This function always returns success, this is nessary since
 890  *      it is called via a function pointer that could call other
 891  *      functions that could return an error.
 892  **/
 893 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 894 {
 895         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 896         bool autoneg = false;
 897         ixgbe_link_speed speed;
 898
 899         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 900
 901         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 902                 /* Set or unset auto-negotiation 10G advertisement */
 903                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 904                                      MDIO_MMD_AN,
 905                                      &autoneg_reg);
 906
 907                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 908                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 909                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 910
 911                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 912                                       MDIO_MMD_AN,
 913                                       autoneg_reg);
 914         }
 915
 916         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 917                 /* Set or unset auto-negotiation 1G advertisement */
 918                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 919                                      MDIO_MMD_AN,
 920                                      &autoneg_reg);
 921
 922                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 923                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 924                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 925
 926                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 927                                       MDIO_MMD_AN,
 928                                       autoneg_reg);
 929         }
 930
 931         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 932                 /* Set or unset auto-negotiation 100M advertisement */
 933                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 934                                      MDIO_MMD_AN,
 935                                      &autoneg_reg);
 936
 937                 autoneg_reg &= ~(ADVERTISE_100FULL |
 938                                  ADVERTISE_100HALF);
 939                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 940                         autoneg_reg |= ADVERTISE_100FULL;
 941
 942                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 943                                       MDIO_MMD_AN,
 944                                       autoneg_reg);
 945         }
 946
 947         /* Blocked by MNG FW so don't reset PHY */
 948         if (ixgbe_check_reset_blocked(hw))
 949                 return 0;
 950
 951         /* Restart PHY autonegotiation and wait for completion */
 952         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 953                              MDIO_MMD_AN, &autoneg_reg);
 954
 955         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 956
 957         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 958                               MDIO_MMD_AN, autoneg_reg);
 959         return 0;
 960 }
 961
 962 /**
 963  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 964  *  @hw: pointer to hardware structure
 965  *  @firmware_version: pointer to the PHY Firmware Version
 966  **/
 967 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 968                                        u16 *firmware_version)
 969 {
 970         s32 status;
 971
 972         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 973                                       MDIO_MMD_VEND1,
 974                                       firmware_version);
 975
 976         return status;
 977 }
 978
 979 /**
 980  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 981  *  @hw: pointer to hardware structure
 982  *  @firmware_version: pointer to the PHY Firmware Version
 983  **/
 984 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 985                                            u16 *firmware_version)
 986 {
 987         s32 status;
 988
 989         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 990                                       MDIO_MMD_VEND1,
 991                                       firmware_version);
 992
 993         return status;
 994 }
 995
 996 /**
 997  *  ixgbe_reset_phy_nl - Performs a PHY reset
 998  *  @hw: pointer to hardware structure
 999  **/
1000 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1001 {
1002         u16 phy_offset, control, eword, edata, block_crc;
1003         bool end_data = false;
1004         u16 list_offset, data_offset;
1005         u16 phy_data = 0;
1006         s32 ret_val;
1007         u32 i;
1008
1009         /* Blocked by MNG FW so bail */
1010         if (ixgbe_check_reset_blocked(hw))
1011                 return 0;
1012
1013         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1014
1015         /* reset the PHY and poll for completion */
1016         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1017                               (phy_data | MDIO_CTRL1_RESET));
1018
1019         for (i = 0; i < 100; i++) {
1020                 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1021                                      &phy_data);
1022                 if ((phy_data & MDIO_CTRL1_RESET) == 0)
1023                         break;
1024                 usleep_range(10000, 20000);
1025         }
1026
1027         if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1028                 hw_dbg(hw, "PHY reset did not complete.\n");
1029                 return IXGBE_ERR_PHY;
1030         }
1031
1032         /* Get init offsets */
1033         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1034                                                       &data_offset);
1035         if (ret_val)
1036                 return ret_val;
1037
1038         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1039         data_offset++;
1040         while (!end_data) {
1041                 /*
1042                  * Read control word from PHY init contents offset
1043                  */
1044                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1045                 if (ret_val)
1046                         goto err_eeprom;
1047                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1048                            IXGBE_CONTROL_SHIFT_NL;
1049                 edata = eword & IXGBE_DATA_MASK_NL;
1050                 switch (control) {
1051                 case IXGBE_DELAY_NL:
1052                         data_offset++;
1053                         hw_dbg(hw, "DELAY: %d MS\n", edata);
1054                         usleep_range(edata * 1000, edata * 2000);
1055                         break;
1056                 case IXGBE_DATA_NL:
1057                         hw_dbg(hw, "DATA:\n");
1058                         data_offset++;
1059                         ret_val = hw->eeprom.ops.read(hw, data_offset++,
1060                                                       &phy_offset);
1061                         if (ret_val)
1062                                 goto err_eeprom;
1063                         for (i = 0; i < edata; i++) {
1064                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1065                                                               &eword);
1066                                 if (ret_val)
1067                                         goto err_eeprom;
1068                                 hw->phy.ops.write_reg(hw, phy_offset,
1069                                                       MDIO_MMD_PMAPMD, eword);
1070                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1071                                        phy_offset);
1072                                 data_offset++;
1073                                 phy_offset++;
1074                         }
1075                         break;
1076                 case IXGBE_CONTROL_NL:
1077                         data_offset++;
1078                         hw_dbg(hw, "CONTROL:\n");
1079                         if (edata == IXGBE_CONTROL_EOL_NL) {
1080                                 hw_dbg(hw, "EOL\n");
1081                                 end_data = true;
1082                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1083                                 hw_dbg(hw, "SOL\n");
1084                         } else {
1085                                 hw_dbg(hw, "Bad control value\n");
1086                                 return IXGBE_ERR_PHY;
1087                         }
1088                         break;
1089                 default:
1090                         hw_dbg(hw, "Bad control type\n");
1091                         return IXGBE_ERR_PHY;
1092                 }
1093         }
1094
1095         return ret_val;
1096
1097 err_eeprom:
1098         hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1099         return IXGBE_ERR_PHY;
1100 }
1101
1102 /**
1103  *  ixgbe_identify_module_generic - Identifies module type
1104  *  @hw: pointer to hardware structure
1105  *
1106  *  Determines HW type and calls appropriate function.
1107  **/
1108 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1109 {
1110         switch (hw->mac.ops.get_media_type(hw)) {
1111         case ixgbe_media_type_fiber:
1112                 return ixgbe_identify_sfp_module_generic(hw);
1113         case ixgbe_media_type_fiber_qsfp:
1114                 return ixgbe_identify_qsfp_module_generic(hw);
1115         default:
1116                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1117                 return IXGBE_ERR_SFP_NOT_PRESENT;
1118         }
1119
1120         return IXGBE_ERR_SFP_NOT_PRESENT;
1121 }
1122
1123 /**
1124  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1125  *  @hw: pointer to hardware structure
1126  *
1127  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1128  **/
1129 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1130 {
1131         struct ixgbe_adapter *adapter = hw->back;
1132         s32 status;
1133         u32 vendor_oui = 0;
1134         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1135         u8 identifier = 0;
1136         u8 comp_codes_1g = 0;
1137         u8 comp_codes_10g = 0;
1138         u8 oui_bytes[3] = {0, 0, 0};
1139         u8 cable_tech = 0;
1140         u8 cable_spec = 0;
1141         u16 enforce_sfp = 0;
1142
1143         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1144                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1145                 return IXGBE_ERR_SFP_NOT_PRESENT;
1146         }
1147
1148         /* LAN ID is needed for sfp_type determination */
1149         hw->mac.ops.set_lan_id(hw);
1150
1151         status = hw->phy.ops.read_i2c_eeprom(hw,
1152                                              IXGBE_SFF_IDENTIFIER,
1153                                              &identifier);
1154
1155         if (status)
1156                 goto err_read_i2c_eeprom;
1157
1158         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1159                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1160                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1161         }
1162         status = hw->phy.ops.read_i2c_eeprom(hw,
1163                                              IXGBE_SFF_1GBE_COMP_CODES,
1164                                              &comp_codes_1g);
1165
1166         if (status)
1167                 goto err_read_i2c_eeprom;
1168
1169         status = hw->phy.ops.read_i2c_eeprom(hw,
1170                                              IXGBE_SFF_10GBE_COMP_CODES,
1171                                              &comp_codes_10g);
1172
1173         if (status)
1174                 goto err_read_i2c_eeprom;
1175         status = hw->phy.ops.read_i2c_eeprom(hw,
1176                                              IXGBE_SFF_CABLE_TECHNOLOGY,
1177                                              &cable_tech);
1178
1179         if (status)
1180                 goto err_read_i2c_eeprom;
1181
1182          /* ID Module
1183           * =========
1184           * 0   SFP_DA_CU
1185           * 1   SFP_SR
1186           * 2   SFP_LR
1187           * 3   SFP_DA_CORE0 - 82599-specific
1188           * 4   SFP_DA_CORE1 - 82599-specific
1189           * 5   SFP_SR/LR_CORE0 - 82599-specific
1190           * 6   SFP_SR/LR_CORE1 - 82599-specific
1191           * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1192           * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1193           * 9   SFP_1g_cu_CORE0 - 82599-specific
1194           * 10  SFP_1g_cu_CORE1 - 82599-specific
1195           * 11  SFP_1g_sx_CORE0 - 82599-specific
1196           * 12  SFP_1g_sx_CORE1 - 82599-specific
1197           */
1198         if (hw->mac.type == ixgbe_mac_82598EB) {
1199                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1200                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1201                 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1202                         hw->phy.sfp_type = ixgbe_sfp_type_sr;
1203                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1204                         hw->phy.sfp_type = ixgbe_sfp_type_lr;
1205                 else
1206                         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1207         } else {
1208                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1209                         if (hw->bus.lan_id == 0)
1210                                 hw->phy.sfp_type =
1211                                              ixgbe_sfp_type_da_cu_core0;
1212                         else
1213                                 hw->phy.sfp_type =
1214                                              ixgbe_sfp_type_da_cu_core1;
1215                 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1216                         hw->phy.ops.read_i2c_eeprom(
1217                                         hw, IXGBE_SFF_CABLE_SPEC_COMP,
1218                                         &cable_spec);
1219                         if (cable_spec &
1220                             IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1221                                 if (hw->bus.lan_id == 0)
1222                                         hw->phy.sfp_type =
1223                                         ixgbe_sfp_type_da_act_lmt_core0;
1224                                 else
1225                                         hw->phy.sfp_type =
1226                                         ixgbe_sfp_type_da_act_lmt_core1;
1227                         } else {
1228                                 hw->phy.sfp_type =
1229                                                 ixgbe_sfp_type_unknown;
1230                         }
1231                 } else if (comp_codes_10g &
1232                            (IXGBE_SFF_10GBASESR_CAPABLE |
1233                             IXGBE_SFF_10GBASELR_CAPABLE)) {
1234                         if (hw->bus.lan_id == 0)
1235                                 hw->phy.sfp_type =
1236                                               ixgbe_sfp_type_srlr_core0;
1237                         else
1238                                 hw->phy.sfp_type =
1239                                               ixgbe_sfp_type_srlr_core1;
1240                 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1241                         if (hw->bus.lan_id == 0)
1242                                 hw->phy.sfp_type =
1243                                         ixgbe_sfp_type_1g_cu_core0;
1244                         else
1245                                 hw->phy.sfp_type =
1246                                         ixgbe_sfp_type_1g_cu_core1;
1247                 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1248                         if (hw->bus.lan_id == 0)
1249                                 hw->phy.sfp_type =
1250                                         ixgbe_sfp_type_1g_sx_core0;
1251                         else
1252                                 hw->phy.sfp_type =
1253                                         ixgbe_sfp_type_1g_sx_core1;
1254                 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1255                         if (hw->bus.lan_id == 0)
1256                                 hw->phy.sfp_type =
1257                                         ixgbe_sfp_type_1g_lx_core0;
1258                         else
1259                                 hw->phy.sfp_type =
1260                                         ixgbe_sfp_type_1g_lx_core1;
1261                 } else {
1262                         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1263                 }
1264         }
1265
1266         if (hw->phy.sfp_type != stored_sfp_type)
1267                 hw->phy.sfp_setup_needed = true;
1268
1269         /* Determine if the SFP+ PHY is dual speed or not. */
1270         hw->phy.multispeed_fiber = false;
1271         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1272              (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1273             ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1274              (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1275                 hw->phy.multispeed_fiber = true;
1276
1277         /* Determine PHY vendor */
1278         if (hw->phy.type != ixgbe_phy_nl) {
1279                 hw->phy.id = identifier;
1280                 status = hw->phy.ops.read_i2c_eeprom(hw,
1281                                             IXGBE_SFF_VENDOR_OUI_BYTE0,
1282                                             &oui_bytes[0]);
1283
1284                 if (status != 0)
1285                         goto err_read_i2c_eeprom;
1286
1287                 status = hw->phy.ops.read_i2c_eeprom(hw,
1288                                             IXGBE_SFF_VENDOR_OUI_BYTE1,
1289                                             &oui_bytes[1]);
1290
1291                 if (status != 0)
1292                         goto err_read_i2c_eeprom;
1293
1294                 status = hw->phy.ops.read_i2c_eeprom(hw,
1295                                             IXGBE_SFF_VENDOR_OUI_BYTE2,
1296                                             &oui_bytes[2]);
1297
1298                 if (status != 0)
1299                         goto err_read_i2c_eeprom;
1300
1301                 vendor_oui =
1302                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1303                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1304                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1305
1306                 switch (vendor_oui) {
1307                 case IXGBE_SFF_VENDOR_OUI_TYCO:
1308                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1309                                 hw->phy.type =
1310                                             ixgbe_phy_sfp_passive_tyco;
1311                         break;
1312                 case IXGBE_SFF_VENDOR_OUI_FTL:
1313                         if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1314                                 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1315                         else
1316                                 hw->phy.type = ixgbe_phy_sfp_ftl;
1317                         break;
1318                 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1319                         hw->phy.type = ixgbe_phy_sfp_avago;
1320                         break;
1321                 case IXGBE_SFF_VENDOR_OUI_INTEL:
1322                         hw->phy.type = ixgbe_phy_sfp_intel;
1323                         break;
1324                 default:
1325                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1326                                 hw->phy.type =
1327                                          ixgbe_phy_sfp_passive_unknown;
1328                         else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1329                                 hw->phy.type =
1330                                         ixgbe_phy_sfp_active_unknown;
1331                         else
1332                                 hw->phy.type = ixgbe_phy_sfp_unknown;
1333                         break;
1334                 }
1335         }
1336
1337         /* Allow any DA cable vendor */
1338         if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1339             IXGBE_SFF_DA_ACTIVE_CABLE))
1340                 return 0;
1341
1342         /* Verify supported 1G SFP modules */
1343         if (comp_codes_10g == 0 &&
1344             !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1345               hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1346               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1347               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1348               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1349               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1350                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1351                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1352         }
1353
1354         /* Anything else 82598-based is supported */
1355         if (hw->mac.type == ixgbe_mac_82598EB)
1356                 return 0;
1357
1358         hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1359         if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1360             !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1361               hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1362               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1363               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1364               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1365               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1366                 /* Make sure we're a supported PHY type */
1367                 if (hw->phy.type == ixgbe_phy_sfp_intel)
1368                         return 0;
1369                 if (hw->allow_unsupported_sfp) {
1370                         e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics.  Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter.  Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1371                         return 0;
1372                 }
1373                 hw_dbg(hw, "SFP+ module not supported\n");
1374                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1375                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1376         }
1377         return 0;
1378
1379 err_read_i2c_eeprom:
1380         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1381         if (hw->phy.type != ixgbe_phy_nl) {
1382                 hw->phy.id = 0;
1383                 hw->phy.type = ixgbe_phy_unknown;
1384         }
1385         return IXGBE_ERR_SFP_NOT_PRESENT;
1386 }
1387
1388 /**
1389  * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1390  * @hw: pointer to hardware structure
1391  *
1392  * Searches for and identifies the QSFP module and assigns appropriate PHY type
1393  **/
1394 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1395 {
1396         struct ixgbe_adapter *adapter = hw->back;
1397         s32 status;
1398         u32 vendor_oui = 0;
1399         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1400         u8 identifier = 0;
1401         u8 comp_codes_1g = 0;
1402         u8 comp_codes_10g = 0;
1403         u8 oui_bytes[3] = {0, 0, 0};
1404         u16 enforce_sfp = 0;
1405         u8 connector = 0;
1406         u8 cable_length = 0;
1407         u8 device_tech = 0;
1408         bool active_cable = false;
1409
1410         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1411                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1412                 return IXGBE_ERR_SFP_NOT_PRESENT;
1413         }
1414
1415         /* LAN ID is needed for sfp_type determination */
1416         hw->mac.ops.set_lan_id(hw);
1417
1418         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1419                                              &identifier);
1420
1421         if (status != 0)
1422                 goto err_read_i2c_eeprom;
1423
1424         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1425                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1426                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1427         }
1428
1429         hw->phy.id = identifier;
1430
1431         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1432                                              &comp_codes_10g);
1433
1434         if (status != 0)
1435                 goto err_read_i2c_eeprom;
1436
1437         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1438                                              &comp_codes_1g);
1439
1440         if (status != 0)
1441                 goto err_read_i2c_eeprom;
1442
1443         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1444                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1445                 if (hw->bus.lan_id == 0)
1446                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1447                 else
1448                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1449         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1450                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1451                 if (hw->bus.lan_id == 0)
1452                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1453                 else
1454                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1455         } else {
1456                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1457                         active_cable = true;
1458
1459                 if (!active_cable) {
1460                         /* check for active DA cables that pre-date
1461                          * SFF-8436 v3.6
1462                          */
1463                         hw->phy.ops.read_i2c_eeprom(hw,
1464                                         IXGBE_SFF_QSFP_CONNECTOR,
1465                                         &connector);
1466
1467                         hw->phy.ops.read_i2c_eeprom(hw,
1468                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1469                                         &cable_length);
1470
1471                         hw->phy.ops.read_i2c_eeprom(hw,
1472                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1473                                         &device_tech);
1474
1475                         if ((connector ==
1476                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1477                             (cable_length > 0) &&
1478                             ((device_tech >> 4) ==
1479                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1480                                 active_cable = true;
1481                 }
1482
1483                 if (active_cable) {
1484                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1485                         if (hw->bus.lan_id == 0)
1486                                 hw->phy.sfp_type =
1487                                                 ixgbe_sfp_type_da_act_lmt_core0;
1488                         else
1489                                 hw->phy.sfp_type =
1490                                                 ixgbe_sfp_type_da_act_lmt_core1;
1491                 } else {
1492                         /* unsupported module type */
1493                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1494                         return IXGBE_ERR_SFP_NOT_SUPPORTED;
1495                 }
1496         }
1497
1498         if (hw->phy.sfp_type != stored_sfp_type)
1499                 hw->phy.sfp_setup_needed = true;
1500
1501         /* Determine if the QSFP+ PHY is dual speed or not. */
1502         hw->phy.multispeed_fiber = false;
1503         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1504              (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1505             ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1506              (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1507                 hw->phy.multispeed_fiber = true;
1508
1509         /* Determine PHY vendor for optical modules */
1510         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1511                               IXGBE_SFF_10GBASELR_CAPABLE)) {
1512                 status = hw->phy.ops.read_i2c_eeprom(hw,
1513                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1514                                         &oui_bytes[0]);
1515
1516                 if (status != 0)
1517                         goto err_read_i2c_eeprom;
1518
1519                 status = hw->phy.ops.read_i2c_eeprom(hw,
1520                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1521                                         &oui_bytes[1]);
1522
1523                 if (status != 0)
1524                         goto err_read_i2c_eeprom;
1525
1526                 status = hw->phy.ops.read_i2c_eeprom(hw,
1527                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1528                                         &oui_bytes[2]);
1529
1530                 if (status != 0)
1531                         goto err_read_i2c_eeprom;
1532
1533                 vendor_oui =
1534                         ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1535                          (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1536                          (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1537
1538                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1539                         hw->phy.type = ixgbe_phy_qsfp_intel;
1540                 else
1541                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1542
1543                 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1544                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1545                         /* Make sure we're a supported PHY type */
1546                         if (hw->phy.type == ixgbe_phy_qsfp_intel)
1547                                 return 0;
1548                         if (hw->allow_unsupported_sfp) {
1549                                 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1550                                 return 0;
1551                         }
1552                         hw_dbg(hw, "QSFP module not supported\n");
1553                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1554                         return IXGBE_ERR_SFP_NOT_SUPPORTED;
1555                 }
1556                 return 0;
1557         }
1558         return 0;
1559
1560 err_read_i2c_eeprom:
1561         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1562         hw->phy.id = 0;
1563         hw->phy.type = ixgbe_phy_unknown;
1564
1565         return IXGBE_ERR_SFP_NOT_PRESENT;
1566 }
1567
1568 /**
1569  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1570  *  @hw: pointer to hardware structure
1571  *  @list_offset: offset to the SFP ID list
1572  *  @data_offset: offset to the SFP data block
1573  *
1574  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1575  *  so it returns the offsets to the phy init sequence block.
1576  **/
1577 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1578                                         u16 *list_offset,
1579                                         u16 *data_offset)
1580 {
1581         u16 sfp_id;
1582         u16 sfp_type = hw->phy.sfp_type;
1583
1584         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1585                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1586
1587         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1588                 return IXGBE_ERR_SFP_NOT_PRESENT;
1589
1590         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1591             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1592                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1593
1594         /*
1595          * Limiting active cables and 1G Phys must be initialized as
1596          * SR modules
1597          */
1598         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1599             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1600             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1601             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1602                 sfp_type = ixgbe_sfp_type_srlr_core0;
1603         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1604                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1605                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1606                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1607                 sfp_type = ixgbe_sfp_type_srlr_core1;
1608
1609         /* Read offset to PHY init contents */
1610         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1611                 hw_err(hw, "eeprom read at %d failed\n",
1612                        IXGBE_PHY_INIT_OFFSET_NL);
1613                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1614         }
1615
1616         if ((!*list_offset) || (*list_offset == 0xFFFF))
1617                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1618
1619         /* Shift offset to first ID word */
1620         (*list_offset)++;
1621
1622         /*
1623          * Find the matching SFP ID in the EEPROM
1624          * and program the init sequence
1625          */
1626         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1627                 goto err_phy;
1628
1629         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1630                 if (sfp_id == sfp_type) {
1631                         (*list_offset)++;
1632                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1633                                 goto err_phy;
1634                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1635                                 hw_dbg(hw, "SFP+ module not supported\n");
1636                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1637                         } else {
1638                                 break;
1639                         }
1640                 } else {
1641                         (*list_offset) += 2;
1642                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1643                                 goto err_phy;
1644                 }
1645         }
1646
1647         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1648                 hw_dbg(hw, "No matching SFP+ module found\n");
1649                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1650         }
1651
1652         return 0;
1653
1654 err_phy:
1655         hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1656         return IXGBE_ERR_PHY;
1657 }
1658
1659 /**
1660  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1661  *  @hw: pointer to hardware structure
1662  *  @byte_offset: EEPROM byte offset to read
1663  *  @eeprom_data: value read
1664  *
1665  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1666  **/
1667 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1668                                   u8 *eeprom_data)
1669 {
1670         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1671                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1672                                          eeprom_data);
1673 }
1674
1675 /**
1676  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1677  *  @hw: pointer to hardware structure
1678  *  @byte_offset: byte offset at address 0xA2
1679  *  @eeprom_data: value read
1680  *
1681  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1682  **/
1683 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1684                                    u8 *sff8472_data)
1685 {
1686         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1687                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1688                                          sff8472_data);
1689 }
1690
1691 /**
1692  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1693  *  @hw: pointer to hardware structure
1694  *  @byte_offset: EEPROM byte offset to write
1695  *  @eeprom_data: value to write
1696  *
1697  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1698  **/
1699 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1700                                    u8 eeprom_data)
1701 {
1702         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1703                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1704                                           eeprom_data);
1705 }
1706
1707 /**
1708  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1709  * @hw: pointer to hardware structure
1710  * @offset: eeprom offset to be read
1711  * @addr: I2C address to be read
1712  */
1713 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1714 {
1715         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1716             offset == IXGBE_SFF_IDENTIFIER &&
1717             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1718                 return true;
1719         return false;
1720 }
1721
1722 /**
1723  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1724  *  @hw: pointer to hardware structure
1725  *  @byte_offset: byte offset to read
1726  *  @data: value read
1727  *  @lock: true if to take and release semaphore
1728  *
1729  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1730  *  a specified device address.
1731  */
1732 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1733                                            u8 dev_addr, u8 *data, bool lock)
1734 {
1735         s32 status;
1736         u32 max_retry = 10;
1737         u32 retry = 0;
1738         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1739         bool nack = true;
1740
1741         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1742                 max_retry = IXGBE_SFP_DETECT_RETRIES;
1743
1744         *data = 0;
1745
1746         do {
1747                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1748                         return IXGBE_ERR_SWFW_SYNC;
1749
1750                 ixgbe_i2c_start(hw);
1751
1752                 /* Device Address and write indication */
1753                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1754                 if (status != 0)
1755                         goto fail;
1756
1757                 status = ixgbe_get_i2c_ack(hw);
1758                 if (status != 0)
1759                         goto fail;
1760
1761                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1762                 if (status != 0)
1763                         goto fail;
1764
1765                 status = ixgbe_get_i2c_ack(hw);
1766                 if (status != 0)
1767                         goto fail;
1768
1769                 ixgbe_i2c_start(hw);
1770
1771                 /* Device Address and read indication */
1772                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1773                 if (status != 0)
1774                         goto fail;
1775
1776                 status = ixgbe_get_i2c_ack(hw);
1777                 if (status != 0)
1778                         goto fail;
1779
1780                 status = ixgbe_clock_in_i2c_byte(hw, data);
1781                 if (status != 0)
1782                         goto fail;
1783
1784                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1785                 if (status != 0)
1786                         goto fail;
1787
1788                 ixgbe_i2c_stop(hw);
1789                 if (lock)
1790                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1791                 return 0;
1792
1793 fail:
1794                 ixgbe_i2c_bus_clear(hw);
1795                 if (lock) {
1796                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1797                         msleep(100);
1798                 }
1799                 retry++;
1800                 if (retry < max_retry)
1801                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
1802                 else
1803                         hw_dbg(hw, "I2C byte read error.\n");
1804
1805         } while (retry < max_retry);
1806
1807         return status;
1808 }
1809
1810 /**
1811  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1812  *  @hw: pointer to hardware structure
1813  *  @byte_offset: byte offset to read
1814  *  @data: value read
1815  *
1816  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1817  *  a specified device address.
1818  */
1819 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1820                                 u8 dev_addr, u8 *data)
1821 {
1822         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1823                                                data, true);
1824 }
1825
1826 /**
1827  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
1828  *  @hw: pointer to hardware structure
1829  *  @byte_offset: byte offset to read
1830  *  @data: value read
1831  *
1832  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1833  *  a specified device address.
1834  */
1835 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1836                                          u8 dev_addr, u8 *data)
1837 {
1838         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1839                                                data, false);
1840 }
1841
1842 /**
1843  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
1844  *  @hw: pointer to hardware structure
1845  *  @byte_offset: byte offset to write
1846  *  @data: value to write
1847  *  @lock: true if to take and release semaphore
1848  *
1849  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1850  *  a specified device address.
1851  */
1852 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1853                                             u8 dev_addr, u8 data, bool lock)
1854 {
1855         s32 status;
1856         u32 max_retry = 1;
1857         u32 retry = 0;
1858         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1859
1860         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1861                 return IXGBE_ERR_SWFW_SYNC;
1862
1863         do {
1864                 ixgbe_i2c_start(hw);
1865
1866                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1867                 if (status != 0)
1868                         goto fail;
1869
1870                 status = ixgbe_get_i2c_ack(hw);
1871                 if (status != 0)
1872                         goto fail;
1873
1874                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1875                 if (status != 0)
1876                         goto fail;
1877
1878                 status = ixgbe_get_i2c_ack(hw);
1879                 if (status != 0)
1880                         goto fail;
1881
1882                 status = ixgbe_clock_out_i2c_byte(hw, data);
1883                 if (status != 0)
1884                         goto fail;
1885
1886                 status = ixgbe_get_i2c_ack(hw);
1887                 if (status != 0)
1888                         goto fail;
1889
1890                 ixgbe_i2c_stop(hw);
1891                 if (lock)
1892                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1893                 return 0;
1894
1895 fail:
1896                 ixgbe_i2c_bus_clear(hw);
1897                 retry++;
1898                 if (retry < max_retry)
1899                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
1900                 else
1901                         hw_dbg(hw, "I2C byte write error.\n");
1902         } while (retry < max_retry);
1903
1904         if (lock)
1905                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1906
1907         return status;
1908 }
1909
1910 /**
1911  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1912  *  @hw: pointer to hardware structure
1913  *  @byte_offset: byte offset to write
1914  *  @data: value to write
1915  *
1916  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1917  *  a specified device address.
1918  */
1919 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1920                                  u8 dev_addr, u8 data)
1921 {
1922         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1923                                                 data, true);
1924 }
1925
1926 /**
1927  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
1928  *  @hw: pointer to hardware structure
1929  *  @byte_offset: byte offset to write
1930  *  @data: value to write
1931  *
1932  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1933  *  a specified device address.
1934  */
1935 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1936                                           u8 dev_addr, u8 data)
1937 {
1938         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1939                                                 data, false);
1940 }
1941
1942 /**
1943  *  ixgbe_i2c_start - Sets I2C start condition
1944  *  @hw: pointer to hardware structure
1945  *
1946  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1947  *  Set bit-bang mode on X550 hardware.
1948  **/
1949 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1950 {
1951         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
1952
1953         i2cctl |= IXGBE_I2C_BB_EN(hw);
1954
1955         /* Start condition must begin with data and clock high */
1956         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1957         ixgbe_raise_i2c_clk(hw, &i2cctl);
1958
1959         /* Setup time for start condition (4.7us) */
1960         udelay(IXGBE_I2C_T_SU_STA);
1961
1962         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1963
1964         /* Hold time for start condition (4us) */
1965         udelay(IXGBE_I2C_T_HD_STA);
1966
1967         ixgbe_lower_i2c_clk(hw, &i2cctl);
1968
1969         /* Minimum low period of clock is 4.7 us */
1970         udelay(IXGBE_I2C_T_LOW);
1971
1972 }
1973
1974 /**
1975  *  ixgbe_i2c_stop - Sets I2C stop condition
1976  *  @hw: pointer to hardware structure
1977  *
1978  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1979  *  Disables bit-bang mode and negates data output enable on X550
1980  *  hardware.
1981  **/
1982 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1983 {
1984         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
1985         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
1986         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
1987         u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
1988
1989         /* Stop condition must begin with data low and clock high */
1990         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1991         ixgbe_raise_i2c_clk(hw, &i2cctl);
1992
1993         /* Setup time for stop condition (4us) */
1994         udelay(IXGBE_I2C_T_SU_STO);
1995
1996         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1997
1998         /* bus free time between stop and start (4.7us)*/
1999         udelay(IXGBE_I2C_T_BUF);
2000
2001         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2002                 i2cctl &= ~bb_en_bit;
2003                 i2cctl |= data_oe_bit | clk_oe_bit;
2004                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2005                 IXGBE_WRITE_FLUSH(hw);
2006         }
2007 }
2008
2009 /**
2010  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2011  *  @hw: pointer to hardware structure
2012  *  @data: data byte to clock in
2013  *
2014  *  Clocks in one byte data via I2C data/clock
2015  **/
2016 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2017 {
2018         s32 i;
2019         bool bit = false;
2020
2021         *data = 0;
2022         for (i = 7; i >= 0; i--) {
2023                 ixgbe_clock_in_i2c_bit(hw, &bit);
2024                 *data |= bit << i;
2025         }
2026
2027         return 0;
2028 }
2029
2030 /**
2031  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2032  *  @hw: pointer to hardware structure
2033  *  @data: data byte clocked out
2034  *
2035  *  Clocks out one byte data via I2C data/clock
2036  **/
2037 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2038 {
2039         s32 status;
2040         s32 i;
2041         u32 i2cctl;
2042         bool bit = false;
2043
2044         for (i = 7; i >= 0; i--) {
2045                 bit = (data >> i) & 0x1;
2046                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2047
2048                 if (status != 0)
2049                         break;
2050         }
2051
2052         /* Release SDA line (set high) */
2053         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2054         i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2055         i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2056         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2057         IXGBE_WRITE_FLUSH(hw);
2058
2059         return status;
2060 }
2061
2062 /**
2063  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2064  *  @hw: pointer to hardware structure
2065  *
2066  *  Clocks in/out one bit via I2C data/clock
2067  **/
2068 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2069 {
2070         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2071         s32 status = 0;
2072         u32 i = 0;
2073         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2074         u32 timeout = 10;
2075         bool ack = true;
2076
2077         if (data_oe_bit) {
2078                 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2079                 i2cctl |= data_oe_bit;
2080                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2081                 IXGBE_WRITE_FLUSH(hw);
2082         }
2083         ixgbe_raise_i2c_clk(hw, &i2cctl);
2084
2085         /* Minimum high period of clock is 4us */
2086         udelay(IXGBE_I2C_T_HIGH);
2087
2088         /* Poll for ACK.  Note that ACK in I2C spec is
2089          * transition from 1 to 0 */
2090         for (i = 0; i < timeout; i++) {
2091                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2092                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2093
2094                 udelay(1);
2095                 if (ack == 0)
2096                         break;
2097         }
2098
2099         if (ack == 1) {
2100                 hw_dbg(hw, "I2C ack was not received.\n");
2101                 status = IXGBE_ERR_I2C;
2102         }
2103
2104         ixgbe_lower_i2c_clk(hw, &i2cctl);
2105
2106         /* Minimum low period of clock is 4.7 us */
2107         udelay(IXGBE_I2C_T_LOW);
2108
2109         return status;
2110 }
2111
2112 /**
2113  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2114  *  @hw: pointer to hardware structure
2115  *  @data: read data value
2116  *
2117  *  Clocks in one bit via I2C data/clock
2118  **/
2119 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2120 {
2121         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2122         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2123
2124         if (data_oe_bit) {
2125                 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2126                 i2cctl |= data_oe_bit;
2127                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2128                 IXGBE_WRITE_FLUSH(hw);
2129         }
2130         ixgbe_raise_i2c_clk(hw, &i2cctl);
2131
2132         /* Minimum high period of clock is 4us */
2133         udelay(IXGBE_I2C_T_HIGH);
2134
2135         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2136         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2137
2138         ixgbe_lower_i2c_clk(hw, &i2cctl);
2139
2140         /* Minimum low period of clock is 4.7 us */
2141         udelay(IXGBE_I2C_T_LOW);
2142
2143         return 0;
2144 }
2145
2146 /**
2147  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2148  *  @hw: pointer to hardware structure
2149  *  @data: data value to write
2150  *
2151  *  Clocks out one bit via I2C data/clock
2152  **/
2153 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2154 {
2155         s32 status;
2156         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2157
2158         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2159         if (status == 0) {
2160                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2161
2162                 /* Minimum high period of clock is 4us */
2163                 udelay(IXGBE_I2C_T_HIGH);
2164
2165                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2166
2167                 /* Minimum low period of clock is 4.7 us.
2168                  * This also takes care of the data hold time.
2169                  */
2170                 udelay(IXGBE_I2C_T_LOW);
2171         } else {
2172                 hw_dbg(hw, "I2C data was not set to %X\n", data);
2173                 return IXGBE_ERR_I2C;
2174         }
2175
2176         return 0;
2177 }
2178 /**
2179  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2180  *  @hw: pointer to hardware structure
2181  *  @i2cctl: Current value of I2CCTL register
2182  *
2183  *  Raises the I2C clock line '0'->'1'
2184  *  Negates the I2C clock output enable on X550 hardware.
2185  **/
2186 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2187 {
2188         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2189         u32 i = 0;
2190         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2191         u32 i2cctl_r = 0;
2192
2193         if (clk_oe_bit) {
2194                 *i2cctl |= clk_oe_bit;
2195                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2196         }
2197
2198         for (i = 0; i < timeout; i++) {
2199                 *i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2200                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2201                 IXGBE_WRITE_FLUSH(hw);
2202                 /* SCL rise time (1000ns) */
2203                 udelay(IXGBE_I2C_T_RISE);
2204
2205                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2206                 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2207                         break;
2208         }
2209 }
2210
2211 /**
2212  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2213  *  @hw: pointer to hardware structure
2214  *  @i2cctl: Current value of I2CCTL register
2215  *
2216  *  Lowers the I2C clock line '1'->'0'
2217  *  Asserts the I2C clock output enable on X550 hardware.
2218  **/
2219 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2220 {
2221
2222         *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2223         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2224
2225         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2226         IXGBE_WRITE_FLUSH(hw);
2227
2228         /* SCL fall time (300ns) */
2229         udelay(IXGBE_I2C_T_FALL);
2230 }
2231
2232 /**
2233  *  ixgbe_set_i2c_data - Sets the I2C data bit
2234  *  @hw: pointer to hardware structure
2235  *  @i2cctl: Current value of I2CCTL register
2236  *  @data: I2C data value (0 or 1) to set
2237  *
2238  *  Sets the I2C data bit
2239  *  Asserts the I2C data output enable on X550 hardware.
2240  **/
2241 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2242 {
2243         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2244
2245         if (data)
2246                 *i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2247         else
2248                 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2249         *i2cctl &= ~data_oe_bit;
2250
2251         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2252         IXGBE_WRITE_FLUSH(hw);
2253
2254         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2255         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2256
2257         if (!data)      /* Can't verify data in this case */
2258                 return 0;
2259         if (data_oe_bit) {
2260                 *i2cctl |= data_oe_bit;
2261                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2262                 IXGBE_WRITE_FLUSH(hw);
2263         }
2264
2265         /* Verify data was set correctly */
2266         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2267         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2268                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2269                 return IXGBE_ERR_I2C;
2270         }
2271
2272         return 0;
2273 }
2274
2275 /**
2276  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2277  *  @hw: pointer to hardware structure
2278  *  @i2cctl: Current value of I2CCTL register
2279  *
2280  *  Returns the I2C data bit value
2281  *  Negates the I2C data output enable on X550 hardware.
2282  **/
2283 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2284 {
2285         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2286
2287         if (data_oe_bit) {
2288                 *i2cctl |= data_oe_bit;
2289                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2290                 IXGBE_WRITE_FLUSH(hw);
2291                 udelay(IXGBE_I2C_T_FALL);
2292         }
2293
2294         if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2295                 return true;
2296         return false;
2297 }
2298
2299 /**
2300  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2301  *  @hw: pointer to hardware structure
2302  *
2303  *  Clears the I2C bus by sending nine clock pulses.
2304  *  Used when data line is stuck low.
2305  **/
2306 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2307 {
2308         u32 i2cctl;
2309         u32 i;
2310
2311         ixgbe_i2c_start(hw);
2312         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2313
2314         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2315
2316         for (i = 0; i < 9; i++) {
2317                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2318
2319                 /* Min high period of clock is 4us */
2320                 udelay(IXGBE_I2C_T_HIGH);
2321
2322                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2323
2324                 /* Min low period of clock is 4.7us*/
2325                 udelay(IXGBE_I2C_T_LOW);
2326         }
2327
2328         ixgbe_i2c_start(hw);
2329
2330         /* Put the i2c bus back to default state */
2331         ixgbe_i2c_stop(hw);
2332 }
2333
2334 /**
2335  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2336  *  @hw: pointer to hardware structure
2337  *
2338  *  Checks if the LASI temp alarm status was triggered due to overtemp
2339  **/
2340 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2341 {
2342         u16 phy_data = 0;
2343
2344         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2345                 return 0;
2346
2347         /* Check that the LASI temp alarm status was triggered */
2348         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2349                              MDIO_MMD_PMAPMD, &phy_data);
2350
2351         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2352                 return 0;
2353
2354         return IXGBE_ERR_OVERTEMP;
2355 }
2356
2357 /** ixgbe_set_copper_phy_power - Control power for copper phy
2358  *  @hw: pointer to hardware structure
2359  *  @on: true for on, false for off
2360  **/
2361 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2362 {
2363         u32 status;
2364         u16 reg;
2365
2366         /* Bail if we don't have copper phy */
2367         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2368                 return 0;
2369
2370         if (!on && ixgbe_mng_present(hw))
2371                 return 0;
2372
2373         status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, &reg);
2374         if (status)
2375                 return status;
2376
2377         if (on) {
2378                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2379         } else {
2380                 if (ixgbe_check_reset_blocked(hw))
2381                         return 0;
2382                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2383         }
2384
2385         status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
2386         return status;
2387 }