2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/dma-mapping.h>
46 #include <linux/tcp.h>
47 #include <linux/udp.h>
48 #include <linux/etherdevice.h>
49 #include <linux/delay.h>
50 #include <linux/ethtool.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/kernel.h>
54 #include <linux/spinlock.h>
55 #include <linux/workqueue.h>
56 #include <linux/phy.h>
57 #include <linux/mv643xx_eth.h>
59 #include <linux/interrupt.h>
60 #include <linux/types.h>
61 #include <linux/slab.h>
62 #include <linux/clk.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_net.h>
66 #include <linux/of_mdio.h>
68 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
69 static char mv643xx_eth_driver_version[] = "1.4";
73 * Registers shared between all ports.
75 #define PHY_ADDR 0x0000
76 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79 #define WINDOW_BAR_ENABLE 0x0290
80 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
86 #define PORT_CONFIG 0x0000
87 #define UNICAST_PROMISCUOUS_MODE 0x00000001
88 #define PORT_CONFIG_EXT 0x0004
89 #define MAC_ADDR_LOW 0x0014
90 #define MAC_ADDR_HIGH 0x0018
91 #define SDMA_CONFIG 0x001c
92 #define TX_BURST_SIZE_16_64BIT 0x01000000
93 #define TX_BURST_SIZE_4_64BIT 0x00800000
94 #define BLM_TX_NO_SWAP 0x00000020
95 #define BLM_RX_NO_SWAP 0x00000010
96 #define RX_BURST_SIZE_16_64BIT 0x00000008
97 #define RX_BURST_SIZE_4_64BIT 0x00000004
98 #define PORT_SERIAL_CONTROL 0x003c
99 #define SET_MII_SPEED_TO_100 0x01000000
100 #define SET_GMII_SPEED_TO_1000 0x00800000
101 #define SET_FULL_DUPLEX_MODE 0x00200000
102 #define MAX_RX_PACKET_9700BYTE 0x000a0000
103 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
105 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108 #define FORCE_LINK_PASS 0x00000002
109 #define SERIAL_PORT_ENABLE 0x00000001
110 #define PORT_STATUS 0x0044
111 #define TX_FIFO_EMPTY 0x00000400
112 #define TX_IN_PROGRESS 0x00000080
113 #define PORT_SPEED_MASK 0x00000030
114 #define PORT_SPEED_1000 0x00000010
115 #define PORT_SPEED_100 0x00000020
116 #define PORT_SPEED_10 0x00000000
117 #define FLOW_CONTROL_ENABLED 0x00000008
118 #define FULL_DUPLEX 0x00000004
119 #define LINK_UP 0x00000002
120 #define TXQ_COMMAND 0x0048
121 #define TXQ_FIX_PRIO_CONF 0x004c
122 #define PORT_SERIAL_CONTROL1 0x004c
123 #define CLK125_BYPASS_EN 0x00000010
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define RX_DISCARD_FRAME_CNT 0x0084
140 #define RX_OVERRUN_FRAME_CNT 0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142 #define TX_BW_RATE_MOVED 0x00e0
143 #define TX_BW_MTU_MOVED 0x00e8
144 #define TX_BW_BURST_MOVED 0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146 #define RXQ_COMMAND 0x0280
147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
153 * Misc per-port registers.
155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
162 * SDMA configuration register default value.
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
170 (RX_BURST_SIZE_4_64BIT | \
173 TX_BURST_SIZE_4_64BIT)
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
182 #define DEFAULT_RX_QUEUE_SIZE 128
183 #define DEFAULT_TX_QUEUE_SIZE 256
184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
190 #if defined(__BIG_ENDIAN)
192 u16 byte_cnt; /* Descriptor buffer byte count */
193 u16 buf_size; /* Buffer size */
194 u32 cmd_sts; /* Descriptor command status */
195 u32 next_desc_ptr; /* Next descriptor pointer */
196 u32 buf_ptr; /* Descriptor buffer pointer */
200 u16 byte_cnt; /* buffer byte count */
201 u16 l4i_chk; /* CPU provided TCP checksum */
202 u32 cmd_sts; /* Command/status field */
203 u32 next_desc_ptr; /* Pointer to next descriptor */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
206 #elif defined(__LITTLE_ENDIAN)
208 u32 cmd_sts; /* Descriptor command status */
209 u16 buf_size; /* Buffer size */
210 u16 byte_cnt; /* Descriptor buffer byte count */
211 u32 buf_ptr; /* Descriptor buffer pointer */
212 u32 next_desc_ptr; /* Next descriptor pointer */
216 u32 cmd_sts; /* Command/status field */
217 u16 l4i_chk; /* CPU provided TCP checksum */
218 u16 byte_cnt; /* buffer byte count */
219 u32 buf_ptr; /* pointer to buffer for this descriptor*/
220 u32 next_desc_ptr; /* Pointer to next descriptor */
223 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
226 /* RX & TX descriptor command */
227 #define BUFFER_OWNED_BY_DMA 0x80000000
229 /* RX & TX descriptor status */
230 #define ERROR_SUMMARY 0x00000001
232 /* RX descriptor status */
233 #define LAYER_4_CHECKSUM_OK 0x40000000
234 #define RX_ENABLE_INTERRUPT 0x20000000
235 #define RX_FIRST_DESC 0x08000000
236 #define RX_LAST_DESC 0x04000000
237 #define RX_IP_HDR_OK 0x02000000
238 #define RX_PKT_IS_IPV4 0x01000000
239 #define RX_PKT_IS_ETHERNETV2 0x00800000
240 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
241 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
242 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
244 /* TX descriptor command */
245 #define TX_ENABLE_INTERRUPT 0x00800000
246 #define GEN_CRC 0x00400000
247 #define TX_FIRST_DESC 0x00200000
248 #define TX_LAST_DESC 0x00100000
249 #define ZERO_PADDING 0x00080000
250 #define GEN_IP_V4_CHECKSUM 0x00040000
251 #define GEN_TCP_UDP_CHECKSUM 0x00020000
252 #define UDP_FRAME 0x00010000
253 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
254 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
256 #define TX_IHL_SHIFT 11
259 /* global *******************************************************************/
260 struct mv643xx_eth_shared_private {
262 * Ethernet controller base address.
267 * Per-port MBUS window access register value.
272 * Hardware-specific parameters.
274 int extended_rx_coal_limit;
280 #define TX_BW_CONTROL_ABSENT 0
281 #define TX_BW_CONTROL_OLD_LAYOUT 1
282 #define TX_BW_CONTROL_NEW_LAYOUT 2
284 static int mv643xx_eth_open(struct net_device *dev);
285 static int mv643xx_eth_stop(struct net_device *dev);
288 /* per-port *****************************************************************/
289 struct mib_counters {
290 u64 good_octets_received;
291 u32 bad_octets_received;
292 u32 internal_mac_transmit_err;
293 u32 good_frames_received;
294 u32 bad_frames_received;
295 u32 broadcast_frames_received;
296 u32 multicast_frames_received;
297 u32 frames_64_octets;
298 u32 frames_65_to_127_octets;
299 u32 frames_128_to_255_octets;
300 u32 frames_256_to_511_octets;
301 u32 frames_512_to_1023_octets;
302 u32 frames_1024_to_max_octets;
303 u64 good_octets_sent;
304 u32 good_frames_sent;
305 u32 excessive_collision;
306 u32 multicast_frames_sent;
307 u32 broadcast_frames_sent;
308 u32 unrec_mac_control_received;
310 u32 good_fc_received;
312 u32 undersize_received;
313 u32 fragments_received;
314 u32 oversize_received;
316 u32 mac_receive_error;
320 /* Non MIB hardware counters */
334 struct rx_desc *rx_desc_area;
335 dma_addr_t rx_desc_dma;
336 int rx_desc_area_size;
337 struct sk_buff **rx_skb;
349 struct tx_desc *tx_desc_area;
350 dma_addr_t tx_desc_dma;
351 int tx_desc_area_size;
353 struct sk_buff_head tx_skb;
355 unsigned long tx_packets;
356 unsigned long tx_bytes;
357 unsigned long tx_dropped;
360 struct mv643xx_eth_private {
361 struct mv643xx_eth_shared_private *shared;
365 struct net_device *dev;
367 struct phy_device *phy;
369 struct timer_list mib_counters_timer;
370 spinlock_t mib_counters_lock;
371 struct mib_counters mib_counters;
373 struct work_struct tx_timeout_task;
375 struct napi_struct napi;
390 unsigned long rx_desc_sram_addr;
391 int rx_desc_sram_size;
393 struct timer_list rx_oom;
394 struct rx_queue rxq[8];
400 unsigned long tx_desc_sram_addr;
401 int tx_desc_sram_size;
403 struct tx_queue txq[8];
406 * Hardware-specific parameters.
413 /* port register accessors **************************************************/
414 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
416 return readl(mp->shared->base + offset);
419 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
421 return readl(mp->base + offset);
424 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
426 writel(data, mp->shared->base + offset);
429 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
431 writel(data, mp->base + offset);
435 /* rxq/txq helper functions *************************************************/
436 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
438 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
441 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
443 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
446 static void rxq_enable(struct rx_queue *rxq)
448 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
449 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
452 static void rxq_disable(struct rx_queue *rxq)
454 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
455 u8 mask = 1 << rxq->index;
457 wrlp(mp, RXQ_COMMAND, mask << 8);
458 while (rdlp(mp, RXQ_COMMAND) & mask)
462 static void txq_reset_hw_ptr(struct tx_queue *txq)
464 struct mv643xx_eth_private *mp = txq_to_mp(txq);
467 addr = (u32)txq->tx_desc_dma;
468 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
469 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
472 static void txq_enable(struct tx_queue *txq)
474 struct mv643xx_eth_private *mp = txq_to_mp(txq);
475 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
478 static void txq_disable(struct tx_queue *txq)
480 struct mv643xx_eth_private *mp = txq_to_mp(txq);
481 u8 mask = 1 << txq->index;
483 wrlp(mp, TXQ_COMMAND, mask << 8);
484 while (rdlp(mp, TXQ_COMMAND) & mask)
488 static void txq_maybe_wake(struct tx_queue *txq)
490 struct mv643xx_eth_private *mp = txq_to_mp(txq);
491 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
493 if (netif_tx_queue_stopped(nq)) {
494 __netif_tx_lock(nq, smp_processor_id());
495 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
496 netif_tx_wake_queue(nq);
497 __netif_tx_unlock(nq);
501 static int rxq_process(struct rx_queue *rxq, int budget)
503 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
504 struct net_device_stats *stats = &mp->dev->stats;
508 while (rx < budget && rxq->rx_desc_count) {
509 struct rx_desc *rx_desc;
510 unsigned int cmd_sts;
514 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
516 cmd_sts = rx_desc->cmd_sts;
517 if (cmd_sts & BUFFER_OWNED_BY_DMA)
521 skb = rxq->rx_skb[rxq->rx_curr_desc];
522 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
525 if (rxq->rx_curr_desc == rxq->rx_ring_size)
526 rxq->rx_curr_desc = 0;
528 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
529 rx_desc->buf_size, DMA_FROM_DEVICE);
530 rxq->rx_desc_count--;
533 mp->work_rx_refill |= 1 << rxq->index;
535 byte_cnt = rx_desc->byte_cnt;
540 * Note that the descriptor byte count includes 2 dummy
541 * bytes automatically inserted by the hardware at the
542 * start of the packet (which we don't count), and a 4
543 * byte CRC at the end of the packet (which we do count).
546 stats->rx_bytes += byte_cnt - 2;
549 * In case we received a packet without first / last bits
550 * on, or the error summary bit is set, the packet needs
553 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
554 != (RX_FIRST_DESC | RX_LAST_DESC))
558 * The -4 is for the CRC in the trailer of the
561 skb_put(skb, byte_cnt - 2 - 4);
563 if (cmd_sts & LAYER_4_CHECKSUM_OK)
564 skb->ip_summed = CHECKSUM_UNNECESSARY;
565 skb->protocol = eth_type_trans(skb, mp->dev);
567 napi_gro_receive(&mp->napi, skb);
574 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
575 (RX_FIRST_DESC | RX_LAST_DESC)) {
578 "received packet spanning multiple descriptors\n");
581 if (cmd_sts & ERROR_SUMMARY)
588 mp->work_rx &= ~(1 << rxq->index);
593 static int rxq_refill(struct rx_queue *rxq, int budget)
595 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
599 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
602 struct rx_desc *rx_desc;
605 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
613 skb_reserve(skb, SKB_DMA_REALIGN);
616 rxq->rx_desc_count++;
618 rx = rxq->rx_used_desc++;
619 if (rxq->rx_used_desc == rxq->rx_ring_size)
620 rxq->rx_used_desc = 0;
622 rx_desc = rxq->rx_desc_area + rx;
624 size = skb_end_pointer(skb) - skb->data;
625 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
628 rx_desc->buf_size = size;
629 rxq->rx_skb[rx] = skb;
631 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
635 * The hardware automatically prepends 2 bytes of
636 * dummy data to each received packet, so that the
637 * IP header ends up 16-byte aligned.
642 if (refilled < budget)
643 mp->work_rx_refill &= ~(1 << rxq->index);
650 /* tx ***********************************************************************/
651 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
655 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
656 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
658 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
665 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
667 struct mv643xx_eth_private *mp = txq_to_mp(txq);
668 int nr_frags = skb_shinfo(skb)->nr_frags;
671 for (frag = 0; frag < nr_frags; frag++) {
672 skb_frag_t *this_frag;
674 struct tx_desc *desc;
676 this_frag = &skb_shinfo(skb)->frags[frag];
677 tx_index = txq->tx_curr_desc++;
678 if (txq->tx_curr_desc == txq->tx_ring_size)
679 txq->tx_curr_desc = 0;
680 desc = &txq->tx_desc_area[tx_index];
683 * The last fragment will generate an interrupt
684 * which will free the skb on TX completion.
686 if (frag == nr_frags - 1) {
687 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
688 ZERO_PADDING | TX_LAST_DESC |
691 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
695 desc->byte_cnt = skb_frag_size(this_frag);
696 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
698 skb_frag_size(this_frag),
703 static inline __be16 sum16_as_be(__sum16 sum)
705 return (__force __be16)sum;
708 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
710 struct mv643xx_eth_private *mp = txq_to_mp(txq);
711 int nr_frags = skb_shinfo(skb)->nr_frags;
713 struct tx_desc *desc;
718 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
721 if (skb->ip_summed == CHECKSUM_PARTIAL) {
725 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
726 skb->protocol != htons(ETH_P_8021Q));
728 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
729 tag_bytes = hdr_len - ETH_HLEN;
730 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
731 unlikely(tag_bytes & ~12)) {
732 if (skb_checksum_help(skb) == 0)
739 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
741 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
743 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
745 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
747 switch (ip_hdr(skb)->protocol) {
749 cmd_sts |= UDP_FRAME;
750 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
753 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
760 /* Errata BTS #50, IHL must be 5 if no HW checksum */
761 cmd_sts |= 5 << TX_IHL_SHIFT;
764 tx_index = txq->tx_curr_desc++;
765 if (txq->tx_curr_desc == txq->tx_ring_size)
766 txq->tx_curr_desc = 0;
767 desc = &txq->tx_desc_area[tx_index];
770 txq_submit_frag_skb(txq, skb);
771 length = skb_headlen(skb);
773 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
777 desc->l4i_chk = l4i_chk;
778 desc->byte_cnt = length;
779 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
780 length, DMA_TO_DEVICE);
782 __skb_queue_tail(&txq->tx_skb, skb);
784 skb_tx_timestamp(skb);
786 /* ensure all other descriptors are written before first cmd_sts */
788 desc->cmd_sts = cmd_sts;
790 /* clear TX_END status */
791 mp->work_tx_end &= ~(1 << txq->index);
793 /* ensure all descriptors are written before poking hardware */
797 txq->tx_desc_count += nr_frags + 1;
802 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
804 struct mv643xx_eth_private *mp = netdev_priv(dev);
806 struct tx_queue *txq;
807 struct netdev_queue *nq;
809 queue = skb_get_queue_mapping(skb);
810 txq = mp->txq + queue;
811 nq = netdev_get_tx_queue(dev, queue);
813 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
815 netdev_printk(KERN_DEBUG, dev,
816 "failed to linearize skb with tiny unaligned fragment\n");
817 return NETDEV_TX_BUSY;
820 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
822 netdev_err(dev, "tx queue full?!\n");
829 if (!txq_submit_skb(txq, skb)) {
832 txq->tx_bytes += length;
835 entries_left = txq->tx_ring_size - txq->tx_desc_count;
836 if (entries_left < MAX_SKB_FRAGS + 1)
837 netif_tx_stop_queue(nq);
844 /* tx napi ******************************************************************/
845 static void txq_kick(struct tx_queue *txq)
847 struct mv643xx_eth_private *mp = txq_to_mp(txq);
848 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
852 __netif_tx_lock(nq, smp_processor_id());
854 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
857 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
858 expected_ptr = (u32)txq->tx_desc_dma +
859 txq->tx_curr_desc * sizeof(struct tx_desc);
861 if (hw_desc_ptr != expected_ptr)
865 __netif_tx_unlock(nq);
867 mp->work_tx_end &= ~(1 << txq->index);
870 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
872 struct mv643xx_eth_private *mp = txq_to_mp(txq);
873 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
876 __netif_tx_lock_bh(nq);
879 while (reclaimed < budget && txq->tx_desc_count > 0) {
881 struct tx_desc *desc;
885 tx_index = txq->tx_used_desc;
886 desc = &txq->tx_desc_area[tx_index];
887 cmd_sts = desc->cmd_sts;
889 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
892 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
895 txq->tx_used_desc = tx_index + 1;
896 if (txq->tx_used_desc == txq->tx_ring_size)
897 txq->tx_used_desc = 0;
900 txq->tx_desc_count--;
903 if (cmd_sts & TX_LAST_DESC)
904 skb = __skb_dequeue(&txq->tx_skb);
906 if (cmd_sts & ERROR_SUMMARY) {
907 netdev_info(mp->dev, "tx error\n");
908 mp->dev->stats.tx_errors++;
911 if (cmd_sts & TX_FIRST_DESC) {
912 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
913 desc->byte_cnt, DMA_TO_DEVICE);
915 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
916 desc->byte_cnt, DMA_TO_DEVICE);
922 __netif_tx_unlock_bh(nq);
924 if (reclaimed < budget)
925 mp->work_tx &= ~(1 << txq->index);
931 /* tx rate control **********************************************************/
933 * Set total maximum TX rate (shared by all TX queues for this port)
934 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
936 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
942 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
943 if (token_rate > 1023)
946 mtu = (mp->dev->mtu + 255) >> 8;
950 bucket_size = (burst + 255) >> 8;
951 if (bucket_size > 65535)
954 switch (mp->shared->tx_bw_control) {
955 case TX_BW_CONTROL_OLD_LAYOUT:
956 wrlp(mp, TX_BW_RATE, token_rate);
957 wrlp(mp, TX_BW_MTU, mtu);
958 wrlp(mp, TX_BW_BURST, bucket_size);
960 case TX_BW_CONTROL_NEW_LAYOUT:
961 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
962 wrlp(mp, TX_BW_MTU_MOVED, mtu);
963 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
968 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
970 struct mv643xx_eth_private *mp = txq_to_mp(txq);
974 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
975 if (token_rate > 1023)
978 bucket_size = (burst + 255) >> 8;
979 if (bucket_size > 65535)
982 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
983 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
986 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
988 struct mv643xx_eth_private *mp = txq_to_mp(txq);
993 * Turn on fixed priority mode.
996 switch (mp->shared->tx_bw_control) {
997 case TX_BW_CONTROL_OLD_LAYOUT:
998 off = TXQ_FIX_PRIO_CONF;
1000 case TX_BW_CONTROL_NEW_LAYOUT:
1001 off = TXQ_FIX_PRIO_CONF_MOVED;
1006 val = rdlp(mp, off);
1007 val |= 1 << txq->index;
1013 /* mii management interface *************************************************/
1014 static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp)
1016 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1017 u32 autoneg_disable = FORCE_LINK_PASS |
1018 DISABLE_AUTO_NEG_SPEED_GMII |
1019 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1020 DISABLE_AUTO_NEG_FOR_DUPLEX;
1022 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1023 /* enable auto negotiation */
1024 pscr &= ~autoneg_disable;
1028 pscr |= autoneg_disable;
1030 if (mp->phy->speed == SPEED_1000) {
1031 /* force gigabit, half duplex not supported */
1032 pscr |= SET_GMII_SPEED_TO_1000;
1033 pscr |= SET_FULL_DUPLEX_MODE;
1037 pscr &= ~SET_GMII_SPEED_TO_1000;
1039 if (mp->phy->speed == SPEED_100)
1040 pscr |= SET_MII_SPEED_TO_100;
1042 pscr &= ~SET_MII_SPEED_TO_100;
1044 if (mp->phy->duplex == DUPLEX_FULL)
1045 pscr |= SET_FULL_DUPLEX_MODE;
1047 pscr &= ~SET_FULL_DUPLEX_MODE;
1050 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1053 /* statistics ***************************************************************/
1054 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1056 struct mv643xx_eth_private *mp = netdev_priv(dev);
1057 struct net_device_stats *stats = &dev->stats;
1058 unsigned long tx_packets = 0;
1059 unsigned long tx_bytes = 0;
1060 unsigned long tx_dropped = 0;
1063 for (i = 0; i < mp->txq_count; i++) {
1064 struct tx_queue *txq = mp->txq + i;
1066 tx_packets += txq->tx_packets;
1067 tx_bytes += txq->tx_bytes;
1068 tx_dropped += txq->tx_dropped;
1071 stats->tx_packets = tx_packets;
1072 stats->tx_bytes = tx_bytes;
1073 stats->tx_dropped = tx_dropped;
1078 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1080 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1083 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1087 for (i = 0; i < 0x80; i += 4)
1090 /* Clear non MIB hw counters also */
1091 rdlp(mp, RX_DISCARD_FRAME_CNT);
1092 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1095 static void mib_counters_update(struct mv643xx_eth_private *mp)
1097 struct mib_counters *p = &mp->mib_counters;
1099 spin_lock_bh(&mp->mib_counters_lock);
1100 p->good_octets_received += mib_read(mp, 0x00);
1101 p->bad_octets_received += mib_read(mp, 0x08);
1102 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1103 p->good_frames_received += mib_read(mp, 0x10);
1104 p->bad_frames_received += mib_read(mp, 0x14);
1105 p->broadcast_frames_received += mib_read(mp, 0x18);
1106 p->multicast_frames_received += mib_read(mp, 0x1c);
1107 p->frames_64_octets += mib_read(mp, 0x20);
1108 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1109 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1110 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1111 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1112 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1113 p->good_octets_sent += mib_read(mp, 0x38);
1114 p->good_frames_sent += mib_read(mp, 0x40);
1115 p->excessive_collision += mib_read(mp, 0x44);
1116 p->multicast_frames_sent += mib_read(mp, 0x48);
1117 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1118 p->unrec_mac_control_received += mib_read(mp, 0x50);
1119 p->fc_sent += mib_read(mp, 0x54);
1120 p->good_fc_received += mib_read(mp, 0x58);
1121 p->bad_fc_received += mib_read(mp, 0x5c);
1122 p->undersize_received += mib_read(mp, 0x60);
1123 p->fragments_received += mib_read(mp, 0x64);
1124 p->oversize_received += mib_read(mp, 0x68);
1125 p->jabber_received += mib_read(mp, 0x6c);
1126 p->mac_receive_error += mib_read(mp, 0x70);
1127 p->bad_crc_event += mib_read(mp, 0x74);
1128 p->collision += mib_read(mp, 0x78);
1129 p->late_collision += mib_read(mp, 0x7c);
1130 /* Non MIB hardware counters */
1131 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1132 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1133 spin_unlock_bh(&mp->mib_counters_lock);
1136 static void mib_counters_timer_wrapper(unsigned long _mp)
1138 struct mv643xx_eth_private *mp = (void *)_mp;
1139 mib_counters_update(mp);
1140 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1144 /* interrupt coalescing *****************************************************/
1146 * Hardware coalescing parameters are set in units of 64 t_clk
1149 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1151 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1153 * In the ->set*() methods, we round the computed register value
1154 * to the nearest integer.
1156 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1158 u32 val = rdlp(mp, SDMA_CONFIG);
1161 if (mp->shared->extended_rx_coal_limit)
1162 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1164 temp = (val & 0x003fff00) >> 8;
1167 do_div(temp, mp->t_clk);
1169 return (unsigned int)temp;
1172 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1177 temp = (u64)usec * mp->t_clk;
1179 do_div(temp, 64000000);
1181 val = rdlp(mp, SDMA_CONFIG);
1182 if (mp->shared->extended_rx_coal_limit) {
1186 val |= (temp & 0x8000) << 10;
1187 val |= (temp & 0x7fff) << 7;
1192 val |= (temp & 0x3fff) << 8;
1194 wrlp(mp, SDMA_CONFIG, val);
1197 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1201 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1203 do_div(temp, mp->t_clk);
1205 return (unsigned int)temp;
1208 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1212 temp = (u64)usec * mp->t_clk;
1214 do_div(temp, 64000000);
1219 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1223 /* ethtool ******************************************************************/
1224 struct mv643xx_eth_stats {
1225 char stat_string[ETH_GSTRING_LEN];
1232 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1233 offsetof(struct net_device, stats.m), -1 }
1235 #define MIBSTAT(m) \
1236 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1237 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1239 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1248 MIBSTAT(good_octets_received),
1249 MIBSTAT(bad_octets_received),
1250 MIBSTAT(internal_mac_transmit_err),
1251 MIBSTAT(good_frames_received),
1252 MIBSTAT(bad_frames_received),
1253 MIBSTAT(broadcast_frames_received),
1254 MIBSTAT(multicast_frames_received),
1255 MIBSTAT(frames_64_octets),
1256 MIBSTAT(frames_65_to_127_octets),
1257 MIBSTAT(frames_128_to_255_octets),
1258 MIBSTAT(frames_256_to_511_octets),
1259 MIBSTAT(frames_512_to_1023_octets),
1260 MIBSTAT(frames_1024_to_max_octets),
1261 MIBSTAT(good_octets_sent),
1262 MIBSTAT(good_frames_sent),
1263 MIBSTAT(excessive_collision),
1264 MIBSTAT(multicast_frames_sent),
1265 MIBSTAT(broadcast_frames_sent),
1266 MIBSTAT(unrec_mac_control_received),
1268 MIBSTAT(good_fc_received),
1269 MIBSTAT(bad_fc_received),
1270 MIBSTAT(undersize_received),
1271 MIBSTAT(fragments_received),
1272 MIBSTAT(oversize_received),
1273 MIBSTAT(jabber_received),
1274 MIBSTAT(mac_receive_error),
1275 MIBSTAT(bad_crc_event),
1277 MIBSTAT(late_collision),
1278 MIBSTAT(rx_discard),
1279 MIBSTAT(rx_overrun),
1283 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1284 struct ethtool_cmd *cmd)
1288 err = phy_read_status(mp->phy);
1290 err = phy_ethtool_gset(mp->phy, cmd);
1293 * The MAC does not support 1000baseT_Half.
1295 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1296 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1302 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1303 struct ethtool_cmd *cmd)
1307 port_status = rdlp(mp, PORT_STATUS);
1309 cmd->supported = SUPPORTED_MII;
1310 cmd->advertising = ADVERTISED_MII;
1311 switch (port_status & PORT_SPEED_MASK) {
1313 ethtool_cmd_speed_set(cmd, SPEED_10);
1315 case PORT_SPEED_100:
1316 ethtool_cmd_speed_set(cmd, SPEED_100);
1318 case PORT_SPEED_1000:
1319 ethtool_cmd_speed_set(cmd, SPEED_1000);
1325 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1326 cmd->port = PORT_MII;
1327 cmd->phy_address = 0;
1328 cmd->transceiver = XCVR_INTERNAL;
1329 cmd->autoneg = AUTONEG_DISABLE;
1337 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1339 struct mv643xx_eth_private *mp = netdev_priv(dev);
1343 phy_ethtool_get_wol(mp->phy, wol);
1347 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1349 struct mv643xx_eth_private *mp = netdev_priv(dev);
1352 if (mp->phy == NULL)
1355 err = phy_ethtool_set_wol(mp->phy, wol);
1356 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1357 * this debugging hint is useful to have.
1359 if (err == -EOPNOTSUPP)
1360 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1365 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1367 struct mv643xx_eth_private *mp = netdev_priv(dev);
1369 if (mp->phy != NULL)
1370 return mv643xx_eth_get_settings_phy(mp, cmd);
1372 return mv643xx_eth_get_settings_phyless(mp, cmd);
1376 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1378 struct mv643xx_eth_private *mp = netdev_priv(dev);
1381 if (mp->phy == NULL)
1385 * The MAC does not support 1000baseT_Half.
1387 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1389 ret = phy_ethtool_sset(mp->phy, cmd);
1391 mv643xx_adjust_pscr(mp);
1395 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1396 struct ethtool_drvinfo *drvinfo)
1398 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1399 sizeof(drvinfo->driver));
1400 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1401 sizeof(drvinfo->version));
1402 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1403 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1404 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1407 static int mv643xx_eth_nway_reset(struct net_device *dev)
1409 struct mv643xx_eth_private *mp = netdev_priv(dev);
1411 if (mp->phy == NULL)
1414 return genphy_restart_aneg(mp->phy);
1418 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1420 struct mv643xx_eth_private *mp = netdev_priv(dev);
1422 ec->rx_coalesce_usecs = get_rx_coal(mp);
1423 ec->tx_coalesce_usecs = get_tx_coal(mp);
1429 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1431 struct mv643xx_eth_private *mp = netdev_priv(dev);
1433 set_rx_coal(mp, ec->rx_coalesce_usecs);
1434 set_tx_coal(mp, ec->tx_coalesce_usecs);
1440 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1442 struct mv643xx_eth_private *mp = netdev_priv(dev);
1444 er->rx_max_pending = 4096;
1445 er->tx_max_pending = 4096;
1447 er->rx_pending = mp->rx_ring_size;
1448 er->tx_pending = mp->tx_ring_size;
1452 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1454 struct mv643xx_eth_private *mp = netdev_priv(dev);
1456 if (er->rx_mini_pending || er->rx_jumbo_pending)
1459 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1460 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1462 if (netif_running(dev)) {
1463 mv643xx_eth_stop(dev);
1464 if (mv643xx_eth_open(dev)) {
1466 "fatal error on re-opening device after ring param change\n");
1476 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1478 struct mv643xx_eth_private *mp = netdev_priv(dev);
1479 bool rx_csum = features & NETIF_F_RXCSUM;
1481 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1486 static void mv643xx_eth_get_strings(struct net_device *dev,
1487 uint32_t stringset, uint8_t *data)
1491 if (stringset == ETH_SS_STATS) {
1492 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1493 memcpy(data + i * ETH_GSTRING_LEN,
1494 mv643xx_eth_stats[i].stat_string,
1500 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1501 struct ethtool_stats *stats,
1504 struct mv643xx_eth_private *mp = netdev_priv(dev);
1507 mv643xx_eth_get_stats(dev);
1508 mib_counters_update(mp);
1510 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1511 const struct mv643xx_eth_stats *stat;
1514 stat = mv643xx_eth_stats + i;
1516 if (stat->netdev_off >= 0)
1517 p = ((void *)mp->dev) + stat->netdev_off;
1519 p = ((void *)mp) + stat->mp_off;
1521 data[i] = (stat->sizeof_stat == 8) ?
1522 *(uint64_t *)p : *(uint32_t *)p;
1526 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1528 if (sset == ETH_SS_STATS)
1529 return ARRAY_SIZE(mv643xx_eth_stats);
1534 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1535 .get_settings = mv643xx_eth_get_settings,
1536 .set_settings = mv643xx_eth_set_settings,
1537 .get_drvinfo = mv643xx_eth_get_drvinfo,
1538 .nway_reset = mv643xx_eth_nway_reset,
1539 .get_link = ethtool_op_get_link,
1540 .get_coalesce = mv643xx_eth_get_coalesce,
1541 .set_coalesce = mv643xx_eth_set_coalesce,
1542 .get_ringparam = mv643xx_eth_get_ringparam,
1543 .set_ringparam = mv643xx_eth_set_ringparam,
1544 .get_strings = mv643xx_eth_get_strings,
1545 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1546 .get_sset_count = mv643xx_eth_get_sset_count,
1547 .get_ts_info = ethtool_op_get_ts_info,
1548 .get_wol = mv643xx_eth_get_wol,
1549 .set_wol = mv643xx_eth_set_wol,
1553 /* address handling *********************************************************/
1554 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1556 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1557 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1559 addr[0] = (mac_h >> 24) & 0xff;
1560 addr[1] = (mac_h >> 16) & 0xff;
1561 addr[2] = (mac_h >> 8) & 0xff;
1562 addr[3] = mac_h & 0xff;
1563 addr[4] = (mac_l >> 8) & 0xff;
1564 addr[5] = mac_l & 0xff;
1567 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1569 wrlp(mp, MAC_ADDR_HIGH,
1570 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1571 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1574 static u32 uc_addr_filter_mask(struct net_device *dev)
1576 struct netdev_hw_addr *ha;
1579 if (dev->flags & IFF_PROMISC)
1582 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1583 netdev_for_each_uc_addr(ha, dev) {
1584 if (memcmp(dev->dev_addr, ha->addr, 5))
1586 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1589 nibbles |= 1 << (ha->addr[5] & 0x0f);
1595 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1597 struct mv643xx_eth_private *mp = netdev_priv(dev);
1602 uc_addr_set(mp, dev->dev_addr);
1604 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1606 nibbles = uc_addr_filter_mask(dev);
1608 port_config |= UNICAST_PROMISCUOUS_MODE;
1612 for (i = 0; i < 16; i += 4) {
1613 int off = UNICAST_TABLE(mp->port_num) + i;
1630 wrlp(mp, PORT_CONFIG, port_config);
1633 static int addr_crc(unsigned char *addr)
1638 for (i = 0; i < 6; i++) {
1641 crc = (crc ^ addr[i]) << 8;
1642 for (j = 7; j >= 0; j--) {
1643 if (crc & (0x100 << j))
1651 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1653 struct mv643xx_eth_private *mp = netdev_priv(dev);
1656 struct netdev_hw_addr *ha;
1659 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1664 port_num = mp->port_num;
1665 accept = 0x01010101;
1666 for (i = 0; i < 0x100; i += 4) {
1667 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1668 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1673 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1674 if (mc_spec == NULL)
1676 mc_other = mc_spec + (0x100 >> 2);
1678 memset(mc_spec, 0, 0x100);
1679 memset(mc_other, 0, 0x100);
1681 netdev_for_each_mc_addr(ha, dev) {
1686 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1691 entry = addr_crc(a);
1694 table[entry >> 2] |= 1 << (8 * (entry & 3));
1697 for (i = 0; i < 0x100; i += 4) {
1698 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1699 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1705 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1707 mv643xx_eth_program_unicast_filter(dev);
1708 mv643xx_eth_program_multicast_filter(dev);
1711 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1713 struct sockaddr *sa = addr;
1715 if (!is_valid_ether_addr(sa->sa_data))
1716 return -EADDRNOTAVAIL;
1718 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1720 netif_addr_lock_bh(dev);
1721 mv643xx_eth_program_unicast_filter(dev);
1722 netif_addr_unlock_bh(dev);
1728 /* rx/tx queue initialisation ***********************************************/
1729 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1731 struct rx_queue *rxq = mp->rxq + index;
1732 struct rx_desc *rx_desc;
1738 rxq->rx_ring_size = mp->rx_ring_size;
1740 rxq->rx_desc_count = 0;
1741 rxq->rx_curr_desc = 0;
1742 rxq->rx_used_desc = 0;
1744 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1746 if (index == 0 && size <= mp->rx_desc_sram_size) {
1747 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1748 mp->rx_desc_sram_size);
1749 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1751 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1752 size, &rxq->rx_desc_dma,
1756 if (rxq->rx_desc_area == NULL) {
1758 "can't allocate rx ring (%d bytes)\n", size);
1761 memset(rxq->rx_desc_area, 0, size);
1763 rxq->rx_desc_area_size = size;
1764 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1766 if (rxq->rx_skb == NULL)
1769 rx_desc = rxq->rx_desc_area;
1770 for (i = 0; i < rxq->rx_ring_size; i++) {
1774 if (nexti == rxq->rx_ring_size)
1777 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1778 nexti * sizeof(struct rx_desc);
1785 if (index == 0 && size <= mp->rx_desc_sram_size)
1786 iounmap(rxq->rx_desc_area);
1788 dma_free_coherent(mp->dev->dev.parent, size,
1796 static void rxq_deinit(struct rx_queue *rxq)
1798 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1803 for (i = 0; i < rxq->rx_ring_size; i++) {
1804 if (rxq->rx_skb[i]) {
1805 dev_kfree_skb(rxq->rx_skb[i]);
1806 rxq->rx_desc_count--;
1810 if (rxq->rx_desc_count) {
1811 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1812 rxq->rx_desc_count);
1815 if (rxq->index == 0 &&
1816 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1817 iounmap(rxq->rx_desc_area);
1819 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1820 rxq->rx_desc_area, rxq->rx_desc_dma);
1825 static int txq_init(struct mv643xx_eth_private *mp, int index)
1827 struct tx_queue *txq = mp->txq + index;
1828 struct tx_desc *tx_desc;
1834 txq->tx_ring_size = mp->tx_ring_size;
1836 txq->tx_desc_count = 0;
1837 txq->tx_curr_desc = 0;
1838 txq->tx_used_desc = 0;
1840 size = txq->tx_ring_size * sizeof(struct tx_desc);
1842 if (index == 0 && size <= mp->tx_desc_sram_size) {
1843 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1844 mp->tx_desc_sram_size);
1845 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1847 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1848 size, &txq->tx_desc_dma,
1852 if (txq->tx_desc_area == NULL) {
1854 "can't allocate tx ring (%d bytes)\n", size);
1857 memset(txq->tx_desc_area, 0, size);
1859 txq->tx_desc_area_size = size;
1861 tx_desc = txq->tx_desc_area;
1862 for (i = 0; i < txq->tx_ring_size; i++) {
1863 struct tx_desc *txd = tx_desc + i;
1867 if (nexti == txq->tx_ring_size)
1871 txd->next_desc_ptr = txq->tx_desc_dma +
1872 nexti * sizeof(struct tx_desc);
1875 skb_queue_head_init(&txq->tx_skb);
1880 static void txq_deinit(struct tx_queue *txq)
1882 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1885 txq_reclaim(txq, txq->tx_ring_size, 1);
1887 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1889 if (txq->index == 0 &&
1890 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1891 iounmap(txq->tx_desc_area);
1893 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
1894 txq->tx_desc_area, txq->tx_desc_dma);
1898 /* netdev ops and related ***************************************************/
1899 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1904 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1909 if (int_cause & INT_EXT) {
1910 int_cause &= ~INT_EXT;
1911 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1915 wrlp(mp, INT_CAUSE, ~int_cause);
1916 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1917 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1918 mp->work_rx |= (int_cause & INT_RX) >> 2;
1921 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1922 if (int_cause_ext) {
1923 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1924 if (int_cause_ext & INT_EXT_LINK_PHY)
1926 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1932 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1934 struct net_device *dev = (struct net_device *)dev_id;
1935 struct mv643xx_eth_private *mp = netdev_priv(dev);
1937 if (unlikely(!mv643xx_eth_collect_events(mp)))
1940 wrlp(mp, INT_MASK, 0);
1941 napi_schedule(&mp->napi);
1946 static void handle_link_event(struct mv643xx_eth_private *mp)
1948 struct net_device *dev = mp->dev;
1954 port_status = rdlp(mp, PORT_STATUS);
1955 if (!(port_status & LINK_UP)) {
1956 if (netif_carrier_ok(dev)) {
1959 netdev_info(dev, "link down\n");
1961 netif_carrier_off(dev);
1963 for (i = 0; i < mp->txq_count; i++) {
1964 struct tx_queue *txq = mp->txq + i;
1966 txq_reclaim(txq, txq->tx_ring_size, 1);
1967 txq_reset_hw_ptr(txq);
1973 switch (port_status & PORT_SPEED_MASK) {
1977 case PORT_SPEED_100:
1980 case PORT_SPEED_1000:
1987 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1988 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1990 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
1991 speed, duplex ? "full" : "half", fc ? "en" : "dis");
1993 if (!netif_carrier_ok(dev))
1994 netif_carrier_on(dev);
1997 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1999 struct mv643xx_eth_private *mp;
2002 mp = container_of(napi, struct mv643xx_eth_private, napi);
2004 if (unlikely(mp->oom)) {
2006 del_timer(&mp->rx_oom);
2010 while (work_done < budget) {
2015 if (mp->work_link) {
2017 handle_link_event(mp);
2022 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2023 if (likely(!mp->oom))
2024 queue_mask |= mp->work_rx_refill;
2027 if (mv643xx_eth_collect_events(mp))
2032 queue = fls(queue_mask) - 1;
2033 queue_mask = 1 << queue;
2035 work_tbd = budget - work_done;
2039 if (mp->work_tx_end & queue_mask) {
2040 txq_kick(mp->txq + queue);
2041 } else if (mp->work_tx & queue_mask) {
2042 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2043 txq_maybe_wake(mp->txq + queue);
2044 } else if (mp->work_rx & queue_mask) {
2045 work_done += rxq_process(mp->rxq + queue, work_tbd);
2046 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2047 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2053 if (work_done < budget) {
2055 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2056 napi_complete(napi);
2057 wrlp(mp, INT_MASK, mp->int_mask);
2063 static inline void oom_timer_wrapper(unsigned long data)
2065 struct mv643xx_eth_private *mp = (void *)data;
2067 napi_schedule(&mp->napi);
2070 static void phy_reset(struct mv643xx_eth_private *mp)
2074 data = phy_read(mp->phy, MII_BMCR);
2079 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2083 data = phy_read(mp->phy, MII_BMCR);
2084 } while (data >= 0 && data & BMCR_RESET);
2087 static void port_start(struct mv643xx_eth_private *mp)
2093 * Perform PHY reset, if there is a PHY.
2095 if (mp->phy != NULL) {
2096 struct ethtool_cmd cmd;
2098 mv643xx_eth_get_settings(mp->dev, &cmd);
2100 mv643xx_eth_set_settings(mp->dev, &cmd);
2104 * Configure basic link parameters.
2106 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2108 pscr |= SERIAL_PORT_ENABLE;
2109 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2111 pscr |= DO_NOT_FORCE_LINK_FAIL;
2112 if (mp->phy == NULL)
2113 pscr |= FORCE_LINK_PASS;
2114 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2117 * Configure TX path and queues.
2119 tx_set_rate(mp, 1000000000, 16777216);
2120 for (i = 0; i < mp->txq_count; i++) {
2121 struct tx_queue *txq = mp->txq + i;
2123 txq_reset_hw_ptr(txq);
2124 txq_set_rate(txq, 1000000000, 16777216);
2125 txq_set_fixed_prio_mode(txq);
2129 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2130 * frames to RX queue #0, and include the pseudo-header when
2131 * calculating receive checksums.
2133 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2136 * Treat BPDUs as normal multicasts, and disable partition mode.
2138 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2141 * Add configured unicast addresses to address filter table.
2143 mv643xx_eth_program_unicast_filter(mp->dev);
2146 * Enable the receive queues.
2148 for (i = 0; i < mp->rxq_count; i++) {
2149 struct rx_queue *rxq = mp->rxq + i;
2152 addr = (u32)rxq->rx_desc_dma;
2153 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2154 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2160 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2165 * Reserve 2+14 bytes for an ethernet header (the hardware
2166 * automatically prepends 2 bytes of dummy data to each
2167 * received packet), 16 bytes for up to four VLAN tags, and
2168 * 4 bytes for the trailing FCS -- 36 bytes total.
2170 skb_size = mp->dev->mtu + 36;
2173 * Make sure that the skb size is a multiple of 8 bytes, as
2174 * the lower three bits of the receive descriptor's buffer
2175 * size field are ignored by the hardware.
2177 mp->skb_size = (skb_size + 7) & ~7;
2180 * If NET_SKB_PAD is smaller than a cache line,
2181 * netdev_alloc_skb() will cause skb->data to be misaligned
2182 * to a cache line boundary. If this is the case, include
2183 * some extra space to allow re-aligning the data area.
2185 mp->skb_size += SKB_DMA_REALIGN;
2188 static int mv643xx_eth_open(struct net_device *dev)
2190 struct mv643xx_eth_private *mp = netdev_priv(dev);
2194 wrlp(mp, INT_CAUSE, 0);
2195 wrlp(mp, INT_CAUSE_EXT, 0);
2196 rdlp(mp, INT_CAUSE_EXT);
2198 err = request_irq(dev->irq, mv643xx_eth_irq,
2199 IRQF_SHARED, dev->name, dev);
2201 netdev_err(dev, "can't assign irq\n");
2205 mv643xx_eth_recalc_skb_size(mp);
2207 napi_enable(&mp->napi);
2209 mp->int_mask = INT_EXT;
2211 for (i = 0; i < mp->rxq_count; i++) {
2212 err = rxq_init(mp, i);
2215 rxq_deinit(mp->rxq + i);
2219 rxq_refill(mp->rxq + i, INT_MAX);
2220 mp->int_mask |= INT_RX_0 << i;
2224 mp->rx_oom.expires = jiffies + (HZ / 10);
2225 add_timer(&mp->rx_oom);
2228 for (i = 0; i < mp->txq_count; i++) {
2229 err = txq_init(mp, i);
2232 txq_deinit(mp->txq + i);
2235 mp->int_mask |= INT_TX_END_0 << i;
2238 add_timer(&mp->mib_counters_timer);
2241 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2242 wrlp(mp, INT_MASK, mp->int_mask);
2248 for (i = 0; i < mp->rxq_count; i++)
2249 rxq_deinit(mp->rxq + i);
2251 free_irq(dev->irq, dev);
2256 static void port_reset(struct mv643xx_eth_private *mp)
2261 for (i = 0; i < mp->rxq_count; i++)
2262 rxq_disable(mp->rxq + i);
2263 for (i = 0; i < mp->txq_count; i++)
2264 txq_disable(mp->txq + i);
2267 u32 ps = rdlp(mp, PORT_STATUS);
2269 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2274 /* Reset the Enable bit in the Configuration Register */
2275 data = rdlp(mp, PORT_SERIAL_CONTROL);
2276 data &= ~(SERIAL_PORT_ENABLE |
2277 DO_NOT_FORCE_LINK_FAIL |
2279 wrlp(mp, PORT_SERIAL_CONTROL, data);
2282 static int mv643xx_eth_stop(struct net_device *dev)
2284 struct mv643xx_eth_private *mp = netdev_priv(dev);
2287 wrlp(mp, INT_MASK_EXT, 0x00000000);
2288 wrlp(mp, INT_MASK, 0x00000000);
2291 napi_disable(&mp->napi);
2293 del_timer_sync(&mp->rx_oom);
2295 netif_carrier_off(dev);
2297 free_irq(dev->irq, dev);
2300 mv643xx_eth_get_stats(dev);
2301 mib_counters_update(mp);
2302 del_timer_sync(&mp->mib_counters_timer);
2304 for (i = 0; i < mp->rxq_count; i++)
2305 rxq_deinit(mp->rxq + i);
2306 for (i = 0; i < mp->txq_count; i++)
2307 txq_deinit(mp->txq + i);
2312 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2314 struct mv643xx_eth_private *mp = netdev_priv(dev);
2317 if (mp->phy == NULL)
2320 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2322 mv643xx_adjust_pscr(mp);
2326 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2328 struct mv643xx_eth_private *mp = netdev_priv(dev);
2330 if (new_mtu < 64 || new_mtu > 9500)
2334 mv643xx_eth_recalc_skb_size(mp);
2335 tx_set_rate(mp, 1000000000, 16777216);
2337 if (!netif_running(dev))
2341 * Stop and then re-open the interface. This will allocate RX
2342 * skbs of the new MTU.
2343 * There is a possible danger that the open will not succeed,
2344 * due to memory being full.
2346 mv643xx_eth_stop(dev);
2347 if (mv643xx_eth_open(dev)) {
2349 "fatal error on re-opening device after MTU change\n");
2355 static void tx_timeout_task(struct work_struct *ugly)
2357 struct mv643xx_eth_private *mp;
2359 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2360 if (netif_running(mp->dev)) {
2361 netif_tx_stop_all_queues(mp->dev);
2364 netif_tx_wake_all_queues(mp->dev);
2368 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2370 struct mv643xx_eth_private *mp = netdev_priv(dev);
2372 netdev_info(dev, "tx timeout\n");
2374 schedule_work(&mp->tx_timeout_task);
2377 #ifdef CONFIG_NET_POLL_CONTROLLER
2378 static void mv643xx_eth_netpoll(struct net_device *dev)
2380 struct mv643xx_eth_private *mp = netdev_priv(dev);
2382 wrlp(mp, INT_MASK, 0x00000000);
2385 mv643xx_eth_irq(dev->irq, dev);
2387 wrlp(mp, INT_MASK, mp->int_mask);
2392 /* platform glue ************************************************************/
2394 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2395 const struct mbus_dram_target_info *dram)
2397 void __iomem *base = msp->base;
2402 for (i = 0; i < 6; i++) {
2403 writel(0, base + WINDOW_BASE(i));
2404 writel(0, base + WINDOW_SIZE(i));
2406 writel(0, base + WINDOW_REMAP_HIGH(i));
2412 for (i = 0; i < dram->num_cs; i++) {
2413 const struct mbus_dram_window *cs = dram->cs + i;
2415 writel((cs->base & 0xffff0000) |
2416 (cs->mbus_attr << 8) |
2417 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2418 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2420 win_enable &= ~(1 << i);
2421 win_protect |= 3 << (2 * i);
2424 writel(win_enable, base + WINDOW_BAR_ENABLE);
2425 msp->win_protect = win_protect;
2428 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2431 * Check whether we have a 14-bit coal limit field in bits
2432 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2433 * SDMA config register.
2435 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2436 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2437 msp->extended_rx_coal_limit = 1;
2439 msp->extended_rx_coal_limit = 0;
2442 * Check whether the MAC supports TX rate control, and if
2443 * yes, whether its associated registers are in the old or
2446 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2447 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2448 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2450 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2451 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2452 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2454 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2458 #if defined(CONFIG_OF)
2459 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2460 { .compatible = "marvell,orion-eth", },
2461 { .compatible = "marvell,kirkwood-eth", },
2464 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2467 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
2468 #define mv643xx_eth_property(_np, _name, _v) \
2471 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2475 static struct platform_device *port_platdev[3];
2477 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2478 struct device_node *pnp)
2480 struct platform_device *ppdev;
2481 struct mv643xx_eth_platform_data ppd;
2482 struct resource res;
2483 const char *mac_addr;
2487 memset(&ppd, 0, sizeof(ppd));
2490 memset(&res, 0, sizeof(res));
2491 if (!of_irq_to_resource(pnp, 0, &res)) {
2492 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2496 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2497 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2501 if (ppd.port_number >= 3) {
2502 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2506 while (dev_num < 3 && port_platdev[dev_num])
2510 dev_err(&pdev->dev, "too many ports registered\n");
2514 mac_addr = of_get_mac_address(pnp);
2516 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN);
2518 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2519 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2520 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2521 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2522 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2523 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2525 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2526 if (!ppd.phy_node) {
2527 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2528 of_property_read_u32(pnp, "speed", &ppd.speed);
2529 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2532 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2535 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2536 ppdev->dev.of_node = pnp;
2538 ret = platform_device_add_resources(ppdev, &res, 1);
2542 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2546 ret = platform_device_add(ppdev);
2550 port_platdev[dev_num] = ppdev;
2555 platform_device_put(ppdev);
2559 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2561 struct mv643xx_eth_shared_platform_data *pd;
2562 struct device_node *pnp, *np = pdev->dev.of_node;
2565 /* bail out if not registered from DT */
2569 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2572 pdev->dev.platform_data = pd;
2574 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2576 for_each_available_child_of_node(np, pnp) {
2577 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2584 static void mv643xx_eth_shared_of_remove(void)
2588 for (n = 0; n < 3; n++) {
2589 platform_device_del(port_platdev[n]);
2590 port_platdev[n] = NULL;
2594 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2599 static inline void mv643xx_eth_shared_of_remove(void)
2604 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2606 static int mv643xx_eth_version_printed;
2607 struct mv643xx_eth_shared_platform_data *pd;
2608 struct mv643xx_eth_shared_private *msp;
2609 const struct mbus_dram_target_info *dram;
2610 struct resource *res;
2613 if (!mv643xx_eth_version_printed++)
2614 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2615 mv643xx_eth_driver_version);
2617 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2621 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2624 platform_set_drvdata(pdev, msp);
2626 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2627 if (msp->base == NULL)
2630 msp->clk = devm_clk_get(&pdev->dev, NULL);
2631 if (!IS_ERR(msp->clk))
2632 clk_prepare_enable(msp->clk);
2635 * (Re-)program MBUS remapping windows if we are asked to.
2637 dram = mv_mbus_dram_info();
2639 mv643xx_eth_conf_mbus_windows(msp, dram);
2641 ret = mv643xx_eth_shared_of_probe(pdev);
2644 pd = dev_get_platdata(&pdev->dev);
2646 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2647 pd->tx_csum_limit : 9 * 1024;
2648 infer_hw_params(msp);
2653 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2655 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2657 mv643xx_eth_shared_of_remove();
2658 if (!IS_ERR(msp->clk))
2659 clk_disable_unprepare(msp->clk);
2663 static struct platform_driver mv643xx_eth_shared_driver = {
2664 .probe = mv643xx_eth_shared_probe,
2665 .remove = mv643xx_eth_shared_remove,
2667 .name = MV643XX_ETH_SHARED_NAME,
2668 .owner = THIS_MODULE,
2669 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2673 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2675 int addr_shift = 5 * mp->port_num;
2678 data = rdl(mp, PHY_ADDR);
2679 data &= ~(0x1f << addr_shift);
2680 data |= (phy_addr & 0x1f) << addr_shift;
2681 wrl(mp, PHY_ADDR, data);
2684 static int phy_addr_get(struct mv643xx_eth_private *mp)
2688 data = rdl(mp, PHY_ADDR);
2690 return (data >> (5 * mp->port_num)) & 0x1f;
2693 static void set_params(struct mv643xx_eth_private *mp,
2694 struct mv643xx_eth_platform_data *pd)
2696 struct net_device *dev = mp->dev;
2698 if (is_valid_ether_addr(pd->mac_addr))
2699 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2701 uc_addr_get(mp, dev->dev_addr);
2703 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2704 if (pd->rx_queue_size)
2705 mp->rx_ring_size = pd->rx_queue_size;
2706 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2707 mp->rx_desc_sram_size = pd->rx_sram_size;
2709 mp->rxq_count = pd->rx_queue_count ? : 1;
2711 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2712 if (pd->tx_queue_size)
2713 mp->tx_ring_size = pd->tx_queue_size;
2714 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2715 mp->tx_desc_sram_size = pd->tx_sram_size;
2717 mp->txq_count = pd->tx_queue_count ? : 1;
2720 static void mv643xx_eth_adjust_link(struct net_device *dev)
2722 struct mv643xx_eth_private *mp = netdev_priv(dev);
2724 mv643xx_adjust_pscr(mp);
2727 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2730 struct phy_device *phydev;
2734 char phy_id[MII_BUS_ID_SIZE + 3];
2736 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2737 start = phy_addr_get(mp) & 0x1f;
2740 start = phy_addr & 0x1f;
2744 /* Attempt to connect to the PHY using orion-mdio */
2745 phydev = ERR_PTR(-ENODEV);
2746 for (i = 0; i < num; i++) {
2747 int addr = (start + i) & 0x1f;
2749 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2750 "orion-mdio-mii", addr);
2752 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2753 PHY_INTERFACE_MODE_GMII);
2754 if (!IS_ERR(phydev)) {
2755 phy_addr_set(mp, addr);
2763 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2765 struct phy_device *phy = mp->phy;
2770 phy->autoneg = AUTONEG_ENABLE;
2773 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2775 phy->autoneg = AUTONEG_DISABLE;
2776 phy->advertising = 0;
2778 phy->duplex = duplex;
2780 phy_start_aneg(phy);
2783 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2787 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2788 if (pscr & SERIAL_PORT_ENABLE) {
2789 pscr &= ~SERIAL_PORT_ENABLE;
2790 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2793 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2794 if (mp->phy == NULL) {
2795 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2796 if (speed == SPEED_1000)
2797 pscr |= SET_GMII_SPEED_TO_1000;
2798 else if (speed == SPEED_100)
2799 pscr |= SET_MII_SPEED_TO_100;
2801 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2803 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2804 if (duplex == DUPLEX_FULL)
2805 pscr |= SET_FULL_DUPLEX_MODE;
2808 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2811 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2812 .ndo_open = mv643xx_eth_open,
2813 .ndo_stop = mv643xx_eth_stop,
2814 .ndo_start_xmit = mv643xx_eth_xmit,
2815 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2816 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2817 .ndo_validate_addr = eth_validate_addr,
2818 .ndo_do_ioctl = mv643xx_eth_ioctl,
2819 .ndo_change_mtu = mv643xx_eth_change_mtu,
2820 .ndo_set_features = mv643xx_eth_set_features,
2821 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2822 .ndo_get_stats = mv643xx_eth_get_stats,
2823 #ifdef CONFIG_NET_POLL_CONTROLLER
2824 .ndo_poll_controller = mv643xx_eth_netpoll,
2828 static int mv643xx_eth_probe(struct platform_device *pdev)
2830 struct mv643xx_eth_platform_data *pd;
2831 struct mv643xx_eth_private *mp;
2832 struct net_device *dev;
2833 struct resource *res;
2836 pd = dev_get_platdata(&pdev->dev);
2838 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2842 if (pd->shared == NULL) {
2843 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2847 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2851 mp = netdev_priv(dev);
2852 platform_set_drvdata(pdev, mp);
2854 mp->shared = platform_get_drvdata(pd->shared);
2855 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2856 mp->port_num = pd->port_number;
2860 /* Kirkwood resets some registers on gated clocks. Especially
2861 * CLK125_BYPASS_EN must be cleared but is not available on
2862 * all other SoCs/System Controllers using this driver.
2864 if (of_device_is_compatible(pdev->dev.of_node,
2865 "marvell,kirkwood-eth-port"))
2866 wrlp(mp, PORT_SERIAL_CONTROL1,
2867 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
2870 * Start with a default rate, and if there is a clock, allow
2871 * it to override the default.
2873 mp->t_clk = 133000000;
2874 mp->clk = devm_clk_get(&pdev->dev, NULL);
2875 if (!IS_ERR(mp->clk)) {
2876 clk_prepare_enable(mp->clk);
2877 mp->t_clk = clk_get_rate(mp->clk);
2878 } else if (!IS_ERR(mp->shared->clk)) {
2879 mp->t_clk = clk_get_rate(mp->shared->clk);
2883 netif_set_real_num_tx_queues(dev, mp->txq_count);
2884 netif_set_real_num_rx_queues(dev, mp->rxq_count);
2888 mp->phy = of_phy_connect(mp->dev, pd->phy_node,
2889 mv643xx_eth_adjust_link, 0,
2890 PHY_INTERFACE_MODE_GMII);
2894 phy_addr_set(mp, mp->phy->addr);
2895 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
2896 mp->phy = phy_scan(mp, pd->phy_addr);
2898 if (IS_ERR(mp->phy))
2899 err = PTR_ERR(mp->phy);
2901 phy_init(mp, pd->speed, pd->duplex);
2903 if (err == -ENODEV) {
2904 err = -EPROBE_DEFER;
2910 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2912 init_pscr(mp, pd->speed, pd->duplex);
2915 mib_counters_clear(mp);
2917 init_timer(&mp->mib_counters_timer);
2918 mp->mib_counters_timer.data = (unsigned long)mp;
2919 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2920 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2922 spin_lock_init(&mp->mib_counters_lock);
2924 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2926 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
2928 init_timer(&mp->rx_oom);
2929 mp->rx_oom.data = (unsigned long)mp;
2930 mp->rx_oom.function = oom_timer_wrapper;
2933 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2935 dev->irq = res->start;
2937 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2939 dev->watchdog_timeo = 2 * HZ;
2942 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2943 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2944 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2946 dev->priv_flags |= IFF_UNICAST_FLT;
2948 SET_NETDEV_DEV(dev, &pdev->dev);
2950 if (mp->shared->win_protect)
2951 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2953 netif_carrier_off(dev);
2955 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2957 set_rx_coal(mp, 250);
2960 err = register_netdev(dev);
2964 netdev_notice(dev, "port %d with MAC address %pM\n",
2965 mp->port_num, dev->dev_addr);
2967 if (mp->tx_desc_sram_size > 0)
2968 netdev_notice(dev, "configured with sram\n");
2973 if (!IS_ERR(mp->clk))
2974 clk_disable_unprepare(mp->clk);
2980 static int mv643xx_eth_remove(struct platform_device *pdev)
2982 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2984 unregister_netdev(mp->dev);
2985 if (mp->phy != NULL)
2986 phy_disconnect(mp->phy);
2987 cancel_work_sync(&mp->tx_timeout_task);
2989 if (!IS_ERR(mp->clk))
2990 clk_disable_unprepare(mp->clk);
2992 free_netdev(mp->dev);
2997 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2999 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3001 /* Mask all interrupts on ethernet port */
3002 wrlp(mp, INT_MASK, 0);
3005 if (netif_running(mp->dev))
3009 static struct platform_driver mv643xx_eth_driver = {
3010 .probe = mv643xx_eth_probe,
3011 .remove = mv643xx_eth_remove,
3012 .shutdown = mv643xx_eth_shutdown,
3014 .name = MV643XX_ETH_NAME,
3015 .owner = THIS_MODULE,
3019 static int __init mv643xx_eth_init_module(void)
3023 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3025 rc = platform_driver_register(&mv643xx_eth_driver);
3027 platform_driver_unregister(&mv643xx_eth_shared_driver);
3032 module_init(mv643xx_eth_init_module);
3034 static void __exit mv643xx_eth_cleanup_module(void)
3036 platform_driver_unregister(&mv643xx_eth_driver);
3037 platform_driver_unregister(&mv643xx_eth_shared_driver);
3039 module_exit(mv643xx_eth_cleanup_module);
3041 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3042 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3043 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3044 MODULE_LICENSE("GPL");
3045 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3046 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);