2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/of_address.h>
30 #include <linux/phy.h>
31 #include <linux/clk.h>
34 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
35 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
36 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
37 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
38 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
39 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
40 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
41 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
42 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
43 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
44 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
45 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
46 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
47 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
48 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
49 #define MVNETA_PORT_RX_RESET 0x1cc0
50 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
51 #define MVNETA_PHY_ADDR 0x2000
52 #define MVNETA_PHY_ADDR_MASK 0x1f
53 #define MVNETA_MBUS_RETRY 0x2010
54 #define MVNETA_UNIT_INTR_CAUSE 0x2080
55 #define MVNETA_UNIT_CONTROL 0x20B0
56 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
57 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
58 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
59 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
60 #define MVNETA_BASE_ADDR_ENABLE 0x2290
61 #define MVNETA_PORT_CONFIG 0x2400
62 #define MVNETA_UNI_PROMISC_MODE BIT(0)
63 #define MVNETA_DEF_RXQ(q) ((q) << 1)
64 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
65 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
66 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
67 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
68 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
69 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
70 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
71 MVNETA_DEF_RXQ_ARP(q) | \
72 MVNETA_DEF_RXQ_TCP(q) | \
73 MVNETA_DEF_RXQ_UDP(q) | \
74 MVNETA_DEF_RXQ_BPDU(q) | \
75 MVNETA_TX_UNSET_ERR_SUM | \
76 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
77 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
78 #define MVNETA_MAC_ADDR_LOW 0x2414
79 #define MVNETA_MAC_ADDR_HIGH 0x2418
80 #define MVNETA_SDMA_CONFIG 0x241c
81 #define MVNETA_SDMA_BRST_SIZE_16 4
82 #define MVNETA_NO_DESC_SWAP 0x0
83 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
84 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
85 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
86 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
87 #define MVNETA_PORT_STATUS 0x2444
88 #define MVNETA_TX_IN_PRGRS BIT(1)
89 #define MVNETA_TX_FIFO_EMPTY BIT(8)
90 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
91 #define MVNETA_SGMII_SERDES_CFG 0x24A0
92 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
93 #define MVNETA_TYPE_PRIO 0x24bc
94 #define MVNETA_FORCE_UNI BIT(21)
95 #define MVNETA_TXQ_CMD_1 0x24e4
96 #define MVNETA_TXQ_CMD 0x2448
97 #define MVNETA_TXQ_DISABLE_SHIFT 8
98 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
99 #define MVNETA_ACC_MODE 0x2500
100 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
101 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
102 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
103 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
104 #define MVNETA_INTR_NEW_CAUSE 0x25a0
105 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
106 #define MVNETA_INTR_NEW_MASK 0x25a4
107 #define MVNETA_INTR_OLD_CAUSE 0x25a8
108 #define MVNETA_INTR_OLD_MASK 0x25ac
109 #define MVNETA_INTR_MISC_CAUSE 0x25b0
110 #define MVNETA_INTR_MISC_MASK 0x25b4
111 #define MVNETA_INTR_ENABLE 0x25b8
112 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
113 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000
114 #define MVNETA_RXQ_CMD 0x2680
115 #define MVNETA_RXQ_DISABLE_SHIFT 8
116 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
117 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
118 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
119 #define MVNETA_GMAC_CTRL_0 0x2c00
120 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
121 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
122 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
123 #define MVNETA_GMAC_CTRL_2 0x2c08
124 #define MVNETA_GMAC2_PSC_ENABLE BIT(3)
125 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
126 #define MVNETA_GMAC2_PORT_RESET BIT(6)
127 #define MVNETA_GMAC_STATUS 0x2c10
128 #define MVNETA_GMAC_LINK_UP BIT(0)
129 #define MVNETA_GMAC_SPEED_1000 BIT(1)
130 #define MVNETA_GMAC_SPEED_100 BIT(2)
131 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
132 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
133 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
134 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
135 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
136 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
137 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
138 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
139 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
140 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
141 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
142 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
143 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
144 #define MVNETA_MIB_COUNTERS_BASE 0x3080
145 #define MVNETA_MIB_LATE_COLLISION 0x7c
146 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
147 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
148 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
149 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
150 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
151 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
152 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
153 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
154 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
155 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
156 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
157 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
158 #define MVNETA_PORT_TX_RESET 0x3cf0
159 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
160 #define MVNETA_TX_MTU 0x3e0c
161 #define MVNETA_TX_TOKEN_SIZE 0x3e14
162 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
163 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
164 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
166 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
168 /* Descriptor ring Macros */
169 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
170 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
172 /* Various constants */
175 #define MVNETA_TXDONE_COAL_PKTS 16
176 #define MVNETA_RX_COAL_PKTS 32
177 #define MVNETA_RX_COAL_USEC 100
180 #define MVNETA_TX_DONE_TIMER_PERIOD 10
182 /* Napi polling weight */
183 #define MVNETA_RX_POLL_WEIGHT 64
185 /* The two bytes Marvell header. Either contains a special value used
186 * by Marvell switches when a specific hardware mode is enabled (not
187 * supported by this driver) or is filled automatically by zeroes on
188 * the RX side. Those two bytes being at the front of the Ethernet
189 * header, they allow to have the IP header aligned on a 4 bytes
190 * boundary automatically: the hardware skips those two bytes on its
193 #define MVNETA_MH_SIZE 2
195 #define MVNETA_VLAN_TAG_LEN 4
197 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
198 #define MVNETA_TX_CSUM_MAX_SIZE 9800
199 #define MVNETA_ACC_MODE_EXT 1
201 /* Timeout constants */
202 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
203 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
204 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
206 #define MVNETA_TX_MTU_MAX 0x3ffff
208 /* Max number of Rx descriptors */
209 #define MVNETA_MAX_RXD 128
211 /* Max number of Tx descriptors */
212 #define MVNETA_MAX_TXD 532
214 /* descriptor aligned size */
215 #define MVNETA_DESC_ALIGNED_SIZE 32
217 #define MVNETA_RX_PKT_SIZE(mtu) \
218 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
219 ETH_HLEN + ETH_FCS_LEN, \
220 MVNETA_CPU_D_CACHE_LINE_SIZE)
222 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
224 struct mvneta_stats {
225 struct u64_stats_sync syncp;
233 struct mvneta_rx_queue *rxqs;
234 struct mvneta_tx_queue *txqs;
235 struct timer_list tx_done_timer;
236 struct net_device *dev;
239 struct napi_struct napi;
243 #define MVNETA_F_TX_DONE_TIMER_BIT 0
253 struct mvneta_stats tx_stats;
254 struct mvneta_stats rx_stats;
256 struct mii_bus *mii_bus;
257 struct phy_device *phy_dev;
258 phy_interface_t phy_interface;
259 struct device_node *phy_node;
265 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
266 * layout of the transmit and reception DMA descriptors, and their
267 * layout is therefore defined by the hardware design
269 struct mvneta_tx_desc {
270 u32 command; /* Options used by HW for packet transmitting.*/
271 #define MVNETA_TX_L3_OFF_SHIFT 0
272 #define MVNETA_TX_IP_HLEN_SHIFT 8
273 #define MVNETA_TX_L4_UDP BIT(16)
274 #define MVNETA_TX_L3_IP6 BIT(17)
275 #define MVNETA_TXD_IP_CSUM BIT(18)
276 #define MVNETA_TXD_Z_PAD BIT(19)
277 #define MVNETA_TXD_L_DESC BIT(20)
278 #define MVNETA_TXD_F_DESC BIT(21)
279 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
280 MVNETA_TXD_L_DESC | \
282 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
283 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
285 u16 reserverd1; /* csum_l4 (for future use) */
286 u16 data_size; /* Data size of transmitted packet in bytes */
287 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
288 u32 reserved2; /* hw_cmd - (for future use, PMT) */
289 u32 reserved3[4]; /* Reserved - (for future use) */
292 struct mvneta_rx_desc {
293 u32 status; /* Info about received packet */
294 #define MVNETA_RXD_ERR_CRC 0x0
295 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
296 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
297 #define MVNETA_RXD_ERR_LEN BIT(18)
298 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
299 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
300 #define MVNETA_RXD_L3_IP4 BIT(25)
301 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
302 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
304 u16 reserved1; /* pnc_info - (for future use, PnC) */
305 u16 data_size; /* Size of received packet in bytes */
306 u32 buf_phys_addr; /* Physical address of the buffer */
307 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
308 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
309 u16 reserved3; /* prefetch_cmd, for future use */
310 u16 reserved4; /* csum_l4 - (for future use, PnC) */
311 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
312 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
315 struct mvneta_tx_queue {
316 /* Number of this TX queue, in the range 0-7 */
319 /* Number of TX DMA descriptors in the descriptor ring */
322 /* Number of currently used TX DMA descriptor in the
327 /* Array of transmitted skb */
328 struct sk_buff **tx_skb;
330 /* Index of last TX DMA descriptor that was inserted */
333 /* Index of the TX DMA descriptor to be cleaned up */
338 /* Virtual address of the TX DMA descriptors array */
339 struct mvneta_tx_desc *descs;
341 /* DMA address of the TX DMA descriptors array */
342 dma_addr_t descs_phys;
344 /* Index of the last TX DMA descriptor */
347 /* Index of the next TX DMA descriptor to process */
348 int next_desc_to_proc;
351 struct mvneta_rx_queue {
352 /* rx queue number, in the range 0-7 */
355 /* num of rx descriptors in the rx descriptor ring */
358 /* counter of times when mvneta_refill() failed */
364 /* Virtual address of the RX DMA descriptors array */
365 struct mvneta_rx_desc *descs;
367 /* DMA address of the RX DMA descriptors array */
368 dma_addr_t descs_phys;
370 /* Index of the last RX DMA descriptor */
373 /* Index of the next RX DMA descriptor to process */
374 int next_desc_to_proc;
377 static int rxq_number = 8;
378 static int txq_number = 8;
382 #define MVNETA_DRIVER_NAME "mvneta"
383 #define MVNETA_DRIVER_VERSION "1.0"
385 /* Utility/helper methods */
387 /* Write helper method */
388 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
390 writel(data, pp->base + offset);
393 /* Read helper method */
394 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
396 return readl(pp->base + offset);
399 /* Increment txq get counter */
400 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
402 txq->txq_get_index++;
403 if (txq->txq_get_index == txq->size)
404 txq->txq_get_index = 0;
407 /* Increment txq put counter */
408 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
410 txq->txq_put_index++;
411 if (txq->txq_put_index == txq->size)
412 txq->txq_put_index = 0;
416 /* Clear all MIB counters */
417 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
422 /* Perform dummy reads from MIB counters */
423 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
424 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
427 /* Get System Network Statistics */
428 struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
429 struct rtnl_link_stats64 *stats)
431 struct mvneta_port *pp = netdev_priv(dev);
434 memset(stats, 0, sizeof(struct rtnl_link_stats64));
437 start = u64_stats_fetch_begin_bh(&pp->rx_stats.syncp);
438 stats->rx_packets = pp->rx_stats.packets;
439 stats->rx_bytes = pp->rx_stats.bytes;
440 } while (u64_stats_fetch_retry_bh(&pp->rx_stats.syncp, start));
444 start = u64_stats_fetch_begin_bh(&pp->tx_stats.syncp);
445 stats->tx_packets = pp->tx_stats.packets;
446 stats->tx_bytes = pp->tx_stats.bytes;
447 } while (u64_stats_fetch_retry_bh(&pp->tx_stats.syncp, start));
449 stats->rx_errors = dev->stats.rx_errors;
450 stats->rx_dropped = dev->stats.rx_dropped;
452 stats->tx_dropped = dev->stats.tx_dropped;
457 /* Rx descriptors helper methods */
459 /* Checks whether the given RX descriptor is both the first and the
460 * last descriptor for the RX packet. Each RX packet is currently
461 * received through a single RX descriptor, so not having each RX
462 * descriptor with its first and last bits set is an error
464 static int mvneta_rxq_desc_is_first_last(struct mvneta_rx_desc *desc)
466 return (desc->status & MVNETA_RXD_FIRST_LAST_DESC) ==
467 MVNETA_RXD_FIRST_LAST_DESC;
470 /* Add number of descriptors ready to receive new packets */
471 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
472 struct mvneta_rx_queue *rxq,
475 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
478 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
479 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
480 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
481 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
482 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
485 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
486 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
489 /* Get number of RX descriptors occupied by received packets */
490 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
491 struct mvneta_rx_queue *rxq)
495 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
496 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
499 /* Update num of rx desc called upon return from rx path or
500 * from mvneta_rxq_drop_pkts().
502 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
503 struct mvneta_rx_queue *rxq,
504 int rx_done, int rx_filled)
508 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
510 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
511 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
515 /* Only 255 descriptors can be added at once */
516 while ((rx_done > 0) || (rx_filled > 0)) {
517 if (rx_done <= 0xff) {
524 if (rx_filled <= 0xff) {
525 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
528 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
531 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
535 /* Get pointer to next RX descriptor to be processed by SW */
536 static struct mvneta_rx_desc *
537 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
539 int rx_desc = rxq->next_desc_to_proc;
541 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
542 return rxq->descs + rx_desc;
545 /* Change maximum receive size of the port. */
546 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
550 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
551 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
552 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
553 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
554 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
558 /* Set rx queue offset */
559 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
560 struct mvneta_rx_queue *rxq,
565 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
566 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
569 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
570 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
574 /* Tx descriptors helper methods */
576 /* Update HW with number of TX descriptors to be sent */
577 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
578 struct mvneta_tx_queue *txq,
583 /* Only 255 descriptors can be added at once ; Assume caller
584 * process TX desriptors in quanta less than 256
587 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
590 /* Get pointer to next TX descriptor to be processed (send) by HW */
591 static struct mvneta_tx_desc *
592 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
594 int tx_desc = txq->next_desc_to_proc;
596 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
597 return txq->descs + tx_desc;
600 /* Release the last allocated TX descriptor. Useful to handle DMA
601 * mapping failures in the TX path.
603 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
605 if (txq->next_desc_to_proc == 0)
606 txq->next_desc_to_proc = txq->last_desc - 1;
608 txq->next_desc_to_proc--;
611 /* Set rxq buf size */
612 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
613 struct mvneta_rx_queue *rxq,
618 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
620 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
621 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
623 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
626 /* Disable buffer management (BM) */
627 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
628 struct mvneta_rx_queue *rxq)
632 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
633 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
634 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
639 /* Sets the RGMII Enable bit (RGMIIEn) in port MAC control register */
640 static void mvneta_gmac_rgmii_set(struct mvneta_port *pp, int enable)
644 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
647 val |= MVNETA_GMAC2_PORT_RGMII;
649 val &= ~MVNETA_GMAC2_PORT_RGMII;
651 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
654 /* Config SGMII port */
655 static void mvneta_port_sgmii_config(struct mvneta_port *pp)
659 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
660 val |= MVNETA_GMAC2_PSC_ENABLE;
661 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
663 mvreg_write(pp, MVNETA_SGMII_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
666 /* Start the Ethernet port RX and TX activity */
667 static void mvneta_port_up(struct mvneta_port *pp)
672 /* Enable all initialized TXs. */
673 mvneta_mib_counters_clear(pp);
675 for (queue = 0; queue < txq_number; queue++) {
676 struct mvneta_tx_queue *txq = &pp->txqs[queue];
677 if (txq->descs != NULL)
678 q_map |= (1 << queue);
680 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
682 /* Enable all initialized RXQs. */
684 for (queue = 0; queue < rxq_number; queue++) {
685 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
686 if (rxq->descs != NULL)
687 q_map |= (1 << queue);
690 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
693 /* Stop the Ethernet port activity */
694 static void mvneta_port_down(struct mvneta_port *pp)
699 /* Stop Rx port activity. Check port Rx activity. */
700 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
702 /* Issue stop command for active channels only */
704 mvreg_write(pp, MVNETA_RXQ_CMD,
705 val << MVNETA_RXQ_DISABLE_SHIFT);
707 /* Wait for all Rx activity to terminate. */
710 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
712 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
718 val = mvreg_read(pp, MVNETA_RXQ_CMD);
719 } while (val & 0xff);
721 /* Stop Tx port activity. Check port Tx activity. Issue stop
722 * command for active channels only
724 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
727 mvreg_write(pp, MVNETA_TXQ_CMD,
728 (val << MVNETA_TXQ_DISABLE_SHIFT));
730 /* Wait for all Tx activity to terminate. */
733 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
735 "TIMEOUT for TX stopped status=0x%08x\n",
741 /* Check TX Command reg that all Txqs are stopped */
742 val = mvreg_read(pp, MVNETA_TXQ_CMD);
744 } while (val & 0xff);
746 /* Double check to verify that TX FIFO is empty */
749 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
751 "TX FIFO empty timeout status=0x08%x\n",
757 val = mvreg_read(pp, MVNETA_PORT_STATUS);
758 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
759 (val & MVNETA_TX_IN_PRGRS));
764 /* Enable the port by setting the port enable bit of the MAC control register */
765 static void mvneta_port_enable(struct mvneta_port *pp)
770 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
771 val |= MVNETA_GMAC0_PORT_ENABLE;
772 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
775 /* Disable the port and wait for about 200 usec before retuning */
776 static void mvneta_port_disable(struct mvneta_port *pp)
780 /* Reset the Enable bit in the Serial Control Register */
781 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
782 val &= ~MVNETA_GMAC0_PORT_ENABLE;
783 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
788 /* Multicast tables methods */
790 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
791 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
799 val = 0x1 | (queue << 1);
800 val |= (val << 24) | (val << 16) | (val << 8);
803 for (offset = 0; offset <= 0xc; offset += 4)
804 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
807 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
808 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
816 val = 0x1 | (queue << 1);
817 val |= (val << 24) | (val << 16) | (val << 8);
820 for (offset = 0; offset <= 0xfc; offset += 4)
821 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
825 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
826 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
832 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
835 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
836 val = 0x1 | (queue << 1);
837 val |= (val << 24) | (val << 16) | (val << 8);
840 for (offset = 0; offset <= 0xfc; offset += 4)
841 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
844 /* This method sets defaults to the NETA port:
845 * Clears interrupt Cause and Mask registers.
846 * Clears all MAC tables.
847 * Sets defaults to all registers.
848 * Resets RX and TX descriptor rings.
850 * This method can be called after mvneta_port_down() to return the port
851 * settings to defaults.
853 static void mvneta_defaults_set(struct mvneta_port *pp)
859 /* Clear all Cause registers */
860 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
861 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
862 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
864 /* Mask all interrupts */
865 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
866 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
867 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
868 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
870 /* Enable MBUS Retry bit16 */
871 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
873 /* Set CPU queue access map - all CPUs have access to all RX
874 * queues and to all TX queues
876 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
877 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
878 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
879 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
881 /* Reset RX and TX DMAs */
882 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
883 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
885 /* Disable Legacy WRR, Disable EJP, Release from reset */
886 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
887 for (queue = 0; queue < txq_number; queue++) {
888 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
889 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
892 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
893 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
895 /* Set Port Acceleration Mode */
896 val = MVNETA_ACC_MODE_EXT;
897 mvreg_write(pp, MVNETA_ACC_MODE, val);
899 /* Update val of portCfg register accordingly with all RxQueue types */
900 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
901 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
904 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
905 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
907 /* Build PORT_SDMA_CONFIG_REG */
910 /* Default burst size */
911 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
912 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
914 val |= (MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP |
915 MVNETA_NO_DESC_SWAP);
917 /* Assign port SDMA configuration */
918 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
920 /* Disable PHY polling in hardware, since we're using the
921 * kernel phylib to do this.
923 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
924 val &= ~MVNETA_PHY_POLLING_ENABLE;
925 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
927 mvneta_set_ucast_table(pp, -1);
928 mvneta_set_special_mcast_table(pp, -1);
929 mvneta_set_other_mcast_table(pp, -1);
931 /* Set port interrupt enable register - default enable all */
932 mvreg_write(pp, MVNETA_INTR_ENABLE,
933 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
934 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
937 /* Set max sizes for tx queues */
938 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
944 mtu = max_tx_size * 8;
945 if (mtu > MVNETA_TX_MTU_MAX)
946 mtu = MVNETA_TX_MTU_MAX;
949 val = mvreg_read(pp, MVNETA_TX_MTU);
950 val &= ~MVNETA_TX_MTU_MAX;
952 mvreg_write(pp, MVNETA_TX_MTU, val);
954 /* TX token size and all TXQs token size must be larger that MTU */
955 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
957 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
960 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
962 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
964 for (queue = 0; queue < txq_number; queue++) {
965 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
967 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
970 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
972 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
977 /* Set unicast address */
978 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
981 unsigned int unicast_reg;
982 unsigned int tbl_offset;
983 unsigned int reg_offset;
985 /* Locate the Unicast table entry */
986 last_nibble = (0xf & last_nibble);
988 /* offset from unicast tbl base */
989 tbl_offset = (last_nibble / 4) * 4;
991 /* offset within the above reg */
992 reg_offset = last_nibble % 4;
994 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
997 /* Clear accepts frame bit at specified unicast DA tbl entry */
998 unicast_reg &= ~(0xff << (8 * reg_offset));
1000 unicast_reg &= ~(0xff << (8 * reg_offset));
1001 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1004 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1007 /* Set mac address */
1008 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1015 mac_l = (addr[4] << 8) | (addr[5]);
1016 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1017 (addr[2] << 8) | (addr[3] << 0);
1019 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1020 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1023 /* Accept frames of this address */
1024 mvneta_set_ucast_addr(pp, addr[5], queue);
1027 /* Set the number of packets that will be received before RX interrupt
1028 * will be generated by HW.
1030 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1031 struct mvneta_rx_queue *rxq, u32 value)
1033 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1034 value | MVNETA_RXQ_NON_OCCUPIED(0));
1035 rxq->pkts_coal = value;
1038 /* Set the time delay in usec before RX interrupt will be generated by
1041 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1042 struct mvneta_rx_queue *rxq, u32 value)
1045 unsigned long clk_rate;
1047 clk_rate = clk_get_rate(pp->clk);
1048 val = (clk_rate / 1000000) * value;
1050 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1051 rxq->time_coal = value;
1054 /* Set threshold for TX_DONE pkts coalescing */
1055 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1056 struct mvneta_tx_queue *txq, u32 value)
1060 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1062 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1063 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1065 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1067 txq->done_pkts_coal = value;
1070 /* Trigger tx done timer in MVNETA_TX_DONE_TIMER_PERIOD msecs */
1071 static void mvneta_add_tx_done_timer(struct mvneta_port *pp)
1073 if (test_and_set_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags) == 0) {
1074 pp->tx_done_timer.expires = jiffies +
1075 msecs_to_jiffies(MVNETA_TX_DONE_TIMER_PERIOD);
1076 add_timer(&pp->tx_done_timer);
1081 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1082 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1083 u32 phys_addr, u32 cookie)
1085 rx_desc->buf_cookie = cookie;
1086 rx_desc->buf_phys_addr = phys_addr;
1089 /* Decrement sent descriptors counter */
1090 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1091 struct mvneta_tx_queue *txq,
1096 /* Only 255 TX descriptors can be updated at once */
1097 while (sent_desc > 0xff) {
1098 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1099 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1100 sent_desc = sent_desc - 0xff;
1103 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1104 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1107 /* Get number of TX descriptors already sent by HW */
1108 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1109 struct mvneta_tx_queue *txq)
1114 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1115 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1116 MVNETA_TXQ_SENT_DESC_SHIFT;
1121 /* Get number of sent descriptors and decrement counter.
1122 * The number of sent descriptors is returned.
1124 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1125 struct mvneta_tx_queue *txq)
1129 /* Get number of sent descriptors */
1130 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1132 /* Decrement sent descriptors counter */
1134 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1139 /* Set TXQ descriptors fields relevant for CSUM calculation */
1140 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1141 int ip_hdr_len, int l4_proto)
1145 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1146 * G_L4_chk, L4_type; required only for checksum
1149 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1150 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1152 if (l3_proto == swab16(ETH_P_IP))
1153 command |= MVNETA_TXD_IP_CSUM;
1155 command |= MVNETA_TX_L3_IP6;
1157 if (l4_proto == IPPROTO_TCP)
1158 command |= MVNETA_TX_L4_CSUM_FULL;
1159 else if (l4_proto == IPPROTO_UDP)
1160 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1162 command |= MVNETA_TX_L4_CSUM_NOT;
1168 /* Display more error info */
1169 static void mvneta_rx_error(struct mvneta_port *pp,
1170 struct mvneta_rx_desc *rx_desc)
1172 u32 status = rx_desc->status;
1174 if (!mvneta_rxq_desc_is_first_last(rx_desc)) {
1176 "bad rx status %08x (buffer oversize), size=%d\n",
1177 rx_desc->status, rx_desc->data_size);
1181 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1182 case MVNETA_RXD_ERR_CRC:
1183 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1184 status, rx_desc->data_size);
1186 case MVNETA_RXD_ERR_OVERRUN:
1187 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1188 status, rx_desc->data_size);
1190 case MVNETA_RXD_ERR_LEN:
1191 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1192 status, rx_desc->data_size);
1194 case MVNETA_RXD_ERR_RESOURCE:
1195 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1196 status, rx_desc->data_size);
1201 /* Handle RX checksum offload */
1202 static void mvneta_rx_csum(struct mvneta_port *pp,
1203 struct mvneta_rx_desc *rx_desc,
1204 struct sk_buff *skb)
1206 if ((rx_desc->status & MVNETA_RXD_L3_IP4) &&
1207 (rx_desc->status & MVNETA_RXD_L4_CSUM_OK)) {
1209 skb->ip_summed = CHECKSUM_UNNECESSARY;
1213 skb->ip_summed = CHECKSUM_NONE;
1216 /* Return tx queue pointer (find last set bit) according to causeTxDone reg */
1217 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1220 int queue = fls(cause) - 1;
1222 return (queue < 0 || queue >= txq_number) ? NULL : &pp->txqs[queue];
1225 /* Free tx queue skbuffs */
1226 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1227 struct mvneta_tx_queue *txq, int num)
1231 for (i = 0; i < num; i++) {
1232 struct mvneta_tx_desc *tx_desc = txq->descs +
1234 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1236 mvneta_txq_inc_get(txq);
1241 dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr,
1242 tx_desc->data_size, DMA_TO_DEVICE);
1243 dev_kfree_skb_any(skb);
1247 /* Handle end of transmission */
1248 static int mvneta_txq_done(struct mvneta_port *pp,
1249 struct mvneta_tx_queue *txq)
1251 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1254 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1257 mvneta_txq_bufs_free(pp, txq, tx_done);
1259 txq->count -= tx_done;
1261 if (netif_tx_queue_stopped(nq)) {
1262 if (txq->size - txq->count >= MAX_SKB_FRAGS + 1)
1263 netif_tx_wake_queue(nq);
1269 /* Refill processing */
1270 static int mvneta_rx_refill(struct mvneta_port *pp,
1271 struct mvneta_rx_desc *rx_desc)
1274 dma_addr_t phys_addr;
1275 struct sk_buff *skb;
1277 skb = netdev_alloc_skb(pp->dev, pp->pkt_size);
1281 phys_addr = dma_map_single(pp->dev->dev.parent, skb->head,
1282 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1284 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1289 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)skb);
1294 /* Handle tx checksum */
1295 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1297 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1301 if (skb->protocol == htons(ETH_P_IP)) {
1302 struct iphdr *ip4h = ip_hdr(skb);
1304 /* Calculate IPv4 checksum and L4 checksum */
1305 ip_hdr_len = ip4h->ihl;
1306 l4_proto = ip4h->protocol;
1307 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1308 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1310 /* Read l4_protocol from one of IPv6 extra headers */
1311 if (skb_network_header_len(skb) > 0)
1312 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1313 l4_proto = ip6h->nexthdr;
1315 return MVNETA_TX_L4_CSUM_NOT;
1317 return mvneta_txq_desc_csum(skb_network_offset(skb),
1318 skb->protocol, ip_hdr_len, l4_proto);
1321 return MVNETA_TX_L4_CSUM_NOT;
1324 /* Returns rx queue pointer (find last set bit) according to causeRxTx
1327 static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp,
1330 int queue = fls(cause >> 8) - 1;
1332 return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue];
1335 /* Drop packets received by the RXQ and free buffers */
1336 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1337 struct mvneta_rx_queue *rxq)
1341 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1342 for (i = 0; i < rxq->size; i++) {
1343 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1344 struct sk_buff *skb = (struct sk_buff *)rx_desc->buf_cookie;
1346 dev_kfree_skb_any(skb);
1347 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1348 rx_desc->data_size, DMA_FROM_DEVICE);
1352 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1355 /* Main rx processing */
1356 static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1357 struct mvneta_rx_queue *rxq)
1359 struct net_device *dev = pp->dev;
1360 int rx_done, rx_filled;
1362 /* Get number of received packets */
1363 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1365 if (rx_todo > rx_done)
1371 /* Fairness NAPI loop */
1372 while (rx_done < rx_todo) {
1373 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1374 struct sk_buff *skb;
1381 rx_status = rx_desc->status;
1382 skb = (struct sk_buff *)rx_desc->buf_cookie;
1384 if (!mvneta_rxq_desc_is_first_last(rx_desc) ||
1385 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1386 dev->stats.rx_errors++;
1387 mvneta_rx_error(pp, rx_desc);
1388 mvneta_rx_desc_fill(rx_desc, rx_desc->buf_phys_addr,
1393 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1394 rx_desc->data_size, DMA_FROM_DEVICE);
1396 rx_bytes = rx_desc->data_size -
1397 (ETH_FCS_LEN + MVNETA_MH_SIZE);
1398 u64_stats_update_begin(&pp->rx_stats.syncp);
1399 pp->rx_stats.packets++;
1400 pp->rx_stats.bytes += rx_bytes;
1401 u64_stats_update_end(&pp->rx_stats.syncp);
1403 /* Linux processing */
1404 skb_reserve(skb, MVNETA_MH_SIZE);
1405 skb_put(skb, rx_bytes);
1407 skb->protocol = eth_type_trans(skb, dev);
1409 mvneta_rx_csum(pp, rx_desc, skb);
1411 napi_gro_receive(&pp->napi, skb);
1413 /* Refill processing */
1414 err = mvneta_rx_refill(pp, rx_desc);
1416 netdev_err(pp->dev, "Linux processing - Can't refill\n");
1422 /* Update rxq management counters */
1423 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled);
1428 /* Handle tx fragmentation processing */
1429 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1430 struct mvneta_tx_queue *txq)
1432 struct mvneta_tx_desc *tx_desc;
1435 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1436 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1437 void *addr = page_address(frag->page.p) + frag->page_offset;
1439 tx_desc = mvneta_txq_next_desc_get(txq);
1440 tx_desc->data_size = frag->size;
1442 tx_desc->buf_phys_addr =
1443 dma_map_single(pp->dev->dev.parent, addr,
1444 tx_desc->data_size, DMA_TO_DEVICE);
1446 if (dma_mapping_error(pp->dev->dev.parent,
1447 tx_desc->buf_phys_addr)) {
1448 mvneta_txq_desc_put(txq);
1452 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
1453 /* Last descriptor */
1454 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
1456 txq->tx_skb[txq->txq_put_index] = skb;
1458 mvneta_txq_inc_put(txq);
1460 /* Descriptor in the middle: Not First, Not Last */
1461 tx_desc->command = 0;
1463 txq->tx_skb[txq->txq_put_index] = NULL;
1464 mvneta_txq_inc_put(txq);
1471 /* Release all descriptors that were used to map fragments of
1472 * this packet, as well as the corresponding DMA mappings
1474 for (i = i - 1; i >= 0; i--) {
1475 tx_desc = txq->descs + i;
1476 dma_unmap_single(pp->dev->dev.parent,
1477 tx_desc->buf_phys_addr,
1480 mvneta_txq_desc_put(txq);
1486 /* Main tx processing */
1487 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1489 struct mvneta_port *pp = netdev_priv(dev);
1490 u16 txq_id = skb_get_queue_mapping(skb);
1491 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
1492 struct mvneta_tx_desc *tx_desc;
1493 struct netdev_queue *nq;
1497 if (!netif_running(dev))
1500 frags = skb_shinfo(skb)->nr_frags + 1;
1501 nq = netdev_get_tx_queue(dev, txq_id);
1503 /* Get a descriptor for the first part of the packet */
1504 tx_desc = mvneta_txq_next_desc_get(txq);
1506 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1508 tx_desc->data_size = skb_headlen(skb);
1510 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1513 if (unlikely(dma_mapping_error(dev->dev.parent,
1514 tx_desc->buf_phys_addr))) {
1515 mvneta_txq_desc_put(txq);
1521 /* First and Last descriptor */
1522 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1523 tx_desc->command = tx_cmd;
1524 txq->tx_skb[txq->txq_put_index] = skb;
1525 mvneta_txq_inc_put(txq);
1527 /* First but not Last */
1528 tx_cmd |= MVNETA_TXD_F_DESC;
1529 txq->tx_skb[txq->txq_put_index] = NULL;
1530 mvneta_txq_inc_put(txq);
1531 tx_desc->command = tx_cmd;
1532 /* Continue with other skb fragments */
1533 if (mvneta_tx_frag_process(pp, skb, txq)) {
1534 dma_unmap_single(dev->dev.parent,
1535 tx_desc->buf_phys_addr,
1538 mvneta_txq_desc_put(txq);
1544 txq->count += frags;
1545 mvneta_txq_pend_desc_add(pp, txq, frags);
1547 if (txq->size - txq->count < MAX_SKB_FRAGS + 1)
1548 netif_tx_stop_queue(nq);
1552 u64_stats_update_begin(&pp->tx_stats.syncp);
1553 pp->tx_stats.packets++;
1554 pp->tx_stats.bytes += skb->len;
1555 u64_stats_update_end(&pp->tx_stats.syncp);
1558 dev->stats.tx_dropped++;
1559 dev_kfree_skb_any(skb);
1562 if (txq->count >= MVNETA_TXDONE_COAL_PKTS)
1563 mvneta_txq_done(pp, txq);
1565 /* If after calling mvneta_txq_done, count equals
1566 * frags, we need to set the timer
1568 if (txq->count == frags && frags > 0)
1569 mvneta_add_tx_done_timer(pp);
1571 return NETDEV_TX_OK;
1575 /* Free tx resources, when resetting a port */
1576 static void mvneta_txq_done_force(struct mvneta_port *pp,
1577 struct mvneta_tx_queue *txq)
1580 int tx_done = txq->count;
1582 mvneta_txq_bufs_free(pp, txq, tx_done);
1586 txq->txq_put_index = 0;
1587 txq->txq_get_index = 0;
1590 /* handle tx done - called from tx done timer callback */
1591 static u32 mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done,
1594 struct mvneta_tx_queue *txq;
1596 struct netdev_queue *nq;
1599 while (cause_tx_done != 0) {
1600 txq = mvneta_tx_done_policy(pp, cause_tx_done);
1604 nq = netdev_get_tx_queue(pp->dev, txq->id);
1605 __netif_tx_lock(nq, smp_processor_id());
1608 tx_done += mvneta_txq_done(pp, txq);
1609 *tx_todo += txq->count;
1612 __netif_tx_unlock(nq);
1613 cause_tx_done &= ~((1 << txq->id));
1619 /* Compute crc8 of the specified address, using a unique algorithm ,
1620 * according to hw spec, different than generic crc8 algorithm
1622 static int mvneta_addr_crc(unsigned char *addr)
1627 for (i = 0; i < ETH_ALEN; i++) {
1630 crc = (crc ^ addr[i]) << 8;
1631 for (j = 7; j >= 0; j--) {
1632 if (crc & (0x100 << j))
1640 /* This method controls the net device special MAC multicast support.
1641 * The Special Multicast Table for MAC addresses supports MAC of the form
1642 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1643 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1644 * Table entries in the DA-Filter table. This method set the Special
1645 * Multicast Table appropriate entry.
1647 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
1648 unsigned char last_byte,
1651 unsigned int smc_table_reg;
1652 unsigned int tbl_offset;
1653 unsigned int reg_offset;
1655 /* Register offset from SMC table base */
1656 tbl_offset = (last_byte / 4);
1657 /* Entry offset within the above reg */
1658 reg_offset = last_byte % 4;
1660 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
1664 smc_table_reg &= ~(0xff << (8 * reg_offset));
1666 smc_table_reg &= ~(0xff << (8 * reg_offset));
1667 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1670 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
1674 /* This method controls the network device Other MAC multicast support.
1675 * The Other Multicast Table is used for multicast of another type.
1676 * A CRC-8 is used as an index to the Other Multicast Table entries
1677 * in the DA-Filter table.
1678 * The method gets the CRC-8 value from the calling routine and
1679 * sets the Other Multicast Table appropriate entry according to the
1682 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
1686 unsigned int omc_table_reg;
1687 unsigned int tbl_offset;
1688 unsigned int reg_offset;
1690 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1691 reg_offset = crc8 % 4; /* Entry offset within the above reg */
1693 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
1696 /* Clear accepts frame bit at specified Other DA table entry */
1697 omc_table_reg &= ~(0xff << (8 * reg_offset));
1699 omc_table_reg &= ~(0xff << (8 * reg_offset));
1700 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1703 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
1706 /* The network device supports multicast using two tables:
1707 * 1) Special Multicast Table for MAC addresses of the form
1708 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1709 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1710 * Table entries in the DA-Filter table.
1711 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
1712 * is used as an index to the Other Multicast Table entries in the
1715 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
1718 unsigned char crc_result = 0;
1720 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
1721 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
1725 crc_result = mvneta_addr_crc(p_addr);
1727 if (pp->mcast_count[crc_result] == 0) {
1728 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
1733 pp->mcast_count[crc_result]--;
1734 if (pp->mcast_count[crc_result] != 0) {
1735 netdev_info(pp->dev,
1736 "After delete there are %d valid Mcast for crc8=0x%02x\n",
1737 pp->mcast_count[crc_result], crc_result);
1741 pp->mcast_count[crc_result]++;
1743 mvneta_set_other_mcast_addr(pp, crc_result, queue);
1748 /* Configure Fitering mode of Ethernet port */
1749 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
1752 u32 port_cfg_reg, val;
1754 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
1756 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
1758 /* Set / Clear UPM bit in port configuration register */
1760 /* Accept all Unicast addresses */
1761 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
1762 val |= MVNETA_FORCE_UNI;
1763 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
1764 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
1766 /* Reject all Unicast addresses */
1767 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
1768 val &= ~MVNETA_FORCE_UNI;
1771 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
1772 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
1775 /* register unicast and multicast addresses */
1776 static void mvneta_set_rx_mode(struct net_device *dev)
1778 struct mvneta_port *pp = netdev_priv(dev);
1779 struct netdev_hw_addr *ha;
1781 if (dev->flags & IFF_PROMISC) {
1782 /* Accept all: Multicast + Unicast */
1783 mvneta_rx_unicast_promisc_set(pp, 1);
1784 mvneta_set_ucast_table(pp, rxq_def);
1785 mvneta_set_special_mcast_table(pp, rxq_def);
1786 mvneta_set_other_mcast_table(pp, rxq_def);
1788 /* Accept single Unicast */
1789 mvneta_rx_unicast_promisc_set(pp, 0);
1790 mvneta_set_ucast_table(pp, -1);
1791 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
1793 if (dev->flags & IFF_ALLMULTI) {
1794 /* Accept all multicast */
1795 mvneta_set_special_mcast_table(pp, rxq_def);
1796 mvneta_set_other_mcast_table(pp, rxq_def);
1798 /* Accept only initialized multicast */
1799 mvneta_set_special_mcast_table(pp, -1);
1800 mvneta_set_other_mcast_table(pp, -1);
1802 if (!netdev_mc_empty(dev)) {
1803 netdev_for_each_mc_addr(ha, dev) {
1804 mvneta_mcast_addr_set(pp, ha->addr,
1812 /* Interrupt handling - the callback for request_irq() */
1813 static irqreturn_t mvneta_isr(int irq, void *dev_id)
1815 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
1817 /* Mask all interrupts */
1818 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1820 napi_schedule(&pp->napi);
1826 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
1827 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
1828 * Bits 8 -15 of the cause Rx Tx register indicate that are received
1829 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
1830 * Each CPU has its own causeRxTx register
1832 static int mvneta_poll(struct napi_struct *napi, int budget)
1836 unsigned long flags;
1837 struct mvneta_port *pp = netdev_priv(napi->dev);
1839 if (!netif_running(pp->dev)) {
1840 napi_complete(napi);
1844 /* Read cause register */
1845 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) &
1846 MVNETA_RX_INTR_MASK(rxq_number);
1848 /* For the case where the last mvneta_poll did not process all
1851 cause_rx_tx |= pp->cause_rx_tx;
1852 if (rxq_number > 1) {
1853 while ((cause_rx_tx != 0) && (budget > 0)) {
1855 struct mvneta_rx_queue *rxq;
1856 /* get rx queue number from cause_rx_tx */
1857 rxq = mvneta_rx_policy(pp, cause_rx_tx);
1861 /* process the packet in that rx queue */
1862 count = mvneta_rx(pp, budget, rxq);
1866 /* set off the rx bit of the
1867 * corresponding bit in the cause rx
1868 * tx register, so that next iteration
1869 * will find the next rx queue where
1870 * packets are received on
1872 cause_rx_tx &= ~((1 << rxq->id) << 8);
1876 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
1882 napi_complete(napi);
1883 local_irq_save(flags);
1884 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1885 MVNETA_RX_INTR_MASK(rxq_number));
1886 local_irq_restore(flags);
1889 pp->cause_rx_tx = cause_rx_tx;
1893 /* tx done timer callback */
1894 static void mvneta_tx_done_timer_callback(unsigned long data)
1896 struct net_device *dev = (struct net_device *)data;
1897 struct mvneta_port *pp = netdev_priv(dev);
1898 int tx_done = 0, tx_todo = 0;
1900 if (!netif_running(dev))
1903 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
1905 tx_done = mvneta_tx_done_gbe(pp,
1906 (((1 << txq_number) - 1) &
1907 MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK),
1910 mvneta_add_tx_done_timer(pp);
1913 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
1914 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
1917 struct net_device *dev = pp->dev;
1920 for (i = 0; i < num; i++) {
1921 struct sk_buff *skb;
1922 struct mvneta_rx_desc *rx_desc;
1923 unsigned long phys_addr;
1925 skb = dev_alloc_skb(pp->pkt_size);
1927 netdev_err(dev, "%s:rxq %d, %d of %d buffs filled\n",
1928 __func__, rxq->id, i, num);
1932 rx_desc = rxq->descs + i;
1933 memset(rx_desc, 0, sizeof(struct mvneta_rx_desc));
1934 phys_addr = dma_map_single(dev->dev.parent, skb->head,
1935 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1937 if (unlikely(dma_mapping_error(dev->dev.parent, phys_addr))) {
1942 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)skb);
1945 /* Add this number of RX descriptors as non occupied (ready to
1948 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
1953 /* Free all packets pending transmit from all TXQs and reset TX port */
1954 static void mvneta_tx_reset(struct mvneta_port *pp)
1958 /* free the skb's in the hal tx ring */
1959 for (queue = 0; queue < txq_number; queue++)
1960 mvneta_txq_done_force(pp, &pp->txqs[queue]);
1962 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1963 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1966 static void mvneta_rx_reset(struct mvneta_port *pp)
1968 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1969 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1972 /* Rx/Tx queue initialization/cleanup methods */
1974 /* Create a specified RX queue */
1975 static int mvneta_rxq_init(struct mvneta_port *pp,
1976 struct mvneta_rx_queue *rxq)
1979 rxq->size = pp->rx_ring_size;
1981 /* Allocate memory for RX descriptors */
1982 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
1983 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
1984 &rxq->descs_phys, GFP_KERNEL);
1985 if (rxq->descs == NULL)
1988 BUG_ON(rxq->descs !=
1989 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
1991 rxq->last_desc = rxq->size - 1;
1993 /* Set Rx descriptors queue starting address */
1994 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
1995 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
1998 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2000 /* Set coalescing pkts and time */
2001 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2002 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2004 /* Fill RXQ with buffers from RX pool */
2005 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
2006 mvneta_rxq_bm_disable(pp, rxq);
2007 mvneta_rxq_fill(pp, rxq, rxq->size);
2012 /* Cleanup Rx queue */
2013 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2014 struct mvneta_rx_queue *rxq)
2016 mvneta_rxq_drop_pkts(pp, rxq);
2019 dma_free_coherent(pp->dev->dev.parent,
2020 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2026 rxq->next_desc_to_proc = 0;
2027 rxq->descs_phys = 0;
2030 /* Create and initialize a tx queue */
2031 static int mvneta_txq_init(struct mvneta_port *pp,
2032 struct mvneta_tx_queue *txq)
2034 txq->size = pp->tx_ring_size;
2036 /* Allocate memory for TX descriptors */
2037 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2038 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2039 &txq->descs_phys, GFP_KERNEL);
2040 if (txq->descs == NULL)
2043 /* Make sure descriptor address is cache line size aligned */
2044 BUG_ON(txq->descs !=
2045 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2047 txq->last_desc = txq->size - 1;
2049 /* Set maximum bandwidth for enabled TXQs */
2050 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2051 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2053 /* Set Tx descriptors queue starting address */
2054 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2055 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2057 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2058 if (txq->tx_skb == NULL) {
2059 dma_free_coherent(pp->dev->dev.parent,
2060 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2061 txq->descs, txq->descs_phys);
2064 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2069 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2070 static void mvneta_txq_deinit(struct mvneta_port *pp,
2071 struct mvneta_tx_queue *txq)
2076 dma_free_coherent(pp->dev->dev.parent,
2077 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2078 txq->descs, txq->descs_phys);
2082 txq->next_desc_to_proc = 0;
2083 txq->descs_phys = 0;
2085 /* Set minimum bandwidth for disabled TXQs */
2086 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2087 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2089 /* Set Tx descriptors queue starting address and size */
2090 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2091 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2094 /* Cleanup all Tx queues */
2095 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2099 for (queue = 0; queue < txq_number; queue++)
2100 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2103 /* Cleanup all Rx queues */
2104 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2108 for (queue = 0; queue < rxq_number; queue++)
2109 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2113 /* Init all Rx queues */
2114 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2118 for (queue = 0; queue < rxq_number; queue++) {
2119 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2121 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2123 mvneta_cleanup_rxqs(pp);
2131 /* Init all tx queues */
2132 static int mvneta_setup_txqs(struct mvneta_port *pp)
2136 for (queue = 0; queue < txq_number; queue++) {
2137 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2139 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2141 mvneta_cleanup_txqs(pp);
2149 static void mvneta_start_dev(struct mvneta_port *pp)
2151 mvneta_max_rx_size_set(pp, pp->pkt_size);
2152 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2154 /* start the Rx/Tx activity */
2155 mvneta_port_enable(pp);
2157 /* Enable polling on the port */
2158 napi_enable(&pp->napi);
2160 /* Unmask interrupts */
2161 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2162 MVNETA_RX_INTR_MASK(rxq_number));
2164 phy_start(pp->phy_dev);
2165 netif_tx_start_all_queues(pp->dev);
2168 static void mvneta_stop_dev(struct mvneta_port *pp)
2170 phy_stop(pp->phy_dev);
2172 napi_disable(&pp->napi);
2174 netif_carrier_off(pp->dev);
2176 mvneta_port_down(pp);
2177 netif_tx_stop_all_queues(pp->dev);
2179 /* Stop the port activity */
2180 mvneta_port_disable(pp);
2182 /* Clear all ethernet port interrupts */
2183 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2184 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2186 /* Mask all ethernet port interrupts */
2187 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2188 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2189 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2191 mvneta_tx_reset(pp);
2192 mvneta_rx_reset(pp);
2195 /* tx timeout callback - display a message and stop/start the network device */
2196 static void mvneta_tx_timeout(struct net_device *dev)
2198 struct mvneta_port *pp = netdev_priv(dev);
2200 netdev_info(dev, "tx timeout\n");
2201 mvneta_stop_dev(pp);
2202 mvneta_start_dev(pp);
2205 /* Return positive if MTU is valid */
2206 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2209 netdev_err(dev, "cannot change mtu to less than 68\n");
2213 /* 9676 == 9700 - 20 and rounding to 8 */
2215 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2219 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2220 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2221 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2222 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2228 /* Change the device mtu */
2229 static int mvneta_change_mtu(struct net_device *dev, int mtu)
2231 struct mvneta_port *pp = netdev_priv(dev);
2234 mtu = mvneta_check_mtu_valid(dev, mtu);
2240 if (!netif_running(dev))
2243 /* The interface is running, so we have to force a
2244 * reallocation of the RXQs
2246 mvneta_stop_dev(pp);
2248 mvneta_cleanup_txqs(pp);
2249 mvneta_cleanup_rxqs(pp);
2251 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2253 ret = mvneta_setup_rxqs(pp);
2255 netdev_err(pp->dev, "unable to setup rxqs after MTU change\n");
2259 mvneta_setup_txqs(pp);
2261 mvneta_start_dev(pp);
2267 /* Get mac address */
2268 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
2270 u32 mac_addr_l, mac_addr_h;
2272 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
2273 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
2274 addr[0] = (mac_addr_h >> 24) & 0xFF;
2275 addr[1] = (mac_addr_h >> 16) & 0xFF;
2276 addr[2] = (mac_addr_h >> 8) & 0xFF;
2277 addr[3] = mac_addr_h & 0xFF;
2278 addr[4] = (mac_addr_l >> 8) & 0xFF;
2279 addr[5] = mac_addr_l & 0xFF;
2282 /* Handle setting mac address */
2283 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2285 struct mvneta_port *pp = netdev_priv(dev);
2289 if (netif_running(dev))
2292 /* Remove previous address table entry */
2293 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2295 /* Set new addr in hw */
2296 mvneta_mac_addr_set(pp, mac, rxq_def);
2298 /* Set addr in the device */
2299 for (i = 0; i < ETH_ALEN; i++)
2300 dev->dev_addr[i] = mac[i];
2305 static void mvneta_adjust_link(struct net_device *ndev)
2307 struct mvneta_port *pp = netdev_priv(ndev);
2308 struct phy_device *phydev = pp->phy_dev;
2309 int status_change = 0;
2312 if ((pp->speed != phydev->speed) ||
2313 (pp->duplex != phydev->duplex)) {
2316 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2317 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2318 MVNETA_GMAC_CONFIG_GMII_SPEED |
2319 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
2320 MVNETA_GMAC_AN_SPEED_EN |
2321 MVNETA_GMAC_AN_DUPLEX_EN);
2324 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2326 if (phydev->speed == SPEED_1000)
2327 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
2329 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2331 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2333 pp->duplex = phydev->duplex;
2334 pp->speed = phydev->speed;
2338 if (phydev->link != pp->link) {
2339 if (!phydev->link) {
2344 pp->link = phydev->link;
2348 if (status_change) {
2350 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2351 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
2352 MVNETA_GMAC_FORCE_LINK_DOWN);
2353 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2355 netdev_info(pp->dev, "link up\n");
2357 mvneta_port_down(pp);
2358 netdev_info(pp->dev, "link down\n");
2363 static int mvneta_mdio_probe(struct mvneta_port *pp)
2365 struct phy_device *phy_dev;
2367 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2370 netdev_err(pp->dev, "could not find the PHY\n");
2374 phy_dev->supported &= PHY_GBIT_FEATURES;
2375 phy_dev->advertising = phy_dev->supported;
2377 pp->phy_dev = phy_dev;
2385 static void mvneta_mdio_remove(struct mvneta_port *pp)
2387 phy_disconnect(pp->phy_dev);
2391 static int mvneta_open(struct net_device *dev)
2393 struct mvneta_port *pp = netdev_priv(dev);
2396 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
2398 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2400 ret = mvneta_setup_rxqs(pp);
2404 ret = mvneta_setup_txqs(pp);
2406 goto err_cleanup_rxqs;
2408 /* Connect to port interrupt line */
2409 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
2410 MVNETA_DRIVER_NAME, pp);
2412 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
2413 goto err_cleanup_txqs;
2416 /* In default link is down */
2417 netif_carrier_off(pp->dev);
2419 ret = mvneta_mdio_probe(pp);
2421 netdev_err(dev, "cannot probe MDIO bus\n");
2425 mvneta_start_dev(pp);
2430 free_irq(pp->dev->irq, pp);
2432 mvneta_cleanup_txqs(pp);
2434 mvneta_cleanup_rxqs(pp);
2438 /* Stop the port, free port interrupt line */
2439 static int mvneta_stop(struct net_device *dev)
2441 struct mvneta_port *pp = netdev_priv(dev);
2443 mvneta_stop_dev(pp);
2444 mvneta_mdio_remove(pp);
2445 free_irq(dev->irq, pp);
2446 mvneta_cleanup_rxqs(pp);
2447 mvneta_cleanup_txqs(pp);
2448 del_timer(&pp->tx_done_timer);
2449 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
2454 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2456 struct mvneta_port *pp = netdev_priv(dev);
2462 ret = phy_mii_ioctl(pp->phy_dev, ifr, cmd);
2464 mvneta_adjust_link(dev);
2469 /* Ethtool methods */
2471 /* Get settings (phy address, speed) for ethtools */
2472 int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2474 struct mvneta_port *pp = netdev_priv(dev);
2479 return phy_ethtool_gset(pp->phy_dev, cmd);
2482 /* Set settings (phy address, speed) for ethtools */
2483 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2485 struct mvneta_port *pp = netdev_priv(dev);
2490 return phy_ethtool_sset(pp->phy_dev, cmd);
2493 /* Set interrupt coalescing for ethtools */
2494 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
2495 struct ethtool_coalesce *c)
2497 struct mvneta_port *pp = netdev_priv(dev);
2500 for (queue = 0; queue < rxq_number; queue++) {
2501 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2502 rxq->time_coal = c->rx_coalesce_usecs;
2503 rxq->pkts_coal = c->rx_max_coalesced_frames;
2504 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2505 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2508 for (queue = 0; queue < txq_number; queue++) {
2509 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2510 txq->done_pkts_coal = c->tx_max_coalesced_frames;
2511 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2517 /* get coalescing for ethtools */
2518 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
2519 struct ethtool_coalesce *c)
2521 struct mvneta_port *pp = netdev_priv(dev);
2523 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
2524 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
2526 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
2531 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
2532 struct ethtool_drvinfo *drvinfo)
2534 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
2535 sizeof(drvinfo->driver));
2536 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
2537 sizeof(drvinfo->version));
2538 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
2539 sizeof(drvinfo->bus_info));
2543 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
2544 struct ethtool_ringparam *ring)
2546 struct mvneta_port *pp = netdev_priv(netdev);
2548 ring->rx_max_pending = MVNETA_MAX_RXD;
2549 ring->tx_max_pending = MVNETA_MAX_TXD;
2550 ring->rx_pending = pp->rx_ring_size;
2551 ring->tx_pending = pp->tx_ring_size;
2554 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
2555 struct ethtool_ringparam *ring)
2557 struct mvneta_port *pp = netdev_priv(dev);
2559 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
2561 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
2562 ring->rx_pending : MVNETA_MAX_RXD;
2563 pp->tx_ring_size = ring->tx_pending < MVNETA_MAX_TXD ?
2564 ring->tx_pending : MVNETA_MAX_TXD;
2566 if (netif_running(dev)) {
2568 if (mvneta_open(dev)) {
2570 "error on opening device after ring param change\n");
2578 static const struct net_device_ops mvneta_netdev_ops = {
2579 .ndo_open = mvneta_open,
2580 .ndo_stop = mvneta_stop,
2581 .ndo_start_xmit = mvneta_tx,
2582 .ndo_set_rx_mode = mvneta_set_rx_mode,
2583 .ndo_set_mac_address = mvneta_set_mac_addr,
2584 .ndo_change_mtu = mvneta_change_mtu,
2585 .ndo_tx_timeout = mvneta_tx_timeout,
2586 .ndo_get_stats64 = mvneta_get_stats64,
2587 .ndo_do_ioctl = mvneta_ioctl,
2590 const struct ethtool_ops mvneta_eth_tool_ops = {
2591 .get_link = ethtool_op_get_link,
2592 .get_settings = mvneta_ethtool_get_settings,
2593 .set_settings = mvneta_ethtool_set_settings,
2594 .set_coalesce = mvneta_ethtool_set_coalesce,
2595 .get_coalesce = mvneta_ethtool_get_coalesce,
2596 .get_drvinfo = mvneta_ethtool_get_drvinfo,
2597 .get_ringparam = mvneta_ethtool_get_ringparam,
2598 .set_ringparam = mvneta_ethtool_set_ringparam,
2602 static int mvneta_init(struct mvneta_port *pp, int phy_addr)
2607 mvneta_port_disable(pp);
2609 /* Set port default values */
2610 mvneta_defaults_set(pp);
2612 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
2617 /* Initialize TX descriptor rings */
2618 for (queue = 0; queue < txq_number; queue++) {
2619 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2621 txq->size = pp->tx_ring_size;
2622 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
2625 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
2632 /* Create Rx descriptor rings */
2633 for (queue = 0; queue < rxq_number; queue++) {
2634 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2636 rxq->size = pp->rx_ring_size;
2637 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
2638 rxq->time_coal = MVNETA_RX_COAL_USEC;
2644 static void mvneta_deinit(struct mvneta_port *pp)
2650 /* platform glue : initialize decoding windows */
2651 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
2652 const struct mbus_dram_target_info *dram)
2658 for (i = 0; i < 6; i++) {
2659 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
2660 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
2663 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
2669 for (i = 0; i < dram->num_cs; i++) {
2670 const struct mbus_dram_window *cs = dram->cs + i;
2671 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
2672 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
2674 mvreg_write(pp, MVNETA_WIN_SIZE(i),
2675 (cs->size - 1) & 0xffff0000);
2677 win_enable &= ~(1 << i);
2678 win_protect |= 3 << (2 * i);
2681 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
2684 /* Power up the port */
2685 static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
2689 /* MAC Cause register should be cleared */
2690 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
2692 if (phy_mode == PHY_INTERFACE_MODE_SGMII)
2693 mvneta_port_sgmii_config(pp);
2695 mvneta_gmac_rgmii_set(pp, 1);
2697 /* Cancel Port Reset */
2698 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
2699 val &= ~MVNETA_GMAC2_PORT_RESET;
2700 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
2702 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
2703 MVNETA_GMAC2_PORT_RESET) != 0)
2707 /* Device initialization routine */
2708 static int mvneta_probe(struct platform_device *pdev)
2710 const struct mbus_dram_target_info *dram_target_info;
2711 struct device_node *dn = pdev->dev.of_node;
2712 struct device_node *phy_node;
2714 struct mvneta_port *pp;
2715 struct net_device *dev;
2716 const char *dt_mac_addr;
2717 char hw_mac_addr[ETH_ALEN];
2718 const char *mac_from;
2722 /* Our multiqueue support is not complete, so for now, only
2723 * allow the usage of the first RX queue
2726 dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def);
2730 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
2734 dev->irq = irq_of_parse_and_map(dn, 0);
2735 if (dev->irq == 0) {
2737 goto err_free_netdev;
2740 phy_node = of_parse_phandle(dn, "phy", 0);
2742 dev_err(&pdev->dev, "no associated PHY\n");
2747 phy_mode = of_get_phy_mode(dn);
2749 dev_err(&pdev->dev, "incorrect phy-mode\n");
2754 dev->tx_queue_len = MVNETA_MAX_TXD;
2755 dev->watchdog_timeo = 5 * HZ;
2756 dev->netdev_ops = &mvneta_netdev_ops;
2758 SET_ETHTOOL_OPS(dev, &mvneta_eth_tool_ops);
2760 pp = netdev_priv(dev);
2762 pp->weight = MVNETA_RX_POLL_WEIGHT;
2763 pp->phy_node = phy_node;
2764 pp->phy_interface = phy_mode;
2766 pp->clk = devm_clk_get(&pdev->dev, NULL);
2767 if (IS_ERR(pp->clk)) {
2768 err = PTR_ERR(pp->clk);
2772 clk_prepare_enable(pp->clk);
2774 pp->base = of_iomap(dn, 0);
2775 if (pp->base == NULL) {
2780 dt_mac_addr = of_get_mac_address(dn);
2781 if (dt_mac_addr && is_valid_ether_addr(dt_mac_addr)) {
2782 mac_from = "device tree";
2783 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
2785 mvneta_get_mac_addr(pp, hw_mac_addr);
2786 if (is_valid_ether_addr(hw_mac_addr)) {
2787 mac_from = "hardware";
2788 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
2790 mac_from = "random";
2791 eth_hw_addr_random(dev);
2795 pp->tx_done_timer.data = (unsigned long)dev;
2796 pp->tx_done_timer.function = mvneta_tx_done_timer_callback;
2797 init_timer(&pp->tx_done_timer);
2798 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
2800 pp->tx_ring_size = MVNETA_MAX_TXD;
2801 pp->rx_ring_size = MVNETA_MAX_RXD;
2804 SET_NETDEV_DEV(dev, &pdev->dev);
2806 err = mvneta_init(pp, phy_addr);
2808 dev_err(&pdev->dev, "can't init eth hal\n");
2811 mvneta_port_power_up(pp, phy_mode);
2813 dram_target_info = mv_mbus_dram_info();
2814 if (dram_target_info)
2815 mvneta_conf_mbus_windows(pp, dram_target_info);
2817 netif_napi_add(dev, &pp->napi, mvneta_poll, pp->weight);
2819 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2820 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2821 dev->vlan_features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2822 dev->priv_flags |= IFF_UNICAST_FLT;
2824 err = register_netdev(dev);
2826 dev_err(&pdev->dev, "failed to register\n");
2830 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
2833 platform_set_drvdata(pdev, pp->dev);
2842 clk_disable_unprepare(pp->clk);
2844 irq_dispose_mapping(dev->irq);
2850 /* Device removal routine */
2851 static int mvneta_remove(struct platform_device *pdev)
2853 struct net_device *dev = platform_get_drvdata(pdev);
2854 struct mvneta_port *pp = netdev_priv(dev);
2856 unregister_netdev(dev);
2858 clk_disable_unprepare(pp->clk);
2860 irq_dispose_mapping(dev->irq);
2866 static const struct of_device_id mvneta_match[] = {
2867 { .compatible = "marvell,armada-370-neta" },
2870 MODULE_DEVICE_TABLE(of, mvneta_match);
2872 static struct platform_driver mvneta_driver = {
2873 .probe = mvneta_probe,
2874 .remove = mvneta_remove,
2876 .name = MVNETA_DRIVER_NAME,
2877 .of_match_table = mvneta_match,
2881 module_platform_driver(mvneta_driver);
2883 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
2884 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
2885 MODULE_LICENSE("GPL");
2887 module_param(rxq_number, int, S_IRUGO);
2888 module_param(txq_number, int, S_IRUGO);
2890 module_param(rxq_def, int, S_IRUGO);