2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/if_vlan.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_net.h>
32 #include <linux/of_address.h>
33 #include <linux/phy.h>
34 #include <linux/clk.h>
35 #include <linux/cpu.h>
38 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
39 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
40 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
41 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
42 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
43 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
44 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
45 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
46 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
47 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
48 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
49 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
50 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
51 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
52 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
53 #define MVNETA_PORT_RX_RESET 0x1cc0
54 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
55 #define MVNETA_PHY_ADDR 0x2000
56 #define MVNETA_PHY_ADDR_MASK 0x1f
57 #define MVNETA_MBUS_RETRY 0x2010
58 #define MVNETA_UNIT_INTR_CAUSE 0x2080
59 #define MVNETA_UNIT_CONTROL 0x20B0
60 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
61 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
62 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
63 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
64 #define MVNETA_BASE_ADDR_ENABLE 0x2290
65 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
66 #define MVNETA_PORT_CONFIG 0x2400
67 #define MVNETA_UNI_PROMISC_MODE BIT(0)
68 #define MVNETA_DEF_RXQ(q) ((q) << 1)
69 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
70 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
71 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
72 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
73 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
74 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
75 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
76 MVNETA_DEF_RXQ_ARP(q) | \
77 MVNETA_DEF_RXQ_TCP(q) | \
78 MVNETA_DEF_RXQ_UDP(q) | \
79 MVNETA_DEF_RXQ_BPDU(q) | \
80 MVNETA_TX_UNSET_ERR_SUM | \
81 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
82 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
83 #define MVNETA_MAC_ADDR_LOW 0x2414
84 #define MVNETA_MAC_ADDR_HIGH 0x2418
85 #define MVNETA_SDMA_CONFIG 0x241c
86 #define MVNETA_SDMA_BRST_SIZE_16 4
87 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
88 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
89 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
90 #define MVNETA_DESC_SWAP BIT(6)
91 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
92 #define MVNETA_PORT_STATUS 0x2444
93 #define MVNETA_TX_IN_PRGRS BIT(1)
94 #define MVNETA_TX_FIFO_EMPTY BIT(8)
95 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
96 #define MVNETA_SERDES_CFG 0x24A0
97 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
98 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
99 #define MVNETA_TYPE_PRIO 0x24bc
100 #define MVNETA_FORCE_UNI BIT(21)
101 #define MVNETA_TXQ_CMD_1 0x24e4
102 #define MVNETA_TXQ_CMD 0x2448
103 #define MVNETA_TXQ_DISABLE_SHIFT 8
104 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
105 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
106 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
107 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
108 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
109 #define MVNETA_ACC_MODE 0x2500
110 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
111 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
112 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
113 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
114 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
115 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
117 /* Exception Interrupt Port/Queue Cause register
119 * Their behavior depend of the mapping done using the PCPX2Q
120 * registers. For a given CPU if the bit associated to a queue is not
121 * set, then for the register a read from this CPU will always return
122 * 0 and a write won't do anything
125 #define MVNETA_INTR_NEW_CAUSE 0x25a0
126 #define MVNETA_INTR_NEW_MASK 0x25a4
128 /* bits 0..7 = TXQ SENT, one bit per queue.
129 * bits 8..15 = RXQ OCCUP, one bit per queue.
130 * bits 16..23 = RXQ FREE, one bit per queue.
131 * bit 29 = OLD_REG_SUM, see old reg ?
132 * bit 30 = TX_ERR_SUM, one bit for 4 ports
133 * bit 31 = MISC_SUM, one bit for 4 ports
135 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
136 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
137 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
138 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
139 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
141 #define MVNETA_INTR_OLD_CAUSE 0x25a8
142 #define MVNETA_INTR_OLD_MASK 0x25ac
144 /* Data Path Port/Queue Cause Register */
145 #define MVNETA_INTR_MISC_CAUSE 0x25b0
146 #define MVNETA_INTR_MISC_MASK 0x25b4
148 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
149 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
150 #define MVNETA_CAUSE_PTP BIT(4)
152 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
153 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
154 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
155 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
156 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
157 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
158 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
159 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
161 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
162 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
163 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
165 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
166 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
167 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
169 #define MVNETA_INTR_ENABLE 0x25b8
170 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
171 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
173 #define MVNETA_RXQ_CMD 0x2680
174 #define MVNETA_RXQ_DISABLE_SHIFT 8
175 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
176 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
177 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
178 #define MVNETA_GMAC_CTRL_0 0x2c00
179 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
180 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
181 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
182 #define MVNETA_GMAC_CTRL_2 0x2c08
183 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
184 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
185 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
186 #define MVNETA_GMAC2_PORT_RESET BIT(6)
187 #define MVNETA_GMAC_STATUS 0x2c10
188 #define MVNETA_GMAC_LINK_UP BIT(0)
189 #define MVNETA_GMAC_SPEED_1000 BIT(1)
190 #define MVNETA_GMAC_SPEED_100 BIT(2)
191 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
192 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
193 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
194 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
195 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
196 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
197 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
198 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
199 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
200 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
201 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
202 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
203 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
204 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
205 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
206 #define MVNETA_MIB_COUNTERS_BASE 0x3000
207 #define MVNETA_MIB_LATE_COLLISION 0x7c
208 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
209 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
210 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
211 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
212 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
213 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
214 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
215 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
216 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
217 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
218 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
219 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
220 #define MVNETA_PORT_TX_RESET 0x3cf0
221 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
222 #define MVNETA_TX_MTU 0x3e0c
223 #define MVNETA_TX_TOKEN_SIZE 0x3e14
224 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
225 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
226 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
228 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
230 /* Descriptor ring Macros */
231 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
232 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
234 /* Various constants */
237 #define MVNETA_TXDONE_COAL_PKTS 1
238 #define MVNETA_RX_COAL_PKTS 32
239 #define MVNETA_RX_COAL_USEC 100
241 /* The two bytes Marvell header. Either contains a special value used
242 * by Marvell switches when a specific hardware mode is enabled (not
243 * supported by this driver) or is filled automatically by zeroes on
244 * the RX side. Those two bytes being at the front of the Ethernet
245 * header, they allow to have the IP header aligned on a 4 bytes
246 * boundary automatically: the hardware skips those two bytes on its
249 #define MVNETA_MH_SIZE 2
251 #define MVNETA_VLAN_TAG_LEN 4
253 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
254 #define MVNETA_TX_CSUM_DEF_SIZE 1600
255 #define MVNETA_TX_CSUM_MAX_SIZE 9800
256 #define MVNETA_ACC_MODE_EXT 1
258 /* Timeout constants */
259 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
260 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
261 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
263 #define MVNETA_TX_MTU_MAX 0x3ffff
265 /* The RSS lookup table actually has 256 entries but we do not use
268 #define MVNETA_RSS_LU_TABLE_SIZE 1
270 /* TSO header size */
271 #define TSO_HEADER_SIZE 128
273 /* Max number of Rx descriptors */
274 #define MVNETA_MAX_RXD 128
276 /* Max number of Tx descriptors */
277 #define MVNETA_MAX_TXD 532
279 /* Max number of allowed TCP segments for software TSO */
280 #define MVNETA_MAX_TSO_SEGS 100
282 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
284 /* descriptor aligned size */
285 #define MVNETA_DESC_ALIGNED_SIZE 32
287 #define MVNETA_RX_PKT_SIZE(mtu) \
288 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
289 ETH_HLEN + ETH_FCS_LEN, \
290 MVNETA_CPU_D_CACHE_LINE_SIZE)
292 #define IS_TSO_HEADER(txq, addr) \
293 ((addr >= txq->tso_hdrs_phys) && \
294 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
296 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
298 struct mvneta_statistic {
299 unsigned short offset;
301 const char name[ETH_GSTRING_LEN];
307 static const struct mvneta_statistic mvneta_statistics[] = {
308 { 0x3000, T_REG_64, "good_octets_received", },
309 { 0x3010, T_REG_32, "good_frames_received", },
310 { 0x3008, T_REG_32, "bad_octets_received", },
311 { 0x3014, T_REG_32, "bad_frames_received", },
312 { 0x3018, T_REG_32, "broadcast_frames_received", },
313 { 0x301c, T_REG_32, "multicast_frames_received", },
314 { 0x3050, T_REG_32, "unrec_mac_control_received", },
315 { 0x3058, T_REG_32, "good_fc_received", },
316 { 0x305c, T_REG_32, "bad_fc_received", },
317 { 0x3060, T_REG_32, "undersize_received", },
318 { 0x3064, T_REG_32, "fragments_received", },
319 { 0x3068, T_REG_32, "oversize_received", },
320 { 0x306c, T_REG_32, "jabber_received", },
321 { 0x3070, T_REG_32, "mac_receive_error", },
322 { 0x3074, T_REG_32, "bad_crc_event", },
323 { 0x3078, T_REG_32, "collision", },
324 { 0x307c, T_REG_32, "late_collision", },
325 { 0x2484, T_REG_32, "rx_discard", },
326 { 0x2488, T_REG_32, "rx_overrun", },
327 { 0x3020, T_REG_32, "frames_64_octets", },
328 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
329 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
330 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
331 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
332 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
333 { 0x3038, T_REG_64, "good_octets_sent", },
334 { 0x3040, T_REG_32, "good_frames_sent", },
335 { 0x3044, T_REG_32, "excessive_collision", },
336 { 0x3048, T_REG_32, "multicast_frames_sent", },
337 { 0x304c, T_REG_32, "broadcast_frames_sent", },
338 { 0x3054, T_REG_32, "fc_sent", },
339 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
342 struct mvneta_pcpu_stats {
343 struct u64_stats_sync syncp;
350 struct mvneta_pcpu_port {
351 /* Pointer to the shared port */
352 struct mvneta_port *pp;
354 /* Pointer to the CPU-local NAPI struct */
355 struct napi_struct napi;
357 /* Cause of the previous interrupt */
362 struct mvneta_pcpu_port __percpu *ports;
363 struct mvneta_pcpu_stats __percpu *stats;
366 unsigned int frag_size;
368 struct mvneta_rx_queue *rxqs;
369 struct mvneta_tx_queue *txqs;
370 struct net_device *dev;
371 struct notifier_block cpu_notifier;
380 struct mii_bus *mii_bus;
381 struct phy_device *phy_dev;
382 phy_interface_t phy_interface;
383 struct device_node *phy_node;
387 unsigned int tx_csum_limit;
388 unsigned int use_inband_status:1;
390 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
392 u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
395 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
396 * layout of the transmit and reception DMA descriptors, and their
397 * layout is therefore defined by the hardware design
400 #define MVNETA_TX_L3_OFF_SHIFT 0
401 #define MVNETA_TX_IP_HLEN_SHIFT 8
402 #define MVNETA_TX_L4_UDP BIT(16)
403 #define MVNETA_TX_L3_IP6 BIT(17)
404 #define MVNETA_TXD_IP_CSUM BIT(18)
405 #define MVNETA_TXD_Z_PAD BIT(19)
406 #define MVNETA_TXD_L_DESC BIT(20)
407 #define MVNETA_TXD_F_DESC BIT(21)
408 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
409 MVNETA_TXD_L_DESC | \
411 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
412 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
414 #define MVNETA_RXD_ERR_CRC 0x0
415 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
416 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
417 #define MVNETA_RXD_ERR_LEN BIT(18)
418 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
419 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
420 #define MVNETA_RXD_L3_IP4 BIT(25)
421 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
422 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
424 #if defined(__LITTLE_ENDIAN)
425 struct mvneta_tx_desc {
426 u32 command; /* Options used by HW for packet transmitting.*/
427 u16 reserverd1; /* csum_l4 (for future use) */
428 u16 data_size; /* Data size of transmitted packet in bytes */
429 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
430 u32 reserved2; /* hw_cmd - (for future use, PMT) */
431 u32 reserved3[4]; /* Reserved - (for future use) */
434 struct mvneta_rx_desc {
435 u32 status; /* Info about received packet */
436 u16 reserved1; /* pnc_info - (for future use, PnC) */
437 u16 data_size; /* Size of received packet in bytes */
439 u32 buf_phys_addr; /* Physical address of the buffer */
440 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
442 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
443 u16 reserved3; /* prefetch_cmd, for future use */
444 u16 reserved4; /* csum_l4 - (for future use, PnC) */
446 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
447 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
450 struct mvneta_tx_desc {
451 u16 data_size; /* Data size of transmitted packet in bytes */
452 u16 reserverd1; /* csum_l4 (for future use) */
453 u32 command; /* Options used by HW for packet transmitting.*/
454 u32 reserved2; /* hw_cmd - (for future use, PMT) */
455 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
456 u32 reserved3[4]; /* Reserved - (for future use) */
459 struct mvneta_rx_desc {
460 u16 data_size; /* Size of received packet in bytes */
461 u16 reserved1; /* pnc_info - (for future use, PnC) */
462 u32 status; /* Info about received packet */
464 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
465 u32 buf_phys_addr; /* Physical address of the buffer */
467 u16 reserved4; /* csum_l4 - (for future use, PnC) */
468 u16 reserved3; /* prefetch_cmd, for future use */
469 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
471 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
472 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
476 struct mvneta_tx_queue {
477 /* Number of this TX queue, in the range 0-7 */
480 /* Number of TX DMA descriptors in the descriptor ring */
483 /* Number of currently used TX DMA descriptor in the
487 int tx_stop_threshold;
488 int tx_wake_threshold;
490 /* Array of transmitted skb */
491 struct sk_buff **tx_skb;
493 /* Index of last TX DMA descriptor that was inserted */
496 /* Index of the TX DMA descriptor to be cleaned up */
501 /* Virtual address of the TX DMA descriptors array */
502 struct mvneta_tx_desc *descs;
504 /* DMA address of the TX DMA descriptors array */
505 dma_addr_t descs_phys;
507 /* Index of the last TX DMA descriptor */
510 /* Index of the next TX DMA descriptor to process */
511 int next_desc_to_proc;
513 /* DMA buffers for TSO headers */
516 /* DMA address of TSO headers */
517 dma_addr_t tso_hdrs_phys;
519 /* Affinity mask for CPUs*/
520 cpumask_t affinity_mask;
523 struct mvneta_rx_queue {
524 /* rx queue number, in the range 0-7 */
527 /* num of rx descriptors in the rx descriptor ring */
530 /* counter of times when mvneta_refill() failed */
536 /* Virtual address of the RX DMA descriptors array */
537 struct mvneta_rx_desc *descs;
539 /* DMA address of the RX DMA descriptors array */
540 dma_addr_t descs_phys;
542 /* Index of the last RX DMA descriptor */
545 /* Index of the next RX DMA descriptor to process */
546 int next_desc_to_proc;
549 /* The hardware supports eight (8) rx queues, but we are only allowing
550 * the first one to be used. Therefore, let's just allocate one queue.
552 static int rxq_number = 8;
553 static int txq_number = 8;
557 static int rx_copybreak __read_mostly = 256;
559 #define MVNETA_DRIVER_NAME "mvneta"
560 #define MVNETA_DRIVER_VERSION "1.0"
562 /* Utility/helper methods */
564 /* Write helper method */
565 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
567 writel(data, pp->base + offset);
570 /* Read helper method */
571 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
573 return readl(pp->base + offset);
576 /* Increment txq get counter */
577 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
579 txq->txq_get_index++;
580 if (txq->txq_get_index == txq->size)
581 txq->txq_get_index = 0;
584 /* Increment txq put counter */
585 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
587 txq->txq_put_index++;
588 if (txq->txq_put_index == txq->size)
589 txq->txq_put_index = 0;
593 /* Clear all MIB counters */
594 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
599 /* Perform dummy reads from MIB counters */
600 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
601 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
602 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
603 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
606 /* Get System Network Statistics */
607 struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
608 struct rtnl_link_stats64 *stats)
610 struct mvneta_port *pp = netdev_priv(dev);
614 for_each_possible_cpu(cpu) {
615 struct mvneta_pcpu_stats *cpu_stats;
621 cpu_stats = per_cpu_ptr(pp->stats, cpu);
623 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
624 rx_packets = cpu_stats->rx_packets;
625 rx_bytes = cpu_stats->rx_bytes;
626 tx_packets = cpu_stats->tx_packets;
627 tx_bytes = cpu_stats->tx_bytes;
628 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
630 stats->rx_packets += rx_packets;
631 stats->rx_bytes += rx_bytes;
632 stats->tx_packets += tx_packets;
633 stats->tx_bytes += tx_bytes;
636 stats->rx_errors = dev->stats.rx_errors;
637 stats->rx_dropped = dev->stats.rx_dropped;
639 stats->tx_dropped = dev->stats.tx_dropped;
644 /* Rx descriptors helper methods */
646 /* Checks whether the RX descriptor having this status is both the first
647 * and the last descriptor for the RX packet. Each RX packet is currently
648 * received through a single RX descriptor, so not having each RX
649 * descriptor with its first and last bits set is an error
651 static int mvneta_rxq_desc_is_first_last(u32 status)
653 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
654 MVNETA_RXD_FIRST_LAST_DESC;
657 /* Add number of descriptors ready to receive new packets */
658 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
659 struct mvneta_rx_queue *rxq,
662 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
665 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
666 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
667 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
668 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
669 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
672 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
673 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
676 /* Get number of RX descriptors occupied by received packets */
677 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
678 struct mvneta_rx_queue *rxq)
682 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
683 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
686 /* Update num of rx desc called upon return from rx path or
687 * from mvneta_rxq_drop_pkts().
689 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
690 struct mvneta_rx_queue *rxq,
691 int rx_done, int rx_filled)
695 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
697 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
698 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
702 /* Only 255 descriptors can be added at once */
703 while ((rx_done > 0) || (rx_filled > 0)) {
704 if (rx_done <= 0xff) {
711 if (rx_filled <= 0xff) {
712 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
715 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
718 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
722 /* Get pointer to next RX descriptor to be processed by SW */
723 static struct mvneta_rx_desc *
724 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
726 int rx_desc = rxq->next_desc_to_proc;
728 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
729 prefetch(rxq->descs + rxq->next_desc_to_proc);
730 return rxq->descs + rx_desc;
733 /* Change maximum receive size of the port. */
734 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
738 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
739 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
740 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
741 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
742 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
746 /* Set rx queue offset */
747 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
748 struct mvneta_rx_queue *rxq,
753 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
754 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
757 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
758 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
762 /* Tx descriptors helper methods */
764 /* Update HW with number of TX descriptors to be sent */
765 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
766 struct mvneta_tx_queue *txq,
771 /* Only 255 descriptors can be added at once ; Assume caller
772 * process TX desriptors in quanta less than 256
775 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
778 /* Get pointer to next TX descriptor to be processed (send) by HW */
779 static struct mvneta_tx_desc *
780 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
782 int tx_desc = txq->next_desc_to_proc;
784 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
785 return txq->descs + tx_desc;
788 /* Release the last allocated TX descriptor. Useful to handle DMA
789 * mapping failures in the TX path.
791 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
793 if (txq->next_desc_to_proc == 0)
794 txq->next_desc_to_proc = txq->last_desc - 1;
796 txq->next_desc_to_proc--;
799 /* Set rxq buf size */
800 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
801 struct mvneta_rx_queue *rxq,
806 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
808 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
809 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
811 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
814 /* Disable buffer management (BM) */
815 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
816 struct mvneta_rx_queue *rxq)
820 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
821 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
822 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
825 /* Start the Ethernet port RX and TX activity */
826 static void mvneta_port_up(struct mvneta_port *pp)
831 /* Enable all initialized TXs. */
833 for (queue = 0; queue < txq_number; queue++) {
834 struct mvneta_tx_queue *txq = &pp->txqs[queue];
835 if (txq->descs != NULL)
836 q_map |= (1 << queue);
838 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
840 /* Enable all initialized RXQs. */
841 for (queue = 0; queue < rxq_number; queue++) {
842 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
844 if (rxq->descs != NULL)
845 q_map |= (1 << queue);
847 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
850 /* Stop the Ethernet port activity */
851 static void mvneta_port_down(struct mvneta_port *pp)
856 /* Stop Rx port activity. Check port Rx activity. */
857 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
859 /* Issue stop command for active channels only */
861 mvreg_write(pp, MVNETA_RXQ_CMD,
862 val << MVNETA_RXQ_DISABLE_SHIFT);
864 /* Wait for all Rx activity to terminate. */
867 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
869 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
875 val = mvreg_read(pp, MVNETA_RXQ_CMD);
876 } while (val & 0xff);
878 /* Stop Tx port activity. Check port Tx activity. Issue stop
879 * command for active channels only
881 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
884 mvreg_write(pp, MVNETA_TXQ_CMD,
885 (val << MVNETA_TXQ_DISABLE_SHIFT));
887 /* Wait for all Tx activity to terminate. */
890 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
892 "TIMEOUT for TX stopped status=0x%08x\n",
898 /* Check TX Command reg that all Txqs are stopped */
899 val = mvreg_read(pp, MVNETA_TXQ_CMD);
901 } while (val & 0xff);
903 /* Double check to verify that TX FIFO is empty */
906 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
908 "TX FIFO empty timeout status=0x08%x\n",
914 val = mvreg_read(pp, MVNETA_PORT_STATUS);
915 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
916 (val & MVNETA_TX_IN_PRGRS));
921 /* Enable the port by setting the port enable bit of the MAC control register */
922 static void mvneta_port_enable(struct mvneta_port *pp)
927 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
928 val |= MVNETA_GMAC0_PORT_ENABLE;
929 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
932 /* Disable the port and wait for about 200 usec before retuning */
933 static void mvneta_port_disable(struct mvneta_port *pp)
937 /* Reset the Enable bit in the Serial Control Register */
938 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
939 val &= ~MVNETA_GMAC0_PORT_ENABLE;
940 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
945 /* Multicast tables methods */
947 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
948 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
956 val = 0x1 | (queue << 1);
957 val |= (val << 24) | (val << 16) | (val << 8);
960 for (offset = 0; offset <= 0xc; offset += 4)
961 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
964 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
965 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
973 val = 0x1 | (queue << 1);
974 val |= (val << 24) | (val << 16) | (val << 8);
977 for (offset = 0; offset <= 0xfc; offset += 4)
978 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
982 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
983 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
989 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
992 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
993 val = 0x1 | (queue << 1);
994 val |= (val << 24) | (val << 16) | (val << 8);
997 for (offset = 0; offset <= 0xfc; offset += 4)
998 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1001 static void mvneta_set_autoneg(struct mvneta_port *pp, int enable)
1006 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1007 val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
1008 MVNETA_GMAC_FORCE_LINK_DOWN |
1009 MVNETA_GMAC_AN_FLOW_CTRL_EN);
1010 val |= MVNETA_GMAC_INBAND_AN_ENABLE |
1011 MVNETA_GMAC_AN_SPEED_EN |
1012 MVNETA_GMAC_AN_DUPLEX_EN;
1013 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1015 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1016 val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
1017 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1019 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1020 val |= MVNETA_GMAC2_INBAND_AN_ENABLE;
1021 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
1023 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1024 val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
1025 MVNETA_GMAC_AN_SPEED_EN |
1026 MVNETA_GMAC_AN_DUPLEX_EN);
1027 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1029 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1030 val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
1031 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1033 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1034 val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE;
1035 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
1039 /* This method sets defaults to the NETA port:
1040 * Clears interrupt Cause and Mask registers.
1041 * Clears all MAC tables.
1042 * Sets defaults to all registers.
1043 * Resets RX and TX descriptor rings.
1045 * This method can be called after mvneta_port_down() to return the port
1046 * settings to defaults.
1048 static void mvneta_defaults_set(struct mvneta_port *pp)
1053 int max_cpu = num_present_cpus();
1055 /* Clear all Cause registers */
1056 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1057 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1058 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1060 /* Mask all interrupts */
1061 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1062 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1063 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1064 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1066 /* Enable MBUS Retry bit16 */
1067 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1069 /* Set CPU queue access map. CPUs are assigned to the RX and
1070 * TX queues modulo their number. If there is only one TX
1071 * queue then it is assigned to the CPU associated to the
1074 for_each_present_cpu(cpu) {
1075 int rxq_map = 0, txq_map = 0;
1078 for (rxq = 0; rxq < rxq_number; rxq++)
1079 if ((rxq % max_cpu) == cpu)
1080 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1082 for (txq = 0; txq < txq_number; txq++)
1083 if ((txq % max_cpu) == cpu)
1084 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1086 /* With only one TX queue we configure a special case
1087 * which will allow to get all the irq on a single
1090 if (txq_number == 1)
1091 txq_map = (cpu == pp->rxq_def) ?
1092 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1094 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1097 /* Reset RX and TX DMAs */
1098 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1099 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1101 /* Disable Legacy WRR, Disable EJP, Release from reset */
1102 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1103 for (queue = 0; queue < txq_number; queue++) {
1104 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1105 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1108 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1109 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1111 /* Set Port Acceleration Mode */
1112 val = MVNETA_ACC_MODE_EXT;
1113 mvreg_write(pp, MVNETA_ACC_MODE, val);
1115 /* Update val of portCfg register accordingly with all RxQueue types */
1116 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1117 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1120 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1121 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1123 /* Build PORT_SDMA_CONFIG_REG */
1126 /* Default burst size */
1127 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1128 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1129 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1131 #if defined(__BIG_ENDIAN)
1132 val |= MVNETA_DESC_SWAP;
1135 /* Assign port SDMA configuration */
1136 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1138 /* Disable PHY polling in hardware, since we're using the
1139 * kernel phylib to do this.
1141 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1142 val &= ~MVNETA_PHY_POLLING_ENABLE;
1143 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1145 mvneta_set_autoneg(pp, pp->use_inband_status);
1146 mvneta_set_ucast_table(pp, -1);
1147 mvneta_set_special_mcast_table(pp, -1);
1148 mvneta_set_other_mcast_table(pp, -1);
1150 /* Set port interrupt enable register - default enable all */
1151 mvreg_write(pp, MVNETA_INTR_ENABLE,
1152 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1153 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1155 mvneta_mib_counters_clear(pp);
1158 /* Set max sizes for tx queues */
1159 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1165 mtu = max_tx_size * 8;
1166 if (mtu > MVNETA_TX_MTU_MAX)
1167 mtu = MVNETA_TX_MTU_MAX;
1170 val = mvreg_read(pp, MVNETA_TX_MTU);
1171 val &= ~MVNETA_TX_MTU_MAX;
1173 mvreg_write(pp, MVNETA_TX_MTU, val);
1175 /* TX token size and all TXQs token size must be larger that MTU */
1176 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1178 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1181 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1183 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1185 for (queue = 0; queue < txq_number; queue++) {
1186 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1188 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1191 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1193 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1198 /* Set unicast address */
1199 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1202 unsigned int unicast_reg;
1203 unsigned int tbl_offset;
1204 unsigned int reg_offset;
1206 /* Locate the Unicast table entry */
1207 last_nibble = (0xf & last_nibble);
1209 /* offset from unicast tbl base */
1210 tbl_offset = (last_nibble / 4) * 4;
1212 /* offset within the above reg */
1213 reg_offset = last_nibble % 4;
1215 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1218 /* Clear accepts frame bit at specified unicast DA tbl entry */
1219 unicast_reg &= ~(0xff << (8 * reg_offset));
1221 unicast_reg &= ~(0xff << (8 * reg_offset));
1222 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1225 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1228 /* Set mac address */
1229 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1236 mac_l = (addr[4] << 8) | (addr[5]);
1237 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1238 (addr[2] << 8) | (addr[3] << 0);
1240 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1241 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1244 /* Accept frames of this address */
1245 mvneta_set_ucast_addr(pp, addr[5], queue);
1248 /* Set the number of packets that will be received before RX interrupt
1249 * will be generated by HW.
1251 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1252 struct mvneta_rx_queue *rxq, u32 value)
1254 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1255 value | MVNETA_RXQ_NON_OCCUPIED(0));
1256 rxq->pkts_coal = value;
1259 /* Set the time delay in usec before RX interrupt will be generated by
1262 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1263 struct mvneta_rx_queue *rxq, u32 value)
1266 unsigned long clk_rate;
1268 clk_rate = clk_get_rate(pp->clk);
1269 val = (clk_rate / 1000000) * value;
1271 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1272 rxq->time_coal = value;
1275 /* Set threshold for TX_DONE pkts coalescing */
1276 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1277 struct mvneta_tx_queue *txq, u32 value)
1281 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1283 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1284 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1286 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1288 txq->done_pkts_coal = value;
1291 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1292 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1293 u32 phys_addr, u32 cookie)
1295 rx_desc->buf_cookie = cookie;
1296 rx_desc->buf_phys_addr = phys_addr;
1299 /* Decrement sent descriptors counter */
1300 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1301 struct mvneta_tx_queue *txq,
1306 /* Only 255 TX descriptors can be updated at once */
1307 while (sent_desc > 0xff) {
1308 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1309 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1310 sent_desc = sent_desc - 0xff;
1313 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1314 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1317 /* Get number of TX descriptors already sent by HW */
1318 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1319 struct mvneta_tx_queue *txq)
1324 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1325 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1326 MVNETA_TXQ_SENT_DESC_SHIFT;
1331 /* Get number of sent descriptors and decrement counter.
1332 * The number of sent descriptors is returned.
1334 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1335 struct mvneta_tx_queue *txq)
1339 /* Get number of sent descriptors */
1340 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1342 /* Decrement sent descriptors counter */
1344 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1349 /* Set TXQ descriptors fields relevant for CSUM calculation */
1350 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1351 int ip_hdr_len, int l4_proto)
1355 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1356 * G_L4_chk, L4_type; required only for checksum
1359 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1360 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1362 if (l3_proto == htons(ETH_P_IP))
1363 command |= MVNETA_TXD_IP_CSUM;
1365 command |= MVNETA_TX_L3_IP6;
1367 if (l4_proto == IPPROTO_TCP)
1368 command |= MVNETA_TX_L4_CSUM_FULL;
1369 else if (l4_proto == IPPROTO_UDP)
1370 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1372 command |= MVNETA_TX_L4_CSUM_NOT;
1378 /* Display more error info */
1379 static void mvneta_rx_error(struct mvneta_port *pp,
1380 struct mvneta_rx_desc *rx_desc)
1382 u32 status = rx_desc->status;
1384 if (!mvneta_rxq_desc_is_first_last(status)) {
1386 "bad rx status %08x (buffer oversize), size=%d\n",
1387 status, rx_desc->data_size);
1391 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1392 case MVNETA_RXD_ERR_CRC:
1393 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1394 status, rx_desc->data_size);
1396 case MVNETA_RXD_ERR_OVERRUN:
1397 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1398 status, rx_desc->data_size);
1400 case MVNETA_RXD_ERR_LEN:
1401 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1402 status, rx_desc->data_size);
1404 case MVNETA_RXD_ERR_RESOURCE:
1405 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1406 status, rx_desc->data_size);
1411 /* Handle RX checksum offload based on the descriptor's status */
1412 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1413 struct sk_buff *skb)
1415 if ((status & MVNETA_RXD_L3_IP4) &&
1416 (status & MVNETA_RXD_L4_CSUM_OK)) {
1418 skb->ip_summed = CHECKSUM_UNNECESSARY;
1422 skb->ip_summed = CHECKSUM_NONE;
1425 /* Return tx queue pointer (find last set bit) according to <cause> returned
1426 * form tx_done reg. <cause> must not be null. The return value is always a
1427 * valid queue for matching the first one found in <cause>.
1429 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1432 int queue = fls(cause) - 1;
1434 return &pp->txqs[queue];
1437 /* Free tx queue skbuffs */
1438 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1439 struct mvneta_tx_queue *txq, int num)
1443 for (i = 0; i < num; i++) {
1444 struct mvneta_tx_desc *tx_desc = txq->descs +
1446 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1448 mvneta_txq_inc_get(txq);
1450 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1451 dma_unmap_single(pp->dev->dev.parent,
1452 tx_desc->buf_phys_addr,
1453 tx_desc->data_size, DMA_TO_DEVICE);
1456 dev_kfree_skb_any(skb);
1460 /* Handle end of transmission */
1461 static void mvneta_txq_done(struct mvneta_port *pp,
1462 struct mvneta_tx_queue *txq)
1464 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1467 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1471 mvneta_txq_bufs_free(pp, txq, tx_done);
1473 txq->count -= tx_done;
1475 if (netif_tx_queue_stopped(nq)) {
1476 if (txq->count <= txq->tx_wake_threshold)
1477 netif_tx_wake_queue(nq);
1481 static void *mvneta_frag_alloc(const struct mvneta_port *pp)
1483 if (likely(pp->frag_size <= PAGE_SIZE))
1484 return netdev_alloc_frag(pp->frag_size);
1486 return kmalloc(pp->frag_size, GFP_ATOMIC);
1489 static void mvneta_frag_free(const struct mvneta_port *pp, void *data)
1491 if (likely(pp->frag_size <= PAGE_SIZE))
1492 skb_free_frag(data);
1497 /* Refill processing */
1498 static int mvneta_rx_refill(struct mvneta_port *pp,
1499 struct mvneta_rx_desc *rx_desc)
1502 dma_addr_t phys_addr;
1505 data = mvneta_frag_alloc(pp);
1509 phys_addr = dma_map_single(pp->dev->dev.parent, data,
1510 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1512 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1513 mvneta_frag_free(pp, data);
1517 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
1521 /* Handle tx checksum */
1522 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1524 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1526 __be16 l3_proto = vlan_get_protocol(skb);
1529 if (l3_proto == htons(ETH_P_IP)) {
1530 struct iphdr *ip4h = ip_hdr(skb);
1532 /* Calculate IPv4 checksum and L4 checksum */
1533 ip_hdr_len = ip4h->ihl;
1534 l4_proto = ip4h->protocol;
1535 } else if (l3_proto == htons(ETH_P_IPV6)) {
1536 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1538 /* Read l4_protocol from one of IPv6 extra headers */
1539 if (skb_network_header_len(skb) > 0)
1540 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1541 l4_proto = ip6h->nexthdr;
1543 return MVNETA_TX_L4_CSUM_NOT;
1545 return mvneta_txq_desc_csum(skb_network_offset(skb),
1546 l3_proto, ip_hdr_len, l4_proto);
1549 return MVNETA_TX_L4_CSUM_NOT;
1552 /* Drop packets received by the RXQ and free buffers */
1553 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1554 struct mvneta_rx_queue *rxq)
1558 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1559 for (i = 0; i < rxq->size; i++) {
1560 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1561 void *data = (void *)rx_desc->buf_cookie;
1563 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1564 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1565 mvneta_frag_free(pp, data);
1569 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1572 /* Main rx processing */
1573 static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1574 struct mvneta_rx_queue *rxq)
1576 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
1577 struct net_device *dev = pp->dev;
1582 /* Get number of received packets */
1583 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1585 if (rx_todo > rx_done)
1590 /* Fairness NAPI loop */
1591 while (rx_done < rx_todo) {
1592 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1593 struct sk_buff *skb;
1594 unsigned char *data;
1595 dma_addr_t phys_addr;
1600 rx_status = rx_desc->status;
1601 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1602 data = (unsigned char *)rx_desc->buf_cookie;
1603 phys_addr = rx_desc->buf_phys_addr;
1605 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1606 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1608 dev->stats.rx_errors++;
1609 mvneta_rx_error(pp, rx_desc);
1610 /* leave the descriptor untouched */
1614 if (rx_bytes <= rx_copybreak) {
1615 /* better copy a small frame and not unmap the DMA region */
1616 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1618 goto err_drop_frame;
1620 dma_sync_single_range_for_cpu(dev->dev.parent,
1621 rx_desc->buf_phys_addr,
1622 MVNETA_MH_SIZE + NET_SKB_PAD,
1625 memcpy(skb_put(skb, rx_bytes),
1626 data + MVNETA_MH_SIZE + NET_SKB_PAD,
1629 skb->protocol = eth_type_trans(skb, dev);
1630 mvneta_rx_csum(pp, rx_status, skb);
1631 napi_gro_receive(&port->napi, skb);
1634 rcvd_bytes += rx_bytes;
1636 /* leave the descriptor and buffer untouched */
1640 /* Refill processing */
1641 err = mvneta_rx_refill(pp, rx_desc);
1643 netdev_err(dev, "Linux processing - Can't refill\n");
1645 goto err_drop_frame;
1648 skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size);
1650 /* After refill old buffer has to be unmapped regardless
1651 * the skb is successfully built or not.
1653 dma_unmap_single(dev->dev.parent, phys_addr,
1654 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1657 goto err_drop_frame;
1660 rcvd_bytes += rx_bytes;
1662 /* Linux processing */
1663 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
1664 skb_put(skb, rx_bytes);
1666 skb->protocol = eth_type_trans(skb, dev);
1668 mvneta_rx_csum(pp, rx_status, skb);
1670 napi_gro_receive(&port->napi, skb);
1674 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1676 u64_stats_update_begin(&stats->syncp);
1677 stats->rx_packets += rcvd_pkts;
1678 stats->rx_bytes += rcvd_bytes;
1679 u64_stats_update_end(&stats->syncp);
1682 /* Update rxq management counters */
1683 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1689 mvneta_tso_put_hdr(struct sk_buff *skb,
1690 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
1692 struct mvneta_tx_desc *tx_desc;
1693 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1695 txq->tx_skb[txq->txq_put_index] = NULL;
1696 tx_desc = mvneta_txq_next_desc_get(txq);
1697 tx_desc->data_size = hdr_len;
1698 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
1699 tx_desc->command |= MVNETA_TXD_F_DESC;
1700 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
1701 txq->txq_put_index * TSO_HEADER_SIZE;
1702 mvneta_txq_inc_put(txq);
1706 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
1707 struct sk_buff *skb, char *data, int size,
1708 bool last_tcp, bool is_last)
1710 struct mvneta_tx_desc *tx_desc;
1712 tx_desc = mvneta_txq_next_desc_get(txq);
1713 tx_desc->data_size = size;
1714 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
1715 size, DMA_TO_DEVICE);
1716 if (unlikely(dma_mapping_error(dev->dev.parent,
1717 tx_desc->buf_phys_addr))) {
1718 mvneta_txq_desc_put(txq);
1722 tx_desc->command = 0;
1723 txq->tx_skb[txq->txq_put_index] = NULL;
1726 /* last descriptor in the TCP packet */
1727 tx_desc->command = MVNETA_TXD_L_DESC;
1729 /* last descriptor in SKB */
1731 txq->tx_skb[txq->txq_put_index] = skb;
1733 mvneta_txq_inc_put(txq);
1737 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
1738 struct mvneta_tx_queue *txq)
1740 int total_len, data_left;
1742 struct mvneta_port *pp = netdev_priv(dev);
1744 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1747 /* Count needed descriptors */
1748 if ((txq->count + tso_count_descs(skb)) >= txq->size)
1751 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
1752 pr_info("*** Is this even possible???!?!?\n");
1756 /* Initialize the TSO handler, and prepare the first payload */
1757 tso_start(skb, &tso);
1759 total_len = skb->len - hdr_len;
1760 while (total_len > 0) {
1763 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
1764 total_len -= data_left;
1767 /* prepare packet headers: MAC + IP + TCP */
1768 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
1769 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
1771 mvneta_tso_put_hdr(skb, pp, txq);
1773 while (data_left > 0) {
1777 size = min_t(int, tso.size, data_left);
1779 if (mvneta_tso_put_data(dev, txq, skb,
1786 tso_build_data(skb, &tso, size);
1793 /* Release all used data descriptors; header descriptors must not
1796 for (i = desc_count - 1; i >= 0; i--) {
1797 struct mvneta_tx_desc *tx_desc = txq->descs + i;
1798 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1799 dma_unmap_single(pp->dev->dev.parent,
1800 tx_desc->buf_phys_addr,
1803 mvneta_txq_desc_put(txq);
1808 /* Handle tx fragmentation processing */
1809 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1810 struct mvneta_tx_queue *txq)
1812 struct mvneta_tx_desc *tx_desc;
1813 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1815 for (i = 0; i < nr_frags; i++) {
1816 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1817 void *addr = page_address(frag->page.p) + frag->page_offset;
1819 tx_desc = mvneta_txq_next_desc_get(txq);
1820 tx_desc->data_size = frag->size;
1822 tx_desc->buf_phys_addr =
1823 dma_map_single(pp->dev->dev.parent, addr,
1824 tx_desc->data_size, DMA_TO_DEVICE);
1826 if (dma_mapping_error(pp->dev->dev.parent,
1827 tx_desc->buf_phys_addr)) {
1828 mvneta_txq_desc_put(txq);
1832 if (i == nr_frags - 1) {
1833 /* Last descriptor */
1834 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
1835 txq->tx_skb[txq->txq_put_index] = skb;
1837 /* Descriptor in the middle: Not First, Not Last */
1838 tx_desc->command = 0;
1839 txq->tx_skb[txq->txq_put_index] = NULL;
1841 mvneta_txq_inc_put(txq);
1847 /* Release all descriptors that were used to map fragments of
1848 * this packet, as well as the corresponding DMA mappings
1850 for (i = i - 1; i >= 0; i--) {
1851 tx_desc = txq->descs + i;
1852 dma_unmap_single(pp->dev->dev.parent,
1853 tx_desc->buf_phys_addr,
1856 mvneta_txq_desc_put(txq);
1862 /* Main tx processing */
1863 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1865 struct mvneta_port *pp = netdev_priv(dev);
1866 u16 txq_id = skb_get_queue_mapping(skb);
1867 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
1868 struct mvneta_tx_desc *tx_desc;
1873 if (!netif_running(dev))
1876 if (skb_is_gso(skb)) {
1877 frags = mvneta_tx_tso(skb, dev, txq);
1881 frags = skb_shinfo(skb)->nr_frags + 1;
1883 /* Get a descriptor for the first part of the packet */
1884 tx_desc = mvneta_txq_next_desc_get(txq);
1886 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1888 tx_desc->data_size = skb_headlen(skb);
1890 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1893 if (unlikely(dma_mapping_error(dev->dev.parent,
1894 tx_desc->buf_phys_addr))) {
1895 mvneta_txq_desc_put(txq);
1901 /* First and Last descriptor */
1902 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1903 tx_desc->command = tx_cmd;
1904 txq->tx_skb[txq->txq_put_index] = skb;
1905 mvneta_txq_inc_put(txq);
1907 /* First but not Last */
1908 tx_cmd |= MVNETA_TXD_F_DESC;
1909 txq->tx_skb[txq->txq_put_index] = NULL;
1910 mvneta_txq_inc_put(txq);
1911 tx_desc->command = tx_cmd;
1912 /* Continue with other skb fragments */
1913 if (mvneta_tx_frag_process(pp, skb, txq)) {
1914 dma_unmap_single(dev->dev.parent,
1915 tx_desc->buf_phys_addr,
1918 mvneta_txq_desc_put(txq);
1926 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1927 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
1929 txq->count += frags;
1930 mvneta_txq_pend_desc_add(pp, txq, frags);
1932 if (txq->count >= txq->tx_stop_threshold)
1933 netif_tx_stop_queue(nq);
1935 u64_stats_update_begin(&stats->syncp);
1936 stats->tx_packets++;
1937 stats->tx_bytes += len;
1938 u64_stats_update_end(&stats->syncp);
1940 dev->stats.tx_dropped++;
1941 dev_kfree_skb_any(skb);
1944 return NETDEV_TX_OK;
1948 /* Free tx resources, when resetting a port */
1949 static void mvneta_txq_done_force(struct mvneta_port *pp,
1950 struct mvneta_tx_queue *txq)
1953 int tx_done = txq->count;
1955 mvneta_txq_bufs_free(pp, txq, tx_done);
1959 txq->txq_put_index = 0;
1960 txq->txq_get_index = 0;
1963 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
1964 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
1966 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
1968 struct mvneta_tx_queue *txq;
1969 struct netdev_queue *nq;
1971 while (cause_tx_done) {
1972 txq = mvneta_tx_done_policy(pp, cause_tx_done);
1974 nq = netdev_get_tx_queue(pp->dev, txq->id);
1975 __netif_tx_lock(nq, smp_processor_id());
1978 mvneta_txq_done(pp, txq);
1980 __netif_tx_unlock(nq);
1981 cause_tx_done &= ~((1 << txq->id));
1985 /* Compute crc8 of the specified address, using a unique algorithm ,
1986 * according to hw spec, different than generic crc8 algorithm
1988 static int mvneta_addr_crc(unsigned char *addr)
1993 for (i = 0; i < ETH_ALEN; i++) {
1996 crc = (crc ^ addr[i]) << 8;
1997 for (j = 7; j >= 0; j--) {
1998 if (crc & (0x100 << j))
2006 /* This method controls the net device special MAC multicast support.
2007 * The Special Multicast Table for MAC addresses supports MAC of the form
2008 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2009 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2010 * Table entries in the DA-Filter table. This method set the Special
2011 * Multicast Table appropriate entry.
2013 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
2014 unsigned char last_byte,
2017 unsigned int smc_table_reg;
2018 unsigned int tbl_offset;
2019 unsigned int reg_offset;
2021 /* Register offset from SMC table base */
2022 tbl_offset = (last_byte / 4);
2023 /* Entry offset within the above reg */
2024 reg_offset = last_byte % 4;
2026 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2030 smc_table_reg &= ~(0xff << (8 * reg_offset));
2032 smc_table_reg &= ~(0xff << (8 * reg_offset));
2033 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2036 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2040 /* This method controls the network device Other MAC multicast support.
2041 * The Other Multicast Table is used for multicast of another type.
2042 * A CRC-8 is used as an index to the Other Multicast Table entries
2043 * in the DA-Filter table.
2044 * The method gets the CRC-8 value from the calling routine and
2045 * sets the Other Multicast Table appropriate entry according to the
2048 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
2052 unsigned int omc_table_reg;
2053 unsigned int tbl_offset;
2054 unsigned int reg_offset;
2056 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2057 reg_offset = crc8 % 4; /* Entry offset within the above reg */
2059 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2062 /* Clear accepts frame bit at specified Other DA table entry */
2063 omc_table_reg &= ~(0xff << (8 * reg_offset));
2065 omc_table_reg &= ~(0xff << (8 * reg_offset));
2066 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2069 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2072 /* The network device supports multicast using two tables:
2073 * 1) Special Multicast Table for MAC addresses of the form
2074 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2075 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2076 * Table entries in the DA-Filter table.
2077 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2078 * is used as an index to the Other Multicast Table entries in the
2081 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2084 unsigned char crc_result = 0;
2086 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2087 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2091 crc_result = mvneta_addr_crc(p_addr);
2093 if (pp->mcast_count[crc_result] == 0) {
2094 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2099 pp->mcast_count[crc_result]--;
2100 if (pp->mcast_count[crc_result] != 0) {
2101 netdev_info(pp->dev,
2102 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2103 pp->mcast_count[crc_result], crc_result);
2107 pp->mcast_count[crc_result]++;
2109 mvneta_set_other_mcast_addr(pp, crc_result, queue);
2114 /* Configure Fitering mode of Ethernet port */
2115 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2118 u32 port_cfg_reg, val;
2120 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
2122 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2124 /* Set / Clear UPM bit in port configuration register */
2126 /* Accept all Unicast addresses */
2127 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2128 val |= MVNETA_FORCE_UNI;
2129 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2130 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2132 /* Reject all Unicast addresses */
2133 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2134 val &= ~MVNETA_FORCE_UNI;
2137 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2138 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2141 /* register unicast and multicast addresses */
2142 static void mvneta_set_rx_mode(struct net_device *dev)
2144 struct mvneta_port *pp = netdev_priv(dev);
2145 struct netdev_hw_addr *ha;
2147 if (dev->flags & IFF_PROMISC) {
2148 /* Accept all: Multicast + Unicast */
2149 mvneta_rx_unicast_promisc_set(pp, 1);
2150 mvneta_set_ucast_table(pp, pp->rxq_def);
2151 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2152 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2154 /* Accept single Unicast */
2155 mvneta_rx_unicast_promisc_set(pp, 0);
2156 mvneta_set_ucast_table(pp, -1);
2157 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
2159 if (dev->flags & IFF_ALLMULTI) {
2160 /* Accept all multicast */
2161 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2162 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2164 /* Accept only initialized multicast */
2165 mvneta_set_special_mcast_table(pp, -1);
2166 mvneta_set_other_mcast_table(pp, -1);
2168 if (!netdev_mc_empty(dev)) {
2169 netdev_for_each_mc_addr(ha, dev) {
2170 mvneta_mcast_addr_set(pp, ha->addr,
2178 /* Interrupt handling - the callback for request_irq() */
2179 static irqreturn_t mvneta_isr(int irq, void *dev_id)
2181 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
2183 disable_percpu_irq(port->pp->dev->irq);
2184 napi_schedule(&port->napi);
2189 static int mvneta_fixed_link_update(struct mvneta_port *pp,
2190 struct phy_device *phy)
2192 struct fixed_phy_status status;
2193 struct fixed_phy_status changed = {};
2194 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2196 status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
2197 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
2198 status.speed = SPEED_1000;
2199 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
2200 status.speed = SPEED_100;
2202 status.speed = SPEED_10;
2203 status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
2207 fixed_phy_update_state(phy, &status, &changed);
2212 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2213 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2214 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2215 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2216 * Each CPU has its own causeRxTx register
2218 static int mvneta_poll(struct napi_struct *napi, int budget)
2223 struct mvneta_port *pp = netdev_priv(napi->dev);
2224 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2226 if (!netif_running(pp->dev)) {
2227 napi_complete(&port->napi);
2231 /* Read cause register */
2232 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2233 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2234 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2236 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2237 if (pp->use_inband_status && (cause_misc &
2238 (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2239 MVNETA_CAUSE_LINK_CHANGE |
2240 MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
2241 mvneta_fixed_link_update(pp, pp->phy_dev);
2245 /* Release Tx descriptors */
2246 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
2247 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
2248 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2251 /* For the case where the last mvneta_poll did not process all
2254 rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
2256 cause_rx_tx |= port->cause_rx_tx;
2259 rx_queue = rx_queue - 1;
2260 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rx_queue]);
2267 napi_complete(&port->napi);
2268 enable_percpu_irq(pp->dev->irq, 0);
2271 port->cause_rx_tx = cause_rx_tx;
2275 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2276 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2281 for (i = 0; i < num; i++) {
2282 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2283 if (mvneta_rx_refill(pp, rxq->descs + i) != 0) {
2284 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
2285 __func__, rxq->id, i, num);
2290 /* Add this number of RX descriptors as non occupied (ready to
2293 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2298 /* Free all packets pending transmit from all TXQs and reset TX port */
2299 static void mvneta_tx_reset(struct mvneta_port *pp)
2303 /* free the skb's in the tx ring */
2304 for (queue = 0; queue < txq_number; queue++)
2305 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2307 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2308 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2311 static void mvneta_rx_reset(struct mvneta_port *pp)
2313 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2314 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2317 /* Rx/Tx queue initialization/cleanup methods */
2319 /* Create a specified RX queue */
2320 static int mvneta_rxq_init(struct mvneta_port *pp,
2321 struct mvneta_rx_queue *rxq)
2324 rxq->size = pp->rx_ring_size;
2326 /* Allocate memory for RX descriptors */
2327 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2328 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2329 &rxq->descs_phys, GFP_KERNEL);
2330 if (rxq->descs == NULL)
2333 BUG_ON(rxq->descs !=
2334 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2336 rxq->last_desc = rxq->size - 1;
2338 /* Set Rx descriptors queue starting address */
2339 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2340 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2343 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2345 /* Set coalescing pkts and time */
2346 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2347 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2349 /* Fill RXQ with buffers from RX pool */
2350 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
2351 mvneta_rxq_bm_disable(pp, rxq);
2352 mvneta_rxq_fill(pp, rxq, rxq->size);
2357 /* Cleanup Rx queue */
2358 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2359 struct mvneta_rx_queue *rxq)
2361 mvneta_rxq_drop_pkts(pp, rxq);
2364 dma_free_coherent(pp->dev->dev.parent,
2365 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2371 rxq->next_desc_to_proc = 0;
2372 rxq->descs_phys = 0;
2375 /* Create and initialize a tx queue */
2376 static int mvneta_txq_init(struct mvneta_port *pp,
2377 struct mvneta_tx_queue *txq)
2381 txq->size = pp->tx_ring_size;
2383 /* A queue must always have room for at least one skb.
2384 * Therefore, stop the queue when the free entries reaches
2385 * the maximum number of descriptors per skb.
2387 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2388 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2391 /* Allocate memory for TX descriptors */
2392 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2393 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2394 &txq->descs_phys, GFP_KERNEL);
2395 if (txq->descs == NULL)
2398 /* Make sure descriptor address is cache line size aligned */
2399 BUG_ON(txq->descs !=
2400 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2402 txq->last_desc = txq->size - 1;
2404 /* Set maximum bandwidth for enabled TXQs */
2405 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2406 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2408 /* Set Tx descriptors queue starting address */
2409 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2410 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2412 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2413 if (txq->tx_skb == NULL) {
2414 dma_free_coherent(pp->dev->dev.parent,
2415 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2416 txq->descs, txq->descs_phys);
2420 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2421 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2422 txq->size * TSO_HEADER_SIZE,
2423 &txq->tso_hdrs_phys, GFP_KERNEL);
2424 if (txq->tso_hdrs == NULL) {
2426 dma_free_coherent(pp->dev->dev.parent,
2427 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2428 txq->descs, txq->descs_phys);
2431 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2433 /* Setup XPS mapping */
2435 cpu = txq->id % num_present_cpus();
2437 cpu = pp->rxq_def % num_present_cpus();
2438 cpumask_set_cpu(cpu, &txq->affinity_mask);
2439 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
2444 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2445 static void mvneta_txq_deinit(struct mvneta_port *pp,
2446 struct mvneta_tx_queue *txq)
2451 dma_free_coherent(pp->dev->dev.parent,
2452 txq->size * TSO_HEADER_SIZE,
2453 txq->tso_hdrs, txq->tso_hdrs_phys);
2455 dma_free_coherent(pp->dev->dev.parent,
2456 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2457 txq->descs, txq->descs_phys);
2461 txq->next_desc_to_proc = 0;
2462 txq->descs_phys = 0;
2464 /* Set minimum bandwidth for disabled TXQs */
2465 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2466 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2468 /* Set Tx descriptors queue starting address and size */
2469 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2470 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2473 /* Cleanup all Tx queues */
2474 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2478 for (queue = 0; queue < txq_number; queue++)
2479 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2482 /* Cleanup all Rx queues */
2483 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2487 for (queue = 0; queue < txq_number; queue++)
2488 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2492 /* Init all Rx queues */
2493 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2497 for (queue = 0; queue < rxq_number; queue++) {
2498 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2501 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2503 mvneta_cleanup_rxqs(pp);
2511 /* Init all tx queues */
2512 static int mvneta_setup_txqs(struct mvneta_port *pp)
2516 for (queue = 0; queue < txq_number; queue++) {
2517 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2519 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2521 mvneta_cleanup_txqs(pp);
2529 static void mvneta_percpu_unmask_interrupt(void *arg)
2531 struct mvneta_port *pp = arg;
2533 /* All the queue are unmasked, but actually only the ones
2534 * maped to this CPU will be unmasked
2536 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2537 MVNETA_RX_INTR_MASK_ALL |
2538 MVNETA_TX_INTR_MASK_ALL |
2539 MVNETA_MISCINTR_INTR_MASK);
2542 static void mvneta_percpu_mask_interrupt(void *arg)
2544 struct mvneta_port *pp = arg;
2546 /* All the queue are masked, but actually only the ones
2547 * maped to this CPU will be masked
2549 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2550 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2551 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2554 static void mvneta_start_dev(struct mvneta_port *pp)
2558 mvneta_max_rx_size_set(pp, pp->pkt_size);
2559 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2561 /* start the Rx/Tx activity */
2562 mvneta_port_enable(pp);
2564 /* Enable polling on the port */
2565 for_each_present_cpu(cpu) {
2566 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2568 napi_enable(&port->napi);
2571 /* Unmask interrupts. It has to be done from each CPU */
2572 for_each_online_cpu(cpu)
2573 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
2575 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2576 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2577 MVNETA_CAUSE_LINK_CHANGE |
2578 MVNETA_CAUSE_PSC_SYNC_CHANGE);
2580 phy_start(pp->phy_dev);
2581 netif_tx_start_all_queues(pp->dev);
2584 static void mvneta_stop_dev(struct mvneta_port *pp)
2588 phy_stop(pp->phy_dev);
2590 for_each_present_cpu(cpu) {
2591 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2593 napi_disable(&port->napi);
2596 netif_carrier_off(pp->dev);
2598 mvneta_port_down(pp);
2599 netif_tx_stop_all_queues(pp->dev);
2601 /* Stop the port activity */
2602 mvneta_port_disable(pp);
2604 /* Clear all ethernet port interrupts */
2605 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2606 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2608 /* Mask all ethernet port interrupts */
2609 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2610 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2611 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2613 mvneta_tx_reset(pp);
2614 mvneta_rx_reset(pp);
2617 /* Return positive if MTU is valid */
2618 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2621 netdev_err(dev, "cannot change mtu to less than 68\n");
2625 /* 9676 == 9700 - 20 and rounding to 8 */
2627 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2631 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2632 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2633 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2634 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2640 /* Change the device mtu */
2641 static int mvneta_change_mtu(struct net_device *dev, int mtu)
2643 struct mvneta_port *pp = netdev_priv(dev);
2646 mtu = mvneta_check_mtu_valid(dev, mtu);
2652 if (!netif_running(dev)) {
2653 netdev_update_features(dev);
2657 /* The interface is running, so we have to force a
2658 * reallocation of the queues
2660 mvneta_stop_dev(pp);
2662 mvneta_cleanup_txqs(pp);
2663 mvneta_cleanup_rxqs(pp);
2665 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
2666 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2667 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2669 ret = mvneta_setup_rxqs(pp);
2671 netdev_err(dev, "unable to setup rxqs after MTU change\n");
2675 ret = mvneta_setup_txqs(pp);
2677 netdev_err(dev, "unable to setup txqs after MTU change\n");
2681 mvneta_start_dev(pp);
2684 netdev_update_features(dev);
2689 static netdev_features_t mvneta_fix_features(struct net_device *dev,
2690 netdev_features_t features)
2692 struct mvneta_port *pp = netdev_priv(dev);
2694 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
2695 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
2697 "Disable IP checksum for MTU greater than %dB\n",
2704 /* Get mac address */
2705 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
2707 u32 mac_addr_l, mac_addr_h;
2709 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
2710 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
2711 addr[0] = (mac_addr_h >> 24) & 0xFF;
2712 addr[1] = (mac_addr_h >> 16) & 0xFF;
2713 addr[2] = (mac_addr_h >> 8) & 0xFF;
2714 addr[3] = mac_addr_h & 0xFF;
2715 addr[4] = (mac_addr_l >> 8) & 0xFF;
2716 addr[5] = mac_addr_l & 0xFF;
2719 /* Handle setting mac address */
2720 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2722 struct mvneta_port *pp = netdev_priv(dev);
2723 struct sockaddr *sockaddr = addr;
2726 ret = eth_prepare_mac_addr_change(dev, addr);
2729 /* Remove previous address table entry */
2730 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2732 /* Set new addr in hw */
2733 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
2735 eth_commit_mac_addr_change(dev, addr);
2739 static void mvneta_adjust_link(struct net_device *ndev)
2741 struct mvneta_port *pp = netdev_priv(ndev);
2742 struct phy_device *phydev = pp->phy_dev;
2743 int status_change = 0;
2746 if ((pp->speed != phydev->speed) ||
2747 (pp->duplex != phydev->duplex)) {
2750 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2751 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2752 MVNETA_GMAC_CONFIG_GMII_SPEED |
2753 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
2756 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2758 if (phydev->speed == SPEED_1000)
2759 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
2760 else if (phydev->speed == SPEED_100)
2761 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2763 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2765 pp->duplex = phydev->duplex;
2766 pp->speed = phydev->speed;
2770 if (phydev->link != pp->link) {
2771 if (!phydev->link) {
2776 pp->link = phydev->link;
2780 if (status_change) {
2782 if (!pp->use_inband_status) {
2783 u32 val = mvreg_read(pp,
2784 MVNETA_GMAC_AUTONEG_CONFIG);
2785 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
2786 val |= MVNETA_GMAC_FORCE_LINK_PASS;
2787 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
2792 if (!pp->use_inband_status) {
2793 u32 val = mvreg_read(pp,
2794 MVNETA_GMAC_AUTONEG_CONFIG);
2795 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
2796 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
2797 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
2800 mvneta_port_down(pp);
2802 phy_print_status(phydev);
2806 static int mvneta_mdio_probe(struct mvneta_port *pp)
2808 struct phy_device *phy_dev;
2810 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2813 netdev_err(pp->dev, "could not find the PHY\n");
2817 phy_dev->supported &= PHY_GBIT_FEATURES;
2818 phy_dev->advertising = phy_dev->supported;
2820 pp->phy_dev = phy_dev;
2828 static void mvneta_mdio_remove(struct mvneta_port *pp)
2830 phy_disconnect(pp->phy_dev);
2834 static void mvneta_percpu_enable(void *arg)
2836 struct mvneta_port *pp = arg;
2838 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
2841 static void mvneta_percpu_disable(void *arg)
2843 struct mvneta_port *pp = arg;
2845 disable_percpu_irq(pp->dev->irq);
2848 static void mvneta_percpu_elect(struct mvneta_port *pp)
2850 int online_cpu_idx, max_cpu, cpu, i = 0;
2852 online_cpu_idx = pp->rxq_def % num_online_cpus();
2853 max_cpu = num_present_cpus();
2855 for_each_online_cpu(cpu) {
2856 int rxq_map = 0, txq_map = 0;
2859 for (rxq = 0; rxq < rxq_number; rxq++)
2860 if ((rxq % max_cpu) == cpu)
2861 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
2863 if (i == online_cpu_idx)
2864 /* Map the default receive queue queue to the
2867 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
2869 /* We update the TX queue map only if we have one
2870 * queue. In this case we associate the TX queue to
2871 * the CPU bound to the default RX queue
2873 if (txq_number == 1)
2874 txq_map = (i == online_cpu_idx) ?
2875 MVNETA_CPU_TXQ_ACCESS(1) : 0;
2877 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
2878 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
2880 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
2882 /* Update the interrupt mask on each CPU according the
2885 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
2892 static int mvneta_percpu_notifier(struct notifier_block *nfb,
2893 unsigned long action, void *hcpu)
2895 struct mvneta_port *pp = container_of(nfb, struct mvneta_port,
2897 int cpu = (unsigned long)hcpu, other_cpu;
2898 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2902 case CPU_ONLINE_FROZEN:
2903 netif_tx_stop_all_queues(pp->dev);
2905 /* We have to synchronise on tha napi of each CPU
2906 * except the one just being waked up
2908 for_each_online_cpu(other_cpu) {
2909 if (other_cpu != cpu) {
2910 struct mvneta_pcpu_port *other_port =
2911 per_cpu_ptr(pp->ports, other_cpu);
2913 napi_synchronize(&other_port->napi);
2917 /* Mask all ethernet port interrupts */
2918 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2919 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2920 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2921 napi_enable(&port->napi);
2924 /* Enable per-CPU interrupts on the CPU that is
2927 smp_call_function_single(cpu, mvneta_percpu_enable,
2930 /* Enable per-CPU interrupt on the one CPU we care
2933 mvneta_percpu_elect(pp);
2935 /* Unmask all ethernet port interrupts, as this
2936 * notifier is called for each CPU then the CPU to
2937 * Queue mapping is applied
2939 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2940 MVNETA_RX_INTR_MASK(rxq_number) |
2941 MVNETA_TX_INTR_MASK(txq_number) |
2942 MVNETA_MISCINTR_INTR_MASK);
2943 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2944 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2945 MVNETA_CAUSE_LINK_CHANGE |
2946 MVNETA_CAUSE_PSC_SYNC_CHANGE);
2947 netif_tx_start_all_queues(pp->dev);
2949 case CPU_DOWN_PREPARE:
2950 case CPU_DOWN_PREPARE_FROZEN:
2951 netif_tx_stop_all_queues(pp->dev);
2952 /* Mask all ethernet port interrupts */
2953 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2954 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2955 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2957 napi_synchronize(&port->napi);
2958 napi_disable(&port->napi);
2959 /* Disable per-CPU interrupts on the CPU that is
2962 smp_call_function_single(cpu, mvneta_percpu_disable,
2967 case CPU_DEAD_FROZEN:
2968 /* Check if a new CPU must be elected now this on is down */
2969 mvneta_percpu_elect(pp);
2970 /* Unmask all ethernet port interrupts */
2971 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2972 MVNETA_RX_INTR_MASK(rxq_number) |
2973 MVNETA_TX_INTR_MASK(txq_number) |
2974 MVNETA_MISCINTR_INTR_MASK);
2975 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2976 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2977 MVNETA_CAUSE_LINK_CHANGE |
2978 MVNETA_CAUSE_PSC_SYNC_CHANGE);
2979 netif_tx_start_all_queues(pp->dev);
2986 static int mvneta_open(struct net_device *dev)
2988 struct mvneta_port *pp = netdev_priv(dev);
2991 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2992 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2993 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2995 ret = mvneta_setup_rxqs(pp);
2999 ret = mvneta_setup_txqs(pp);
3001 goto err_cleanup_rxqs;
3003 /* Connect to port interrupt line */
3004 ret = request_percpu_irq(pp->dev->irq, mvneta_isr,
3005 MVNETA_DRIVER_NAME, pp->ports);
3007 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
3008 goto err_cleanup_txqs;
3011 /* Even though the documentation says that request_percpu_irq
3012 * doesn't enable the interrupts automatically, it actually
3013 * does so on the local CPU.
3015 * Make sure it's disabled.
3017 mvneta_percpu_disable(pp);
3019 /* Enable per-CPU interrupt on all the CPU to handle our RX
3022 for_each_online_cpu(cpu)
3023 smp_call_function_single(cpu, mvneta_percpu_enable,
3027 /* Register a CPU notifier to handle the case where our CPU
3028 * might be taken offline.
3030 register_cpu_notifier(&pp->cpu_notifier);
3032 /* In default link is down */
3033 netif_carrier_off(pp->dev);
3035 ret = mvneta_mdio_probe(pp);
3037 netdev_err(dev, "cannot probe MDIO bus\n");
3041 mvneta_start_dev(pp);
3046 free_percpu_irq(pp->dev->irq, pp->ports);
3048 mvneta_cleanup_txqs(pp);
3050 mvneta_cleanup_rxqs(pp);
3054 /* Stop the port, free port interrupt line */
3055 static int mvneta_stop(struct net_device *dev)
3057 struct mvneta_port *pp = netdev_priv(dev);
3060 mvneta_stop_dev(pp);
3061 mvneta_mdio_remove(pp);
3062 unregister_cpu_notifier(&pp->cpu_notifier);
3063 for_each_present_cpu(cpu)
3064 smp_call_function_single(cpu, mvneta_percpu_disable, pp, true);
3065 free_percpu_irq(dev->irq, pp->ports);
3066 mvneta_cleanup_rxqs(pp);
3067 mvneta_cleanup_txqs(pp);
3072 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3074 struct mvneta_port *pp = netdev_priv(dev);
3079 return phy_mii_ioctl(pp->phy_dev, ifr, cmd);
3082 /* Ethtool methods */
3084 /* Get settings (phy address, speed) for ethtools */
3085 int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3087 struct mvneta_port *pp = netdev_priv(dev);
3092 return phy_ethtool_gset(pp->phy_dev, cmd);
3095 /* Set settings (phy address, speed) for ethtools */
3096 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3098 struct mvneta_port *pp = netdev_priv(dev);
3099 struct phy_device *phydev = pp->phy_dev;
3104 if ((cmd->autoneg == AUTONEG_ENABLE) != pp->use_inband_status) {
3107 mvneta_set_autoneg(pp, cmd->autoneg == AUTONEG_ENABLE);
3109 if (cmd->autoneg == AUTONEG_DISABLE) {
3110 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3111 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
3112 MVNETA_GMAC_CONFIG_GMII_SPEED |
3113 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
3116 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3118 if (phydev->speed == SPEED_1000)
3119 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3120 else if (phydev->speed == SPEED_100)
3121 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
3123 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3126 pp->use_inband_status = (cmd->autoneg == AUTONEG_ENABLE);
3127 netdev_info(pp->dev, "autoneg status set to %i\n",
3128 pp->use_inband_status);
3130 if (netif_running(dev)) {
3131 mvneta_port_down(pp);
3136 return phy_ethtool_sset(pp->phy_dev, cmd);
3139 /* Set interrupt coalescing for ethtools */
3140 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
3141 struct ethtool_coalesce *c)
3143 struct mvneta_port *pp = netdev_priv(dev);
3146 for (queue = 0; queue < rxq_number; queue++) {
3147 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3148 rxq->time_coal = c->rx_coalesce_usecs;
3149 rxq->pkts_coal = c->rx_max_coalesced_frames;
3150 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3151 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3154 for (queue = 0; queue < txq_number; queue++) {
3155 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3156 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3157 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3163 /* get coalescing for ethtools */
3164 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
3165 struct ethtool_coalesce *c)
3167 struct mvneta_port *pp = netdev_priv(dev);
3169 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
3170 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
3172 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
3177 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
3178 struct ethtool_drvinfo *drvinfo)
3180 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
3181 sizeof(drvinfo->driver));
3182 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
3183 sizeof(drvinfo->version));
3184 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3185 sizeof(drvinfo->bus_info));
3189 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
3190 struct ethtool_ringparam *ring)
3192 struct mvneta_port *pp = netdev_priv(netdev);
3194 ring->rx_max_pending = MVNETA_MAX_RXD;
3195 ring->tx_max_pending = MVNETA_MAX_TXD;
3196 ring->rx_pending = pp->rx_ring_size;
3197 ring->tx_pending = pp->tx_ring_size;
3200 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
3201 struct ethtool_ringparam *ring)
3203 struct mvneta_port *pp = netdev_priv(dev);
3205 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
3207 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
3208 ring->rx_pending : MVNETA_MAX_RXD;
3210 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
3211 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
3212 if (pp->tx_ring_size != ring->tx_pending)
3213 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
3214 pp->tx_ring_size, ring->tx_pending);
3216 if (netif_running(dev)) {
3218 if (mvneta_open(dev)) {
3220 "error on opening device after ring param change\n");
3228 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
3231 if (sset == ETH_SS_STATS) {
3234 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3235 memcpy(data + i * ETH_GSTRING_LEN,
3236 mvneta_statistics[i].name, ETH_GSTRING_LEN);
3240 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
3242 const struct mvneta_statistic *s;
3243 void __iomem *base = pp->base;
3247 for (i = 0, s = mvneta_statistics;
3248 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
3254 val = readl_relaxed(base + s->offset);
3257 /* Docs say to read low 32-bit then high */
3258 low = readl_relaxed(base + s->offset);
3259 high = readl_relaxed(base + s->offset + 4);
3260 val = (u64)high << 32 | low;
3264 pp->ethtool_stats[i] += val;
3268 static void mvneta_ethtool_get_stats(struct net_device *dev,
3269 struct ethtool_stats *stats, u64 *data)
3271 struct mvneta_port *pp = netdev_priv(dev);
3274 mvneta_ethtool_update_stats(pp);
3276 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3277 *data++ = pp->ethtool_stats[i];
3280 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
3282 if (sset == ETH_SS_STATS)
3283 return ARRAY_SIZE(mvneta_statistics);
3287 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
3289 return MVNETA_RSS_LU_TABLE_SIZE;
3292 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
3293 struct ethtool_rxnfc *info,
3294 u32 *rules __always_unused)
3296 switch (info->cmd) {
3297 case ETHTOOL_GRXRINGS:
3298 info->data = rxq_number;
3307 static int mvneta_config_rss(struct mvneta_port *pp)
3312 netif_tx_stop_all_queues(pp->dev);
3314 for_each_online_cpu(cpu)
3315 smp_call_function_single(cpu, mvneta_percpu_mask_interrupt,
3318 /* We have to synchronise on the napi of each CPU */
3319 for_each_online_cpu(cpu) {
3320 struct mvneta_pcpu_port *pcpu_port =
3321 per_cpu_ptr(pp->ports, cpu);
3323 napi_synchronize(&pcpu_port->napi);
3324 napi_disable(&pcpu_port->napi);
3327 pp->rxq_def = pp->indir[0];
3329 /* Update unicast mapping */
3330 mvneta_set_rx_mode(pp->dev);
3332 /* Update val of portCfg register accordingly with all RxQueue types */
3333 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
3334 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
3336 /* Update the elected CPU matching the new rxq_def */
3337 mvneta_percpu_elect(pp);
3339 /* We have to synchronise on the napi of each CPU */
3340 for_each_online_cpu(cpu) {
3341 struct mvneta_pcpu_port *pcpu_port =
3342 per_cpu_ptr(pp->ports, cpu);
3344 napi_enable(&pcpu_port->napi);
3347 netif_tx_start_all_queues(pp->dev);
3352 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
3353 const u8 *key, const u8 hfunc)
3355 struct mvneta_port *pp = netdev_priv(dev);
3356 /* We require at least one supported parameter to be changed
3357 * and no change in any of the unsupported parameters
3360 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3366 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
3368 return mvneta_config_rss(pp);
3371 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3374 struct mvneta_port *pp = netdev_priv(dev);
3377 *hfunc = ETH_RSS_HASH_TOP;
3382 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
3387 static const struct net_device_ops mvneta_netdev_ops = {
3388 .ndo_open = mvneta_open,
3389 .ndo_stop = mvneta_stop,
3390 .ndo_start_xmit = mvneta_tx,
3391 .ndo_set_rx_mode = mvneta_set_rx_mode,
3392 .ndo_set_mac_address = mvneta_set_mac_addr,
3393 .ndo_change_mtu = mvneta_change_mtu,
3394 .ndo_fix_features = mvneta_fix_features,
3395 .ndo_get_stats64 = mvneta_get_stats64,
3396 .ndo_do_ioctl = mvneta_ioctl,
3399 const struct ethtool_ops mvneta_eth_tool_ops = {
3400 .get_link = ethtool_op_get_link,
3401 .get_settings = mvneta_ethtool_get_settings,
3402 .set_settings = mvneta_ethtool_set_settings,
3403 .set_coalesce = mvneta_ethtool_set_coalesce,
3404 .get_coalesce = mvneta_ethtool_get_coalesce,
3405 .get_drvinfo = mvneta_ethtool_get_drvinfo,
3406 .get_ringparam = mvneta_ethtool_get_ringparam,
3407 .set_ringparam = mvneta_ethtool_set_ringparam,
3408 .get_strings = mvneta_ethtool_get_strings,
3409 .get_ethtool_stats = mvneta_ethtool_get_stats,
3410 .get_sset_count = mvneta_ethtool_get_sset_count,
3411 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
3412 .get_rxnfc = mvneta_ethtool_get_rxnfc,
3413 .get_rxfh = mvneta_ethtool_get_rxfh,
3414 .set_rxfh = mvneta_ethtool_set_rxfh,
3418 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
3423 mvneta_port_disable(pp);
3425 /* Set port default values */
3426 mvneta_defaults_set(pp);
3428 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue),
3433 /* Initialize TX descriptor rings */
3434 for (queue = 0; queue < txq_number; queue++) {
3435 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3437 txq->size = pp->tx_ring_size;
3438 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
3441 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue),
3446 /* Create Rx descriptor rings */
3447 for (queue = 0; queue < rxq_number; queue++) {
3448 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3450 rxq->size = pp->rx_ring_size;
3451 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
3452 rxq->time_coal = MVNETA_RX_COAL_USEC;
3458 /* platform glue : initialize decoding windows */
3459 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
3460 const struct mbus_dram_target_info *dram)
3466 for (i = 0; i < 6; i++) {
3467 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
3468 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
3471 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
3477 for (i = 0; i < dram->num_cs; i++) {
3478 const struct mbus_dram_window *cs = dram->cs + i;
3479 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
3480 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
3482 mvreg_write(pp, MVNETA_WIN_SIZE(i),
3483 (cs->size - 1) & 0xffff0000);
3485 win_enable &= ~(1 << i);
3486 win_protect |= 3 << (2 * i);
3489 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
3490 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
3493 /* Power up the port */
3494 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
3498 /* MAC Cause register should be cleared */
3499 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
3501 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
3503 /* Even though it might look weird, when we're configured in
3504 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3507 case PHY_INTERFACE_MODE_QSGMII:
3508 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
3509 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3511 case PHY_INTERFACE_MODE_SGMII:
3512 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
3513 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3515 case PHY_INTERFACE_MODE_RGMII:
3516 case PHY_INTERFACE_MODE_RGMII_ID:
3517 ctrl |= MVNETA_GMAC2_PORT_RGMII;
3523 /* Cancel Port Reset */
3524 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
3525 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
3527 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
3528 MVNETA_GMAC2_PORT_RESET) != 0)
3534 /* Device initialization routine */
3535 static int mvneta_probe(struct platform_device *pdev)
3537 const struct mbus_dram_target_info *dram_target_info;
3538 struct resource *res;
3539 struct device_node *dn = pdev->dev.of_node;
3540 struct device_node *phy_node;
3541 struct mvneta_port *pp;
3542 struct net_device *dev;
3543 const char *dt_mac_addr;
3544 char hw_mac_addr[ETH_ALEN];
3545 const char *mac_from;
3546 const char *managed;
3552 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
3556 dev->irq = irq_of_parse_and_map(dn, 0);
3557 if (dev->irq == 0) {
3559 goto err_free_netdev;
3562 phy_node = of_parse_phandle(dn, "phy", 0);
3564 if (!of_phy_is_fixed_link(dn)) {
3565 dev_err(&pdev->dev, "no PHY specified\n");
3570 err = of_phy_register_fixed_link(dn);
3572 dev_err(&pdev->dev, "cannot register fixed PHY\n");
3576 /* In the case of a fixed PHY, the DT node associated
3577 * to the PHY is the Ethernet MAC DT node.
3579 phy_node = of_node_get(dn);
3582 phy_mode = of_get_phy_mode(dn);
3584 dev_err(&pdev->dev, "incorrect phy-mode\n");
3586 goto err_put_phy_node;
3589 dev->tx_queue_len = MVNETA_MAX_TXD;
3590 dev->watchdog_timeo = 5 * HZ;
3591 dev->netdev_ops = &mvneta_netdev_ops;
3593 dev->ethtool_ops = &mvneta_eth_tool_ops;
3595 pp = netdev_priv(dev);
3596 pp->phy_node = phy_node;
3597 pp->phy_interface = phy_mode;
3599 err = of_property_read_string(dn, "managed", &managed);
3600 pp->use_inband_status = (err == 0 &&
3601 strcmp(managed, "in-band-status") == 0);
3602 pp->cpu_notifier.notifier_call = mvneta_percpu_notifier;
3604 pp->rxq_def = rxq_def;
3606 pp->indir[0] = rxq_def;
3608 pp->clk = devm_clk_get(&pdev->dev, NULL);
3609 if (IS_ERR(pp->clk)) {
3610 err = PTR_ERR(pp->clk);
3611 goto err_put_phy_node;
3614 clk_prepare_enable(pp->clk);
3616 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3617 pp->base = devm_ioremap_resource(&pdev->dev, res);
3618 if (IS_ERR(pp->base)) {
3619 err = PTR_ERR(pp->base);
3623 /* Alloc per-cpu port structure */
3624 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
3630 /* Alloc per-cpu stats */
3631 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
3634 goto err_free_ports;
3637 dt_mac_addr = of_get_mac_address(dn);
3639 mac_from = "device tree";
3640 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
3642 mvneta_get_mac_addr(pp, hw_mac_addr);
3643 if (is_valid_ether_addr(hw_mac_addr)) {
3644 mac_from = "hardware";
3645 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
3647 mac_from = "random";
3648 eth_hw_addr_random(dev);
3652 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
3653 if (tx_csum_limit < 0 ||
3654 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
3655 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
3656 dev_info(&pdev->dev,
3657 "Wrong TX csum limit in DT, set to %dB\n",
3658 MVNETA_TX_CSUM_DEF_SIZE);
3660 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
3661 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
3663 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
3666 pp->tx_csum_limit = tx_csum_limit;
3668 pp->tx_ring_size = MVNETA_MAX_TXD;
3669 pp->rx_ring_size = MVNETA_MAX_RXD;
3672 SET_NETDEV_DEV(dev, &pdev->dev);
3674 err = mvneta_init(&pdev->dev, pp);
3676 goto err_free_stats;
3678 err = mvneta_port_power_up(pp, phy_mode);
3680 dev_err(&pdev->dev, "can't power up port\n");
3681 goto err_free_stats;
3684 dram_target_info = mv_mbus_dram_info();
3685 if (dram_target_info)
3686 mvneta_conf_mbus_windows(pp, dram_target_info);
3688 for_each_present_cpu(cpu) {
3689 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3691 netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT);
3695 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3696 dev->hw_features |= dev->features;
3697 dev->vlan_features |= dev->features;
3698 dev->priv_flags |= IFF_UNICAST_FLT;
3699 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
3701 err = register_netdev(dev);
3703 dev_err(&pdev->dev, "failed to register\n");
3704 goto err_free_stats;
3707 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
3710 platform_set_drvdata(pdev, pp->dev);
3712 if (pp->use_inband_status) {
3713 struct phy_device *phy = of_phy_find_device(dn);
3715 mvneta_fixed_link_update(pp, phy);
3717 put_device(&phy->mdio.dev);
3723 free_percpu(pp->stats);
3725 free_percpu(pp->ports);
3727 clk_disable_unprepare(pp->clk);
3729 of_node_put(phy_node);
3731 irq_dispose_mapping(dev->irq);
3737 /* Device removal routine */
3738 static int mvneta_remove(struct platform_device *pdev)
3740 struct net_device *dev = platform_get_drvdata(pdev);
3741 struct mvneta_port *pp = netdev_priv(dev);
3743 unregister_netdev(dev);
3744 clk_disable_unprepare(pp->clk);
3745 free_percpu(pp->ports);
3746 free_percpu(pp->stats);
3747 irq_dispose_mapping(dev->irq);
3748 of_node_put(pp->phy_node);
3754 static const struct of_device_id mvneta_match[] = {
3755 { .compatible = "marvell,armada-370-neta" },
3756 { .compatible = "marvell,armada-xp-neta" },
3759 MODULE_DEVICE_TABLE(of, mvneta_match);
3761 static struct platform_driver mvneta_driver = {
3762 .probe = mvneta_probe,
3763 .remove = mvneta_remove,
3765 .name = MVNETA_DRIVER_NAME,
3766 .of_match_table = mvneta_match,
3770 module_platform_driver(mvneta_driver);
3772 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
3773 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
3774 MODULE_LICENSE("GPL");
3776 module_param(rxq_number, int, S_IRUGO);
3777 module_param(txq_number, int, S_IRUGO);
3779 module_param(rxq_def, int, S_IRUGO);
3780 module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);