2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/skbuff.h>
18 #include <linux/inetdevice.h>
19 #include <linux/mbus.h>
20 #include <linux/module.h>
21 #include <linux/interrupt.h>
22 #include <linux/cpumask.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_mdio.h>
26 #include <linux/of_net.h>
27 #include <linux/of_address.h>
28 #include <linux/phy.h>
29 #include <linux/clk.h>
30 #include <uapi/linux/ppp_defs.h>
34 /* RX Fifo Registers */
35 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
36 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
37 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
38 #define MVPP2_RX_FIFO_INIT_REG 0x64
40 /* RX DMA Top Registers */
41 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
42 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
43 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
44 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
45 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
46 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
47 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
48 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
49 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
50 #define MVPP2_RXQ_POOL_SHORT_MASK 0x700000
51 #define MVPP2_RXQ_POOL_LONG_OFFS 24
52 #define MVPP2_RXQ_POOL_LONG_MASK 0x7000000
53 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
54 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
55 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
57 /* Parser Registers */
58 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
59 #define MVPP2_PRS_PORT_LU_MAX 0xf
60 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
61 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
62 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
63 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
64 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
65 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
66 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
67 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
68 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
69 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
70 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
71 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
72 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
73 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
74 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
76 /* Classifier Registers */
77 #define MVPP2_CLS_MODE_REG 0x1800
78 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
79 #define MVPP2_CLS_PORT_WAY_REG 0x1810
80 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
81 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
82 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
83 #define MVPP2_CLS_LKP_TBL_REG 0x1818
84 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
85 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
86 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
87 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
88 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
89 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
90 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
91 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
92 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
93 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
94 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
95 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
97 /* Descriptor Manager Top Registers */
98 #define MVPP2_RXQ_NUM_REG 0x2040
99 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
100 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
101 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
102 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
103 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
104 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
105 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
106 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
107 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
108 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
109 #define MVPP2_RXQ_THRESH_REG 0x204c
110 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
111 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
112 #define MVPP2_RXQ_INDEX_REG 0x2050
113 #define MVPP2_TXQ_NUM_REG 0x2080
114 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
115 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
116 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
117 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
118 #define MVPP2_TXQ_THRESH_REG 0x2094
119 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
120 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
121 #define MVPP2_TXQ_INDEX_REG 0x2098
122 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
123 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
124 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
125 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
126 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
127 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
128 #define MVPP2_TXQ_PENDING_REG 0x20a0
129 #define MVPP2_TXQ_PENDING_MASK 0x3fff
130 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
131 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
132 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
133 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
134 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
135 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
136 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
137 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
138 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
139 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
140 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
141 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
142 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
143 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
144 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
145 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
147 /* MBUS bridge registers */
148 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
149 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
150 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
151 #define MVPP2_BASE_ADDR_ENABLE 0x4060
153 /* Interrupt Cause and Mask registers */
154 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
155 #define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
156 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
157 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
158 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
159 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
160 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
161 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
162 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
163 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
164 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
165 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
166 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
167 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
168 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
169 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
170 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
171 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
172 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
173 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
175 /* Buffer Manager registers */
176 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
177 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
178 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
179 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
180 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
181 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
182 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
183 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
184 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
185 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
186 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
187 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
188 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
189 #define MVPP2_BM_START_MASK BIT(0)
190 #define MVPP2_BM_STOP_MASK BIT(1)
191 #define MVPP2_BM_STATE_MASK BIT(4)
192 #define MVPP2_BM_LOW_THRESH_OFFS 8
193 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
194 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
195 MVPP2_BM_LOW_THRESH_OFFS)
196 #define MVPP2_BM_HIGH_THRESH_OFFS 16
197 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
198 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
199 MVPP2_BM_HIGH_THRESH_OFFS)
200 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
201 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
202 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
203 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
204 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
205 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
206 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
207 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
208 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
209 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
210 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
211 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
212 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
213 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
214 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
215 #define MVPP2_BM_MC_RLS_REG 0x64c4
216 #define MVPP2_BM_MC_ID_MASK 0xfff
217 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
219 /* TX Scheduler registers */
220 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
221 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
222 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
223 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
224 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
225 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
226 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
227 #define MVPP2_TXP_MTU_MAX 0x7FFFF
228 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
229 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
230 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
231 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
232 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
233 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
234 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
235 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
236 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
237 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
238 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
239 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
240 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
241 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
243 /* TX general registers */
244 #define MVPP2_TX_SNOOP_REG 0x8800
245 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
246 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
249 #define MVPP2_SRC_ADDR_MIDDLE 0x24
250 #define MVPP2_SRC_ADDR_HIGH 0x28
251 #define MVPP2_PHY_AN_CFG0_REG 0x34
252 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
253 #define MVPP2_MIB_COUNTERS_BASE(port) (0x1000 + ((port) >> 1) * \
254 0x400 + (port) * 0x400)
255 #define MVPP2_MIB_LATE_COLLISION 0x7c
256 #define MVPP2_ISR_SUM_MASK_REG 0x220c
257 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
258 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
260 /* Per-port registers */
261 #define MVPP2_GMAC_CTRL_0_REG 0x0
262 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
263 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
264 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
265 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
266 #define MVPP2_GMAC_CTRL_1_REG 0x4
267 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
268 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
269 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
270 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
271 #define MVPP2_GMAC_SA_LOW_OFFS 7
272 #define MVPP2_GMAC_CTRL_2_REG 0x8
273 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
274 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
275 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
276 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
277 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
278 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
279 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
280 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
281 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
282 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
283 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
284 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
285 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
286 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
287 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
288 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
289 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
290 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
292 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
294 /* Descriptor ring Macros */
295 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
296 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
298 /* Various constants */
301 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
302 #define MVPP2_RX_COAL_PKTS 32
303 #define MVPP2_RX_COAL_USEC 100
305 /* The two bytes Marvell header. Either contains a special value used
306 * by Marvell switches when a specific hardware mode is enabled (not
307 * supported by this driver) or is filled automatically by zeroes on
308 * the RX side. Those two bytes being at the front of the Ethernet
309 * header, they allow to have the IP header aligned on a 4 bytes
310 * boundary automatically: the hardware skips those two bytes on its
313 #define MVPP2_MH_SIZE 2
314 #define MVPP2_ETH_TYPE_LEN 2
315 #define MVPP2_PPPOE_HDR_SIZE 8
316 #define MVPP2_VLAN_TAG_LEN 4
318 /* Lbtd 802.3 type */
319 #define MVPP2_IP_LBDT_TYPE 0xfffa
321 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
322 #define MVPP2_TX_CSUM_MAX_SIZE 9800
324 /* Timeout constants */
325 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
326 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
328 #define MVPP2_TX_MTU_MAX 0x7ffff
330 /* Maximum number of T-CONTs of PON port */
331 #define MVPP2_MAX_TCONT 16
333 /* Maximum number of supported ports */
334 #define MVPP2_MAX_PORTS 4
336 /* Maximum number of TXQs used by single port */
337 #define MVPP2_MAX_TXQ 8
339 /* Maximum number of RXQs used by single port */
340 #define MVPP2_MAX_RXQ 8
342 /* Dfault number of RXQs in use */
343 #define MVPP2_DEFAULT_RXQ 4
345 /* Total number of RXQs available to all ports */
346 #define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
348 /* Max number of Rx descriptors */
349 #define MVPP2_MAX_RXD 128
351 /* Max number of Tx descriptors */
352 #define MVPP2_MAX_TXD 1024
354 /* Amount of Tx descriptors that can be reserved at once by CPU */
355 #define MVPP2_CPU_DESC_CHUNK 64
357 /* Max number of Tx descriptors in each aggregated queue */
358 #define MVPP2_AGGR_TXQ_SIZE 256
360 /* Descriptor aligned size */
361 #define MVPP2_DESC_ALIGNED_SIZE 32
363 /* Descriptor alignment mask */
364 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
366 /* RX FIFO constants */
367 #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
368 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
369 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
371 /* RX buffer constants */
372 #define MVPP2_SKB_SHINFO_SIZE \
373 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
375 #define MVPP2_RX_PKT_SIZE(mtu) \
376 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
377 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
379 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
380 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
381 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
382 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
384 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
386 /* IPv6 max L3 address size */
387 #define MVPP2_MAX_L3_ADDR_SIZE 16
390 #define MVPP2_F_LOOPBACK BIT(0)
392 /* Marvell tag types */
393 enum mvpp2_tag_type {
394 MVPP2_TAG_TYPE_NONE = 0,
395 MVPP2_TAG_TYPE_MH = 1,
396 MVPP2_TAG_TYPE_DSA = 2,
397 MVPP2_TAG_TYPE_EDSA = 3,
398 MVPP2_TAG_TYPE_VLAN = 4,
399 MVPP2_TAG_TYPE_LAST = 5
402 /* Parser constants */
403 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
404 #define MVPP2_PRS_TCAM_WORDS 6
405 #define MVPP2_PRS_SRAM_WORDS 4
406 #define MVPP2_PRS_FLOW_ID_SIZE 64
407 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
408 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
409 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
410 #define MVPP2_PRS_IPV4_HEAD 0x40
411 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
412 #define MVPP2_PRS_IPV4_MC 0xe0
413 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
414 #define MVPP2_PRS_IPV4_BC_MASK 0xff
415 #define MVPP2_PRS_IPV4_IHL 0x5
416 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
417 #define MVPP2_PRS_IPV6_MC 0xff
418 #define MVPP2_PRS_IPV6_MC_MASK 0xff
419 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
420 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
421 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
422 #define MVPP2_PRS_DBL_VLANS_MAX 100
425 * - lookup ID - 4 bits
427 * - additional information - 1 byte
428 * - header data - 8 bytes
429 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
431 #define MVPP2_PRS_AI_BITS 8
432 #define MVPP2_PRS_PORT_MASK 0xff
433 #define MVPP2_PRS_LU_MASK 0xf
434 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
435 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
436 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
437 (((offs) * 2) - ((offs) % 2) + 2)
438 #define MVPP2_PRS_TCAM_AI_BYTE 16
439 #define MVPP2_PRS_TCAM_PORT_BYTE 17
440 #define MVPP2_PRS_TCAM_LU_BYTE 20
441 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
442 #define MVPP2_PRS_TCAM_INV_WORD 5
443 /* Tcam entries ID */
444 #define MVPP2_PE_DROP_ALL 0
445 #define MVPP2_PE_FIRST_FREE_TID 1
446 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
447 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
448 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
449 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
450 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
451 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
452 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
453 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
454 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
455 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
456 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
457 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
458 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
459 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
460 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
461 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
462 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
463 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
464 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
465 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
466 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
467 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
468 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
469 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
470 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
473 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
475 #define MVPP2_PRS_SRAM_RI_OFFS 0
476 #define MVPP2_PRS_SRAM_RI_WORD 0
477 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
478 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
479 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
480 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
481 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
482 #define MVPP2_PRS_SRAM_UDF_OFFS 73
483 #define MVPP2_PRS_SRAM_UDF_BITS 8
484 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
485 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
486 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
487 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
488 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
489 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
490 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
491 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
492 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
493 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
494 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
495 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
496 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
497 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
498 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
499 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
500 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
501 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
502 #define MVPP2_PRS_SRAM_AI_OFFS 90
503 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
504 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
505 #define MVPP2_PRS_SRAM_AI_MASK 0xff
506 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
507 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
508 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
509 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
511 /* Sram result info bits assignment */
512 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
513 #define MVPP2_PRS_RI_DSA_MASK 0x2
514 #define MVPP2_PRS_RI_VLAN_MASK 0xc
515 #define MVPP2_PRS_RI_VLAN_NONE ~(BIT(2) | BIT(3))
516 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
517 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
518 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
519 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
520 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
521 #define MVPP2_PRS_RI_L2_CAST_MASK 0x600
522 #define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10))
523 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
524 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
525 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
526 #define MVPP2_PRS_RI_L3_PROTO_MASK 0x7000
527 #define MVPP2_PRS_RI_L3_UN ~(BIT(12) | BIT(13) | BIT(14))
528 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
529 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
530 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
531 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
532 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
533 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
534 #define MVPP2_PRS_RI_L3_ADDR_MASK 0x18000
535 #define MVPP2_PRS_RI_L3_UCAST ~(BIT(15) | BIT(16))
536 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
537 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
538 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
539 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
540 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
541 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
542 #define MVPP2_PRS_RI_L4_TCP BIT(22)
543 #define MVPP2_PRS_RI_L4_UDP BIT(23)
544 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
545 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
546 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
547 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
549 /* Sram additional info bits assignment */
550 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
551 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
552 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
553 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
554 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
555 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
556 #define MVPP2_PRS_SINGLE_VLAN_AI 0
557 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
560 #define MVPP2_PRS_TAGGED true
561 #define MVPP2_PRS_UNTAGGED false
562 #define MVPP2_PRS_EDSA true
563 #define MVPP2_PRS_DSA false
565 /* MAC entries, shadow udf */
567 MVPP2_PRS_UDF_MAC_DEF,
568 MVPP2_PRS_UDF_MAC_RANGE,
569 MVPP2_PRS_UDF_L2_DEF,
570 MVPP2_PRS_UDF_L2_DEF_COPY,
571 MVPP2_PRS_UDF_L2_USER,
575 enum mvpp2_prs_lookup {
589 enum mvpp2_prs_l3_cast {
590 MVPP2_PRS_L3_UNI_CAST,
591 MVPP2_PRS_L3_MULTI_CAST,
592 MVPP2_PRS_L3_BROAD_CAST
595 /* Classifier constants */
596 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
597 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
598 #define MVPP2_CLS_LKP_TBL_SIZE 64
601 #define MVPP2_BM_POOLS_NUM 8
602 #define MVPP2_BM_LONG_BUF_NUM 1024
603 #define MVPP2_BM_SHORT_BUF_NUM 2048
604 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
605 #define MVPP2_BM_POOL_PTR_ALIGN 128
606 #define MVPP2_BM_SWF_LONG_POOL(port) ((port > 2) ? 2 : port)
607 #define MVPP2_BM_SWF_SHORT_POOL 3
609 /* BM cookie (32 bits) definition */
610 #define MVPP2_BM_COOKIE_POOL_OFFS 8
611 #define MVPP2_BM_COOKIE_CPU_OFFS 24
613 /* BM short pool packet size
614 * These value assure that for SWF the total number
615 * of bytes allocated for each buffer will be 512
617 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
627 /* Shared Packet Processor resources */
629 /* Shared registers' base addresses */
631 void __iomem *lms_base;
637 /* List of pointers to port structures */
638 struct mvpp2_port **port_list;
640 /* Aggregated TXQs */
641 struct mvpp2_tx_queue *aggr_txqs;
644 struct mvpp2_bm_pool *bm_pools;
646 /* PRS shadow table */
647 struct mvpp2_prs_shadow *prs_shadow;
648 /* PRS auxiliary table for double vlan entries control */
649 bool *prs_double_vlans;
655 struct mvpp2_pcpu_stats {
656 struct u64_stats_sync syncp;
670 /* Per-port registers' base address */
673 struct mvpp2_rx_queue **rxqs;
674 struct mvpp2_tx_queue **txqs;
675 struct net_device *dev;
679 u32 pending_cause_rx;
680 struct napi_struct napi;
687 struct mvpp2_pcpu_stats __percpu *stats;
689 struct phy_device *phy_dev;
690 phy_interface_t phy_interface;
691 struct device_node *phy_node;
696 struct mvpp2_bm_pool *pool_long;
697 struct mvpp2_bm_pool *pool_short;
699 /* Index of first port's physical RXQ */
703 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
704 * layout of the transmit and reception DMA descriptors, and their
705 * layout is therefore defined by the hardware design
708 #define MVPP2_TXD_L3_OFF_SHIFT 0
709 #define MVPP2_TXD_IP_HLEN_SHIFT 8
710 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
711 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
712 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
713 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
714 #define MVPP2_TXD_L4_UDP BIT(24)
715 #define MVPP2_TXD_L3_IP6 BIT(26)
716 #define MVPP2_TXD_L_DESC BIT(28)
717 #define MVPP2_TXD_F_DESC BIT(29)
719 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
720 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
721 #define MVPP2_RXD_ERR_CRC 0x0
722 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
723 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
724 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
725 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
726 #define MVPP2_RXD_HWF_SYNC BIT(21)
727 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
728 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
729 #define MVPP2_RXD_L4_TCP BIT(25)
730 #define MVPP2_RXD_L4_UDP BIT(26)
731 #define MVPP2_RXD_L3_IP4 BIT(28)
732 #define MVPP2_RXD_L3_IP6 BIT(30)
733 #define MVPP2_RXD_BUF_HDR BIT(31)
735 struct mvpp2_tx_desc {
736 u32 command; /* Options used by HW for packet transmitting.*/
737 u8 packet_offset; /* the offset from the buffer beginning */
738 u8 phys_txq; /* destination queue ID */
739 u16 data_size; /* data size of transmitted packet in bytes */
740 u32 buf_phys_addr; /* physical addr of transmitted buffer */
741 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
742 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
743 u32 reserved2; /* reserved (for future use) */
746 struct mvpp2_rx_desc {
747 u32 status; /* info about received packet */
748 u16 reserved1; /* parser_info (for future use, PnC) */
749 u16 data_size; /* size of received packet in bytes */
750 u32 buf_phys_addr; /* physical address of the buffer */
751 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
752 u16 reserved2; /* gem_port_id (for future use, PON) */
753 u16 reserved3; /* csum_l4 (for future use, PnC) */
754 u8 reserved4; /* bm_qset (for future use, BM) */
756 u16 reserved6; /* classify_info (for future use, PnC) */
757 u32 reserved7; /* flow_id (for future use, PnC) */
761 /* Per-CPU Tx queue control */
762 struct mvpp2_txq_pcpu {
765 /* Number of Tx DMA descriptors in the descriptor ring */
768 /* Number of currently used Tx DMA descriptor in the
773 /* Number of Tx DMA descriptors reserved for each CPU */
776 /* Array of transmitted skb */
777 struct sk_buff **tx_skb;
779 /* Index of last TX DMA descriptor that was inserted */
782 /* Index of the TX DMA descriptor to be cleaned up */
786 struct mvpp2_tx_queue {
787 /* Physical number of this Tx queue */
790 /* Logical number of this Tx queue */
793 /* Number of Tx DMA descriptors in the descriptor ring */
796 /* Number of currently used Tx DMA descriptor in the descriptor ring */
799 /* Per-CPU control of physical Tx queues */
800 struct mvpp2_txq_pcpu __percpu *pcpu;
802 /* Array of transmitted skb */
803 struct sk_buff **tx_skb;
807 /* Virtual address of thex Tx DMA descriptors array */
808 struct mvpp2_tx_desc *descs;
810 /* DMA address of the Tx DMA descriptors array */
811 dma_addr_t descs_phys;
813 /* Index of the last Tx DMA descriptor */
816 /* Index of the next Tx DMA descriptor to process */
817 int next_desc_to_proc;
820 struct mvpp2_rx_queue {
821 /* RX queue number, in the range 0-31 for physical RXQs */
824 /* Num of rx descriptors in the rx descriptor ring */
830 /* Virtual address of the RX DMA descriptors array */
831 struct mvpp2_rx_desc *descs;
833 /* DMA address of the RX DMA descriptors array */
834 dma_addr_t descs_phys;
836 /* Index of the last RX DMA descriptor */
839 /* Index of the next RX DMA descriptor to process */
840 int next_desc_to_proc;
842 /* ID of port to which physical RXQ is mapped */
845 /* Port's logic RXQ number to which physical RXQ is mapped */
849 union mvpp2_prs_tcam_entry {
850 u32 word[MVPP2_PRS_TCAM_WORDS];
851 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
854 union mvpp2_prs_sram_entry {
855 u32 word[MVPP2_PRS_SRAM_WORDS];
856 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
859 struct mvpp2_prs_entry {
861 union mvpp2_prs_tcam_entry tcam;
862 union mvpp2_prs_sram_entry sram;
865 struct mvpp2_prs_shadow {
872 /* User defined offset */
880 struct mvpp2_cls_flow_entry {
882 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
885 struct mvpp2_cls_lookup_entry {
891 struct mvpp2_bm_pool {
892 /* Pool number in the range 0-7 */
894 enum mvpp2_bm_type type;
896 /* Buffer Pointers Pool External (BPPE) size */
898 /* Number of buffers for this pool */
900 /* Pool buffer size */
905 /* BPPE virtual base address */
907 /* BPPE physical base address */
908 dma_addr_t phys_addr;
910 /* Ports using BM pool */
913 /* Occupied buffers indicator */
920 struct mvpp2_buff_hdr {
921 u32 next_buff_phys_addr;
922 u32 next_buff_virt_addr;
925 u8 reserved1; /* bm_qset (for future use, BM) */
928 /* Buffer header info bits */
929 #define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff
930 #define MVPP2_B_HDR_INFO_MC_ID(info) ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
931 #define MVPP2_B_HDR_INFO_LAST_OFFS 12
932 #define MVPP2_B_HDR_INFO_LAST_MASK BIT(12)
933 #define MVPP2_B_HDR_INFO_IS_LAST(info) \
934 ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
936 /* Static declaractions */
938 /* Number of RXQs used by single port */
939 static int rxq_number = MVPP2_DEFAULT_RXQ;
940 /* Number of TXQs used by single port */
941 static int txq_number = MVPP2_MAX_TXQ;
943 #define MVPP2_DRIVER_NAME "mvpp2"
944 #define MVPP2_DRIVER_VERSION "1.0"
946 /* Utility/helper methods */
948 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
950 writel(data, priv->base + offset);
953 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
955 return readl(priv->base + offset);
958 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
960 txq_pcpu->txq_get_index++;
961 if (txq_pcpu->txq_get_index == txq_pcpu->size)
962 txq_pcpu->txq_get_index = 0;
965 static void mvpp2_txq_inc_put(struct mvpp2_txq_pcpu *txq_pcpu,
968 txq_pcpu->tx_skb[txq_pcpu->txq_put_index] = skb;
969 txq_pcpu->txq_put_index++;
970 if (txq_pcpu->txq_put_index == txq_pcpu->size)
971 txq_pcpu->txq_put_index = 0;
974 /* Get number of physical egress port */
975 static inline int mvpp2_egress_port(struct mvpp2_port *port)
977 return MVPP2_MAX_TCONT + port->id;
980 /* Get number of physical TXQ */
981 static inline int mvpp2_txq_phys(int port, int txq)
983 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
986 /* Parser configuration routines */
988 /* Update parser tcam and sram hw entries */
989 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
993 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
996 /* Clear entry invalidation bit */
997 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
999 /* Write tcam index - indirect access */
1000 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1001 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1002 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1004 /* Write sram index - indirect access */
1005 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1006 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1007 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1012 /* Read tcam entry from hw */
1013 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1017 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1020 /* Write tcam index - indirect access */
1021 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1023 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1024 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1025 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1026 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1028 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1029 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1031 /* Write sram index - indirect access */
1032 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1033 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1034 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1039 /* Invalidate tcam hw entry */
1040 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1042 /* Write index - indirect access */
1043 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1044 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1045 MVPP2_PRS_TCAM_INV_MASK);
1048 /* Enable shadow table entry and set its lookup ID */
1049 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1051 priv->prs_shadow[index].valid = true;
1052 priv->prs_shadow[index].lu = lu;
1055 /* Update ri fields in shadow table entry */
1056 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1057 unsigned int ri, unsigned int ri_mask)
1059 priv->prs_shadow[index].ri_mask = ri_mask;
1060 priv->prs_shadow[index].ri = ri;
1063 /* Update lookup field in tcam sw entry */
1064 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1066 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1068 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1069 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1072 /* Update mask for single port in tcam sw entry */
1073 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1074 unsigned int port, bool add)
1076 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1079 pe->tcam.byte[enable_off] &= ~(1 << port);
1081 pe->tcam.byte[enable_off] |= 1 << port;
1084 /* Update port map in tcam sw entry */
1085 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1088 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1089 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1091 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1092 pe->tcam.byte[enable_off] &= ~port_mask;
1093 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1096 /* Obtain port map from tcam sw entry */
1097 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1099 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1101 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1104 /* Set byte of data and its enable bits in tcam sw entry */
1105 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1106 unsigned int offs, unsigned char byte,
1107 unsigned char enable)
1109 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1110 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1113 /* Get byte of data and its enable bits from tcam sw entry */
1114 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1115 unsigned int offs, unsigned char *byte,
1116 unsigned char *enable)
1118 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1119 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1122 /* Compare tcam data bytes with a pattern */
1123 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs,
1126 int off = MVPP2_PRS_TCAM_DATA_BYTE(offs);
1129 tcam_data = (8 << pe->tcam.byte[off + 1]) | pe->tcam.byte[off];
1130 if (tcam_data != data)
1135 /* Update ai bits in tcam sw entry */
1136 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe,
1137 unsigned int bits, unsigned int enable)
1139 int i, ai_idx = MVPP2_PRS_TCAM_AI_BYTE;
1141 for (i = 0; i < MVPP2_PRS_AI_BITS; i++) {
1143 if (!(enable & BIT(i)))
1147 pe->tcam.byte[ai_idx] |= 1 << i;
1149 pe->tcam.byte[ai_idx] &= ~(1 << i);
1152 pe->tcam.byte[MVPP2_PRS_TCAM_EN_OFFS(ai_idx)] |= enable;
1155 /* Get ai bits from tcam sw entry */
1156 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe)
1158 return pe->tcam.byte[MVPP2_PRS_TCAM_AI_BYTE];
1161 /* Set ethertype in tcam sw entry */
1162 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1163 unsigned short ethertype)
1165 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1166 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1169 /* Set bits in sram sw entry */
1170 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1173 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1176 /* Clear bits in sram sw entry */
1177 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1180 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1183 /* Update ri bits in sram sw entry */
1184 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1185 unsigned int bits, unsigned int mask)
1189 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1190 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1192 if (!(mask & BIT(i)))
1196 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1198 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1200 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1204 /* Obtain ri bits from sram sw entry */
1205 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe)
1207 return pe->sram.word[MVPP2_PRS_SRAM_RI_WORD];
1210 /* Update ai bits in sram sw entry */
1211 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1212 unsigned int bits, unsigned int mask)
1215 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1217 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1219 if (!(mask & BIT(i)))
1223 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1225 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1227 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1231 /* Read ai bits from sram sw entry */
1232 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1235 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1236 int ai_en_off = ai_off + 1;
1237 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1239 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1240 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1245 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1248 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1251 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1253 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1254 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1255 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1258 /* In the sram sw entry set sign and value of the next lookup offset
1259 * and the offset value generated to the classifier
1261 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1266 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1269 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1273 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1274 (unsigned char)shift;
1276 /* Reset and set operation */
1277 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1278 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1279 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1281 /* Set base offset as current */
1282 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1285 /* In the sram sw entry set sign and value of the user defined offset
1286 * generated to the classifier
1288 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1289 unsigned int type, int offset,
1294 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1295 offset = 0 - offset;
1297 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1301 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1302 MVPP2_PRS_SRAM_UDF_MASK);
1303 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1304 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1305 MVPP2_PRS_SRAM_UDF_BITS)] &=
1306 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1307 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1308 MVPP2_PRS_SRAM_UDF_BITS)] |=
1309 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1311 /* Set offset type */
1312 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1313 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1314 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1316 /* Set offset operation */
1317 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1318 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1319 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1321 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1322 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1323 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1324 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1326 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1327 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1328 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1330 /* Set base offset as current */
1331 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1334 /* Find parser flow entry */
1335 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1337 struct mvpp2_prs_entry *pe;
1340 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1343 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1345 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1346 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1349 if (!priv->prs_shadow[tid].valid ||
1350 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1354 mvpp2_prs_hw_read(priv, pe);
1355 bits = mvpp2_prs_sram_ai_get(pe);
1357 /* Sram store classification lookup ID in AI bits [5:0] */
1358 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1366 /* Return first free tcam index, seeking from start to end */
1367 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1375 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1376 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1378 for (tid = start; tid <= end; tid++) {
1379 if (!priv->prs_shadow[tid].valid)
1386 /* Enable/disable dropping all mac da's */
1387 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1389 struct mvpp2_prs_entry pe;
1391 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1392 /* Entry exist - update port only */
1393 pe.index = MVPP2_PE_DROP_ALL;
1394 mvpp2_prs_hw_read(priv, &pe);
1396 /* Entry doesn't exist - create new */
1397 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1398 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1399 pe.index = MVPP2_PE_DROP_ALL;
1401 /* Non-promiscuous mode for all ports - DROP unknown packets */
1402 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1403 MVPP2_PRS_RI_DROP_MASK);
1405 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1406 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1408 /* Update shadow table */
1409 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1411 /* Mask all ports */
1412 mvpp2_prs_tcam_port_map_set(&pe, 0);
1415 /* Update port mask */
1416 mvpp2_prs_tcam_port_set(&pe, port, add);
1418 mvpp2_prs_hw_write(priv, &pe);
1421 /* Set port to promiscuous mode */
1422 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1424 struct mvpp2_prs_entry pe;
1426 /* Promiscous mode - Accept unknown packets */
1428 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1429 /* Entry exist - update port only */
1430 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1431 mvpp2_prs_hw_read(priv, &pe);
1433 /* Entry doesn't exist - create new */
1434 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1435 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1436 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1438 /* Continue - set next lookup */
1439 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1441 /* Set result info bits */
1442 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1443 MVPP2_PRS_RI_L2_CAST_MASK);
1445 /* Shift to ethertype */
1446 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1447 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1449 /* Mask all ports */
1450 mvpp2_prs_tcam_port_map_set(&pe, 0);
1452 /* Update shadow table */
1453 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1456 /* Update port mask */
1457 mvpp2_prs_tcam_port_set(&pe, port, add);
1459 mvpp2_prs_hw_write(priv, &pe);
1462 /* Accept multicast */
1463 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1466 struct mvpp2_prs_entry pe;
1467 unsigned char da_mc;
1469 /* Ethernet multicast address first byte is
1470 * 0x01 for IPv4 and 0x33 for IPv6
1472 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1474 if (priv->prs_shadow[index].valid) {
1475 /* Entry exist - update port only */
1477 mvpp2_prs_hw_read(priv, &pe);
1479 /* Entry doesn't exist - create new */
1480 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1481 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1484 /* Continue - set next lookup */
1485 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1487 /* Set result info bits */
1488 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1489 MVPP2_PRS_RI_L2_CAST_MASK);
1491 /* Update tcam entry data first byte */
1492 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1494 /* Shift to ethertype */
1495 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1496 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1498 /* Mask all ports */
1499 mvpp2_prs_tcam_port_map_set(&pe, 0);
1501 /* Update shadow table */
1502 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1505 /* Update port mask */
1506 mvpp2_prs_tcam_port_set(&pe, port, add);
1508 mvpp2_prs_hw_write(priv, &pe);
1511 /* Set entry for dsa packets */
1512 static void mvpp2_prs_dsa_tag_set(struct mvpp2 *priv, int port, bool add,
1513 bool tagged, bool extend)
1515 struct mvpp2_prs_entry pe;
1519 tid = tagged ? MVPP2_PE_EDSA_TAGGED : MVPP2_PE_EDSA_UNTAGGED;
1522 tid = tagged ? MVPP2_PE_DSA_TAGGED : MVPP2_PE_DSA_UNTAGGED;
1526 if (priv->prs_shadow[tid].valid) {
1527 /* Entry exist - update port only */
1529 mvpp2_prs_hw_read(priv, &pe);
1531 /* Entry doesn't exist - create new */
1532 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1533 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
1536 /* Shift 4 bytes if DSA tag or 8 bytes in case of EDSA tag*/
1537 mvpp2_prs_sram_shift_set(&pe, shift,
1538 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1540 /* Update shadow table */
1541 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);
1544 /* Set tagged bit in DSA tag */
1545 mvpp2_prs_tcam_data_byte_set(&pe, 0,
1546 MVPP2_PRS_TCAM_DSA_TAGGED_BIT,
1547 MVPP2_PRS_TCAM_DSA_TAGGED_BIT);
1548 /* Clear all ai bits for next iteration */
1549 mvpp2_prs_sram_ai_update(&pe, 0,
1550 MVPP2_PRS_SRAM_AI_MASK);
1551 /* If packet is tagged continue check vlans */
1552 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
1554 /* Set result info bits to 'no vlans' */
1555 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
1556 MVPP2_PRS_RI_VLAN_MASK);
1557 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
1560 /* Mask all ports */
1561 mvpp2_prs_tcam_port_map_set(&pe, 0);
1564 /* Update port mask */
1565 mvpp2_prs_tcam_port_set(&pe, port, add);
1567 mvpp2_prs_hw_write(priv, &pe);
1570 /* Set entry for dsa ethertype */
1571 static void mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2 *priv, int port,
1572 bool add, bool tagged, bool extend)
1574 struct mvpp2_prs_entry pe;
1575 int tid, shift, port_mask;
1578 tid = tagged ? MVPP2_PE_ETYPE_EDSA_TAGGED :
1579 MVPP2_PE_ETYPE_EDSA_UNTAGGED;
1583 tid = tagged ? MVPP2_PE_ETYPE_DSA_TAGGED :
1584 MVPP2_PE_ETYPE_DSA_UNTAGGED;
1585 port_mask = MVPP2_PRS_PORT_MASK;
1589 if (priv->prs_shadow[tid].valid) {
1590 /* Entry exist - update port only */
1592 mvpp2_prs_hw_read(priv, &pe);
1594 /* Entry doesn't exist - create new */
1595 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1596 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
1600 mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA);
1601 mvpp2_prs_match_etype(&pe, 2, 0);
1603 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK,
1604 MVPP2_PRS_RI_DSA_MASK);
1605 /* Shift ethertype + 2 byte reserved + tag*/
1606 mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift,
1607 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1609 /* Update shadow table */
1610 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);
1613 /* Set tagged bit in DSA tag */
1614 mvpp2_prs_tcam_data_byte_set(&pe,
1615 MVPP2_ETH_TYPE_LEN + 2 + 3,
1616 MVPP2_PRS_TCAM_DSA_TAGGED_BIT,
1617 MVPP2_PRS_TCAM_DSA_TAGGED_BIT);
1618 /* Clear all ai bits for next iteration */
1619 mvpp2_prs_sram_ai_update(&pe, 0,
1620 MVPP2_PRS_SRAM_AI_MASK);
1621 /* If packet is tagged continue check vlans */
1622 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
1624 /* Set result info bits to 'no vlans' */
1625 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
1626 MVPP2_PRS_RI_VLAN_MASK);
1627 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
1629 /* Mask/unmask all ports, depending on dsa type */
1630 mvpp2_prs_tcam_port_map_set(&pe, port_mask);
1633 /* Update port mask */
1634 mvpp2_prs_tcam_port_set(&pe, port, add);
1636 mvpp2_prs_hw_write(priv, &pe);
1639 /* Search for existing single/triple vlan entry */
1640 static struct mvpp2_prs_entry *mvpp2_prs_vlan_find(struct mvpp2 *priv,
1641 unsigned short tpid, int ai)
1643 struct mvpp2_prs_entry *pe;
1646 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1649 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN);
1651 /* Go through the all entries with MVPP2_PRS_LU_VLAN */
1652 for (tid = MVPP2_PE_FIRST_FREE_TID;
1653 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
1654 unsigned int ri_bits, ai_bits;
1657 if (!priv->prs_shadow[tid].valid ||
1658 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN)
1663 mvpp2_prs_hw_read(priv, pe);
1664 match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid));
1669 ri_bits = mvpp2_prs_sram_ri_get(pe);
1670 ri_bits &= MVPP2_PRS_RI_VLAN_MASK;
1672 /* Get current ai value from tcam */
1673 ai_bits = mvpp2_prs_tcam_ai_get(pe);
1674 /* Clear double vlan bit */
1675 ai_bits &= ~MVPP2_PRS_DBL_VLAN_AI_BIT;
1680 if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE ||
1681 ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE)
1689 /* Add/update single/triple vlan entry */
1690 static int mvpp2_prs_vlan_add(struct mvpp2 *priv, unsigned short tpid, int ai,
1691 unsigned int port_map)
1693 struct mvpp2_prs_entry *pe;
1696 pe = mvpp2_prs_vlan_find(priv, tpid, ai);
1699 /* Create new tcam entry */
1700 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_LAST_FREE_TID,
1701 MVPP2_PE_FIRST_FREE_TID);
1705 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1709 /* Get last double vlan tid */
1710 for (tid_aux = MVPP2_PE_LAST_FREE_TID;
1711 tid_aux >= MVPP2_PE_FIRST_FREE_TID; tid_aux--) {
1712 unsigned int ri_bits;
1714 if (!priv->prs_shadow[tid_aux].valid ||
1715 priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN)
1718 pe->index = tid_aux;
1719 mvpp2_prs_hw_read(priv, pe);
1720 ri_bits = mvpp2_prs_sram_ri_get(pe);
1721 if ((ri_bits & MVPP2_PRS_RI_VLAN_MASK) ==
1722 MVPP2_PRS_RI_VLAN_DOUBLE)
1729 memset(pe, 0 , sizeof(struct mvpp2_prs_entry));
1730 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN);
1733 mvpp2_prs_match_etype(pe, 0, tpid);
1735 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_L2);
1736 /* Shift 4 bytes - skip 1 vlan tag */
1737 mvpp2_prs_sram_shift_set(pe, MVPP2_VLAN_TAG_LEN,
1738 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1739 /* Clear all ai bits for next iteration */
1740 mvpp2_prs_sram_ai_update(pe, 0, MVPP2_PRS_SRAM_AI_MASK);
1742 if (ai == MVPP2_PRS_SINGLE_VLAN_AI) {
1743 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_SINGLE,
1744 MVPP2_PRS_RI_VLAN_MASK);
1746 ai |= MVPP2_PRS_DBL_VLAN_AI_BIT;
1747 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_TRIPLE,
1748 MVPP2_PRS_RI_VLAN_MASK);
1750 mvpp2_prs_tcam_ai_update(pe, ai, MVPP2_PRS_SRAM_AI_MASK);
1752 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN);
1754 /* Update ports' mask */
1755 mvpp2_prs_tcam_port_map_set(pe, port_map);
1757 mvpp2_prs_hw_write(priv, pe);
1764 /* Get first free double vlan ai number */
1765 static int mvpp2_prs_double_vlan_ai_free_get(struct mvpp2 *priv)
1769 for (i = 1; i < MVPP2_PRS_DBL_VLANS_MAX; i++) {
1770 if (!priv->prs_double_vlans[i])
1777 /* Search for existing double vlan entry */
1778 static struct mvpp2_prs_entry *mvpp2_prs_double_vlan_find(struct mvpp2 *priv,
1779 unsigned short tpid1,
1780 unsigned short tpid2)
1782 struct mvpp2_prs_entry *pe;
1785 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1788 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN);
1790 /* Go through the all entries with MVPP2_PRS_LU_VLAN */
1791 for (tid = MVPP2_PE_FIRST_FREE_TID;
1792 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
1793 unsigned int ri_mask;
1796 if (!priv->prs_shadow[tid].valid ||
1797 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN)
1801 mvpp2_prs_hw_read(priv, pe);
1803 match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid1))
1804 && mvpp2_prs_tcam_data_cmp(pe, 4, swab16(tpid2));
1809 ri_mask = mvpp2_prs_sram_ri_get(pe) & MVPP2_PRS_RI_VLAN_MASK;
1810 if (ri_mask == MVPP2_PRS_RI_VLAN_DOUBLE)
1818 /* Add or update double vlan entry */
1819 static int mvpp2_prs_double_vlan_add(struct mvpp2 *priv, unsigned short tpid1,
1820 unsigned short tpid2,
1821 unsigned int port_map)
1823 struct mvpp2_prs_entry *pe;
1824 int tid_aux, tid, ai;
1826 pe = mvpp2_prs_double_vlan_find(priv, tpid1, tpid2);
1829 /* Create new tcam entry */
1830 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1831 MVPP2_PE_LAST_FREE_TID);
1835 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1839 /* Set ai value for new double vlan entry */
1840 ai = mvpp2_prs_double_vlan_ai_free_get(priv);
1844 /* Get first single/triple vlan tid */
1845 for (tid_aux = MVPP2_PE_FIRST_FREE_TID;
1846 tid_aux <= MVPP2_PE_LAST_FREE_TID; tid_aux++) {
1847 unsigned int ri_bits;
1849 if (!priv->prs_shadow[tid_aux].valid ||
1850 priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN)
1853 pe->index = tid_aux;
1854 mvpp2_prs_hw_read(priv, pe);
1855 ri_bits = mvpp2_prs_sram_ri_get(pe);
1856 ri_bits &= MVPP2_PRS_RI_VLAN_MASK;
1857 if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE ||
1858 ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE)
1865 memset(pe, 0, sizeof(struct mvpp2_prs_entry));
1866 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN);
1869 priv->prs_double_vlans[ai] = true;
1871 mvpp2_prs_match_etype(pe, 0, tpid1);
1872 mvpp2_prs_match_etype(pe, 4, tpid2);
1874 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_VLAN);
1875 /* Shift 8 bytes - skip 2 vlan tags */
1876 mvpp2_prs_sram_shift_set(pe, 2 * MVPP2_VLAN_TAG_LEN,
1877 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1878 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_DOUBLE,
1879 MVPP2_PRS_RI_VLAN_MASK);
1880 mvpp2_prs_sram_ai_update(pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT,
1881 MVPP2_PRS_SRAM_AI_MASK);
1883 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN);
1886 /* Update ports' mask */
1887 mvpp2_prs_tcam_port_map_set(pe, port_map);
1888 mvpp2_prs_hw_write(priv, pe);
1894 /* IPv4 header parsing for fragmentation and L4 offset */
1895 static int mvpp2_prs_ip4_proto(struct mvpp2 *priv, unsigned short proto,
1896 unsigned int ri, unsigned int ri_mask)
1898 struct mvpp2_prs_entry pe;
1901 if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) &&
1902 (proto != IPPROTO_IGMP))
1905 /* Fragmented packet */
1906 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1907 MVPP2_PE_LAST_FREE_TID);
1911 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1912 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
1915 /* Set next lu to IPv4 */
1916 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1917 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1919 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
1920 sizeof(struct iphdr) - 4,
1921 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1922 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
1923 MVPP2_PRS_IPV4_DIP_AI_BIT);
1924 mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_MASK,
1925 ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK);
1927 mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK);
1928 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
1929 /* Unmask all ports */
1930 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1932 /* Update shadow table and hw entry */
1933 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1934 mvpp2_prs_hw_write(priv, &pe);
1936 /* Not fragmented packet */
1937 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1938 MVPP2_PE_LAST_FREE_TID);
1943 /* Clear ri before updating */
1944 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
1945 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
1946 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
1948 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, MVPP2_PRS_TCAM_PROTO_MASK_L);
1949 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, MVPP2_PRS_TCAM_PROTO_MASK);
1951 /* Update shadow table and hw entry */
1952 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1953 mvpp2_prs_hw_write(priv, &pe);
1958 /* IPv4 L3 multicast or broadcast */
1959 static int mvpp2_prs_ip4_cast(struct mvpp2 *priv, unsigned short l3_cast)
1961 struct mvpp2_prs_entry pe;
1964 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1965 MVPP2_PE_LAST_FREE_TID);
1969 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1970 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
1974 case MVPP2_PRS_L3_MULTI_CAST:
1975 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC,
1976 MVPP2_PRS_IPV4_MC_MASK);
1977 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,
1978 MVPP2_PRS_RI_L3_ADDR_MASK);
1980 case MVPP2_PRS_L3_BROAD_CAST:
1981 mask = MVPP2_PRS_IPV4_BC_MASK;
1982 mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask);
1983 mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask);
1984 mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask);
1985 mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask);
1986 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST,
1987 MVPP2_PRS_RI_L3_ADDR_MASK);
1993 /* Finished: go to flowid generation */
1994 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1995 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1997 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
1998 MVPP2_PRS_IPV4_DIP_AI_BIT);
1999 /* Unmask all ports */
2000 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2002 /* Update shadow table and hw entry */
2003 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2004 mvpp2_prs_hw_write(priv, &pe);
2009 /* Set entries for protocols over IPv6 */
2010 static int mvpp2_prs_ip6_proto(struct mvpp2 *priv, unsigned short proto,
2011 unsigned int ri, unsigned int ri_mask)
2013 struct mvpp2_prs_entry pe;
2016 if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) &&
2017 (proto != IPPROTO_ICMPV6) && (proto != IPPROTO_IPIP))
2020 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2021 MVPP2_PE_LAST_FREE_TID);
2025 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2026 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2029 /* Finished: go to flowid generation */
2030 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2031 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2032 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
2033 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
2034 sizeof(struct ipv6hdr) - 6,
2035 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2037 mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK);
2038 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2039 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2040 /* Unmask all ports */
2041 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2044 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
2045 mvpp2_prs_hw_write(priv, &pe);
2050 /* IPv6 L3 multicast entry */
2051 static int mvpp2_prs_ip6_cast(struct mvpp2 *priv, unsigned short l3_cast)
2053 struct mvpp2_prs_entry pe;
2056 if (l3_cast != MVPP2_PRS_L3_MULTI_CAST)
2059 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2060 MVPP2_PE_LAST_FREE_TID);
2064 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2065 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2068 /* Finished: go to flowid generation */
2069 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2070 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,
2071 MVPP2_PRS_RI_L3_ADDR_MASK);
2072 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2073 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2074 /* Shift back to IPv6 NH */
2075 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2077 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC,
2078 MVPP2_PRS_IPV6_MC_MASK);
2079 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2080 /* Unmask all ports */
2081 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2083 /* Update shadow table and hw entry */
2084 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
2085 mvpp2_prs_hw_write(priv, &pe);
2090 /* Parser per-port initialization */
2091 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
2092 int lu_max, int offset)
2097 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
2098 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
2099 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
2100 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
2102 /* Set maximum number of loops for packet received from port */
2103 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
2104 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
2105 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
2106 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
2108 /* Set initial offset for packet header extraction for the first
2111 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
2112 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
2113 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
2114 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
2117 /* Default flow entries initialization for all ports */
2118 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
2120 struct mvpp2_prs_entry pe;
2123 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
2124 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2125 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2126 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
2128 /* Mask all ports */
2129 mvpp2_prs_tcam_port_map_set(&pe, 0);
2132 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
2133 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2135 /* Update shadow table and hw entry */
2136 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
2137 mvpp2_prs_hw_write(priv, &pe);
2141 /* Set default entry for Marvell Header field */
2142 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
2144 struct mvpp2_prs_entry pe;
2146 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2148 pe.index = MVPP2_PE_MH_DEFAULT;
2149 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
2150 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
2151 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2152 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
2154 /* Unmask all ports */
2155 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2157 /* Update shadow table and hw entry */
2158 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
2159 mvpp2_prs_hw_write(priv, &pe);
2162 /* Set default entires (place holder) for promiscuous, non-promiscuous and
2163 * multicast MAC addresses
2165 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
2167 struct mvpp2_prs_entry pe;
2169 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2171 /* Non-promiscuous mode for all ports - DROP unknown packets */
2172 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
2173 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
2175 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
2176 MVPP2_PRS_RI_DROP_MASK);
2177 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2178 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2180 /* Unmask all ports */
2181 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2183 /* Update shadow table and hw entry */
2184 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
2185 mvpp2_prs_hw_write(priv, &pe);
2187 /* place holders only - no ports */
2188 mvpp2_prs_mac_drop_all_set(priv, 0, false);
2189 mvpp2_prs_mac_promisc_set(priv, 0, false);
2190 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
2191 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
2194 /* Set default entries for various types of dsa packets */
2195 static void mvpp2_prs_dsa_init(struct mvpp2 *priv)
2197 struct mvpp2_prs_entry pe;
2199 /* None tagged EDSA entry - place holder */
2200 mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED,
2203 /* Tagged EDSA entry - place holder */
2204 mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
2206 /* None tagged DSA entry - place holder */
2207 mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED,
2210 /* Tagged DSA entry - place holder */
2211 mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
2213 /* None tagged EDSA ethertype entry - place holder*/
2214 mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false,
2215 MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
2217 /* Tagged EDSA ethertype entry - place holder*/
2218 mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false,
2219 MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
2221 /* None tagged DSA ethertype entry */
2222 mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true,
2223 MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
2225 /* Tagged DSA ethertype entry */
2226 mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true,
2227 MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
2229 /* Set default entry, in case DSA or EDSA tag not found */
2230 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2231 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
2232 pe.index = MVPP2_PE_DSA_DEFAULT;
2233 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
2236 mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2237 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
2239 /* Clear all sram ai bits for next iteration */
2240 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
2242 /* Unmask all ports */
2243 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2245 mvpp2_prs_hw_write(priv, &pe);
2248 /* Match basic ethertypes */
2249 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
2251 struct mvpp2_prs_entry pe;
2254 /* Ethertype: PPPoE */
2255 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2256 MVPP2_PE_LAST_FREE_TID);
2260 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2261 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2264 mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES);
2266 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
2267 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2268 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2269 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
2270 MVPP2_PRS_RI_PPPOE_MASK);
2272 /* Update shadow table and hw entry */
2273 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2274 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2275 priv->prs_shadow[pe.index].finish = false;
2276 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
2277 MVPP2_PRS_RI_PPPOE_MASK);
2278 mvpp2_prs_hw_write(priv, &pe);
2280 /* Ethertype: ARP */
2281 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2282 MVPP2_PE_LAST_FREE_TID);
2286 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2287 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2290 mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP);
2292 /* Generate flow in the next iteration*/
2293 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2294 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2295 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
2296 MVPP2_PRS_RI_L3_PROTO_MASK);
2298 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2300 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2302 /* Update shadow table and hw entry */
2303 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2304 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2305 priv->prs_shadow[pe.index].finish = true;
2306 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
2307 MVPP2_PRS_RI_L3_PROTO_MASK);
2308 mvpp2_prs_hw_write(priv, &pe);
2310 /* Ethertype: LBTD */
2311 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2312 MVPP2_PE_LAST_FREE_TID);
2316 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2317 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2320 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
2322 /* Generate flow in the next iteration*/
2323 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2324 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2325 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2326 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2327 MVPP2_PRS_RI_CPU_CODE_MASK |
2328 MVPP2_PRS_RI_UDF3_MASK);
2330 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2332 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2334 /* Update shadow table and hw entry */
2335 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2336 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2337 priv->prs_shadow[pe.index].finish = true;
2338 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2339 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2340 MVPP2_PRS_RI_CPU_CODE_MASK |
2341 MVPP2_PRS_RI_UDF3_MASK);
2342 mvpp2_prs_hw_write(priv, &pe);
2344 /* Ethertype: IPv4 without options */
2345 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2346 MVPP2_PE_LAST_FREE_TID);
2350 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2351 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2354 mvpp2_prs_match_etype(&pe, 0, ETH_P_IP);
2355 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2356 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2357 MVPP2_PRS_IPV4_HEAD_MASK |
2358 MVPP2_PRS_IPV4_IHL_MASK);
2360 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2361 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2362 MVPP2_PRS_RI_L3_PROTO_MASK);
2363 /* Skip eth_type + 4 bytes of IP header */
2364 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2365 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2367 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2369 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2371 /* Update shadow table and hw entry */
2372 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2373 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2374 priv->prs_shadow[pe.index].finish = false;
2375 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
2376 MVPP2_PRS_RI_L3_PROTO_MASK);
2377 mvpp2_prs_hw_write(priv, &pe);
2379 /* Ethertype: IPv4 with options */
2380 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2381 MVPP2_PE_LAST_FREE_TID);
2387 /* Clear tcam data before updating */
2388 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
2389 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
2391 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2392 MVPP2_PRS_IPV4_HEAD,
2393 MVPP2_PRS_IPV4_HEAD_MASK);
2395 /* Clear ri before updating */
2396 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2397 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2398 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2399 MVPP2_PRS_RI_L3_PROTO_MASK);
2401 /* Update shadow table and hw entry */
2402 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2403 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2404 priv->prs_shadow[pe.index].finish = false;
2405 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
2406 MVPP2_PRS_RI_L3_PROTO_MASK);
2407 mvpp2_prs_hw_write(priv, &pe);
2409 /* Ethertype: IPv6 without options */
2410 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2411 MVPP2_PE_LAST_FREE_TID);
2415 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2416 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2419 mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6);
2421 /* Skip DIP of IPV6 header */
2422 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2423 MVPP2_MAX_L3_ADDR_SIZE,
2424 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2425 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2426 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2427 MVPP2_PRS_RI_L3_PROTO_MASK);
2429 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2431 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2433 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2434 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2435 priv->prs_shadow[pe.index].finish = false;
2436 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2437 MVPP2_PRS_RI_L3_PROTO_MASK);
2438 mvpp2_prs_hw_write(priv, &pe);
2440 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2441 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2442 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2443 pe.index = MVPP2_PE_ETH_TYPE_UN;
2445 /* Unmask all ports */
2446 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2448 /* Generate flow in the next iteration*/
2449 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2450 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2451 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2452 MVPP2_PRS_RI_L3_PROTO_MASK);
2453 /* Set L3 offset even it's unknown L3 */
2454 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2456 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2458 /* Update shadow table and hw entry */
2459 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2460 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2461 priv->prs_shadow[pe.index].finish = true;
2462 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2463 MVPP2_PRS_RI_L3_PROTO_MASK);
2464 mvpp2_prs_hw_write(priv, &pe);
2469 /* Configure vlan entries and detect up to 2 successive VLAN tags.
2476 static int mvpp2_prs_vlan_init(struct platform_device *pdev, struct mvpp2 *priv)
2478 struct mvpp2_prs_entry pe;
2481 priv->prs_double_vlans = devm_kcalloc(&pdev->dev, sizeof(bool),
2482 MVPP2_PRS_DBL_VLANS_MAX,
2484 if (!priv->prs_double_vlans)
2487 /* Double VLAN: 0x8100, 0x88A8 */
2488 err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021AD,
2489 MVPP2_PRS_PORT_MASK);
2493 /* Double VLAN: 0x8100, 0x8100 */
2494 err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021Q,
2495 MVPP2_PRS_PORT_MASK);
2499 /* Single VLAN: 0x88a8 */
2500 err = mvpp2_prs_vlan_add(priv, ETH_P_8021AD, MVPP2_PRS_SINGLE_VLAN_AI,
2501 MVPP2_PRS_PORT_MASK);
2505 /* Single VLAN: 0x8100 */
2506 err = mvpp2_prs_vlan_add(priv, ETH_P_8021Q, MVPP2_PRS_SINGLE_VLAN_AI,
2507 MVPP2_PRS_PORT_MASK);
2511 /* Set default double vlan entry */
2512 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2513 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
2514 pe.index = MVPP2_PE_VLAN_DBL;
2516 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
2517 /* Clear ai for next iterations */
2518 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
2519 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE,
2520 MVPP2_PRS_RI_VLAN_MASK);
2522 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT,
2523 MVPP2_PRS_DBL_VLAN_AI_BIT);
2524 /* Unmask all ports */
2525 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2527 /* Update shadow table and hw entry */
2528 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
2529 mvpp2_prs_hw_write(priv, &pe);
2531 /* Set default vlan none entry */
2532 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2533 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
2534 pe.index = MVPP2_PE_VLAN_NONE;
2536 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
2537 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
2538 MVPP2_PRS_RI_VLAN_MASK);
2540 /* Unmask all ports */
2541 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2543 /* Update shadow table and hw entry */
2544 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
2545 mvpp2_prs_hw_write(priv, &pe);
2550 /* Set entries for PPPoE ethertype */
2551 static int mvpp2_prs_pppoe_init(struct mvpp2 *priv)
2553 struct mvpp2_prs_entry pe;
2556 /* IPv4 over PPPoE with options */
2557 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2558 MVPP2_PE_LAST_FREE_TID);
2562 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2563 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2566 mvpp2_prs_match_etype(&pe, 0, PPP_IP);
2568 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2569 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2570 MVPP2_PRS_RI_L3_PROTO_MASK);
2571 /* Skip eth_type + 4 bytes of IP header */
2572 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2573 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2575 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2577 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2579 /* Update shadow table and hw entry */
2580 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
2581 mvpp2_prs_hw_write(priv, &pe);
2583 /* IPv4 over PPPoE without options */
2584 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2585 MVPP2_PE_LAST_FREE_TID);
2591 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2592 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2593 MVPP2_PRS_IPV4_HEAD_MASK |
2594 MVPP2_PRS_IPV4_IHL_MASK);
2596 /* Clear ri before updating */
2597 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2598 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2599 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2600 MVPP2_PRS_RI_L3_PROTO_MASK);
2602 /* Update shadow table and hw entry */
2603 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
2604 mvpp2_prs_hw_write(priv, &pe);
2606 /* IPv6 over PPPoE */
2607 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2608 MVPP2_PE_LAST_FREE_TID);
2612 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2613 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2616 mvpp2_prs_match_etype(&pe, 0, PPP_IPV6);
2618 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2619 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2620 MVPP2_PRS_RI_L3_PROTO_MASK);
2621 /* Skip eth_type + 4 bytes of IPv6 header */
2622 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2623 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2625 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2627 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2629 /* Update shadow table and hw entry */
2630 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
2631 mvpp2_prs_hw_write(priv, &pe);
2633 /* Non-IP over PPPoE */
2634 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2635 MVPP2_PE_LAST_FREE_TID);
2639 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2640 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2643 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2644 MVPP2_PRS_RI_L3_PROTO_MASK);
2646 /* Finished: go to flowid generation */
2647 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2648 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2649 /* Set L3 offset even if it's unknown L3 */
2650 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2652 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2654 /* Update shadow table and hw entry */
2655 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
2656 mvpp2_prs_hw_write(priv, &pe);
2661 /* Initialize entries for IPv4 */
2662 static int mvpp2_prs_ip4_init(struct mvpp2 *priv)
2664 struct mvpp2_prs_entry pe;
2667 /* Set entries for TCP, UDP and IGMP over IPv4 */
2668 err = mvpp2_prs_ip4_proto(priv, IPPROTO_TCP, MVPP2_PRS_RI_L4_TCP,
2669 MVPP2_PRS_RI_L4_PROTO_MASK);
2673 err = mvpp2_prs_ip4_proto(priv, IPPROTO_UDP, MVPP2_PRS_RI_L4_UDP,
2674 MVPP2_PRS_RI_L4_PROTO_MASK);
2678 err = mvpp2_prs_ip4_proto(priv, IPPROTO_IGMP,
2679 MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2680 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2681 MVPP2_PRS_RI_CPU_CODE_MASK |
2682 MVPP2_PRS_RI_UDF3_MASK);
2686 /* IPv4 Broadcast */
2687 err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_BROAD_CAST);
2691 /* IPv4 Multicast */
2692 err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_MULTI_CAST);
2696 /* Default IPv4 entry for unknown protocols */
2697 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2698 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
2699 pe.index = MVPP2_PE_IP4_PROTO_UN;
2701 /* Set next lu to IPv4 */
2702 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2703 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2705 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
2706 sizeof(struct iphdr) - 4,
2707 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2708 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
2709 MVPP2_PRS_IPV4_DIP_AI_BIT);
2710 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
2711 MVPP2_PRS_RI_L4_PROTO_MASK);
2713 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
2714 /* Unmask all ports */
2715 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2717 /* Update shadow table and hw entry */
2718 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2719 mvpp2_prs_hw_write(priv, &pe);
2721 /* Default IPv4 entry for unicast address */
2722 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2723 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
2724 pe.index = MVPP2_PE_IP4_ADDR_UN;
2726 /* Finished: go to flowid generation */
2727 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2728 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2729 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,
2730 MVPP2_PRS_RI_L3_ADDR_MASK);
2732 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
2733 MVPP2_PRS_IPV4_DIP_AI_BIT);
2734 /* Unmask all ports */
2735 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2737 /* Update shadow table and hw entry */
2738 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2739 mvpp2_prs_hw_write(priv, &pe);
2744 /* Initialize entries for IPv6 */
2745 static int mvpp2_prs_ip6_init(struct mvpp2 *priv)
2747 struct mvpp2_prs_entry pe;
2750 /* Set entries for TCP, UDP and ICMP over IPv6 */
2751 err = mvpp2_prs_ip6_proto(priv, IPPROTO_TCP,
2752 MVPP2_PRS_RI_L4_TCP,
2753 MVPP2_PRS_RI_L4_PROTO_MASK);
2757 err = mvpp2_prs_ip6_proto(priv, IPPROTO_UDP,
2758 MVPP2_PRS_RI_L4_UDP,
2759 MVPP2_PRS_RI_L4_PROTO_MASK);
2763 err = mvpp2_prs_ip6_proto(priv, IPPROTO_ICMPV6,
2764 MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2765 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2766 MVPP2_PRS_RI_CPU_CODE_MASK |
2767 MVPP2_PRS_RI_UDF3_MASK);
2771 /* IPv4 is the last header. This is similar case as 6-TCP or 17-UDP */
2772 /* Result Info: UDF7=1, DS lite */
2773 err = mvpp2_prs_ip6_proto(priv, IPPROTO_IPIP,
2774 MVPP2_PRS_RI_UDF7_IP6_LITE,
2775 MVPP2_PRS_RI_UDF7_MASK);
2779 /* IPv6 multicast */
2780 err = mvpp2_prs_ip6_cast(priv, MVPP2_PRS_L3_MULTI_CAST);
2784 /* Entry for checking hop limit */
2785 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2786 MVPP2_PE_LAST_FREE_TID);
2790 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2791 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2794 /* Finished: go to flowid generation */
2795 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2796 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2797 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN |
2798 MVPP2_PRS_RI_DROP_MASK,
2799 MVPP2_PRS_RI_L3_PROTO_MASK |
2800 MVPP2_PRS_RI_DROP_MASK);
2802 mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK);
2803 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2804 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2806 /* Update shadow table and hw entry */
2807 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2808 mvpp2_prs_hw_write(priv, &pe);
2810 /* Default IPv6 entry for unknown protocols */
2811 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2812 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2813 pe.index = MVPP2_PE_IP6_PROTO_UN;
2815 /* Finished: go to flowid generation */
2816 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2817 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2818 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
2819 MVPP2_PRS_RI_L4_PROTO_MASK);
2820 /* Set L4 offset relatively to our current place */
2821 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
2822 sizeof(struct ipv6hdr) - 4,
2823 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2825 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2826 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2827 /* Unmask all ports */
2828 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2830 /* Update shadow table and hw entry */
2831 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2832 mvpp2_prs_hw_write(priv, &pe);
2834 /* Default IPv6 entry for unknown ext protocols */
2835 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2836 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2837 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN;
2839 /* Finished: go to flowid generation */
2840 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2841 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2842 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
2843 MVPP2_PRS_RI_L4_PROTO_MASK);
2845 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT,
2846 MVPP2_PRS_IPV6_EXT_AI_BIT);
2847 /* Unmask all ports */
2848 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2850 /* Update shadow table and hw entry */
2851 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2852 mvpp2_prs_hw_write(priv, &pe);
2854 /* Default IPv6 entry for unicast address */
2855 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2856 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2857 pe.index = MVPP2_PE_IP6_ADDR_UN;
2859 /* Finished: go to IPv6 again */
2860 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2861 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,
2862 MVPP2_PRS_RI_L3_ADDR_MASK);
2863 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2864 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2865 /* Shift back to IPV6 NH */
2866 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2868 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2869 /* Unmask all ports */
2870 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2872 /* Update shadow table and hw entry */
2873 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
2874 mvpp2_prs_hw_write(priv, &pe);
2879 /* Parser default initialization */
2880 static int mvpp2_prs_default_init(struct platform_device *pdev,
2885 /* Enable tcam table */
2886 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2888 /* Clear all tcam and sram entries */
2889 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2890 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2891 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2892 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2894 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2895 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2896 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2899 /* Invalidate all tcam entries */
2900 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2901 mvpp2_prs_hw_inv(priv, index);
2903 priv->prs_shadow = devm_kcalloc(&pdev->dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2904 sizeof(struct mvpp2_prs_shadow),
2906 if (!priv->prs_shadow)
2909 /* Always start from lookup = 0 */
2910 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2911 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2912 MVPP2_PRS_PORT_LU_MAX, 0);
2914 mvpp2_prs_def_flow_init(priv);
2916 mvpp2_prs_mh_init(priv);
2918 mvpp2_prs_mac_init(priv);
2920 mvpp2_prs_dsa_init(priv);
2922 err = mvpp2_prs_etype_init(priv);
2926 err = mvpp2_prs_vlan_init(pdev, priv);
2930 err = mvpp2_prs_pppoe_init(priv);
2934 err = mvpp2_prs_ip6_init(priv);
2938 err = mvpp2_prs_ip4_init(priv);
2945 /* Compare MAC DA with tcam entry data */
2946 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2947 const u8 *da, unsigned char *mask)
2949 unsigned char tcam_byte, tcam_mask;
2952 for (index = 0; index < ETH_ALEN; index++) {
2953 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2954 if (tcam_mask != mask[index])
2957 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2964 /* Find tcam entry with matched pair <MAC DA, port> */
2965 static struct mvpp2_prs_entry *
2966 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2967 unsigned char *mask, int udf_type)
2969 struct mvpp2_prs_entry *pe;
2972 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2975 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2977 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2978 for (tid = MVPP2_PE_FIRST_FREE_TID;
2979 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2980 unsigned int entry_pmap;
2982 if (!priv->prs_shadow[tid].valid ||
2983 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2984 (priv->prs_shadow[tid].udf != udf_type))
2988 mvpp2_prs_hw_read(priv, pe);
2989 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2991 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
3000 /* Update parser's mac da entry */
3001 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
3002 const u8 *da, bool add)
3004 struct mvpp2_prs_entry *pe;
3005 unsigned int pmap, len, ri;
3006 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3009 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
3010 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
3011 MVPP2_PRS_UDF_MAC_DEF);
3018 /* Create new TCAM entry */
3019 /* Find first range mac entry*/
3020 for (tid = MVPP2_PE_FIRST_FREE_TID;
3021 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
3022 if (priv->prs_shadow[tid].valid &&
3023 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
3024 (priv->prs_shadow[tid].udf ==
3025 MVPP2_PRS_UDF_MAC_RANGE))
3028 /* Go through the all entries from first to last */
3029 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
3034 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
3037 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
3040 /* Mask all ports */
3041 mvpp2_prs_tcam_port_map_set(pe, 0);
3044 /* Update port mask */
3045 mvpp2_prs_tcam_port_set(pe, port, add);
3047 /* Invalidate the entry if no ports are left enabled */
3048 pmap = mvpp2_prs_tcam_port_map_get(pe);
3054 mvpp2_prs_hw_inv(priv, pe->index);
3055 priv->prs_shadow[pe->index].valid = false;
3060 /* Continue - set next lookup */
3061 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
3063 /* Set match on DA */
3066 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
3068 /* Set result info bits */
3069 if (is_broadcast_ether_addr(da))
3070 ri = MVPP2_PRS_RI_L2_BCAST;
3071 else if (is_multicast_ether_addr(da))
3072 ri = MVPP2_PRS_RI_L2_MCAST;
3074 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
3076 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
3077 MVPP2_PRS_RI_MAC_ME_MASK);
3078 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
3079 MVPP2_PRS_RI_MAC_ME_MASK);
3081 /* Shift to ethertype */
3082 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
3083 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
3085 /* Update shadow table and hw entry */
3086 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
3087 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
3088 mvpp2_prs_hw_write(priv, pe);
3095 static int mvpp2_prs_update_mac_da(struct net_device *dev, const u8 *da)
3097 struct mvpp2_port *port = netdev_priv(dev);
3100 /* Remove old parser entry */
3101 err = mvpp2_prs_mac_da_accept(port->priv, port->id, dev->dev_addr,
3106 /* Add new parser entry */
3107 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
3111 /* Set addr in the device */
3112 ether_addr_copy(dev->dev_addr, da);
3117 /* Delete all port's multicast simple (not range) entries */
3118 static void mvpp2_prs_mcast_del_all(struct mvpp2 *priv, int port)
3120 struct mvpp2_prs_entry pe;
3123 for (tid = MVPP2_PE_FIRST_FREE_TID;
3124 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
3125 unsigned char da[ETH_ALEN], da_mask[ETH_ALEN];
3127 if (!priv->prs_shadow[tid].valid ||
3128 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
3129 (priv->prs_shadow[tid].udf != MVPP2_PRS_UDF_MAC_DEF))
3132 /* Only simple mac entries */
3134 mvpp2_prs_hw_read(priv, &pe);
3136 /* Read mac addr from entry */
3137 for (index = 0; index < ETH_ALEN; index++)
3138 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index],
3141 if (is_multicast_ether_addr(da) && !is_broadcast_ether_addr(da))
3142 /* Delete this entry */
3143 mvpp2_prs_mac_da_accept(priv, port, da, false);
3147 static int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type)
3150 case MVPP2_TAG_TYPE_EDSA:
3151 /* Add port to EDSA entries */
3152 mvpp2_prs_dsa_tag_set(priv, port, true,
3153 MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
3154 mvpp2_prs_dsa_tag_set(priv, port, true,
3155 MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
3156 /* Remove port from DSA entries */
3157 mvpp2_prs_dsa_tag_set(priv, port, false,
3158 MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
3159 mvpp2_prs_dsa_tag_set(priv, port, false,
3160 MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
3163 case MVPP2_TAG_TYPE_DSA:
3164 /* Add port to DSA entries */
3165 mvpp2_prs_dsa_tag_set(priv, port, true,
3166 MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
3167 mvpp2_prs_dsa_tag_set(priv, port, true,
3168 MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
3169 /* Remove port from EDSA entries */
3170 mvpp2_prs_dsa_tag_set(priv, port, false,
3171 MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
3172 mvpp2_prs_dsa_tag_set(priv, port, false,
3173 MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
3176 case MVPP2_TAG_TYPE_MH:
3177 case MVPP2_TAG_TYPE_NONE:
3178 /* Remove port form EDSA and DSA entries */
3179 mvpp2_prs_dsa_tag_set(priv, port, false,
3180 MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
3181 mvpp2_prs_dsa_tag_set(priv, port, false,
3182 MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
3183 mvpp2_prs_dsa_tag_set(priv, port, false,
3184 MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
3185 mvpp2_prs_dsa_tag_set(priv, port, false,
3186 MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
3190 if ((type < 0) || (type > MVPP2_TAG_TYPE_EDSA))
3197 /* Set prs flow for the port */
3198 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
3200 struct mvpp2_prs_entry *pe;
3203 pe = mvpp2_prs_flow_find(port->priv, port->id);
3205 /* Such entry not exist */
3207 /* Go through the all entires from last to first */
3208 tid = mvpp2_prs_tcam_first_free(port->priv,
3209 MVPP2_PE_LAST_FREE_TID,
3210 MVPP2_PE_FIRST_FREE_TID);
3214 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
3218 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
3222 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
3223 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
3225 /* Update shadow table */
3226 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
3229 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
3230 mvpp2_prs_hw_write(port->priv, pe);
3236 /* Classifier configuration routines */
3238 /* Update classification flow table registers */
3239 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
3240 struct mvpp2_cls_flow_entry *fe)
3242 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
3243 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
3244 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
3245 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
3248 /* Update classification lookup table register */
3249 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
3250 struct mvpp2_cls_lookup_entry *le)
3254 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
3255 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
3256 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
3259 /* Classifier default initialization */
3260 static void mvpp2_cls_init(struct mvpp2 *priv)
3262 struct mvpp2_cls_lookup_entry le;
3263 struct mvpp2_cls_flow_entry fe;
3266 /* Enable classifier */
3267 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
3269 /* Clear classifier flow table */
3270 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
3271 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
3273 mvpp2_cls_flow_write(priv, &fe);
3276 /* Clear classifier lookup table */
3278 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
3281 mvpp2_cls_lookup_write(priv, &le);
3284 mvpp2_cls_lookup_write(priv, &le);
3288 static void mvpp2_cls_port_config(struct mvpp2_port *port)
3290 struct mvpp2_cls_lookup_entry le;
3293 /* Set way for the port */
3294 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
3295 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
3296 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
3298 /* Pick the entry to be accessed in lookup ID decoding table
3299 * according to the way and lkpid.
3301 le.lkpid = port->id;
3305 /* Set initial CPU queue for receiving packets */
3306 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
3307 le.data |= port->first_rxq;
3309 /* Disable classification engines */
3310 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
3312 /* Update lookup ID table entry */
3313 mvpp2_cls_lookup_write(port->priv, &le);
3316 /* Set CPU queue number for oversize packets */
3317 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
3321 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
3322 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
3324 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
3325 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
3327 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
3328 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
3329 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
3332 /* Buffer Manager configuration routines */
3335 static int mvpp2_bm_pool_create(struct platform_device *pdev,
3337 struct mvpp2_bm_pool *bm_pool, int size)
3342 size_bytes = sizeof(u32) * size;
3343 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, size_bytes,
3344 &bm_pool->phys_addr,
3346 if (!bm_pool->virt_addr)
3349 if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVPP2_BM_POOL_PTR_ALIGN)) {
3350 dma_free_coherent(&pdev->dev, size_bytes, bm_pool->virt_addr,
3351 bm_pool->phys_addr);
3352 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
3353 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
3357 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
3358 bm_pool->phys_addr);
3359 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
3361 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
3362 val |= MVPP2_BM_START_MASK;
3363 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
3365 bm_pool->type = MVPP2_BM_FREE;
3366 bm_pool->size = size;
3367 bm_pool->pkt_size = 0;
3368 bm_pool->buf_num = 0;
3369 atomic_set(&bm_pool->in_use, 0);
3370 spin_lock_init(&bm_pool->lock);
3375 /* Set pool buffer size */
3376 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
3377 struct mvpp2_bm_pool *bm_pool,
3382 bm_pool->buf_size = buf_size;
3384 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
3385 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
3388 /* Free all buffers from the pool */
3389 static void mvpp2_bm_bufs_free(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
3393 for (i = 0; i < bm_pool->buf_num; i++) {
3396 /* Get buffer virtual adress (indirect access) */
3397 mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
3398 vaddr = mvpp2_read(priv, MVPP2_BM_VIRT_ALLOC_REG);
3401 dev_kfree_skb_any((struct sk_buff *)vaddr);
3404 /* Update BM driver with number of buffers removed from pool */
3405 bm_pool->buf_num -= i;
3409 static int mvpp2_bm_pool_destroy(struct platform_device *pdev,
3411 struct mvpp2_bm_pool *bm_pool)
3415 mvpp2_bm_bufs_free(priv, bm_pool);
3416 if (bm_pool->buf_num) {
3417 WARN(1, "cannot free all buffers in pool %d\n", bm_pool->id);
3421 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
3422 val |= MVPP2_BM_STOP_MASK;
3423 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
3425 dma_free_coherent(&pdev->dev, sizeof(u32) * bm_pool->size,
3427 bm_pool->phys_addr);
3431 static int mvpp2_bm_pools_init(struct platform_device *pdev,
3435 struct mvpp2_bm_pool *bm_pool;
3437 /* Create all pools with maximum size */
3438 size = MVPP2_BM_POOL_SIZE_MAX;
3439 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
3440 bm_pool = &priv->bm_pools[i];
3442 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size);
3444 goto err_unroll_pools;
3445 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
3450 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
3451 for (i = i - 1; i >= 0; i--)
3452 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]);
3456 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv)
3460 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
3461 /* Mask BM all interrupts */
3462 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
3463 /* Clear BM cause register */
3464 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
3467 /* Allocate and initialize BM pools */
3468 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM,
3469 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
3470 if (!priv->bm_pools)
3473 err = mvpp2_bm_pools_init(pdev, priv);
3479 /* Attach long pool to rxq */
3480 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
3481 int lrxq, int long_pool)
3486 /* Get queue physical ID */
3487 prxq = port->rxqs[lrxq]->id;
3489 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3490 val &= ~MVPP2_RXQ_POOL_LONG_MASK;
3491 val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) &
3492 MVPP2_RXQ_POOL_LONG_MASK);
3494 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3497 /* Attach short pool to rxq */
3498 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
3499 int lrxq, int short_pool)
3504 /* Get queue physical ID */
3505 prxq = port->rxqs[lrxq]->id;
3507 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3508 val &= ~MVPP2_RXQ_POOL_SHORT_MASK;
3509 val |= ((short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) &
3510 MVPP2_RXQ_POOL_SHORT_MASK);
3512 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3515 /* Allocate skb for BM pool */
3516 static struct sk_buff *mvpp2_skb_alloc(struct mvpp2_port *port,
3517 struct mvpp2_bm_pool *bm_pool,
3518 dma_addr_t *buf_phys_addr,
3521 struct sk_buff *skb;
3522 dma_addr_t phys_addr;
3524 skb = __dev_alloc_skb(bm_pool->pkt_size, gfp_mask);
3528 phys_addr = dma_map_single(port->dev->dev.parent, skb->head,
3529 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
3531 if (unlikely(dma_mapping_error(port->dev->dev.parent, phys_addr))) {
3532 dev_kfree_skb_any(skb);
3535 *buf_phys_addr = phys_addr;
3540 /* Set pool number in a BM cookie */
3541 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
3545 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
3546 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
3551 /* Get pool number from a BM cookie */
3552 static inline int mvpp2_bm_cookie_pool_get(u32 cookie)
3554 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
3557 /* Release buffer to BM */
3558 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
3559 u32 buf_phys_addr, u32 buf_virt_addr)
3561 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
3562 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr);
3565 /* Release multicast buffer */
3566 static void mvpp2_bm_pool_mc_put(struct mvpp2_port *port, int pool,
3567 u32 buf_phys_addr, u32 buf_virt_addr,
3572 val |= (mc_id & MVPP2_BM_MC_ID_MASK);
3573 mvpp2_write(port->priv, MVPP2_BM_MC_RLS_REG, val);
3575 mvpp2_bm_pool_put(port, pool,
3576 buf_phys_addr | MVPP2_BM_PHY_RLS_MC_BUFF_MASK,
3580 /* Refill BM pool */
3581 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
3582 u32 phys_addr, u32 cookie)
3584 int pool = mvpp2_bm_cookie_pool_get(bm);
3586 mvpp2_bm_pool_put(port, pool, phys_addr, cookie);
3589 /* Allocate buffers for the pool */
3590 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
3591 struct mvpp2_bm_pool *bm_pool, int buf_num)
3593 struct sk_buff *skb;
3594 int i, buf_size, total_size;
3596 dma_addr_t phys_addr;
3598 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
3599 total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
3602 (buf_num + bm_pool->buf_num > bm_pool->size)) {
3603 netdev_err(port->dev,
3604 "cannot allocate %d buffers for pool %d\n",
3605 buf_num, bm_pool->id);
3609 bm = mvpp2_bm_cookie_pool_set(0, bm_pool->id);
3610 for (i = 0; i < buf_num; i++) {
3611 skb = mvpp2_skb_alloc(port, bm_pool, &phys_addr, GFP_KERNEL);
3615 mvpp2_pool_refill(port, bm, (u32)phys_addr, (u32)skb);
3618 /* Update BM driver with number of buffers added to pool */
3619 bm_pool->buf_num += i;
3620 bm_pool->in_use_thresh = bm_pool->buf_num / 4;
3622 netdev_dbg(port->dev,
3623 "%s pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
3624 bm_pool->type == MVPP2_BM_SWF_SHORT ? "short" : " long",
3625 bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
3627 netdev_dbg(port->dev,
3628 "%s pool %d: %d of %d buffers added\n",
3629 bm_pool->type == MVPP2_BM_SWF_SHORT ? "short" : " long",
3630 bm_pool->id, i, buf_num);
3634 /* Notify the driver that BM pool is being used as specific type and return the
3635 * pool pointer on success
3637 static struct mvpp2_bm_pool *
3638 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
3641 unsigned long flags = 0;
3642 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
3645 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
3646 netdev_err(port->dev, "mixing pool types is forbidden\n");
3650 spin_lock_irqsave(&new_pool->lock, flags);
3652 if (new_pool->type == MVPP2_BM_FREE)
3653 new_pool->type = type;
3655 /* Allocate buffers in case BM pool is used as long pool, but packet
3656 * size doesn't match MTU or BM pool hasn't being used yet
3658 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
3659 (new_pool->pkt_size == 0)) {
3662 /* Set default buffer number or free all the buffers in case
3663 * the pool is not empty
3665 pkts_num = new_pool->buf_num;
3667 pkts_num = type == MVPP2_BM_SWF_LONG ?
3668 MVPP2_BM_LONG_BUF_NUM :
3669 MVPP2_BM_SHORT_BUF_NUM;
3671 mvpp2_bm_bufs_free(port->priv, new_pool);
3673 new_pool->pkt_size = pkt_size;
3675 /* Allocate buffers for this pool */
3676 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
3677 if (num != pkts_num) {
3678 WARN(1, "pool %d: %d of %d allocated\n",
3679 new_pool->id, num, pkts_num);
3680 /* We need to undo the bufs_add() allocations */
3681 spin_unlock_irqrestore(&new_pool->lock, flags);
3686 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
3687 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
3689 spin_unlock_irqrestore(&new_pool->lock, flags);
3694 /* Initialize pools for swf */
3695 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
3697 unsigned long flags = 0;
3700 if (!port->pool_long) {
3702 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
3705 if (!port->pool_long)
3708 spin_lock_irqsave(&port->pool_long->lock, flags);
3709 port->pool_long->port_map |= (1 << port->id);
3710 spin_unlock_irqrestore(&port->pool_long->lock, flags);
3712 for (rxq = 0; rxq < rxq_number; rxq++)
3713 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
3716 if (!port->pool_short) {
3718 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_SHORT_POOL,
3720 MVPP2_BM_SHORT_PKT_SIZE);
3721 if (!port->pool_short)
3724 spin_lock_irqsave(&port->pool_short->lock, flags);
3725 port->pool_short->port_map |= (1 << port->id);
3726 spin_unlock_irqrestore(&port->pool_short->lock, flags);
3728 for (rxq = 0; rxq < rxq_number; rxq++)
3729 mvpp2_rxq_short_pool_set(port, rxq,
3730 port->pool_short->id);
3736 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
3738 struct mvpp2_port *port = netdev_priv(dev);
3739 struct mvpp2_bm_pool *port_pool = port->pool_long;
3740 int num, pkts_num = port_pool->buf_num;
3741 int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3743 /* Update BM pool with new buffer size */
3744 mvpp2_bm_bufs_free(port->priv, port_pool);
3745 if (port_pool->buf_num) {
3746 WARN(1, "cannot free all buffers in pool %d\n", port_pool->id);
3750 port_pool->pkt_size = pkt_size;
3751 num = mvpp2_bm_bufs_add(port, port_pool, pkts_num);
3752 if (num != pkts_num) {
3753 WARN(1, "pool %d: %d of %d allocated\n",
3754 port_pool->id, num, pkts_num);
3758 mvpp2_bm_pool_bufsize_set(port->priv, port_pool,
3759 MVPP2_RX_BUF_SIZE(port_pool->pkt_size));
3761 netdev_update_features(dev);
3765 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
3767 int cpu, cpu_mask = 0;
3769 for_each_present_cpu(cpu)
3770 cpu_mask |= 1 << cpu;
3771 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
3772 MVPP2_ISR_ENABLE_INTERRUPT(cpu_mask));
3775 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
3777 int cpu, cpu_mask = 0;
3779 for_each_present_cpu(cpu)
3780 cpu_mask |= 1 << cpu;
3781 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
3782 MVPP2_ISR_DISABLE_INTERRUPT(cpu_mask));
3785 /* Mask the current CPU's Rx/Tx interrupts */
3786 static void mvpp2_interrupts_mask(void *arg)
3788 struct mvpp2_port *port = arg;
3790 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
3793 /* Unmask the current CPU's Rx/Tx interrupts */
3794 static void mvpp2_interrupts_unmask(void *arg)
3796 struct mvpp2_port *port = arg;
3798 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_MASK_REG(port->id),
3799 (MVPP2_CAUSE_MISC_SUM_MASK |
3800 MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK |
3801 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK));
3804 /* Port configuration routines */
3806 static void mvpp2_port_mii_set(struct mvpp2_port *port)
3810 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3812 switch (port->phy_interface) {
3813 case PHY_INTERFACE_MODE_SGMII:
3814 val |= MVPP2_GMAC_INBAND_AN_MASK;
3816 case PHY_INTERFACE_MODE_RGMII:
3817 val |= MVPP2_GMAC_PORT_RGMII_MASK;
3819 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
3822 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3825 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
3829 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3830 val |= MVPP2_GMAC_FC_ADV_EN;
3831 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3834 static void mvpp2_port_enable(struct mvpp2_port *port)
3838 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3839 val |= MVPP2_GMAC_PORT_EN_MASK;
3840 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
3841 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3844 static void mvpp2_port_disable(struct mvpp2_port *port)
3848 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3849 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
3850 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3853 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
3854 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
3858 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
3859 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
3860 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
3863 /* Configure loopback port */
3864 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
3868 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3870 if (port->speed == 1000)
3871 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
3873 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
3875 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
3876 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
3878 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
3880 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
3883 static void mvpp2_port_reset(struct mvpp2_port *port)
3887 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
3888 ~MVPP2_GMAC_PORT_RESET_MASK;
3889 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3891 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
3892 MVPP2_GMAC_PORT_RESET_MASK)
3896 /* Change maximum receive size of the port */
3897 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
3901 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3902 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
3903 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
3904 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
3905 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3908 /* Set defaults to the MVPP2 port */
3909 static void mvpp2_defaults_set(struct mvpp2_port *port)
3911 int tx_port_num, val, queue, ptxq, lrxq;
3913 /* Configure port to loopback if needed */
3914 if (port->flags & MVPP2_F_LOOPBACK)
3915 mvpp2_port_loopback_set(port);
3917 /* Update TX FIFO MIN Threshold */
3918 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3919 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3920 /* Min. TX threshold must be less than minimal packet length */
3921 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
3922 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3924 /* Disable Legacy WRR, Disable EJP, Release from reset */
3925 tx_port_num = mvpp2_egress_port(port);
3926 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
3928 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
3930 /* Close bandwidth for all queues */
3931 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
3932 ptxq = mvpp2_txq_phys(port->id, queue);
3933 mvpp2_write(port->priv,
3934 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
3937 /* Set refill period to 1 usec, refill tokens
3938 * and bucket size to maximum
3940 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
3941 port->priv->tclk / USEC_PER_SEC);
3942 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
3943 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
3944 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
3945 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
3946 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
3947 val = MVPP2_TXP_TOKEN_SIZE_MAX;
3948 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3950 /* Set MaximumLowLatencyPacketSize value to 256 */
3951 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
3952 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
3953 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
3955 /* Enable Rx cache snoop */
3956 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3957 queue = port->rxqs[lrxq]->id;
3958 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3959 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
3960 MVPP2_SNOOP_BUF_HDR_MASK;
3961 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3964 /* At default, mask all interrupts to all present cpus */
3965 mvpp2_interrupts_disable(port);
3968 /* Enable/disable receiving packets */
3969 static void mvpp2_ingress_enable(struct mvpp2_port *port)
3974 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3975 queue = port->rxqs[lrxq]->id;
3976 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3977 val &= ~MVPP2_RXQ_DISABLE_MASK;
3978 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3982 static void mvpp2_ingress_disable(struct mvpp2_port *port)
3987 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3988 queue = port->rxqs[lrxq]->id;
3989 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3990 val |= MVPP2_RXQ_DISABLE_MASK;
3991 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3995 /* Enable transmit via physical egress queue
3996 * - HW starts take descriptors from DRAM
3998 static void mvpp2_egress_enable(struct mvpp2_port *port)
4002 int tx_port_num = mvpp2_egress_port(port);
4004 /* Enable all initialized TXs. */
4006 for (queue = 0; queue < txq_number; queue++) {
4007 struct mvpp2_tx_queue *txq = port->txqs[queue];
4009 if (txq->descs != NULL)
4010 qmap |= (1 << queue);
4013 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4014 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
4017 /* Disable transmit via physical egress queue
4018 * - HW doesn't take descriptors from DRAM
4020 static void mvpp2_egress_disable(struct mvpp2_port *port)
4024 int tx_port_num = mvpp2_egress_port(port);
4026 /* Issue stop command for active channels only */
4027 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4028 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
4029 MVPP2_TXP_SCHED_ENQ_MASK;
4031 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
4032 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
4034 /* Wait for all Tx activity to terminate. */
4037 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
4038 netdev_warn(port->dev,
4039 "Tx stop timed out, status=0x%08x\n",
4046 /* Check port TX Command register that all
4047 * Tx queues are stopped
4049 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
4050 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
4053 /* Rx descriptors helper methods */
4055 /* Get number of Rx descriptors occupied by received packets */
4057 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
4059 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
4061 return val & MVPP2_RXQ_OCCUPIED_MASK;
4064 /* Update Rx queue status with the number of occupied and available
4065 * Rx descriptor slots.
4068 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
4069 int used_count, int free_count)
4071 /* Decrement the number of used descriptors and increment count
4072 * increment the number of free descriptors.
4074 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
4076 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
4079 /* Get pointer to next RX descriptor to be processed by SW */
4080 static inline struct mvpp2_rx_desc *
4081 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
4083 int rx_desc = rxq->next_desc_to_proc;
4085 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
4086 prefetch(rxq->descs + rxq->next_desc_to_proc);
4087 return rxq->descs + rx_desc;
4090 /* Set rx queue offset */
4091 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
4092 int prxq, int offset)
4096 /* Convert offset from bytes to units of 32 bytes */
4097 offset = offset >> 5;
4099 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
4100 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
4103 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
4104 MVPP2_RXQ_PACKET_OFFSET_MASK);
4106 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
4109 /* Obtain BM cookie information from descriptor */
4110 static u32 mvpp2_bm_cookie_build(struct mvpp2_rx_desc *rx_desc)
4112 int pool = (rx_desc->status & MVPP2_RXD_BM_POOL_ID_MASK) >>
4113 MVPP2_RXD_BM_POOL_ID_OFFS;
4114 int cpu = smp_processor_id();
4116 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
4117 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
4120 /* Tx descriptors helper methods */
4122 /* Get number of Tx descriptors waiting to be transmitted by HW */
4123 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
4124 struct mvpp2_tx_queue *txq)
4128 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4129 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4131 return val & MVPP2_TXQ_PENDING_MASK;
4134 /* Get pointer to next Tx descriptor to be processed (send) by HW */
4135 static struct mvpp2_tx_desc *
4136 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
4138 int tx_desc = txq->next_desc_to_proc;
4140 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
4141 return txq->descs + tx_desc;
4144 /* Update HW with number of aggregated Tx descriptors to be sent */
4145 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
4147 /* aggregated access - relevant TXQ number is written in TX desc */
4148 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
4152 /* Check if there are enough free descriptors in aggregated txq.
4153 * If not, update the number of occupied descriptors and repeat the check.
4155 static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv,
4156 struct mvpp2_tx_queue *aggr_txq, int num)
4158 if ((aggr_txq->count + num) > aggr_txq->size) {
4159 /* Update number of occupied aggregated Tx descriptors */
4160 int cpu = smp_processor_id();
4161 u32 val = mvpp2_read(priv, MVPP2_AGGR_TXQ_STATUS_REG(cpu));
4163 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
4166 if ((aggr_txq->count + num) > aggr_txq->size)
4172 /* Reserved Tx descriptors allocation request */
4173 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2 *priv,
4174 struct mvpp2_tx_queue *txq, int num)
4178 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
4179 mvpp2_write(priv, MVPP2_TXQ_RSVD_REQ_REG, val);
4181 val = mvpp2_read(priv, MVPP2_TXQ_RSVD_RSLT_REG);
4183 return val & MVPP2_TXQ_RSVD_RSLT_MASK;
4186 /* Check if there are enough reserved descriptors for transmission.
4187 * If not, request chunk of reserved descriptors and check again.
4189 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv,
4190 struct mvpp2_tx_queue *txq,
4191 struct mvpp2_txq_pcpu *txq_pcpu,
4194 int req, cpu, desc_count;
4196 if (txq_pcpu->reserved_num >= num)
4199 /* Not enough descriptors reserved! Update the reserved descriptor
4200 * count and check again.
4204 /* Compute total of used descriptors */
4205 for_each_present_cpu(cpu) {
4206 struct mvpp2_txq_pcpu *txq_pcpu_aux;
4208 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, cpu);
4209 desc_count += txq_pcpu_aux->count;
4210 desc_count += txq_pcpu_aux->reserved_num;
4213 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
4217 (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK)))
4220 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req);
4222 /* OK, the descriptor cound has been updated: check again. */
4223 if (txq_pcpu->reserved_num < num)
4228 /* Release the last allocated Tx descriptor. Useful to handle DMA
4229 * mapping failures in the Tx path.
4231 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
4233 if (txq->next_desc_to_proc == 0)
4234 txq->next_desc_to_proc = txq->last_desc - 1;
4236 txq->next_desc_to_proc--;
4239 /* Set Tx descriptors fields relevant for CSUM calculation */
4240 static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto,
4241 int ip_hdr_len, int l4_proto)
4245 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
4246 * G_L4_chk, L4_type required only for checksum calculation
4248 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
4249 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
4250 command |= MVPP2_TXD_IP_CSUM_DISABLE;
4252 if (l3_proto == swab16(ETH_P_IP)) {
4253 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */
4254 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */
4256 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */
4259 if (l4_proto == IPPROTO_TCP) {
4260 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */
4261 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
4262 } else if (l4_proto == IPPROTO_UDP) {
4263 command |= MVPP2_TXD_L4_UDP; /* enable UDP */
4264 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
4266 command |= MVPP2_TXD_L4_CSUM_NOT;
4272 /* Get number of sent descriptors and decrement counter.
4273 * The number of sent descriptors is returned.
4276 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
4277 struct mvpp2_tx_queue *txq)
4281 /* Reading status reg resets transmitted descriptor counter */
4282 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
4284 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
4285 MVPP2_TRANSMITTED_COUNT_OFFSET;
4288 static void mvpp2_txq_sent_counter_clear(void *arg)
4290 struct mvpp2_port *port = arg;
4293 for (queue = 0; queue < txq_number; queue++) {
4294 int id = port->txqs[queue]->id;
4296 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
4300 /* Set max sizes for Tx queues */
4301 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
4304 int txq, tx_port_num;
4306 mtu = port->pkt_size * 8;
4307 if (mtu > MVPP2_TXP_MTU_MAX)
4308 mtu = MVPP2_TXP_MTU_MAX;
4310 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
4313 /* Indirect access to registers */
4314 tx_port_num = mvpp2_egress_port(port);
4315 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4318 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
4319 val &= ~MVPP2_TXP_MTU_MAX;
4321 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
4323 /* TXP token size and all TXQs token size must be larger that MTU */
4324 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
4325 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
4328 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
4330 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
4333 for (txq = 0; txq < txq_number; txq++) {
4334 val = mvpp2_read(port->priv,
4335 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
4336 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
4340 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
4342 mvpp2_write(port->priv,
4343 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
4349 /* Set the number of packets that will be received before Rx interrupt
4350 * will be generated by HW.
4352 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
4353 struct mvpp2_rx_queue *rxq, u32 pkts)
4357 val = (pkts & MVPP2_OCCUPIED_THRESH_MASK);
4358 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4359 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val);
4361 rxq->pkts_coal = pkts;
4364 /* Set the time delay in usec before Rx interrupt */
4365 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
4366 struct mvpp2_rx_queue *rxq, u32 usec)
4370 val = (port->priv->tclk / USEC_PER_SEC) * usec;
4371 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
4373 rxq->time_coal = usec;
4376 /* Set threshold for TX_DONE pkts coalescing */
4377 static void mvpp2_tx_done_pkts_coal_set(void *arg)
4379 struct mvpp2_port *port = arg;
4383 for (queue = 0; queue < txq_number; queue++) {
4384 struct mvpp2_tx_queue *txq = port->txqs[queue];
4386 val = (txq->done_pkts_coal << MVPP2_TRANSMITTED_THRESH_OFFSET) &
4387 MVPP2_TRANSMITTED_THRESH_MASK;
4388 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4389 mvpp2_write(port->priv, MVPP2_TXQ_THRESH_REG, val);
4393 /* Free Tx queue skbuffs */
4394 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
4395 struct mvpp2_tx_queue *txq,
4396 struct mvpp2_txq_pcpu *txq_pcpu, int num)
4400 for (i = 0; i < num; i++) {
4401 struct mvpp2_tx_desc *tx_desc = txq->descs +
4402 txq_pcpu->txq_get_index;
4403 struct sk_buff *skb = txq_pcpu->tx_skb[txq_pcpu->txq_get_index];
4405 mvpp2_txq_inc_get(txq_pcpu);
4410 dma_unmap_single(port->dev->dev.parent, tx_desc->buf_phys_addr,
4411 tx_desc->data_size, DMA_TO_DEVICE);
4412 dev_kfree_skb_any(skb);
4416 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
4419 int queue = fls(cause) - 1;
4421 return port->rxqs[queue];
4424 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
4427 int queue = fls(cause >> 16) - 1;
4429 return port->txqs[queue];
4432 /* Handle end of transmission */
4433 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4434 struct mvpp2_txq_pcpu *txq_pcpu)
4436 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
4439 if (txq_pcpu->cpu != smp_processor_id())
4440 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
4442 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
4445 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
4447 txq_pcpu->count -= tx_done;
4449 if (netif_tx_queue_stopped(nq))
4450 if (txq_pcpu->size - txq_pcpu->count >= MAX_SKB_FRAGS + 1)
4451 netif_tx_wake_queue(nq);
4454 /* Rx/Tx queue initialization/cleanup methods */
4456 /* Allocate and initialize descriptors for aggr TXQ */
4457 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
4458 struct mvpp2_tx_queue *aggr_txq,
4459 int desc_num, int cpu,
4462 /* Allocate memory for TX descriptors */
4463 aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
4464 desc_num * MVPP2_DESC_ALIGNED_SIZE,
4465 &aggr_txq->descs_phys, GFP_KERNEL);
4466 if (!aggr_txq->descs)
4469 /* Make sure descriptor address is cache line size aligned */
4470 BUG_ON(aggr_txq->descs !=
4471 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4473 aggr_txq->last_desc = aggr_txq->size - 1;
4475 /* Aggr TXQ no reset WA */
4476 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
4477 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
4479 /* Set Tx descriptors queue starting address */
4480 /* indirect access */
4481 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
4482 aggr_txq->descs_phys);
4483 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
4488 /* Create a specified Rx queue */
4489 static int mvpp2_rxq_init(struct mvpp2_port *port,
4490 struct mvpp2_rx_queue *rxq)
4493 rxq->size = port->rx_ring_size;
4495 /* Allocate memory for RX descriptors */
4496 rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
4497 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
4498 &rxq->descs_phys, GFP_KERNEL);
4502 BUG_ON(rxq->descs !=
4503 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4505 rxq->last_desc = rxq->size - 1;
4507 /* Zero occupied and non-occupied counters - direct access */
4508 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4510 /* Set Rx descriptors queue starting address - indirect access */
4511 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4512 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_phys);
4513 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
4514 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
4517 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
4519 /* Set coalescing pkts and time */
4520 mvpp2_rx_pkts_coal_set(port, rxq, rxq->pkts_coal);
4521 mvpp2_rx_time_coal_set(port, rxq, rxq->time_coal);
4523 /* Add number of descriptors ready for receiving packets */
4524 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
4529 /* Push packets received by the RXQ to BM pool */
4530 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
4531 struct mvpp2_rx_queue *rxq)
4535 rx_received = mvpp2_rxq_received(port, rxq->id);
4539 for (i = 0; i < rx_received; i++) {
4540 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
4541 u32 bm = mvpp2_bm_cookie_build(rx_desc);
4543 mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
4544 rx_desc->buf_cookie);
4546 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
4549 /* Cleanup Rx queue */
4550 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
4551 struct mvpp2_rx_queue *rxq)
4553 mvpp2_rxq_drop_pkts(port, rxq);
4556 dma_free_coherent(port->dev->dev.parent,
4557 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
4563 rxq->next_desc_to_proc = 0;
4564 rxq->descs_phys = 0;
4566 /* Clear Rx descriptors queue starting address and size;
4567 * free descriptor number
4569 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4570 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4571 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
4572 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
4575 /* Create and initialize a Tx queue */
4576 static int mvpp2_txq_init(struct mvpp2_port *port,
4577 struct mvpp2_tx_queue *txq)
4580 int cpu, desc, desc_per_txq, tx_port_num;
4581 struct mvpp2_txq_pcpu *txq_pcpu;
4583 txq->size = port->tx_ring_size;
4585 /* Allocate memory for Tx descriptors */
4586 txq->descs = dma_alloc_coherent(port->dev->dev.parent,
4587 txq->size * MVPP2_DESC_ALIGNED_SIZE,
4588 &txq->descs_phys, GFP_KERNEL);
4592 /* Make sure descriptor address is cache line size aligned */
4593 BUG_ON(txq->descs !=
4594 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4596 txq->last_desc = txq->size - 1;
4598 /* Set Tx descriptors queue starting address - indirect access */
4599 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4600 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_phys);
4601 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
4602 MVPP2_TXQ_DESC_SIZE_MASK);
4603 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
4604 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
4605 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
4606 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4607 val &= ~MVPP2_TXQ_PENDING_MASK;
4608 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
4610 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
4611 * for each existing TXQ.
4612 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
4613 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
4616 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
4617 (txq->log_id * desc_per_txq);
4619 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
4620 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
4621 MVPP2_PREF_BUF_THRESH(desc_per_txq/2));
4623 /* WRR / EJP configuration - indirect access */
4624 tx_port_num = mvpp2_egress_port(port);
4625 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4627 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
4628 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
4629 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
4630 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
4631 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
4633 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
4634 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
4637 for_each_present_cpu(cpu) {
4638 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4639 txq_pcpu->size = txq->size;
4640 txq_pcpu->tx_skb = kmalloc(txq_pcpu->size *
4641 sizeof(*txq_pcpu->tx_skb),
4643 if (!txq_pcpu->tx_skb) {
4644 dma_free_coherent(port->dev->dev.parent,
4645 txq->size * MVPP2_DESC_ALIGNED_SIZE,
4646 txq->descs, txq->descs_phys);
4650 txq_pcpu->count = 0;
4651 txq_pcpu->reserved_num = 0;
4652 txq_pcpu->txq_put_index = 0;
4653 txq_pcpu->txq_get_index = 0;
4659 /* Free allocated TXQ resources */
4660 static void mvpp2_txq_deinit(struct mvpp2_port *port,
4661 struct mvpp2_tx_queue *txq)
4663 struct mvpp2_txq_pcpu *txq_pcpu;
4666 for_each_present_cpu(cpu) {
4667 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4668 kfree(txq_pcpu->tx_skb);
4672 dma_free_coherent(port->dev->dev.parent,
4673 txq->size * MVPP2_DESC_ALIGNED_SIZE,
4674 txq->descs, txq->descs_phys);
4678 txq->next_desc_to_proc = 0;
4679 txq->descs_phys = 0;
4681 /* Set minimum bandwidth for disabled TXQs */
4682 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
4684 /* Set Tx descriptors queue starting address and size */
4685 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4686 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
4687 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
4690 /* Cleanup Tx ports */
4691 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
4693 struct mvpp2_txq_pcpu *txq_pcpu;
4694 int delay, pending, cpu;
4697 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4698 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4699 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4700 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4702 /* The napi queue has been stopped so wait for all packets
4703 * to be transmitted.
4707 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
4708 netdev_warn(port->dev,
4709 "port %d: cleaning queue %d timed out\n",
4710 port->id, txq->log_id);
4716 pending = mvpp2_txq_pend_desc_num_get(port, txq);
4719 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4720 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4722 for_each_present_cpu(cpu) {
4723 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4725 /* Release all packets */
4726 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
4729 txq_pcpu->count = 0;
4730 txq_pcpu->txq_put_index = 0;
4731 txq_pcpu->txq_get_index = 0;
4735 /* Cleanup all Tx queues */
4736 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
4738 struct mvpp2_tx_queue *txq;
4742 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
4744 /* Reset Tx ports and delete Tx queues */
4745 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
4746 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4748 for (queue = 0; queue < txq_number; queue++) {
4749 txq = port->txqs[queue];
4750 mvpp2_txq_clean(port, txq);
4751 mvpp2_txq_deinit(port, txq);
4754 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
4756 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
4757 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4760 /* Cleanup all Rx queues */
4761 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
4765 for (queue = 0; queue < rxq_number; queue++)
4766 mvpp2_rxq_deinit(port, port->rxqs[queue]);
4769 /* Init all Rx queues for port */
4770 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
4774 for (queue = 0; queue < rxq_number; queue++) {
4775 err = mvpp2_rxq_init(port, port->rxqs[queue]);
4782 mvpp2_cleanup_rxqs(port);
4786 /* Init all tx queues for port */
4787 static int mvpp2_setup_txqs(struct mvpp2_port *port)
4789 struct mvpp2_tx_queue *txq;
4792 for (queue = 0; queue < txq_number; queue++) {
4793 txq = port->txqs[queue];
4794 err = mvpp2_txq_init(port, txq);
4799 on_each_cpu(mvpp2_tx_done_pkts_coal_set, port, 1);
4800 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
4804 mvpp2_cleanup_txqs(port);
4808 /* The callback for per-port interrupt */
4809 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
4811 struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
4813 mvpp2_interrupts_disable(port);
4815 napi_schedule(&port->napi);
4821 static void mvpp2_link_event(struct net_device *dev)
4823 struct mvpp2_port *port = netdev_priv(dev);
4824 struct phy_device *phydev = port->phy_dev;
4825 int status_change = 0;
4829 if ((port->speed != phydev->speed) ||
4830 (port->duplex != phydev->duplex)) {
4833 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4834 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
4835 MVPP2_GMAC_CONFIG_GMII_SPEED |
4836 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
4837 MVPP2_GMAC_AN_SPEED_EN |
4838 MVPP2_GMAC_AN_DUPLEX_EN);
4841 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4843 if (phydev->speed == SPEED_1000)
4844 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4846 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
4848 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4850 port->duplex = phydev->duplex;
4851 port->speed = phydev->speed;
4855 if (phydev->link != port->link) {
4856 if (!phydev->link) {
4861 port->link = phydev->link;
4865 if (status_change) {
4867 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4868 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
4869 MVPP2_GMAC_FORCE_LINK_DOWN);
4870 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4871 mvpp2_egress_enable(port);
4872 mvpp2_ingress_enable(port);
4874 mvpp2_ingress_disable(port);
4875 mvpp2_egress_disable(port);
4877 phy_print_status(phydev);
4881 /* Main RX/TX processing routines */
4883 /* Display more error info */
4884 static void mvpp2_rx_error(struct mvpp2_port *port,
4885 struct mvpp2_rx_desc *rx_desc)
4887 u32 status = rx_desc->status;
4889 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
4890 case MVPP2_RXD_ERR_CRC:
4891 netdev_err(port->dev, "bad rx status %08x (crc error), size=%d\n",
4892 status, rx_desc->data_size);
4894 case MVPP2_RXD_ERR_OVERRUN:
4895 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%d\n",
4896 status, rx_desc->data_size);
4898 case MVPP2_RXD_ERR_RESOURCE:
4899 netdev_err(port->dev, "bad rx status %08x (resource error), size=%d\n",
4900 status, rx_desc->data_size);
4905 /* Handle RX checksum offload */
4906 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
4907 struct sk_buff *skb)
4909 if (((status & MVPP2_RXD_L3_IP4) &&
4910 !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
4911 (status & MVPP2_RXD_L3_IP6))
4912 if (((status & MVPP2_RXD_L4_UDP) ||
4913 (status & MVPP2_RXD_L4_TCP)) &&
4914 (status & MVPP2_RXD_L4_CSUM_OK)) {
4916 skb->ip_summed = CHECKSUM_UNNECESSARY;
4920 skb->ip_summed = CHECKSUM_NONE;
4923 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
4924 static int mvpp2_rx_refill(struct mvpp2_port *port,
4925 struct mvpp2_bm_pool *bm_pool,
4926 u32 bm, int is_recycle)
4928 struct sk_buff *skb;
4929 dma_addr_t phys_addr;
4932 (atomic_read(&bm_pool->in_use) < bm_pool->in_use_thresh))
4935 /* No recycle or too many buffers are in use, so allocate a new skb */
4936 skb = mvpp2_skb_alloc(port, bm_pool, &phys_addr, GFP_ATOMIC);
4940 mvpp2_pool_refill(port, bm, (u32)phys_addr, (u32)skb);
4941 atomic_dec(&bm_pool->in_use);
4945 /* Handle tx checksum */
4946 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
4948 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4952 if (skb->protocol == htons(ETH_P_IP)) {
4953 struct iphdr *ip4h = ip_hdr(skb);
4955 /* Calculate IPv4 checksum and L4 checksum */
4956 ip_hdr_len = ip4h->ihl;
4957 l4_proto = ip4h->protocol;
4958 } else if (skb->protocol == htons(ETH_P_IPV6)) {
4959 struct ipv6hdr *ip6h = ipv6_hdr(skb);
4961 /* Read l4_protocol from one of IPv6 extra headers */
4962 if (skb_network_header_len(skb) > 0)
4963 ip_hdr_len = (skb_network_header_len(skb) >> 2);
4964 l4_proto = ip6h->nexthdr;
4966 return MVPP2_TXD_L4_CSUM_NOT;
4969 return mvpp2_txq_desc_csum(skb_network_offset(skb),
4970 skb->protocol, ip_hdr_len, l4_proto);
4973 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
4976 static void mvpp2_buff_hdr_rx(struct mvpp2_port *port,
4977 struct mvpp2_rx_desc *rx_desc)
4979 struct mvpp2_buff_hdr *buff_hdr;
4980 struct sk_buff *skb;
4981 u32 rx_status = rx_desc->status;
4984 u32 buff_phys_addr_next;
4985 u32 buff_virt_addr_next;
4989 pool_id = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
4990 MVPP2_RXD_BM_POOL_ID_OFFS;
4991 buff_phys_addr = rx_desc->buf_phys_addr;
4992 buff_virt_addr = rx_desc->buf_cookie;
4995 skb = (struct sk_buff *)buff_virt_addr;
4996 buff_hdr = (struct mvpp2_buff_hdr *)skb->head;
4998 mc_id = MVPP2_B_HDR_INFO_MC_ID(buff_hdr->info);
5000 buff_phys_addr_next = buff_hdr->next_buff_phys_addr;
5001 buff_virt_addr_next = buff_hdr->next_buff_virt_addr;
5003 /* Release buffer */
5004 mvpp2_bm_pool_mc_put(port, pool_id, buff_phys_addr,
5005 buff_virt_addr, mc_id);
5007 buff_phys_addr = buff_phys_addr_next;
5008 buff_virt_addr = buff_virt_addr_next;
5010 } while (!MVPP2_B_HDR_INFO_IS_LAST(buff_hdr->info));
5013 /* Main rx processing */
5014 static int mvpp2_rx(struct mvpp2_port *port, int rx_todo,
5015 struct mvpp2_rx_queue *rxq)
5017 struct net_device *dev = port->dev;
5018 int rx_received, rx_filled, i;
5022 /* Get number of received packets and clamp the to-do */
5023 rx_received = mvpp2_rxq_received(port, rxq->id);
5024 if (rx_todo > rx_received)
5025 rx_todo = rx_received;
5028 for (i = 0; i < rx_todo; i++) {
5029 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
5030 struct mvpp2_bm_pool *bm_pool;
5031 struct sk_buff *skb;
5033 int pool, rx_bytes, err;
5036 rx_status = rx_desc->status;
5037 rx_bytes = rx_desc->data_size - MVPP2_MH_SIZE;
5039 bm = mvpp2_bm_cookie_build(rx_desc);
5040 pool = mvpp2_bm_cookie_pool_get(bm);
5041 bm_pool = &port->priv->bm_pools[pool];
5042 /* Check if buffer header is used */
5043 if (rx_status & MVPP2_RXD_BUF_HDR) {
5044 mvpp2_buff_hdr_rx(port, rx_desc);
5048 /* In case of an error, release the requested buffer pointer
5049 * to the Buffer Manager. This request process is controlled
5050 * by the hardware, and the information about the buffer is
5051 * comprised by the RX descriptor.
5053 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
5054 dev->stats.rx_errors++;
5055 mvpp2_rx_error(port, rx_desc);
5056 mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
5057 rx_desc->buf_cookie);
5061 skb = (struct sk_buff *)rx_desc->buf_cookie;
5064 rcvd_bytes += rx_bytes;
5065 atomic_inc(&bm_pool->in_use);
5067 skb_reserve(skb, MVPP2_MH_SIZE);
5068 skb_put(skb, rx_bytes);
5069 skb->protocol = eth_type_trans(skb, dev);
5070 mvpp2_rx_csum(port, rx_status, skb);
5072 napi_gro_receive(&port->napi, skb);
5074 err = mvpp2_rx_refill(port, bm_pool, bm, 0);
5076 netdev_err(port->dev, "failed to refill BM pools\n");
5082 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
5084 u64_stats_update_begin(&stats->syncp);
5085 stats->rx_packets += rcvd_pkts;
5086 stats->rx_bytes += rcvd_bytes;
5087 u64_stats_update_end(&stats->syncp);
5090 /* Update Rx queue management counters */
5092 mvpp2_rxq_status_update(port, rxq->id, rx_todo, rx_filled);
5098 tx_desc_unmap_put(struct device *dev, struct mvpp2_tx_queue *txq,
5099 struct mvpp2_tx_desc *desc)
5101 dma_unmap_single(dev, desc->buf_phys_addr,
5102 desc->data_size, DMA_TO_DEVICE);
5103 mvpp2_txq_desc_put(txq);
5106 /* Handle tx fragmentation processing */
5107 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
5108 struct mvpp2_tx_queue *aggr_txq,
5109 struct mvpp2_tx_queue *txq)
5111 struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu);
5112 struct mvpp2_tx_desc *tx_desc;
5114 dma_addr_t buf_phys_addr;
5116 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5117 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5118 void *addr = page_address(frag->page.p) + frag->page_offset;
5120 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
5121 tx_desc->phys_txq = txq->id;
5122 tx_desc->data_size = frag->size;
5124 buf_phys_addr = dma_map_single(port->dev->dev.parent, addr,
5127 if (dma_mapping_error(port->dev->dev.parent, buf_phys_addr)) {
5128 mvpp2_txq_desc_put(txq);
5132 tx_desc->packet_offset = buf_phys_addr & MVPP2_TX_DESC_ALIGN;
5133 tx_desc->buf_phys_addr = buf_phys_addr & (~MVPP2_TX_DESC_ALIGN);
5135 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
5136 /* Last descriptor */
5137 tx_desc->command = MVPP2_TXD_L_DESC;
5138 mvpp2_txq_inc_put(txq_pcpu, skb);
5140 /* Descriptor in the middle: Not First, Not Last */
5141 tx_desc->command = 0;
5142 mvpp2_txq_inc_put(txq_pcpu, NULL);
5149 /* Release all descriptors that were used to map fragments of
5150 * this packet, as well as the corresponding DMA mappings
5152 for (i = i - 1; i >= 0; i--) {
5153 tx_desc = txq->descs + i;
5154 tx_desc_unmap_put(port->dev->dev.parent, txq, tx_desc);
5160 /* Main tx processing */
5161 static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
5163 struct mvpp2_port *port = netdev_priv(dev);
5164 struct mvpp2_tx_queue *txq, *aggr_txq;
5165 struct mvpp2_txq_pcpu *txq_pcpu;
5166 struct mvpp2_tx_desc *tx_desc;
5167 dma_addr_t buf_phys_addr;
5172 txq_id = skb_get_queue_mapping(skb);
5173 txq = port->txqs[txq_id];
5174 txq_pcpu = this_cpu_ptr(txq->pcpu);
5175 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
5177 frags = skb_shinfo(skb)->nr_frags + 1;
5179 /* Check number of available descriptors */
5180 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) ||
5181 mvpp2_txq_reserved_desc_num_proc(port->priv, txq,
5187 /* Get a descriptor for the first part of the packet */
5188 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
5189 tx_desc->phys_txq = txq->id;
5190 tx_desc->data_size = skb_headlen(skb);
5192 buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
5193 tx_desc->data_size, DMA_TO_DEVICE);
5194 if (unlikely(dma_mapping_error(dev->dev.parent, buf_phys_addr))) {
5195 mvpp2_txq_desc_put(txq);
5199 tx_desc->packet_offset = buf_phys_addr & MVPP2_TX_DESC_ALIGN;
5200 tx_desc->buf_phys_addr = buf_phys_addr & ~MVPP2_TX_DESC_ALIGN;
5202 tx_cmd = mvpp2_skb_tx_csum(port, skb);
5205 /* First and Last descriptor */
5206 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
5207 tx_desc->command = tx_cmd;
5208 mvpp2_txq_inc_put(txq_pcpu, skb);
5210 /* First but not Last */
5211 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
5212 tx_desc->command = tx_cmd;
5213 mvpp2_txq_inc_put(txq_pcpu, NULL);
5215 /* Continue with other skb fragments */
5216 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
5217 tx_desc_unmap_put(port->dev->dev.parent, txq, tx_desc);
5223 txq_pcpu->reserved_num -= frags;
5224 txq_pcpu->count += frags;
5225 aggr_txq->count += frags;
5227 /* Enable transmit */
5229 mvpp2_aggr_txq_pend_desc_add(port, frags);
5231 if (txq_pcpu->size - txq_pcpu->count < MAX_SKB_FRAGS + 1) {
5232 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
5234 netif_tx_stop_queue(nq);
5238 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
5240 u64_stats_update_begin(&stats->syncp);
5241 stats->tx_packets++;
5242 stats->tx_bytes += skb->len;
5243 u64_stats_update_end(&stats->syncp);
5245 dev->stats.tx_dropped++;
5246 dev_kfree_skb_any(skb);
5249 return NETDEV_TX_OK;
5252 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
5254 if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
5255 netdev_err(dev, "FCS error\n");
5256 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
5257 netdev_err(dev, "rx fifo overrun error\n");
5258 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
5259 netdev_err(dev, "tx fifo underrun error\n");
5262 static void mvpp2_txq_done_percpu(void *arg)
5264 struct mvpp2_port *port = arg;
5265 u32 cause_rx_tx, cause_tx, cause_misc;
5267 /* Rx/Tx cause register
5269 * Bits 0-15: each bit indicates received packets on the Rx queue
5270 * (bit 0 is for Rx queue 0).
5272 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
5273 * (bit 16 is for Tx queue 0).
5275 * Each CPU has its own Rx/Tx cause register
5277 cause_rx_tx = mvpp2_read(port->priv,
5278 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
5279 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
5280 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
5283 mvpp2_cause_error(port->dev, cause_misc);
5285 /* Clear the cause register */
5286 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
5287 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
5288 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
5291 /* Release TX descriptors */
5293 struct mvpp2_tx_queue *txq = mvpp2_get_tx_queue(port, cause_tx);
5294 struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu);
5296 if (txq_pcpu->count)
5297 mvpp2_txq_done(port, txq, txq_pcpu);
5301 static int mvpp2_poll(struct napi_struct *napi, int budget)
5303 u32 cause_rx_tx, cause_rx;
5305 struct mvpp2_port *port = netdev_priv(napi->dev);
5307 on_each_cpu(mvpp2_txq_done_percpu, port, 1);
5309 cause_rx_tx = mvpp2_read(port->priv,
5310 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
5311 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
5313 /* Process RX packets */
5314 cause_rx |= port->pending_cause_rx;
5315 while (cause_rx && budget > 0) {
5317 struct mvpp2_rx_queue *rxq;
5319 rxq = mvpp2_get_rx_queue(port, cause_rx);
5323 count = mvpp2_rx(port, budget, rxq);
5327 /* Clear the bit associated to this Rx queue
5328 * so that next iteration will continue from
5329 * the next Rx queue.
5331 cause_rx &= ~(1 << rxq->logic_rxq);
5337 napi_complete(napi);
5339 mvpp2_interrupts_enable(port);
5341 port->pending_cause_rx = cause_rx;
5345 /* Set hw internals when starting port */
5346 static void mvpp2_start_dev(struct mvpp2_port *port)
5348 mvpp2_gmac_max_rx_size_set(port);
5349 mvpp2_txp_max_tx_size_set(port);
5351 napi_enable(&port->napi);
5353 /* Enable interrupts on all CPUs */
5354 mvpp2_interrupts_enable(port);
5356 mvpp2_port_enable(port);
5357 phy_start(port->phy_dev);
5358 netif_tx_start_all_queues(port->dev);
5361 /* Set hw internals when stopping port */
5362 static void mvpp2_stop_dev(struct mvpp2_port *port)
5364 /* Stop new packets from arriving to RXQs */
5365 mvpp2_ingress_disable(port);
5369 /* Disable interrupts on all CPUs */
5370 mvpp2_interrupts_disable(port);
5372 napi_disable(&port->napi);
5374 netif_carrier_off(port->dev);
5375 netif_tx_stop_all_queues(port->dev);
5377 mvpp2_egress_disable(port);
5378 mvpp2_port_disable(port);
5379 phy_stop(port->phy_dev);
5382 /* Return positive if MTU is valid */
5383 static inline int mvpp2_check_mtu_valid(struct net_device *dev, int mtu)
5386 netdev_err(dev, "cannot change mtu to less than 68\n");
5390 /* 9676 == 9700 - 20 and rounding to 8 */
5392 netdev_info(dev, "illegal MTU value %d, round to 9676\n", mtu);
5396 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
5397 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
5398 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
5399 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
5405 static int mvpp2_check_ringparam_valid(struct net_device *dev,
5406 struct ethtool_ringparam *ring)
5408 u16 new_rx_pending = ring->rx_pending;
5409 u16 new_tx_pending = ring->tx_pending;
5411 if (ring->rx_pending == 0 || ring->tx_pending == 0)
5414 if (ring->rx_pending > MVPP2_MAX_RXD)
5415 new_rx_pending = MVPP2_MAX_RXD;
5416 else if (!IS_ALIGNED(ring->rx_pending, 16))
5417 new_rx_pending = ALIGN(ring->rx_pending, 16);
5419 if (ring->tx_pending > MVPP2_MAX_TXD)
5420 new_tx_pending = MVPP2_MAX_TXD;
5421 else if (!IS_ALIGNED(ring->tx_pending, 32))
5422 new_tx_pending = ALIGN(ring->tx_pending, 32);
5424 if (ring->rx_pending != new_rx_pending) {
5425 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
5426 ring->rx_pending, new_rx_pending);
5427 ring->rx_pending = new_rx_pending;
5430 if (ring->tx_pending != new_tx_pending) {
5431 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
5432 ring->tx_pending, new_tx_pending);
5433 ring->tx_pending = new_tx_pending;
5439 static void mvpp2_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
5441 u32 mac_addr_l, mac_addr_m, mac_addr_h;
5443 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
5444 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
5445 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
5446 addr[0] = (mac_addr_h >> 24) & 0xFF;
5447 addr[1] = (mac_addr_h >> 16) & 0xFF;
5448 addr[2] = (mac_addr_h >> 8) & 0xFF;
5449 addr[3] = mac_addr_h & 0xFF;
5450 addr[4] = mac_addr_m & 0xFF;
5451 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
5454 static int mvpp2_phy_connect(struct mvpp2_port *port)
5456 struct phy_device *phy_dev;
5458 phy_dev = of_phy_connect(port->dev, port->phy_node, mvpp2_link_event, 0,
5459 port->phy_interface);
5461 netdev_err(port->dev, "cannot connect to phy\n");
5464 phy_dev->supported &= PHY_GBIT_FEATURES;
5465 phy_dev->advertising = phy_dev->supported;
5467 port->phy_dev = phy_dev;
5475 static void mvpp2_phy_disconnect(struct mvpp2_port *port)
5477 phy_disconnect(port->phy_dev);
5478 port->phy_dev = NULL;
5481 static int mvpp2_open(struct net_device *dev)
5483 struct mvpp2_port *port = netdev_priv(dev);
5484 unsigned char mac_bcast[ETH_ALEN] = {
5485 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
5488 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
5490 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
5493 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
5494 dev->dev_addr, true);
5496 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
5499 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
5501 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
5504 err = mvpp2_prs_def_flow(port);
5506 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
5510 /* Allocate the Rx/Tx queues */
5511 err = mvpp2_setup_rxqs(port);
5513 netdev_err(port->dev, "cannot allocate Rx queues\n");
5517 err = mvpp2_setup_txqs(port);
5519 netdev_err(port->dev, "cannot allocate Tx queues\n");
5520 goto err_cleanup_rxqs;
5523 err = request_irq(port->irq, mvpp2_isr, 0, dev->name, port);
5525 netdev_err(port->dev, "cannot request IRQ %d\n", port->irq);
5526 goto err_cleanup_txqs;
5529 /* In default link is down */
5530 netif_carrier_off(port->dev);
5532 err = mvpp2_phy_connect(port);
5536 /* Unmask interrupts on all CPUs */
5537 on_each_cpu(mvpp2_interrupts_unmask, port, 1);
5539 mvpp2_start_dev(port);
5544 free_irq(port->irq, port);
5546 mvpp2_cleanup_txqs(port);
5548 mvpp2_cleanup_rxqs(port);
5552 static int mvpp2_stop(struct net_device *dev)
5554 struct mvpp2_port *port = netdev_priv(dev);
5556 mvpp2_stop_dev(port);
5557 mvpp2_phy_disconnect(port);
5559 /* Mask interrupts on all CPUs */
5560 on_each_cpu(mvpp2_interrupts_mask, port, 1);
5562 free_irq(port->irq, port);
5563 mvpp2_cleanup_rxqs(port);
5564 mvpp2_cleanup_txqs(port);
5569 static void mvpp2_set_rx_mode(struct net_device *dev)
5571 struct mvpp2_port *port = netdev_priv(dev);
5572 struct mvpp2 *priv = port->priv;
5573 struct netdev_hw_addr *ha;
5575 bool allmulti = dev->flags & IFF_ALLMULTI;
5577 mvpp2_prs_mac_promisc_set(priv, id, dev->flags & IFF_PROMISC);
5578 mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_ALL, allmulti);
5579 mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_IP6, allmulti);
5581 /* Remove all port->id's mcast enries */
5582 mvpp2_prs_mcast_del_all(priv, id);
5584 if (allmulti && !netdev_mc_empty(dev)) {
5585 netdev_for_each_mc_addr(ha, dev)
5586 mvpp2_prs_mac_da_accept(priv, id, ha->addr, true);
5590 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
5592 struct mvpp2_port *port = netdev_priv(dev);
5593 const struct sockaddr *addr = p;
5596 if (!is_valid_ether_addr(addr->sa_data)) {
5597 err = -EADDRNOTAVAIL;
5601 if (!netif_running(dev)) {
5602 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
5605 /* Reconfigure parser to accept the original MAC address */
5606 err = mvpp2_prs_update_mac_da(dev, dev->dev_addr);
5611 mvpp2_stop_dev(port);
5613 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
5617 /* Reconfigure parser accept the original MAC address */
5618 err = mvpp2_prs_update_mac_da(dev, dev->dev_addr);
5622 mvpp2_start_dev(port);
5623 mvpp2_egress_enable(port);
5624 mvpp2_ingress_enable(port);
5628 netdev_err(dev, "fail to change MAC address\n");
5632 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
5634 struct mvpp2_port *port = netdev_priv(dev);
5637 mtu = mvpp2_check_mtu_valid(dev, mtu);
5643 if (!netif_running(dev)) {
5644 err = mvpp2_bm_update_mtu(dev, mtu);
5646 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
5650 /* Reconfigure BM to the original MTU */
5651 err = mvpp2_bm_update_mtu(dev, dev->mtu);
5656 mvpp2_stop_dev(port);
5658 err = mvpp2_bm_update_mtu(dev, mtu);
5660 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
5664 /* Reconfigure BM to the original MTU */
5665 err = mvpp2_bm_update_mtu(dev, dev->mtu);
5670 mvpp2_start_dev(port);
5671 mvpp2_egress_enable(port);
5672 mvpp2_ingress_enable(port);
5677 netdev_err(dev, "fail to change MTU\n");
5681 static struct rtnl_link_stats64 *
5682 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5684 struct mvpp2_port *port = netdev_priv(dev);
5688 for_each_possible_cpu(cpu) {
5689 struct mvpp2_pcpu_stats *cpu_stats;
5695 cpu_stats = per_cpu_ptr(port->stats, cpu);
5697 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
5698 rx_packets = cpu_stats->rx_packets;
5699 rx_bytes = cpu_stats->rx_bytes;
5700 tx_packets = cpu_stats->tx_packets;
5701 tx_bytes = cpu_stats->tx_bytes;
5702 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
5704 stats->rx_packets += rx_packets;
5705 stats->rx_bytes += rx_bytes;
5706 stats->tx_packets += tx_packets;
5707 stats->tx_bytes += tx_bytes;
5710 stats->rx_errors = dev->stats.rx_errors;
5711 stats->rx_dropped = dev->stats.rx_dropped;
5712 stats->tx_dropped = dev->stats.tx_dropped;
5717 /* Ethtool methods */
5719 /* Get settings (phy address, speed) for ethtools */
5720 static int mvpp2_ethtool_get_settings(struct net_device *dev,
5721 struct ethtool_cmd *cmd)
5723 struct mvpp2_port *port = netdev_priv(dev);
5727 return phy_ethtool_gset(port->phy_dev, cmd);
5730 /* Set settings (phy address, speed) for ethtools */
5731 static int mvpp2_ethtool_set_settings(struct net_device *dev,
5732 struct ethtool_cmd *cmd)
5734 struct mvpp2_port *port = netdev_priv(dev);
5738 return phy_ethtool_sset(port->phy_dev, cmd);
5741 /* Set interrupt coalescing for ethtools */
5742 static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
5743 struct ethtool_coalesce *c)
5745 struct mvpp2_port *port = netdev_priv(dev);
5748 for (queue = 0; queue < rxq_number; queue++) {
5749 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5751 rxq->time_coal = c->rx_coalesce_usecs;
5752 rxq->pkts_coal = c->rx_max_coalesced_frames;
5753 mvpp2_rx_pkts_coal_set(port, rxq, rxq->pkts_coal);
5754 mvpp2_rx_time_coal_set(port, rxq, rxq->time_coal);
5757 for (queue = 0; queue < txq_number; queue++) {
5758 struct mvpp2_tx_queue *txq = port->txqs[queue];
5760 txq->done_pkts_coal = c->tx_max_coalesced_frames;
5763 on_each_cpu(mvpp2_tx_done_pkts_coal_set, port, 1);
5767 /* get coalescing for ethtools */
5768 static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
5769 struct ethtool_coalesce *c)
5771 struct mvpp2_port *port = netdev_priv(dev);
5773 c->rx_coalesce_usecs = port->rxqs[0]->time_coal;
5774 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
5775 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
5779 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
5780 struct ethtool_drvinfo *drvinfo)
5782 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
5783 sizeof(drvinfo->driver));
5784 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
5785 sizeof(drvinfo->version));
5786 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
5787 sizeof(drvinfo->bus_info));
5790 static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
5791 struct ethtool_ringparam *ring)
5793 struct mvpp2_port *port = netdev_priv(dev);
5795 ring->rx_max_pending = MVPP2_MAX_RXD;
5796 ring->tx_max_pending = MVPP2_MAX_TXD;
5797 ring->rx_pending = port->rx_ring_size;
5798 ring->tx_pending = port->tx_ring_size;
5801 static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
5802 struct ethtool_ringparam *ring)
5804 struct mvpp2_port *port = netdev_priv(dev);
5805 u16 prev_rx_ring_size = port->rx_ring_size;
5806 u16 prev_tx_ring_size = port->tx_ring_size;
5809 err = mvpp2_check_ringparam_valid(dev, ring);
5813 if (!netif_running(dev)) {
5814 port->rx_ring_size = ring->rx_pending;
5815 port->tx_ring_size = ring->tx_pending;
5819 /* The interface is running, so we have to force a
5820 * reallocation of the queues
5822 mvpp2_stop_dev(port);
5823 mvpp2_cleanup_rxqs(port);
5824 mvpp2_cleanup_txqs(port);
5826 port->rx_ring_size = ring->rx_pending;
5827 port->tx_ring_size = ring->tx_pending;
5829 err = mvpp2_setup_rxqs(port);
5831 /* Reallocate Rx queues with the original ring size */
5832 port->rx_ring_size = prev_rx_ring_size;
5833 ring->rx_pending = prev_rx_ring_size;
5834 err = mvpp2_setup_rxqs(port);
5838 err = mvpp2_setup_txqs(port);
5840 /* Reallocate Tx queues with the original ring size */
5841 port->tx_ring_size = prev_tx_ring_size;
5842 ring->tx_pending = prev_tx_ring_size;
5843 err = mvpp2_setup_txqs(port);
5845 goto err_clean_rxqs;
5848 mvpp2_start_dev(port);
5849 mvpp2_egress_enable(port);
5850 mvpp2_ingress_enable(port);
5855 mvpp2_cleanup_rxqs(port);
5857 netdev_err(dev, "fail to change ring parameters");
5863 static const struct net_device_ops mvpp2_netdev_ops = {
5864 .ndo_open = mvpp2_open,
5865 .ndo_stop = mvpp2_stop,
5866 .ndo_start_xmit = mvpp2_tx,
5867 .ndo_set_rx_mode = mvpp2_set_rx_mode,
5868 .ndo_set_mac_address = mvpp2_set_mac_address,
5869 .ndo_change_mtu = mvpp2_change_mtu,
5870 .ndo_get_stats64 = mvpp2_get_stats64,
5873 static const struct ethtool_ops mvpp2_eth_tool_ops = {
5874 .get_link = ethtool_op_get_link,
5875 .get_settings = mvpp2_ethtool_get_settings,
5876 .set_settings = mvpp2_ethtool_set_settings,
5877 .set_coalesce = mvpp2_ethtool_set_coalesce,
5878 .get_coalesce = mvpp2_ethtool_get_coalesce,
5879 .get_drvinfo = mvpp2_ethtool_get_drvinfo,
5880 .get_ringparam = mvpp2_ethtool_get_ringparam,
5881 .set_ringparam = mvpp2_ethtool_set_ringparam,
5884 /* Driver initialization */
5886 static void mvpp2_port_power_up(struct mvpp2_port *port)
5888 mvpp2_port_mii_set(port);
5889 mvpp2_port_periodic_xon_disable(port);
5890 mvpp2_port_fc_adv_enable(port);
5891 mvpp2_port_reset(port);
5894 /* Initialize port HW */
5895 static int mvpp2_port_init(struct mvpp2_port *port)
5897 struct device *dev = port->dev->dev.parent;
5898 struct mvpp2 *priv = port->priv;
5899 struct mvpp2_txq_pcpu *txq_pcpu;
5900 int queue, cpu, err;
5902 if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
5906 mvpp2_egress_disable(port);
5907 mvpp2_port_disable(port);
5909 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
5914 /* Associate physical Tx queues to this port and initialize.
5915 * The mapping is predefined.
5917 for (queue = 0; queue < txq_number; queue++) {
5918 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
5919 struct mvpp2_tx_queue *txq;
5921 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
5925 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
5928 goto err_free_percpu;
5931 txq->id = queue_phy_id;
5932 txq->log_id = queue;
5933 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
5934 for_each_present_cpu(cpu) {
5935 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
5936 txq_pcpu->cpu = cpu;
5939 port->txqs[queue] = txq;
5942 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
5946 goto err_free_percpu;
5949 /* Allocate and initialize Rx queue for this port */
5950 for (queue = 0; queue < rxq_number; queue++) {
5951 struct mvpp2_rx_queue *rxq;
5953 /* Map physical Rx queue to port's logical Rx queue */
5954 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
5956 goto err_free_percpu;
5957 /* Map this Rx queue to a physical queue */
5958 rxq->id = port->first_rxq + queue;
5959 rxq->port = port->id;
5960 rxq->logic_rxq = queue;
5962 port->rxqs[queue] = rxq;
5965 /* Configure Rx queue group interrupt for this port */
5966 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), rxq_number);
5968 /* Create Rx descriptor rings */
5969 for (queue = 0; queue < rxq_number; queue++) {
5970 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5972 rxq->size = port->rx_ring_size;
5973 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
5974 rxq->time_coal = MVPP2_RX_COAL_USEC;
5977 mvpp2_ingress_disable(port);
5979 /* Port default configuration */
5980 mvpp2_defaults_set(port);
5982 /* Port's classifier configuration */
5983 mvpp2_cls_oversize_rxq_set(port);
5984 mvpp2_cls_port_config(port);
5986 /* Provide an initial Rx packet size */
5987 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
5989 /* Initialize pools for swf */
5990 err = mvpp2_swf_bm_pool_init(port);
5992 goto err_free_percpu;
5997 for (queue = 0; queue < txq_number; queue++) {
5998 if (!port->txqs[queue])
6000 free_percpu(port->txqs[queue]->pcpu);
6005 /* Ports initialization */
6006 static int mvpp2_port_probe(struct platform_device *pdev,
6007 struct device_node *port_node,
6009 int *next_first_rxq)
6011 struct device_node *phy_node;
6012 struct mvpp2_port *port;
6013 struct net_device *dev;
6014 struct resource *res;
6015 const char *dt_mac_addr;
6016 const char *mac_from;
6017 char hw_mac_addr[ETH_ALEN];
6021 int priv_common_regs_num = 2;
6024 dev = alloc_etherdev_mqs(sizeof(struct mvpp2_port), txq_number,
6029 phy_node = of_parse_phandle(port_node, "phy", 0);
6031 dev_err(&pdev->dev, "missing phy\n");
6033 goto err_free_netdev;
6036 phy_mode = of_get_phy_mode(port_node);
6038 dev_err(&pdev->dev, "incorrect phy mode\n");
6040 goto err_free_netdev;
6043 if (of_property_read_u32(port_node, "port-id", &id)) {
6045 dev_err(&pdev->dev, "missing port-id value\n");
6046 goto err_free_netdev;
6049 dev->tx_queue_len = MVPP2_MAX_TXD;
6050 dev->watchdog_timeo = 5 * HZ;
6051 dev->netdev_ops = &mvpp2_netdev_ops;
6052 dev->ethtool_ops = &mvpp2_eth_tool_ops;
6054 port = netdev_priv(dev);
6056 port->irq = irq_of_parse_and_map(port_node, 0);
6057 if (port->irq <= 0) {
6059 goto err_free_netdev;
6062 if (of_property_read_bool(port_node, "marvell,loopback"))
6063 port->flags |= MVPP2_F_LOOPBACK;
6067 port->first_rxq = *next_first_rxq;
6068 port->phy_node = phy_node;
6069 port->phy_interface = phy_mode;
6071 res = platform_get_resource(pdev, IORESOURCE_MEM,
6072 priv_common_regs_num + id);
6073 port->base = devm_ioremap_resource(&pdev->dev, res);
6074 if (IS_ERR(port->base)) {
6075 err = PTR_ERR(port->base);
6079 /* Alloc per-cpu stats */
6080 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
6086 dt_mac_addr = of_get_mac_address(port_node);
6087 if (dt_mac_addr && is_valid_ether_addr(dt_mac_addr)) {
6088 mac_from = "device tree";
6089 ether_addr_copy(dev->dev_addr, dt_mac_addr);
6091 mvpp2_get_mac_address(port, hw_mac_addr);
6092 if (is_valid_ether_addr(hw_mac_addr)) {
6093 mac_from = "hardware";
6094 ether_addr_copy(dev->dev_addr, hw_mac_addr);
6096 mac_from = "random";
6097 eth_hw_addr_random(dev);
6101 port->tx_ring_size = MVPP2_MAX_TXD;
6102 port->rx_ring_size = MVPP2_MAX_RXD;
6104 SET_NETDEV_DEV(dev, &pdev->dev);
6106 err = mvpp2_port_init(port);
6108 dev_err(&pdev->dev, "failed to init port %d\n", id);
6109 goto err_free_stats;
6111 mvpp2_port_power_up(port);
6113 netif_napi_add(dev, &port->napi, mvpp2_poll, NAPI_POLL_WEIGHT);
6114 features = NETIF_F_SG | NETIF_F_IP_CSUM;
6115 dev->features = features | NETIF_F_RXCSUM;
6116 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO;
6117 dev->vlan_features |= features;
6119 err = register_netdev(dev);
6121 dev_err(&pdev->dev, "failed to register netdev\n");
6122 goto err_free_txq_pcpu;
6124 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
6126 /* Increment the first Rx queue number to be used by the next port */
6127 *next_first_rxq += rxq_number;
6128 priv->port_list[id] = port;
6132 for (i = 0; i < txq_number; i++)
6133 free_percpu(port->txqs[i]->pcpu);
6135 free_percpu(port->stats);
6137 irq_dispose_mapping(port->irq);
6143 /* Ports removal routine */
6144 static void mvpp2_port_remove(struct mvpp2_port *port)
6148 unregister_netdev(port->dev);
6149 free_percpu(port->stats);
6150 for (i = 0; i < txq_number; i++)
6151 free_percpu(port->txqs[i]->pcpu);
6152 irq_dispose_mapping(port->irq);
6153 free_netdev(port->dev);
6156 /* Initialize decoding windows */
6157 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
6163 for (i = 0; i < 6; i++) {
6164 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
6165 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
6168 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
6173 for (i = 0; i < dram->num_cs; i++) {
6174 const struct mbus_dram_window *cs = dram->cs + i;
6176 mvpp2_write(priv, MVPP2_WIN_BASE(i),
6177 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
6178 dram->mbus_dram_target_id);
6180 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
6181 (cs->size - 1) & 0xffff0000);
6183 win_enable |= (1 << i);
6186 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
6189 /* Initialize Rx FIFO's */
6190 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
6194 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
6195 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
6196 MVPP2_RX_FIFO_PORT_DATA_SIZE);
6197 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
6198 MVPP2_RX_FIFO_PORT_ATTR_SIZE);
6201 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
6202 MVPP2_RX_FIFO_PORT_MIN_PKT);
6203 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
6206 /* Initialize network controller common part HW */
6207 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
6209 const struct mbus_dram_target_info *dram_target_info;
6213 /* Checks for hardware constraints */
6214 if (rxq_number % 4 || (rxq_number > MVPP2_MAX_RXQ) ||
6215 (txq_number > MVPP2_MAX_TXQ)) {
6216 dev_err(&pdev->dev, "invalid queue size parameter\n");
6220 /* MBUS windows configuration */
6221 dram_target_info = mv_mbus_dram_info();
6222 if (dram_target_info)
6223 mvpp2_conf_mbus_windows(dram_target_info, priv);
6225 /* Disable HW PHY polling */
6226 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
6227 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
6228 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
6230 /* Allocate and initialize aggregated TXQs */
6231 priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(),
6232 sizeof(struct mvpp2_tx_queue),
6234 if (!priv->aggr_txqs)
6237 for_each_present_cpu(i) {
6238 priv->aggr_txqs[i].id = i;
6239 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
6240 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i],
6241 MVPP2_AGGR_TXQ_SIZE, i, priv);
6247 mvpp2_rx_fifo_init(priv);
6249 /* Reset Rx queue group interrupt configuration */
6250 for (i = 0; i < MVPP2_MAX_PORTS; i++)
6251 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i), rxq_number);
6253 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
6254 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
6256 /* Allow cache snoop when transmiting packets */
6257 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
6259 /* Buffer Manager initialization */
6260 err = mvpp2_bm_init(pdev, priv);
6264 /* Parser default initialization */
6265 err = mvpp2_prs_default_init(pdev, priv);
6269 /* Classifier default initialization */
6270 mvpp2_cls_init(priv);
6275 static int mvpp2_probe(struct platform_device *pdev)
6277 struct device_node *dn = pdev->dev.of_node;
6278 struct device_node *port_node;
6280 struct resource *res;
6281 int port_count, first_rxq;
6284 priv = devm_kzalloc(&pdev->dev, sizeof(struct mvpp2), GFP_KERNEL);
6288 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6289 priv->base = devm_ioremap_resource(&pdev->dev, res);
6290 if (IS_ERR(priv->base))
6291 return PTR_ERR(priv->base);
6293 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
6294 priv->lms_base = devm_ioremap_resource(&pdev->dev, res);
6295 if (IS_ERR(priv->lms_base))
6296 return PTR_ERR(priv->lms_base);
6298 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
6299 if (IS_ERR(priv->pp_clk))
6300 return PTR_ERR(priv->pp_clk);
6301 err = clk_prepare_enable(priv->pp_clk);
6305 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
6306 if (IS_ERR(priv->gop_clk)) {
6307 err = PTR_ERR(priv->gop_clk);
6310 err = clk_prepare_enable(priv->gop_clk);
6314 /* Get system's tclk rate */
6315 priv->tclk = clk_get_rate(priv->pp_clk);
6317 /* Initialize network controller */
6318 err = mvpp2_init(pdev, priv);
6320 dev_err(&pdev->dev, "failed to initialize controller\n");
6324 port_count = of_get_available_child_count(dn);
6325 if (port_count == 0) {
6326 dev_err(&pdev->dev, "no ports enabled\n");
6331 priv->port_list = devm_kcalloc(&pdev->dev, port_count,
6332 sizeof(struct mvpp2_port *),
6334 if (!priv->port_list) {
6339 /* Initialize ports */
6341 for_each_available_child_of_node(dn, port_node) {
6342 err = mvpp2_port_probe(pdev, port_node, priv, &first_rxq);
6347 platform_set_drvdata(pdev, priv);
6351 clk_disable_unprepare(priv->gop_clk);
6353 clk_disable_unprepare(priv->pp_clk);
6357 static int mvpp2_remove(struct platform_device *pdev)
6359 struct mvpp2 *priv = platform_get_drvdata(pdev);
6360 struct device_node *dn = pdev->dev.of_node;
6361 struct device_node *port_node;
6364 for_each_available_child_of_node(dn, port_node) {
6365 if (priv->port_list[i])
6366 mvpp2_port_remove(priv->port_list[i]);
6370 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
6371 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
6373 mvpp2_bm_pool_destroy(pdev, priv, bm_pool);
6376 for_each_present_cpu(i) {
6377 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
6379 dma_free_coherent(&pdev->dev,
6380 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
6382 aggr_txq->descs_phys);
6385 clk_disable_unprepare(priv->pp_clk);
6386 clk_disable_unprepare(priv->gop_clk);
6391 static const struct of_device_id mvpp2_match[] = {
6392 { .compatible = "marvell,armada-375-pp2" },
6395 MODULE_DEVICE_TABLE(of, mvpp2_match);
6397 static struct platform_driver mvpp2_driver = {
6398 .probe = mvpp2_probe,
6399 .remove = mvpp2_remove,
6401 .name = MVPP2_DRIVER_NAME,
6402 .of_match_table = mvpp2_match,
6406 module_platform_driver(mvpp2_driver);
6408 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
6409 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
6410 MODULE_LICENSE("GPL v2");