drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/busy_poll.h>
  35 #include <linux/bpf.h>
  36 #include <linux/bpf_trace.h>
  37 #include <linux/mlx4/cq.h>
  38 #include <linux/slab.h>
  39 #include <linux/mlx4/qp.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/rculist.h>
  42 #include <linux/if_ether.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/irq.h>
  46
  47 #if IS_ENABLED(CONFIG_IPV6)
  48 #include <net/ip6_checksum.h>
  49 #endif
  50
  51 #include "mlx4_en.h"
  52
  53 static int mlx4_alloc_page(struct mlx4_en_priv *priv,
  54                            struct mlx4_en_rx_alloc *frag,
  55                            gfp_t gfp)
  56 {
  57         struct page *page;
  58         dma_addr_t dma;
  59
  60         page = alloc_page(gfp);
  61         if (unlikely(!page))
  62                 return -ENOMEM;
  63         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE, priv->dma_dir);
  64         if (unlikely(dma_mapping_error(priv->ddev, dma))) {
  65                 __free_page(page);
  66                 return -ENOMEM;
  67         }
  68         frag->page = page;
  69         frag->dma = dma;
  70         frag->page_offset = priv->rx_headroom;
  71         return 0;
  72 }
  73
  74 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  75                                struct mlx4_en_rx_ring *ring,
  76                                struct mlx4_en_rx_desc *rx_desc,
  77                                struct mlx4_en_rx_alloc *frags,
  78                                gfp_t gfp)
  79 {
  80         int i;
  81
  82         for (i = 0; i < priv->num_frags; i++, frags++) {
  83                 if (!frags->page) {
  84                         if (mlx4_alloc_page(priv, frags, gfp))
  85                                 return -ENOMEM;
  86                         ring->rx_alloc_pages++;
  87                 }
  88                 rx_desc->data[i].addr = cpu_to_be64(frags->dma +
  89                                                     frags->page_offset);
  90         }
  91         return 0;
  92 }
  93
  94 static void mlx4_en_free_frag(const struct mlx4_en_priv *priv,
  95                               struct mlx4_en_rx_alloc *frag)
  96 {
  97         if (frag->page) {
  98                 dma_unmap_page(priv->ddev, frag->dma,
  99                                PAGE_SIZE, priv->dma_dir);
 100                 __free_page(frag->page);
 101         }
 102         /* We need to clear all fields, otherwise a change of priv->log_rx_info
 103          * could lead to see garbage later in frag->page.
 104          */
 105         memset(frag, 0, sizeof(*frag));
 106 }
 107
 108 static void mlx4_en_init_rx_desc(const struct mlx4_en_priv *priv,
 109                                  struct mlx4_en_rx_ring *ring, int index)
 110 {
 111         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 112         int possible_frags;
 113         int i;
 114
 115         /* Set size and memtype fields */
 116         for (i = 0; i < priv->num_frags; i++) {
 117                 rx_desc->data[i].byte_count =
 118                         cpu_to_be32(priv->frag_info[i].frag_size);
 119                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 120         }
 121
 122         /* If the number of used fragments does not fill up the ring stride,
 123          * remaining (unused) fragments must be padded with null address/size
 124          * and a special memory key */
 125         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 126         for (i = priv->num_frags; i < possible_frags; i++) {
 127                 rx_desc->data[i].byte_count = 0;
 128                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 129                 rx_desc->data[i].addr = 0;
 130         }
 131 }
 132
 133 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 134                                    struct mlx4_en_rx_ring *ring, int index,
 135                                    gfp_t gfp)
 136 {
 137         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 138         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 139                                         (index << priv->log_rx_info);
 140         if (ring->page_cache.index > 0) {
 141                 /* XDP uses a single page per frame */
 142                 if (!frags->page) {
 143                         ring->page_cache.index--;
 144                         frags->page = ring->page_cache.buf[ring->page_cache.index].page;
 145                         frags->dma  = ring->page_cache.buf[ring->page_cache.index].dma;
 146                 }
 147                 frags->page_offset = XDP_PACKET_HEADROOM;
 148                 rx_desc->data[0].addr = cpu_to_be64(frags->dma +
 149                                                     XDP_PACKET_HEADROOM);
 150                 return 0;
 151         }
 152
 153         return mlx4_en_alloc_frags(priv, ring, rx_desc, frags, gfp);
 154 }
 155
 156 static bool mlx4_en_is_ring_empty(const struct mlx4_en_rx_ring *ring)
 157 {
 158         return ring->prod == ring->cons;
 159 }
 160
 161 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 162 {
 163         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 164 }
 165
 166 /* slow path */
 167 static void mlx4_en_free_rx_desc(const struct mlx4_en_priv *priv,
 168                                  struct mlx4_en_rx_ring *ring,
 169                                  int index)
 170 {
 171         struct mlx4_en_rx_alloc *frags;
 172         int nr;
 173
 174         frags = ring->rx_info + (index << priv->log_rx_info);
 175         for (nr = 0; nr < priv->num_frags; nr++) {
 176                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 177                 mlx4_en_free_frag(priv, frags + nr);
 178         }
 179 }
 180
 181 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 182 {
 183         struct mlx4_en_rx_ring *ring;
 184         int ring_ind;
 185         int buf_ind;
 186         int new_size;
 187
 188         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 189                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 190                         ring = priv->rx_ring[ring_ind];
 191
 192                         if (mlx4_en_prepare_rx_desc(priv, ring,
 193                                                     ring->actual_size,
 194                                                     GFP_KERNEL | __GFP_COLD)) {
 195                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 196                                         en_err(priv, "Failed to allocate enough rx buffers\n");
 197                                         return -ENOMEM;
 198                                 } else {
 199                                         new_size = rounddown_pow_of_two(ring->actual_size);
 200                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
 201                                                 ring->actual_size, new_size);
 202                                         goto reduce_rings;
 203                                 }
 204                         }
 205                         ring->actual_size++;
 206                         ring->prod++;
 207                 }
 208         }
 209         return 0;
 210
 211 reduce_rings:
 212         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 213                 ring = priv->rx_ring[ring_ind];
 214                 while (ring->actual_size > new_size) {
 215                         ring->actual_size--;
 216                         ring->prod--;
 217                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 218                 }
 219         }
 220
 221         return 0;
 222 }
 223
 224 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 225                                 struct mlx4_en_rx_ring *ring)
 226 {
 227         int index;
 228
 229         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 230                ring->cons, ring->prod);
 231
 232         /* Unmap and free Rx buffers */
 233         for (index = 0; index < ring->size; index++) {
 234                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 235                 mlx4_en_free_rx_desc(priv, ring, index);
 236         }
 237         ring->cons = 0;
 238         ring->prod = 0;
 239 }
 240
 241 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
 242 {
 243         int i;
 244         int num_of_eqs;
 245         int num_rx_rings;
 246         struct mlx4_dev *dev = mdev->dev;
 247
 248         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
 249                 num_of_eqs = max_t(int, MIN_RX_RINGS,
 250                                    min_t(int,
 251                                          mlx4_get_eqs_per_port(mdev->dev, i),
 252                                          DEF_RX_RINGS));
 253
 254                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
 255                         min_t(int, num_of_eqs,
 256                               netif_get_num_default_rss_queues());
 257                 mdev->profile.prof[i].rx_ring_num =
 258                         rounddown_pow_of_two(num_rx_rings);
 259         }
 260 }
 261
 262 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 263                            struct mlx4_en_rx_ring **pring,
 264                            u32 size, u16 stride, int node)
 265 {
 266         struct mlx4_en_dev *mdev = priv->mdev;
 267         struct mlx4_en_rx_ring *ring;
 268         int err = -ENOMEM;
 269         int tmp;
 270
 271         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
 272         if (!ring) {
 273                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 274                 if (!ring) {
 275                         en_err(priv, "Failed to allocate RX ring structure\n");
 276                         return -ENOMEM;
 277                 }
 278         }
 279
 280         ring->prod = 0;
 281         ring->cons = 0;
 282         ring->size = size;
 283         ring->size_mask = size - 1;
 284         ring->stride = stride;
 285         ring->log_stride = ffs(ring->stride) - 1;
 286         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 287
 288         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 289                                         sizeof(struct mlx4_en_rx_alloc));
 290         ring->rx_info = vzalloc_node(tmp, node);
 291         if (!ring->rx_info) {
 292                 ring->rx_info = vzalloc(tmp);
 293                 if (!ring->rx_info) {
 294                         err = -ENOMEM;
 295                         goto err_ring;
 296                 }
 297         }
 298
 299         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 300                  ring->rx_info, tmp);
 301
 302         /* Allocate HW buffers on provided NUMA node */
 303         set_dev_node(&mdev->dev->persist->pdev->dev, node);
 304         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 305         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
 306         if (err)
 307                 goto err_info;
 308
 309         ring->buf = ring->wqres.buf.direct.buf;
 310
 311         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 312
 313         *pring = ring;
 314         return 0;
 315
 316 err_info:
 317         vfree(ring->rx_info);
 318         ring->rx_info = NULL;
 319 err_ring:
 320         kfree(ring);
 321         *pring = NULL;
 322
 323         return err;
 324 }
 325
 326 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 327 {
 328         struct mlx4_en_rx_ring *ring;
 329         int i;
 330         int ring_ind;
 331         int err;
 332         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 333                                         DS_SIZE * priv->num_frags);
 334
 335         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 336                 ring = priv->rx_ring[ring_ind];
 337
 338                 ring->prod = 0;
 339                 ring->cons = 0;
 340                 ring->actual_size = 0;
 341                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 342
 343                 ring->stride = stride;
 344                 if (ring->stride <= TXBB_SIZE) {
 345                         /* Stamp first unused send wqe */
 346                         __be32 *ptr = (__be32 *)ring->buf;
 347                         __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT);
 348                         *ptr = stamp;
 349                         /* Move pointer to start of rx section */
 350                         ring->buf += TXBB_SIZE;
 351                 }
 352
 353                 ring->log_stride = ffs(ring->stride) - 1;
 354                 ring->buf_size = ring->size * ring->stride;
 355
 356                 memset(ring->buf, 0, ring->buf_size);
 357                 mlx4_en_update_rx_prod_db(ring);
 358
 359                 /* Initialize all descriptors */
 360                 for (i = 0; i < ring->size; i++)
 361                         mlx4_en_init_rx_desc(priv, ring, i);
 362         }
 363         err = mlx4_en_fill_rx_buffers(priv);
 364         if (err)
 365                 goto err_buffers;
 366
 367         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 368                 ring = priv->rx_ring[ring_ind];
 369
 370                 ring->size_mask = ring->actual_size - 1;
 371                 mlx4_en_update_rx_prod_db(ring);
 372         }
 373
 374         return 0;
 375
 376 err_buffers:
 377         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 378                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 379
 380         ring_ind = priv->rx_ring_num - 1;
 381         while (ring_ind >= 0) {
 382                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
 383                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
 384                 ring_ind--;
 385         }
 386         return err;
 387 }
 388
 389 /* We recover from out of memory by scheduling our napi poll
 390  * function (mlx4_en_process_cq), which tries to allocate
 391  * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
 392  */
 393 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
 394 {
 395         int ring;
 396
 397         if (!priv->port_up)
 398                 return;
 399
 400         for (ring = 0; ring < priv->rx_ring_num; ring++) {
 401                 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) {
 402                         local_bh_disable();
 403                         napi_reschedule(&priv->rx_cq[ring]->napi);
 404                         local_bh_enable();
 405                 }
 406         }
 407 }
 408
 409 /* When the rx ring is running in page-per-packet mode, a released frame can go
 410  * directly into a small cache, to avoid unmapping or touching the page
 411  * allocator. In bpf prog performance scenarios, buffers are either forwarded
 412  * or dropped, never converted to skbs, so every page can come directly from
 413  * this cache when it is sized to be a multiple of the napi budget.
 414  */
 415 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
 416                         struct mlx4_en_rx_alloc *frame)
 417 {
 418         struct mlx4_en_page_cache *cache = &ring->page_cache;
 419
 420         if (cache->index >= MLX4_EN_CACHE_SIZE)
 421                 return false;
 422
 423         cache->buf[cache->index].page = frame->page;
 424         cache->buf[cache->index].dma = frame->dma;
 425         cache->index++;
 426         return true;
 427 }
 428
 429 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 430                              struct mlx4_en_rx_ring **pring,
 431                              u32 size, u16 stride)
 432 {
 433         struct mlx4_en_dev *mdev = priv->mdev;
 434         struct mlx4_en_rx_ring *ring = *pring;
 435         struct bpf_prog *old_prog;
 436
 437         old_prog = rcu_dereference_protected(
 438                                         ring->xdp_prog,
 439                                         lockdep_is_held(&mdev->state_lock));
 440         if (old_prog)
 441                 bpf_prog_put(old_prog);
 442         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 443         vfree(ring->rx_info);
 444         ring->rx_info = NULL;
 445         kfree(ring);
 446         *pring = NULL;
 447 }
 448
 449 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 450                                 struct mlx4_en_rx_ring *ring)
 451 {
 452         int i;
 453
 454         for (i = 0; i < ring->page_cache.index; i++) {
 455                 dma_unmap_page(priv->ddev, ring->page_cache.buf[i].dma,
 456                                PAGE_SIZE, priv->dma_dir);
 457                 put_page(ring->page_cache.buf[i].page);
 458         }
 459         ring->page_cache.index = 0;
 460         mlx4_en_free_rx_buf(priv, ring);
 461         if (ring->stride <= TXBB_SIZE)
 462                 ring->buf -= TXBB_SIZE;
 463 }
 464
 465
 466 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 467                                     struct mlx4_en_rx_alloc *frags,
 468                                     struct sk_buff *skb,
 469                                     int length)
 470 {
 471         const struct mlx4_en_frag_info *frag_info = priv->frag_info;
 472         unsigned int truesize = 0;
 473         int nr, frag_size;
 474         struct page *page;
 475         dma_addr_t dma;
 476         bool release;
 477
 478         /* Collect used fragments while replacing them in the HW descriptors */
 479         for (nr = 0;; frags++) {
 480                 frag_size = min_t(int, length, frag_info->frag_size);
 481
 482                 page = frags->page;
 483                 if (unlikely(!page))
 484                         goto fail;
 485
 486                 dma = frags->dma;
 487                 dma_sync_single_range_for_cpu(priv->ddev, dma, frags->page_offset,
 488                                               frag_size, priv->dma_dir);
 489
 490                 __skb_fill_page_desc(skb, nr, page, frags->page_offset,
 491                                      frag_size);
 492
 493                 truesize += frag_info->frag_stride;
 494                 if (frag_info->frag_stride == PAGE_SIZE / 2) {
 495                         frags->page_offset ^= PAGE_SIZE / 2;
 496                         release = page_count(page) != 1 ||
 497                                   page_is_pfmemalloc(page) ||
 498                                   page_to_nid(page) != numa_mem_id();
 499                 } else {
 500                         u32 sz_align = ALIGN(frag_size, SMP_CACHE_BYTES);
 501
 502                         frags->page_offset += sz_align;
 503                         release = frags->page_offset + frag_info->frag_size > PAGE_SIZE;
 504                 }
 505                 if (release) {
 506                         dma_unmap_page(priv->ddev, dma, PAGE_SIZE, priv->dma_dir);
 507                         frags->page = NULL;
 508                 } else {
 509                         page_ref_inc(page);
 510                 }
 511
 512                 nr++;
 513                 length -= frag_size;
 514                 if (!length)
 515                         break;
 516                 frag_info++;
 517         }
 518         skb->truesize += truesize;
 519         return nr;
 520
 521 fail:
 522         while (nr > 0) {
 523                 nr--;
 524                 __skb_frag_unref(skb_shinfo(skb)->frags + nr);
 525         }
 526         return 0;
 527 }
 528
 529
 530 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
 531                                       struct mlx4_en_rx_alloc *frags,
 532                                       unsigned int length)
 533 {
 534         struct sk_buff *skb;
 535         void *va;
 536         int used_frags;
 537         dma_addr_t dma;
 538
 539         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
 540         if (unlikely(!skb)) {
 541                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
 542                 return NULL;
 543         }
 544         skb_reserve(skb, NET_IP_ALIGN);
 545         skb->len = length;
 546
 547         /* Get pointer to first fragment so we could copy the headers into the
 548          * (linear part of the) skb */
 549         va = page_address(frags[0].page) + frags[0].page_offset;
 550
 551         if (length <= SMALL_PACKET_SIZE) {
 552                 /* We are copying all relevant data to the skb - temporarily
 553                  * sync buffers for the copy */
 554
 555                 dma = frags[0].dma + frags[0].page_offset;
 556                 dma_sync_single_for_cpu(priv->ddev, dma, length,
 557                                         DMA_FROM_DEVICE);
 558                 skb_copy_to_linear_data(skb, va, length);
 559                 skb->tail += length;
 560         } else {
 561                 unsigned int pull_len;
 562
 563                 /* Move relevant fragments to skb */
 564                 used_frags = mlx4_en_complete_rx_desc(priv, frags,
 565                                                         skb, length);
 566                 if (unlikely(!used_frags)) {
 567                         kfree_skb(skb);
 568                         return NULL;
 569                 }
 570                 skb_shinfo(skb)->nr_frags = used_frags;
 571
 572                 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
 573                 /* Copy headers into the skb linear buffer */
 574                 memcpy(skb->data, va, pull_len);
 575                 skb->tail += pull_len;
 576
 577                 /* Skip headers in first fragment */
 578                 skb_shinfo(skb)->frags[0].page_offset += pull_len;
 579
 580                 /* Adjust size of first fragment */
 581                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
 582                 skb->data_len = length - pull_len;
 583         }
 584         return skb;
 585 }
 586
 587 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
 588 {
 589         int i;
 590         int offset = ETH_HLEN;
 591
 592         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 593                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
 594                         goto out_loopback;
 595         }
 596         /* Loopback found */
 597         priv->loopback_ok = 1;
 598
 599 out_loopback:
 600         dev_kfree_skb_any(skb);
 601 }
 602
 603 static bool mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 604                                       struct mlx4_en_rx_ring *ring)
 605 {
 606         u32 missing = ring->actual_size - (ring->prod - ring->cons);
 607
 608         /* Try to batch allocations, but not too much. */
 609         if (missing < 8)
 610                 return false;
 611         do {
 612                 if (mlx4_en_prepare_rx_desc(priv, ring,
 613                                             ring->prod & ring->size_mask,
 614                                             GFP_ATOMIC | __GFP_COLD |
 615                                             __GFP_MEMALLOC))
 616                         break;
 617                 ring->prod++;
 618         } while (--missing);
 619
 620         return true;
 621 }
 622
 623 /* When hardware doesn't strip the vlan, we need to calculate the checksum
 624  * over it and add it to the hardware's checksum calculation
 625  */
 626 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
 627                                          struct vlan_hdr *vlanh)
 628 {
 629         return csum_add(hw_checksum, *(__wsum *)vlanh);
 630 }
 631
 632 /* Although the stack expects checksum which doesn't include the pseudo
 633  * header, the HW adds it. To address that, we are subtracting the pseudo
 634  * header checksum from the checksum value provided by the HW.
 635  */
 636 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
 637                                 struct iphdr *iph)
 638 {
 639         __u16 length_for_csum = 0;
 640         __wsum csum_pseudo_header = 0;
 641
 642         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
 643         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
 644                                                 length_for_csum, iph->protocol, 0);
 645         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
 646 }
 647
 648 #if IS_ENABLED(CONFIG_IPV6)
 649 /* In IPv6 packets, besides subtracting the pseudo header checksum,
 650  * we also compute/add the IP header checksum which
 651  * is not added by the HW.
 652  */
 653 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
 654                                struct ipv6hdr *ipv6h)
 655 {
 656         __wsum csum_pseudo_hdr = 0;
 657
 658         if (unlikely(ipv6h->nexthdr == IPPROTO_FRAGMENT ||
 659                      ipv6h->nexthdr == IPPROTO_HOPOPTS))
 660                 return -1;
 661         hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr));
 662
 663         csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
 664                                        sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
 665         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
 666         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
 667
 668         skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
 669         skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
 670         return 0;
 671 }
 672 #endif
 673 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
 674                       netdev_features_t dev_features)
 675 {
 676         __wsum hw_checksum = 0;
 677
 678         void *hdr = (u8 *)va + sizeof(struct ethhdr);
 679
 680         hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
 681
 682         if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
 683             !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
 684                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
 685                 hdr += sizeof(struct vlan_hdr);
 686         }
 687
 688         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
 689                 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
 690 #if IS_ENABLED(CONFIG_IPV6)
 691         else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
 692                 if (unlikely(get_fixed_ipv6_csum(hw_checksum, skb, hdr)))
 693                         return -1;
 694 #endif
 695         return 0;
 696 }
 697
 698 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 699 {
 700         struct mlx4_en_priv *priv = netdev_priv(dev);
 701         struct mlx4_en_dev *mdev = priv->mdev;
 702         struct mlx4_cqe *cqe;
 703         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 704         struct mlx4_en_rx_alloc *frags;
 705         struct bpf_prog *xdp_prog;
 706         int doorbell_pending;
 707         struct sk_buff *skb;
 708         int index;
 709         int nr;
 710         unsigned int length;
 711         int polled = 0;
 712         int ip_summed;
 713         int factor = priv->cqe_factor;
 714         u64 timestamp;
 715         bool l2_tunnel;
 716
 717         if (unlikely(!priv->port_up))
 718                 return 0;
 719
 720         if (unlikely(budget <= 0))
 721                 return polled;
 722
 723         /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */
 724         rcu_read_lock();
 725         xdp_prog = rcu_dereference(ring->xdp_prog);
 726         doorbell_pending = 0;
 727
 728         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 729          * descriptor offset can be deduced from the CQE index instead of
 730          * reading 'cqe->index' */
 731         index = cq->mcq.cons_index & ring->size_mask;
 732         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 733
 734         /* Process all completed CQEs */
 735         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 736                     cq->mcq.cons_index & cq->size)) {
 737
 738                 frags = ring->rx_info + (index << priv->log_rx_info);
 739
 740                 /*
 741                  * make sure we read the CQE after we read the ownership bit
 742                  */
 743                 dma_rmb();
 744
 745                 /* Drop packet on bad receive or bad checksum */
 746                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 747                                                 MLX4_CQE_OPCODE_ERROR)) {
 748                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 749                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 750                                ((struct mlx4_err_cqe *)cqe)->syndrome);
 751                         goto next;
 752                 }
 753                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 754                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 755                         goto next;
 756                 }
 757
 758                 /* Check if we need to drop the packet if SRIOV is not enabled
 759                  * and not performing the selftest or flb disabled
 760                  */
 761                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 762                         struct ethhdr *ethh;
 763                         dma_addr_t dma;
 764                         /* Get pointer to first fragment since we haven't
 765                          * skb yet and cast it to ethhdr struct
 766                          */
 767                         dma = frags[0].dma + frags[0].page_offset;
 768                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 769                                                 DMA_FROM_DEVICE);
 770                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
 771                                                  frags[0].page_offset);
 772
 773                         if (is_multicast_ether_addr(ethh->h_dest)) {
 774                                 struct mlx4_mac_entry *entry;
 775                                 struct hlist_head *bucket;
 776                                 unsigned int mac_hash;
 777
 778                                 /* Drop the packet, since HW loopback-ed it */
 779                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 780                                 bucket = &priv->mac_hash[mac_hash];
 781                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 782                                         if (ether_addr_equal_64bits(entry->mac,
 783                                                                     ethh->h_source))
 784                                                 goto next;
 785                                 }
 786                         }
 787                 }
 788
 789                 /*
 790                  * Packet is OK - process it.
 791                  */
 792                 length = be32_to_cpu(cqe->byte_cnt);
 793                 length -= ring->fcs_del;
 794                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
 795                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
 796
 797                 /* A bpf program gets first chance to drop the packet. It may
 798                  * read bytes but not past the end of the frag.
 799                  */
 800                 if (xdp_prog) {
 801                         struct xdp_buff xdp;
 802                         dma_addr_t dma;
 803                         void *orig_data;
 804                         u32 act;
 805
 806                         dma = frags[0].dma + frags[0].page_offset;
 807                         dma_sync_single_for_cpu(priv->ddev, dma,
 808                                                 priv->frag_info[0].frag_size,
 809                                                 DMA_FROM_DEVICE);
 810
 811                         xdp.data_hard_start = page_address(frags[0].page);
 812                         xdp.data = xdp.data_hard_start + frags[0].page_offset;
 813                         xdp.data_end = xdp.data + length;
 814                         orig_data = xdp.data;
 815
 816                         act = bpf_prog_run_xdp(xdp_prog, &xdp);
 817
 818                         if (xdp.data != orig_data) {
 819                                 length = xdp.data_end - xdp.data;
 820                                 frags[0].page_offset = xdp.data -
 821                                         xdp.data_hard_start;
 822                         }
 823
 824                         switch (act) {
 825                         case XDP_PASS:
 826                                 break;
 827                         case XDP_TX:
 828                                 if (likely(!mlx4_en_xmit_frame(ring, frags, dev,
 829                                                         length, cq->ring,
 830                                                         &doorbell_pending))) {
 831                                         frags[0].page = NULL;
 832                                         goto next;
 833                                 }
 834                                 trace_xdp_exception(dev, xdp_prog, act);
 835                                 goto xdp_drop_no_cnt; /* Drop on xmit failure */
 836                         default:
 837                                 bpf_warn_invalid_xdp_action(act);
 838                         case XDP_ABORTED:
 839                                 trace_xdp_exception(dev, xdp_prog, act);
 840                         case XDP_DROP:
 841                                 ring->xdp_drop++;
 842 xdp_drop_no_cnt:
 843                                 goto next;
 844                         }
 845                 }
 846
 847                 ring->bytes += length;
 848                 ring->packets++;
 849
 850                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 851                         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
 852                                                       MLX4_CQE_STATUS_UDP)) {
 853                                 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 854                                     cqe->checksum == cpu_to_be16(0xffff)) {
 855                                         ip_summed = CHECKSUM_UNNECESSARY;
 856                                         ring->csum_ok++;
 857                                 } else {
 858                                         ip_summed = CHECKSUM_NONE;
 859                                         ring->csum_none++;
 860                                 }
 861                         } else {
 862                                 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
 863                                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 864                                                                MLX4_CQE_STATUS_IPV6))) {
 865                                         ip_summed = CHECKSUM_COMPLETE;
 866                                         ring->csum_complete++;
 867                                 } else {
 868                                         ip_summed = CHECKSUM_NONE;
 869                                         ring->csum_none++;
 870                                 }
 871                         }
 872                 } else {
 873                         ip_summed = CHECKSUM_NONE;
 874                         ring->csum_none++;
 875                 }
 876
 877                 /* This packet is eligible for GRO if it is:
 878                  * - DIX Ethernet (type interpretation)
 879                  * - TCP/IP (v4)
 880                  * - without IP options
 881                  * - not an IP fragment
 882                  */
 883                 if (dev->features & NETIF_F_GRO) {
 884                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
 885                         if (!gro_skb)
 886                                 goto next;
 887
 888                         nr = mlx4_en_complete_rx_desc(priv, frags, gro_skb,
 889                                                       length);
 890                         if (!nr)
 891                                 goto next;
 892
 893                         if (ip_summed == CHECKSUM_COMPLETE) {
 894                                 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
 895                                 if (check_csum(cqe, gro_skb, va,
 896                                                dev->features)) {
 897                                         ip_summed = CHECKSUM_NONE;
 898                                         ring->csum_none++;
 899                                         ring->csum_complete--;
 900                                 }
 901                         }
 902
 903                         skb_shinfo(gro_skb)->nr_frags = nr;
 904                         gro_skb->len = length;
 905                         gro_skb->data_len = length;
 906                         gro_skb->ip_summed = ip_summed;
 907
 908                         if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 909                                 gro_skb->csum_level = 1;
 910
 911                         if ((cqe->vlan_my_qpn &
 912                             cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
 913                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
 914                                 u16 vid = be16_to_cpu(cqe->sl_vid);
 915
 916                                 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
 917                         } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
 918                                   MLX4_CQE_SVLAN_PRESENT_MASK) &&
 919                                  (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
 920                                 __vlan_hwaccel_put_tag(gro_skb,
 921                                                        htons(ETH_P_8021AD),
 922                                                        be16_to_cpu(cqe->sl_vid));
 923                         }
 924
 925                         if (dev->features & NETIF_F_RXHASH)
 926                                 skb_set_hash(gro_skb,
 927                                              be32_to_cpu(cqe->immed_rss_invalid),
 928                                              (ip_summed == CHECKSUM_UNNECESSARY) ?
 929                                                 PKT_HASH_TYPE_L4 :
 930                                                 PKT_HASH_TYPE_L3);
 931
 932                         skb_record_rx_queue(gro_skb, cq->ring);
 933
 934                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 935                                 timestamp = mlx4_en_get_cqe_ts(cqe);
 936                                 mlx4_en_fill_hwtstamps(mdev,
 937                                                        skb_hwtstamps(gro_skb),
 938                                                        timestamp);
 939                         }
 940
 941                         napi_gro_frags(&cq->napi);
 942                         goto next;
 943                 }
 944
 945                 /* GRO not possible, complete processing here */
 946                 skb = mlx4_en_rx_skb(priv, frags, length);
 947                 if (unlikely(!skb)) {
 948                         ring->dropped++;
 949                         goto next;
 950                 }
 951
 952                 if (unlikely(priv->validate_loopback)) {
 953                         validate_loopback(priv, skb);
 954                         goto next;
 955                 }
 956
 957                 if (ip_summed == CHECKSUM_COMPLETE) {
 958                         if (check_csum(cqe, skb, skb->data, dev->features)) {
 959                                 ip_summed = CHECKSUM_NONE;
 960                                 ring->csum_complete--;
 961                                 ring->csum_none++;
 962                         }
 963                 }
 964
 965                 skb->ip_summed = ip_summed;
 966                 skb->protocol = eth_type_trans(skb, dev);
 967                 skb_record_rx_queue(skb, cq->ring);
 968
 969                 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 970                         skb->csum_level = 1;
 971
 972                 if (dev->features & NETIF_F_RXHASH)
 973                         skb_set_hash(skb,
 974                                      be32_to_cpu(cqe->immed_rss_invalid),
 975                                      (ip_summed == CHECKSUM_UNNECESSARY) ?
 976                                         PKT_HASH_TYPE_L4 :
 977                                         PKT_HASH_TYPE_L3);
 978
 979                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
 980                     MLX4_CQE_CVLAN_PRESENT_MASK) &&
 981                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
 982                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
 983                 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
 984                           MLX4_CQE_SVLAN_PRESENT_MASK) &&
 985                          (dev->features & NETIF_F_HW_VLAN_STAG_RX))
 986                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
 987                                                be16_to_cpu(cqe->sl_vid));
 988
 989                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 990                         timestamp = mlx4_en_get_cqe_ts(cqe);
 991                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
 992                                                timestamp);
 993                 }
 994
 995                 napi_gro_receive(&cq->napi, skb);
 996 next:
 997                 ++cq->mcq.cons_index;
 998                 index = (cq->mcq.cons_index) & ring->size_mask;
 999                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1000                 if (++polled == budget)
1001                         goto out;
1002         }
1003
1004 out:
1005         rcu_read_unlock();
1006
1007         if (polled) {
1008                 if (doorbell_pending)
1009                         mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq->ring]);
1010
1011                 mlx4_cq_set_ci(&cq->mcq);
1012                 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1013                 ring->cons = cq->mcq.cons_index;
1014         }
1015         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1016
1017         if (mlx4_en_refill_rx_buffers(priv, ring))
1018                 mlx4_en_update_rx_prod_db(ring);
1019
1020         return polled;
1021 }
1022
1023
1024 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1025 {
1026         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1027         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1028
1029         if (likely(priv->port_up))
1030                 napi_schedule_irqoff(&cq->napi);
1031         else
1032                 mlx4_en_arm_cq(priv, cq);
1033 }
1034
1035 /* Rx CQ polling - called by NAPI */
1036 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1037 {
1038         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1039         struct net_device *dev = cq->dev;
1040         struct mlx4_en_priv *priv = netdev_priv(dev);
1041         int done;
1042
1043         done = mlx4_en_process_rx_cq(dev, cq, budget);
1044
1045         /* If we used up all the quota - we're probably not done yet... */
1046         if (done == budget) {
1047                 const struct cpumask *aff;
1048                 struct irq_data *idata;
1049                 int cpu_curr;
1050
1051                 INC_PERF_COUNTER(priv->pstats.napi_quota);
1052
1053                 cpu_curr = smp_processor_id();
1054                 idata = irq_desc_get_irq_data(cq->irq_desc);
1055                 aff = irq_data_get_affinity_mask(idata);
1056
1057                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1058                         return budget;
1059
1060                 /* Current cpu is not according to smp_irq_affinity -
1061                  * probably affinity changed. Need to stop this NAPI
1062                  * poll, and restart it on the right CPU.
1063                  * Try to avoid returning a too small value (like 0),
1064                  * to not fool net_rx_action() and its netdev_budget
1065                  */
1066                 if (done)
1067                         done--;
1068         }
1069         /* Done for now */
1070         if (napi_complete_done(napi, done))
1071                 mlx4_en_arm_cq(priv, cq);
1072         return done;
1073 }
1074
1075 void mlx4_en_calc_rx_buf(struct net_device *dev)
1076 {
1077         struct mlx4_en_priv *priv = netdev_priv(dev);
1078         int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);
1079         int i = 0;
1080
1081         /* bpf requires buffers to be set up as 1 packet per page.
1082          * This only works when num_frags == 1.
1083          */
1084         if (priv->tx_ring_num[TX_XDP]) {
1085                 priv->frag_info[0].frag_size = eff_mtu;
1086                 /* This will gain efficient xdp frame recycling at the
1087                  * expense of more costly truesize accounting
1088                  */
1089                 priv->frag_info[0].frag_stride = PAGE_SIZE;
1090                 priv->dma_dir = PCI_DMA_BIDIRECTIONAL;
1091                 priv->rx_headroom = XDP_PACKET_HEADROOM;
1092                 i = 1;
1093         } else {
1094                 int frag_size_max = 2048, buf_size = 0;
1095
1096                 /* should not happen, right ? */
1097                 if (eff_mtu > PAGE_SIZE + (MLX4_EN_MAX_RX_FRAGS - 1) * 2048)
1098                         frag_size_max = PAGE_SIZE;
1099
1100                 while (buf_size < eff_mtu) {
1101                         int frag_stride, frag_size = eff_mtu - buf_size;
1102                         int pad, nb;
1103
1104                         if (i < MLX4_EN_MAX_RX_FRAGS - 1)
1105                                 frag_size = min(frag_size, frag_size_max);
1106
1107                         priv->frag_info[i].frag_size = frag_size;
1108                         frag_stride = ALIGN(frag_size, SMP_CACHE_BYTES);
1109                         /* We can only pack 2 1536-bytes frames in on 4K page
1110                          * Therefore, each frame would consume more bytes (truesize)
1111                          */
1112                         nb = PAGE_SIZE / frag_stride;
1113                         pad = (PAGE_SIZE - nb * frag_stride) / nb;
1114                         pad &= ~(SMP_CACHE_BYTES - 1);
1115                         priv->frag_info[i].frag_stride = frag_stride + pad;
1116
1117                         buf_size += frag_size;
1118                         i++;
1119                 }
1120                 priv->dma_dir = PCI_DMA_FROMDEVICE;
1121                 priv->rx_headroom = 0;
1122         }
1123
1124         priv->num_frags = i;
1125         priv->rx_skb_size = eff_mtu;
1126         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1127
1128         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1129                eff_mtu, priv->num_frags);
1130         for (i = 0; i < priv->num_frags; i++) {
1131                 en_err(priv,
1132                        "  frag:%d - size:%d stride:%d\n",
1133                        i,
1134                        priv->frag_info[i].frag_size,
1135                        priv->frag_info[i].frag_stride);
1136         }
1137 }
1138
1139 /* RSS related functions */
1140
1141 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1142                                  struct mlx4_en_rx_ring *ring,
1143                                  enum mlx4_qp_state *state,
1144                                  struct mlx4_qp *qp)
1145 {
1146         struct mlx4_en_dev *mdev = priv->mdev;
1147         struct mlx4_qp_context *context;
1148         int err = 0;
1149
1150         context = kmalloc(sizeof(*context), GFP_KERNEL);
1151         if (!context)
1152                 return -ENOMEM;
1153
1154         err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1155         if (err) {
1156                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1157                 goto out;
1158         }
1159         qp->event = mlx4_en_sqp_event;
1160
1161         memset(context, 0, sizeof *context);
1162         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1163                                 qpn, ring->cqn, -1, context);
1164         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1165
1166         /* Cancel FCS removal if FW allows */
1167         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1168                 context->param3 |= cpu_to_be32(1 << 29);
1169                 if (priv->dev->features & NETIF_F_RXFCS)
1170                         ring->fcs_del = 0;
1171                 else
1172                         ring->fcs_del = ETH_FCS_LEN;
1173         } else
1174                 ring->fcs_del = 0;
1175
1176         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1177         if (err) {
1178                 mlx4_qp_remove(mdev->dev, qp);
1179                 mlx4_qp_free(mdev->dev, qp);
1180         }
1181         mlx4_en_update_rx_prod_db(ring);
1182 out:
1183         kfree(context);
1184         return err;
1185 }
1186
1187 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1188 {
1189         int err;
1190         u32 qpn;
1191
1192         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1193                                     MLX4_RESERVE_A0_QP);
1194         if (err) {
1195                 en_err(priv, "Failed reserving drop qpn\n");
1196                 return err;
1197         }
1198         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1199         if (err) {
1200                 en_err(priv, "Failed allocating drop qp\n");
1201                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1202                 return err;
1203         }
1204
1205         return 0;
1206 }
1207
1208 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1209 {
1210         u32 qpn;
1211
1212         qpn = priv->drop_qp.qpn;
1213         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1214         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1215         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1216 }
1217
1218 /* Allocate rx qp's and configure them according to rss map */
1219 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1220 {
1221         struct mlx4_en_dev *mdev = priv->mdev;
1222         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1223         struct mlx4_qp_context context;
1224         struct mlx4_rss_context *rss_context;
1225         int rss_rings;
1226         void *ptr;
1227         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1228                         MLX4_RSS_TCP_IPV6);
1229         int i, qpn;
1230         int err = 0;
1231         int good_qps = 0;
1232
1233         en_dbg(DRV, priv, "Configuring rss steering\n");
1234         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1235                                     priv->rx_ring_num,
1236                                     &rss_map->base_qpn, 0);
1237         if (err) {
1238                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1239                 return err;
1240         }
1241
1242         for (i = 0; i < priv->rx_ring_num; i++) {
1243                 qpn = rss_map->base_qpn + i;
1244                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1245                                             &rss_map->state[i],
1246                                             &rss_map->qps[i]);
1247                 if (err)
1248                         goto rss_err;
1249
1250                 ++good_qps;
1251         }
1252
1253         /* Configure RSS indirection qp */
1254         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1255         if (err) {
1256                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1257                 goto rss_err;
1258         }
1259         rss_map->indir_qp.event = mlx4_en_sqp_event;
1260         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1261                                 priv->rx_ring[0]->cqn, -1, &context);
1262
1263         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1264                 rss_rings = priv->rx_ring_num;
1265         else
1266                 rss_rings = priv->prof->rss_rings;
1267
1268         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1269                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1270         rss_context = ptr;
1271         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1272                                             (rss_map->base_qpn));
1273         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1274         if (priv->mdev->profile.udp_rss) {
1275                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1276                 rss_context->base_qpn_udp = rss_context->default_qpn;
1277         }
1278
1279         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1280                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1281                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1282         }
1283
1284         rss_context->flags = rss_mask;
1285         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1286         if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1287                 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1288         } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1289                 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1290                 memcpy(rss_context->rss_key, priv->rss_key,
1291                        MLX4_EN_RSS_KEY_SIZE);
1292         } else {
1293                 en_err(priv, "Unknown RSS hash function requested\n");
1294                 err = -EINVAL;
1295                 goto indir_err;
1296         }
1297         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1298                                &rss_map->indir_qp, &rss_map->indir_state);
1299         if (err)
1300                 goto indir_err;
1301
1302         return 0;
1303
1304 indir_err:
1305         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1306                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1307         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1308         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1309 rss_err:
1310         for (i = 0; i < good_qps; i++) {
1311                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1312                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1313                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1314                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1315         }
1316         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1317         return err;
1318 }
1319
1320 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1321 {
1322         struct mlx4_en_dev *mdev = priv->mdev;
1323         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1324         int i;
1325
1326         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1327                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1328         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1329         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1330
1331         for (i = 0; i < priv->rx_ring_num; i++) {
1332                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1333                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1334                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1335                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1336         }
1337         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1338 }