2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <net/busy_poll.h>
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/rculist.h>
40 #include <linux/if_ether.h>
41 #include <linux/if_vlan.h>
42 #include <linux/vmalloc.h>
43 #include <linux/irq.h>
45 #if IS_ENABLED(CONFIG_IPV6)
46 #include <net/ip6_checksum.h>
51 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
52 struct mlx4_en_rx_alloc *page_alloc,
53 const struct mlx4_en_frag_info *frag_info,
60 for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) {
64 gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC;
65 page = alloc_pages(gfp, order);
69 ((PAGE_SIZE << order) < frag_info->frag_size))
72 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
74 if (dma_mapping_error(priv->ddev, dma)) {
78 page_alloc->page_size = PAGE_SIZE << order;
79 page_alloc->page = page;
80 page_alloc->dma = dma;
81 page_alloc->page_offset = 0;
82 /* Not doing get_page() for each frag is a big win
83 * on asymetric workloads. Note we can not use atomic_set().
85 page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1);
89 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
90 struct mlx4_en_rx_desc *rx_desc,
91 struct mlx4_en_rx_alloc *frags,
92 struct mlx4_en_rx_alloc *ring_alloc,
95 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
96 const struct mlx4_en_frag_info *frag_info;
101 for (i = 0; i < priv->num_frags; i++) {
102 frag_info = &priv->frag_info[i];
103 page_alloc[i] = ring_alloc[i];
104 page_alloc[i].page_offset += frag_info->frag_stride;
106 if (page_alloc[i].page_offset + frag_info->frag_stride <=
107 ring_alloc[i].page_size)
110 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
114 for (i = 0; i < priv->num_frags; i++) {
115 frags[i] = ring_alloc[i];
116 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
117 ring_alloc[i] = page_alloc[i];
118 rx_desc->data[i].addr = cpu_to_be64(dma);
125 if (page_alloc[i].page != ring_alloc[i].page) {
126 dma_unmap_page(priv->ddev, page_alloc[i].dma,
127 page_alloc[i].page_size, PCI_DMA_FROMDEVICE);
128 page = page_alloc[i].page;
129 /* Revert changes done by mlx4_alloc_pages */
130 page_ref_sub(page, page_alloc[i].page_size /
131 priv->frag_info[i].frag_stride - 1);
138 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
139 struct mlx4_en_rx_alloc *frags,
142 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
143 u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
146 if (next_frag_end > frags[i].page_size)
147 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
151 put_page(frags[i].page);
154 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
155 struct mlx4_en_rx_ring *ring)
158 struct mlx4_en_rx_alloc *page_alloc;
160 for (i = 0; i < priv->num_frags; i++) {
161 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
163 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
164 frag_info, GFP_KERNEL | __GFP_COLD))
167 en_dbg(DRV, priv, " frag %d allocator: - size:%d frags:%d\n",
168 i, ring->page_alloc[i].page_size,
169 page_ref_count(ring->page_alloc[i].page));
177 page_alloc = &ring->page_alloc[i];
178 dma_unmap_page(priv->ddev, page_alloc->dma,
179 page_alloc->page_size, PCI_DMA_FROMDEVICE);
180 page = page_alloc->page;
181 /* Revert changes done by mlx4_alloc_pages */
182 page_ref_sub(page, page_alloc->page_size /
183 priv->frag_info[i].frag_stride - 1);
185 page_alloc->page = NULL;
190 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
191 struct mlx4_en_rx_ring *ring)
193 struct mlx4_en_rx_alloc *page_alloc;
196 for (i = 0; i < priv->num_frags; i++) {
197 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
199 page_alloc = &ring->page_alloc[i];
200 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
201 i, page_count(page_alloc->page));
203 dma_unmap_page(priv->ddev, page_alloc->dma,
204 page_alloc->page_size, PCI_DMA_FROMDEVICE);
205 while (page_alloc->page_offset + frag_info->frag_stride <
206 page_alloc->page_size) {
207 put_page(page_alloc->page);
208 page_alloc->page_offset += frag_info->frag_stride;
210 page_alloc->page = NULL;
214 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
215 struct mlx4_en_rx_ring *ring, int index)
217 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
221 /* Set size and memtype fields */
222 for (i = 0; i < priv->num_frags; i++) {
223 rx_desc->data[i].byte_count =
224 cpu_to_be32(priv->frag_info[i].frag_size);
225 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
228 /* If the number of used fragments does not fill up the ring stride,
229 * remaining (unused) fragments must be padded with null address/size
230 * and a special memory key */
231 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
232 for (i = priv->num_frags; i < possible_frags; i++) {
233 rx_desc->data[i].byte_count = 0;
234 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
235 rx_desc->data[i].addr = 0;
239 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
240 struct mlx4_en_rx_ring *ring, int index,
243 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
244 struct mlx4_en_rx_alloc *frags = ring->rx_info +
245 (index << priv->log_rx_info);
247 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
250 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
252 return ring->prod == ring->cons;
255 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
257 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
260 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
261 struct mlx4_en_rx_ring *ring,
264 struct mlx4_en_rx_alloc *frags;
267 frags = ring->rx_info + (index << priv->log_rx_info);
268 for (nr = 0; nr < priv->num_frags; nr++) {
269 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
270 mlx4_en_free_frag(priv, frags, nr);
274 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
276 struct mlx4_en_rx_ring *ring;
281 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
282 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
283 ring = priv->rx_ring[ring_ind];
285 if (mlx4_en_prepare_rx_desc(priv, ring,
287 GFP_KERNEL | __GFP_COLD)) {
288 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
289 en_err(priv, "Failed to allocate enough rx buffers\n");
292 new_size = rounddown_pow_of_two(ring->actual_size);
293 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
294 ring->actual_size, new_size);
305 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
306 ring = priv->rx_ring[ring_ind];
307 while (ring->actual_size > new_size) {
310 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
317 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
318 struct mlx4_en_rx_ring *ring)
322 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
323 ring->cons, ring->prod);
325 /* Unmap and free Rx buffers */
326 while (!mlx4_en_is_ring_empty(ring)) {
327 index = ring->cons & ring->size_mask;
328 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
329 mlx4_en_free_rx_desc(priv, ring, index);
334 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
339 struct mlx4_dev *dev = mdev->dev;
341 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
342 num_of_eqs = max_t(int, MIN_RX_RINGS,
344 mlx4_get_eqs_per_port(mdev->dev, i),
347 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
348 min_t(int, num_of_eqs,
349 netif_get_num_default_rss_queues());
350 mdev->profile.prof[i].rx_ring_num =
351 rounddown_pow_of_two(num_rx_rings);
355 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
356 struct mlx4_en_rx_ring **pring,
357 u32 size, u16 stride, int node)
359 struct mlx4_en_dev *mdev = priv->mdev;
360 struct mlx4_en_rx_ring *ring;
364 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
366 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
368 en_err(priv, "Failed to allocate RX ring structure\n");
376 ring->size_mask = size - 1;
377 ring->stride = stride;
378 ring->log_stride = ffs(ring->stride) - 1;
379 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
381 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
382 sizeof(struct mlx4_en_rx_alloc));
383 ring->rx_info = vmalloc_node(tmp, node);
384 if (!ring->rx_info) {
385 ring->rx_info = vmalloc(tmp);
386 if (!ring->rx_info) {
392 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
395 /* Allocate HW buffers on provided NUMA node */
396 set_dev_node(&mdev->dev->persist->pdev->dev, node);
397 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
398 ring->buf_size, 2 * PAGE_SIZE);
399 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
403 err = mlx4_en_map_buffer(&ring->wqres.buf);
405 en_err(priv, "Failed to map RX buffer\n");
408 ring->buf = ring->wqres.buf.direct.buf;
410 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
416 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
418 vfree(ring->rx_info);
419 ring->rx_info = NULL;
427 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
429 struct mlx4_en_rx_ring *ring;
433 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
434 DS_SIZE * priv->num_frags);
436 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
437 ring = priv->rx_ring[ring_ind];
441 ring->actual_size = 0;
442 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
444 ring->stride = stride;
445 if (ring->stride <= TXBB_SIZE)
446 ring->buf += TXBB_SIZE;
448 ring->log_stride = ffs(ring->stride) - 1;
449 ring->buf_size = ring->size * ring->stride;
451 memset(ring->buf, 0, ring->buf_size);
452 mlx4_en_update_rx_prod_db(ring);
454 /* Initialize all descriptors */
455 for (i = 0; i < ring->size; i++)
456 mlx4_en_init_rx_desc(priv, ring, i);
458 /* Initialize page allocators */
459 err = mlx4_en_init_allocator(priv, ring);
461 en_err(priv, "Failed initializing ring allocator\n");
462 if (ring->stride <= TXBB_SIZE)
463 ring->buf -= TXBB_SIZE;
468 err = mlx4_en_fill_rx_buffers(priv);
472 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
473 ring = priv->rx_ring[ring_ind];
475 ring->size_mask = ring->actual_size - 1;
476 mlx4_en_update_rx_prod_db(ring);
482 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
483 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
485 ring_ind = priv->rx_ring_num - 1;
487 while (ring_ind >= 0) {
488 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
489 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
490 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
496 /* We recover from out of memory by scheduling our napi poll
497 * function (mlx4_en_process_cq), which tries to allocate
498 * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
500 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
507 for (ring = 0; ring < priv->rx_ring_num; ring++) {
508 if (mlx4_en_is_ring_empty(priv->rx_ring[ring]))
509 napi_reschedule(&priv->rx_cq[ring]->napi);
513 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
514 struct mlx4_en_rx_ring **pring,
515 u32 size, u16 stride)
517 struct mlx4_en_dev *mdev = priv->mdev;
518 struct mlx4_en_rx_ring *ring = *pring;
520 mlx4_en_unmap_buffer(&ring->wqres.buf);
521 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
522 vfree(ring->rx_info);
523 ring->rx_info = NULL;
526 #ifdef CONFIG_RFS_ACCEL
527 mlx4_en_cleanup_filters(priv);
531 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
532 struct mlx4_en_rx_ring *ring)
534 mlx4_en_free_rx_buf(priv, ring);
535 if (ring->stride <= TXBB_SIZE)
536 ring->buf -= TXBB_SIZE;
537 mlx4_en_destroy_allocator(priv, ring);
541 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
542 struct mlx4_en_rx_desc *rx_desc,
543 struct mlx4_en_rx_alloc *frags,
547 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
548 struct mlx4_en_frag_info *frag_info;
552 /* Collect used fragments while replacing them in the HW descriptors */
553 for (nr = 0; nr < priv->num_frags; nr++) {
554 frag_info = &priv->frag_info[nr];
555 if (length <= frag_info->frag_prefix_size)
560 dma = be64_to_cpu(rx_desc->data[nr].addr);
561 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
564 /* Save page reference in skb */
565 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
566 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
567 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
568 skb->truesize += frag_info->frag_stride;
569 frags[nr].page = NULL;
571 /* Adjust size of last fragment to match actual length */
573 skb_frag_size_set(&skb_frags_rx[nr - 1],
574 length - priv->frag_info[nr - 1].frag_prefix_size);
580 __skb_frag_unref(&skb_frags_rx[nr]);
586 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
587 struct mlx4_en_rx_desc *rx_desc,
588 struct mlx4_en_rx_alloc *frags,
596 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
598 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
601 skb_reserve(skb, NET_IP_ALIGN);
604 /* Get pointer to first fragment so we could copy the headers into the
605 * (linear part of the) skb */
606 va = page_address(frags[0].page) + frags[0].page_offset;
608 if (length <= SMALL_PACKET_SIZE) {
609 /* We are copying all relevant data to the skb - temporarily
610 * sync buffers for the copy */
611 dma = be64_to_cpu(rx_desc->data[0].addr);
612 dma_sync_single_for_cpu(priv->ddev, dma, length,
614 skb_copy_to_linear_data(skb, va, length);
617 unsigned int pull_len;
619 /* Move relevant fragments to skb */
620 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
622 if (unlikely(!used_frags)) {
626 skb_shinfo(skb)->nr_frags = used_frags;
628 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
629 /* Copy headers into the skb linear buffer */
630 memcpy(skb->data, va, pull_len);
631 skb->tail += pull_len;
633 /* Skip headers in first fragment */
634 skb_shinfo(skb)->frags[0].page_offset += pull_len;
636 /* Adjust size of first fragment */
637 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
638 skb->data_len = length - pull_len;
643 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
646 int offset = ETH_HLEN;
648 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
649 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
653 priv->loopback_ok = 1;
656 dev_kfree_skb_any(skb);
659 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
660 struct mlx4_en_rx_ring *ring)
662 int index = ring->prod & ring->size_mask;
664 while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
665 if (mlx4_en_prepare_rx_desc(priv, ring, index,
666 GFP_ATOMIC | __GFP_COLD))
669 index = ring->prod & ring->size_mask;
673 /* When hardware doesn't strip the vlan, we need to calculate the checksum
674 * over it and add it to the hardware's checksum calculation
676 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
677 struct vlan_hdr *vlanh)
679 return csum_add(hw_checksum, *(__wsum *)vlanh);
682 /* Although the stack expects checksum which doesn't include the pseudo
683 * header, the HW adds it. To address that, we are subtracting the pseudo
684 * header checksum from the checksum value provided by the HW.
686 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
689 __u16 length_for_csum = 0;
690 __wsum csum_pseudo_header = 0;
692 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
693 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
694 length_for_csum, iph->protocol, 0);
695 skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
698 #if IS_ENABLED(CONFIG_IPV6)
699 /* In IPv6 packets, besides subtracting the pseudo header checksum,
700 * we also compute/add the IP header checksum which
701 * is not added by the HW.
703 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
704 struct ipv6hdr *ipv6h)
706 __wsum csum_pseudo_hdr = 0;
708 if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS)
710 hw_checksum = csum_add(hw_checksum, (__force __wsum)(ipv6h->nexthdr << 8));
712 csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
713 sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
714 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
715 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
717 skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
718 skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
722 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
723 netdev_features_t dev_features)
725 __wsum hw_checksum = 0;
727 void *hdr = (u8 *)va + sizeof(struct ethhdr);
729 hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
731 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
732 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
733 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
734 hdr += sizeof(struct vlan_hdr);
737 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
738 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
739 #if IS_ENABLED(CONFIG_IPV6)
740 else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
741 if (get_fixed_ipv6_csum(hw_checksum, skb, hdr))
747 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
749 struct mlx4_en_priv *priv = netdev_priv(dev);
750 struct mlx4_en_dev *mdev = priv->mdev;
751 struct mlx4_cqe *cqe;
752 struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
753 struct mlx4_en_rx_alloc *frags;
754 struct mlx4_en_rx_desc *rx_desc;
761 int factor = priv->cqe_factor;
771 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
772 * descriptor offset can be deduced from the CQE index instead of
773 * reading 'cqe->index' */
774 index = cq->mcq.cons_index & ring->size_mask;
775 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
777 /* Process all completed CQEs */
778 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
779 cq->mcq.cons_index & cq->size)) {
781 frags = ring->rx_info + (index << priv->log_rx_info);
782 rx_desc = ring->buf + (index << ring->log_stride);
785 * make sure we read the CQE after we read the ownership bit
789 /* Drop packet on bad receive or bad checksum */
790 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
791 MLX4_CQE_OPCODE_ERROR)) {
792 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
793 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
794 ((struct mlx4_err_cqe *)cqe)->syndrome);
797 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
798 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
802 /* Check if we need to drop the packet if SRIOV is not enabled
803 * and not performing the selftest or flb disabled
805 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
808 /* Get pointer to first fragment since we haven't
809 * skb yet and cast it to ethhdr struct
811 dma = be64_to_cpu(rx_desc->data[0].addr);
812 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
814 ethh = (struct ethhdr *)(page_address(frags[0].page) +
815 frags[0].page_offset);
817 if (is_multicast_ether_addr(ethh->h_dest)) {
818 struct mlx4_mac_entry *entry;
819 struct hlist_head *bucket;
820 unsigned int mac_hash;
822 /* Drop the packet, since HW loopback-ed it */
823 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
824 bucket = &priv->mac_hash[mac_hash];
826 hlist_for_each_entry_rcu(entry, bucket, hlist) {
827 if (ether_addr_equal_64bits(entry->mac,
838 * Packet is OK - process it.
840 length = be32_to_cpu(cqe->byte_cnt);
841 length -= ring->fcs_del;
842 ring->bytes += length;
844 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
845 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
847 if (likely(dev->features & NETIF_F_RXCSUM)) {
848 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
849 MLX4_CQE_STATUS_UDP)) {
850 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
851 cqe->checksum == cpu_to_be16(0xffff)) {
852 ip_summed = CHECKSUM_UNNECESSARY;
855 ip_summed = CHECKSUM_NONE;
859 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
860 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
861 MLX4_CQE_STATUS_IPV6))) {
862 ip_summed = CHECKSUM_COMPLETE;
863 ring->csum_complete++;
865 ip_summed = CHECKSUM_NONE;
870 ip_summed = CHECKSUM_NONE;
874 /* This packet is eligible for GRO if it is:
875 * - DIX Ethernet (type interpretation)
877 * - without IP options
878 * - not an IP fragment
880 if (dev->features & NETIF_F_GRO) {
881 struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
885 nr = mlx4_en_complete_rx_desc(priv,
886 rx_desc, frags, gro_skb,
891 if (ip_summed == CHECKSUM_COMPLETE) {
892 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
893 if (check_csum(cqe, gro_skb, va,
895 ip_summed = CHECKSUM_NONE;
897 ring->csum_complete--;
901 skb_shinfo(gro_skb)->nr_frags = nr;
902 gro_skb->len = length;
903 gro_skb->data_len = length;
904 gro_skb->ip_summed = ip_summed;
906 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
907 gro_skb->csum_level = 1;
909 if ((cqe->vlan_my_qpn &
910 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
911 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
912 u16 vid = be16_to_cpu(cqe->sl_vid);
914 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
915 } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
916 MLX4_CQE_SVLAN_PRESENT_MASK) &&
917 (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
918 __vlan_hwaccel_put_tag(gro_skb,
920 be16_to_cpu(cqe->sl_vid));
923 if (dev->features & NETIF_F_RXHASH)
924 skb_set_hash(gro_skb,
925 be32_to_cpu(cqe->immed_rss_invalid),
926 (ip_summed == CHECKSUM_UNNECESSARY) ?
930 skb_record_rx_queue(gro_skb, cq->ring);
932 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
933 timestamp = mlx4_en_get_cqe_ts(cqe);
934 mlx4_en_fill_hwtstamps(mdev,
935 skb_hwtstamps(gro_skb),
939 napi_gro_frags(&cq->napi);
943 /* GRO not possible, complete processing here */
944 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
950 if (unlikely(priv->validate_loopback)) {
951 validate_loopback(priv, skb);
955 if (ip_summed == CHECKSUM_COMPLETE) {
956 if (check_csum(cqe, skb, skb->data, dev->features)) {
957 ip_summed = CHECKSUM_NONE;
958 ring->csum_complete--;
963 skb->ip_summed = ip_summed;
964 skb->protocol = eth_type_trans(skb, dev);
965 skb_record_rx_queue(skb, cq->ring);
967 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
970 if (dev->features & NETIF_F_RXHASH)
972 be32_to_cpu(cqe->immed_rss_invalid),
973 (ip_summed == CHECKSUM_UNNECESSARY) ?
977 if ((be32_to_cpu(cqe->vlan_my_qpn) &
978 MLX4_CQE_CVLAN_PRESENT_MASK) &&
979 (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
980 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
981 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
982 MLX4_CQE_SVLAN_PRESENT_MASK) &&
983 (dev->features & NETIF_F_HW_VLAN_STAG_RX))
984 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
985 be16_to_cpu(cqe->sl_vid));
987 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
988 timestamp = mlx4_en_get_cqe_ts(cqe);
989 mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
993 napi_gro_receive(&cq->napi, skb);
995 for (nr = 0; nr < priv->num_frags; nr++)
996 mlx4_en_free_frag(priv, frags, nr);
998 ++cq->mcq.cons_index;
999 index = (cq->mcq.cons_index) & ring->size_mask;
1000 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1001 if (++polled == budget)
1006 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1007 mlx4_cq_set_ci(&cq->mcq);
1008 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1009 ring->cons = cq->mcq.cons_index;
1010 mlx4_en_refill_rx_buffers(priv, ring);
1011 mlx4_en_update_rx_prod_db(ring);
1016 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1018 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1019 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1021 if (likely(priv->port_up))
1022 napi_schedule_irqoff(&cq->napi);
1024 mlx4_en_arm_cq(priv, cq);
1027 /* Rx CQ polling - called by NAPI */
1028 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1030 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1031 struct net_device *dev = cq->dev;
1032 struct mlx4_en_priv *priv = netdev_priv(dev);
1035 done = mlx4_en_process_rx_cq(dev, cq, budget);
1037 /* If we used up all the quota - we're probably not done yet... */
1038 if (done == budget) {
1039 const struct cpumask *aff;
1040 struct irq_data *idata;
1043 INC_PERF_COUNTER(priv->pstats.napi_quota);
1045 cpu_curr = smp_processor_id();
1046 idata = irq_desc_get_irq_data(cq->irq_desc);
1047 aff = irq_data_get_affinity_mask(idata);
1049 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1052 /* Current cpu is not according to smp_irq_affinity -
1053 * probably affinity changed. need to stop this NAPI
1054 * poll, and restart it on the right CPU
1059 napi_complete_done(napi, done);
1060 mlx4_en_arm_cq(priv, cq);
1064 static const int frag_sizes[] = {
1071 void mlx4_en_calc_rx_buf(struct net_device *dev)
1073 struct mlx4_en_priv *priv = netdev_priv(dev);
1074 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
1075 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
1077 int eff_mtu = dev->mtu + ETH_HLEN + (2 * VLAN_HLEN);
1081 while (buf_size < eff_mtu) {
1082 priv->frag_info[i].frag_size =
1083 (eff_mtu > buf_size + frag_sizes[i]) ?
1084 frag_sizes[i] : eff_mtu - buf_size;
1085 priv->frag_info[i].frag_prefix_size = buf_size;
1086 priv->frag_info[i].frag_stride =
1087 ALIGN(priv->frag_info[i].frag_size,
1089 buf_size += priv->frag_info[i].frag_size;
1093 priv->num_frags = i;
1094 priv->rx_skb_size = eff_mtu;
1095 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1097 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1098 eff_mtu, priv->num_frags);
1099 for (i = 0; i < priv->num_frags; i++) {
1101 " frag:%d - size:%d prefix:%d stride:%d\n",
1103 priv->frag_info[i].frag_size,
1104 priv->frag_info[i].frag_prefix_size,
1105 priv->frag_info[i].frag_stride);
1109 /* RSS related functions */
1111 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1112 struct mlx4_en_rx_ring *ring,
1113 enum mlx4_qp_state *state,
1116 struct mlx4_en_dev *mdev = priv->mdev;
1117 struct mlx4_qp_context *context;
1120 context = kmalloc(sizeof(*context), GFP_KERNEL);
1124 err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1126 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1129 qp->event = mlx4_en_sqp_event;
1131 memset(context, 0, sizeof *context);
1132 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1133 qpn, ring->cqn, -1, context);
1134 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1136 /* Cancel FCS removal if FW allows */
1137 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1138 context->param3 |= cpu_to_be32(1 << 29);
1139 if (priv->dev->features & NETIF_F_RXFCS)
1142 ring->fcs_del = ETH_FCS_LEN;
1146 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1148 mlx4_qp_remove(mdev->dev, qp);
1149 mlx4_qp_free(mdev->dev, qp);
1151 mlx4_en_update_rx_prod_db(ring);
1157 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1162 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1163 MLX4_RESERVE_A0_QP);
1165 en_err(priv, "Failed reserving drop qpn\n");
1168 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1170 en_err(priv, "Failed allocating drop qp\n");
1171 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1178 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1182 qpn = priv->drop_qp.qpn;
1183 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1184 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1185 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1188 /* Allocate rx qp's and configure them according to rss map */
1189 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1191 struct mlx4_en_dev *mdev = priv->mdev;
1192 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1193 struct mlx4_qp_context context;
1194 struct mlx4_rss_context *rss_context;
1197 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1203 en_dbg(DRV, priv, "Configuring rss steering\n");
1204 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1206 &rss_map->base_qpn, 0);
1208 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1212 for (i = 0; i < priv->rx_ring_num; i++) {
1213 qpn = rss_map->base_qpn + i;
1214 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1223 /* Configure RSS indirection qp */
1224 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1226 en_err(priv, "Failed to allocate RSS indirection QP\n");
1229 rss_map->indir_qp.event = mlx4_en_sqp_event;
1230 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1231 priv->rx_ring[0]->cqn, -1, &context);
1233 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1234 rss_rings = priv->rx_ring_num;
1236 rss_rings = priv->prof->rss_rings;
1238 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1239 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1241 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1242 (rss_map->base_qpn));
1243 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1244 if (priv->mdev->profile.udp_rss) {
1245 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1246 rss_context->base_qpn_udp = rss_context->default_qpn;
1249 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1250 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1251 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1254 rss_context->flags = rss_mask;
1255 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1256 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1257 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1258 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1259 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1260 memcpy(rss_context->rss_key, priv->rss_key,
1261 MLX4_EN_RSS_KEY_SIZE);
1263 en_err(priv, "Unknown RSS hash function requested\n");
1267 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1268 &rss_map->indir_qp, &rss_map->indir_state);
1275 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1276 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1277 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1278 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1280 for (i = 0; i < good_qps; i++) {
1281 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1282 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1283 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1284 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1286 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1290 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1292 struct mlx4_en_dev *mdev = priv->mdev;
1293 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1296 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1297 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1298 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1299 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1301 for (i = 0; i < priv->rx_ring_num; i++) {
1302 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1303 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1304 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1305 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1307 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);