2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/vmalloc.h>
42 #include <linux/tcp.h>
44 #include <linux/moduleparam.h>
48 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
49 struct mlx4_en_tx_ring **pring, u32 size,
50 u16 stride, int node, int queue_index)
52 struct mlx4_en_dev *mdev = priv->mdev;
53 struct mlx4_en_tx_ring *ring;
57 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
59 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
61 en_err(priv, "Failed allocating TX ring\n");
67 ring->size_mask = size - 1;
68 ring->stride = stride;
69 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS;
71 tmp = size * sizeof(struct mlx4_en_tx_info);
72 ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node);
74 ring->tx_info = vmalloc(tmp);
81 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
84 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
85 if (!ring->bounce_buf) {
86 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
87 if (!ring->bounce_buf) {
92 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
94 /* Allocate HW buffers on provided NUMA node */
95 set_dev_node(&mdev->dev->persist->pdev->dev, node);
96 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
98 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
100 en_err(priv, "Failed allocating hwq resources\n");
104 err = mlx4_en_map_buffer(&ring->wqres.buf);
106 en_err(priv, "Failed to map TX buffer\n");
110 ring->buf = ring->wqres.buf.direct.buf;
112 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
113 ring, ring->buf, ring->size, ring->buf_size,
114 (unsigned long long) ring->wqres.buf.direct.map);
116 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
117 MLX4_RESERVE_ETH_BF_QP);
119 en_err(priv, "failed reserving qp for TX ring\n");
123 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL);
125 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
128 ring->qp.event = mlx4_en_sqp_event;
130 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
132 en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
133 ring->bf.uar = &mdev->priv_uar;
134 ring->bf.uar->map = mdev->uar_map;
135 ring->bf_enabled = false;
136 ring->bf_alloced = false;
137 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
139 ring->bf_alloced = true;
140 ring->bf_enabled = !!(priv->pflags &
141 MLX4_EN_PRIV_FLAGS_BLUEFLAME);
144 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
145 ring->queue_index = queue_index;
147 if (queue_index < priv->num_tx_rings_p_up)
148 cpumask_set_cpu(cpumask_local_spread(queue_index,
149 priv->mdev->dev->numa_node),
150 &ring->affinity_mask);
156 mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
158 mlx4_en_unmap_buffer(&ring->wqres.buf);
160 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
162 kfree(ring->bounce_buf);
163 ring->bounce_buf = NULL;
165 kvfree(ring->tx_info);
166 ring->tx_info = NULL;
173 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
174 struct mlx4_en_tx_ring **pring)
176 struct mlx4_en_dev *mdev = priv->mdev;
177 struct mlx4_en_tx_ring *ring = *pring;
178 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
180 if (ring->bf_alloced)
181 mlx4_bf_free(mdev->dev, &ring->bf);
182 mlx4_qp_remove(mdev->dev, &ring->qp);
183 mlx4_qp_free(mdev->dev, &ring->qp);
184 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
185 mlx4_en_unmap_buffer(&ring->wqres.buf);
186 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
187 kfree(ring->bounce_buf);
188 ring->bounce_buf = NULL;
189 kvfree(ring->tx_info);
190 ring->tx_info = NULL;
195 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
196 struct mlx4_en_tx_ring *ring,
197 int cq, int user_prio)
199 struct mlx4_en_dev *mdev = priv->mdev;
204 ring->cons = 0xffffffff;
205 ring->last_nr_txbb = 1;
206 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
207 memset(ring->buf, 0, ring->buf_size);
209 ring->qp_state = MLX4_QP_STATE_RST;
210 ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8);
211 ring->mr_key = cpu_to_be32(mdev->mr.key);
213 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
214 ring->cqn, user_prio, &ring->context);
215 if (ring->bf_alloced)
216 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
218 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
219 &ring->qp, &ring->qp_state);
220 if (!cpumask_empty(&ring->affinity_mask))
221 netif_set_xps_queue(priv->dev, &ring->affinity_mask,
227 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
228 struct mlx4_en_tx_ring *ring)
230 struct mlx4_en_dev *mdev = priv->mdev;
232 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
233 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
236 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring)
238 return ring->prod - ring->cons > ring->full_size;
241 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
242 struct mlx4_en_tx_ring *ring, int index,
245 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
246 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
247 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
248 void *end = ring->buf + ring->buf_size;
249 __be32 *ptr = (__be32 *)tx_desc;
252 /* Optimize the common case when there are no wraparounds */
253 if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
254 /* Stamp the freed descriptor */
255 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
261 /* Stamp the freed descriptor */
262 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
266 if ((void *)ptr >= end) {
268 stamp ^= cpu_to_be32(0x80000000);
275 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
276 struct mlx4_en_tx_ring *ring,
277 int index, u8 owner, u64 timestamp)
279 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
280 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
281 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
282 void *end = ring->buf + ring->buf_size;
283 struct sk_buff *skb = tx_info->skb;
284 int nr_maps = tx_info->nr_maps;
287 /* We do not touch skb here, so prefetch skb->users location
288 * to speedup consume_skb()
290 prefetchw(&skb->users);
292 if (unlikely(timestamp)) {
293 struct skb_shared_hwtstamps hwts;
295 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
296 skb_tstamp_tx(skb, &hwts);
299 /* Optimize the common case when there are no wraparounds */
300 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
303 dma_unmap_single(priv->ddev,
305 tx_info->map0_byte_count,
308 dma_unmap_page(priv->ddev,
310 tx_info->map0_byte_count,
312 for (i = 1; i < nr_maps; i++) {
314 dma_unmap_page(priv->ddev,
315 (dma_addr_t)be64_to_cpu(data->addr),
316 be32_to_cpu(data->byte_count),
322 if ((void *) data >= end) {
323 data = ring->buf + ((void *)data - end);
327 dma_unmap_single(priv->ddev,
329 tx_info->map0_byte_count,
332 dma_unmap_page(priv->ddev,
334 tx_info->map0_byte_count,
336 for (i = 1; i < nr_maps; i++) {
338 /* Check for wraparound before unmapping */
339 if ((void *) data >= end)
341 dma_unmap_page(priv->ddev,
342 (dma_addr_t)be64_to_cpu(data->addr),
343 be32_to_cpu(data->byte_count),
348 dev_consume_skb_any(skb);
349 return tx_info->nr_txbb;
353 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
355 struct mlx4_en_priv *priv = netdev_priv(dev);
358 /* Skip last polled descriptor */
359 ring->cons += ring->last_nr_txbb;
360 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
361 ring->cons, ring->prod);
363 if ((u32) (ring->prod - ring->cons) > ring->size) {
364 if (netif_msg_tx_err(priv))
365 en_warn(priv, "Tx consumer passed producer!\n");
369 while (ring->cons != ring->prod) {
370 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
371 ring->cons & ring->size_mask,
372 !!(ring->cons & ring->size), 0);
373 ring->cons += ring->last_nr_txbb;
377 netdev_tx_reset_queue(ring->tx_queue);
380 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
385 static bool mlx4_en_process_tx_cq(struct net_device *dev,
386 struct mlx4_en_cq *cq)
388 struct mlx4_en_priv *priv = netdev_priv(dev);
389 struct mlx4_cq *mcq = &cq->mcq;
390 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
391 struct mlx4_cqe *cqe;
393 u16 new_index, ring_index, stamp_index;
394 u32 txbbs_skipped = 0;
396 u32 cons_index = mcq->cons_index;
398 u32 size_mask = ring->size_mask;
399 struct mlx4_cqe *buf = cq->buf;
402 int factor = priv->cqe_factor;
405 int budget = priv->tx_work_limit;
412 netdev_txq_bql_complete_prefetchw(ring->tx_queue);
414 index = cons_index & size_mask;
415 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
416 last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb);
417 ring_cons = ACCESS_ONCE(ring->cons);
418 ring_index = ring_cons & size_mask;
419 stamp_index = ring_index;
421 /* Process all completed CQEs */
422 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
423 cons_index & size) && (done < budget)) {
425 * make sure we read the CQE after we read the
430 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
431 MLX4_CQE_OPCODE_ERROR)) {
432 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe;
434 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n",
435 cqe_err->vendor_err_syndrome,
439 /* Skip over last polled CQE */
440 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
443 txbbs_skipped += last_nr_txbb;
444 ring_index = (ring_index + last_nr_txbb) & size_mask;
445 if (ring->tx_info[ring_index].ts_requested)
446 timestamp = mlx4_en_get_cqe_ts(cqe);
448 /* free next descriptor */
449 last_nr_txbb = mlx4_en_free_tx_desc(
450 priv, ring, ring_index,
451 !!((ring_cons + txbbs_skipped) &
452 ring->size), timestamp);
454 mlx4_en_stamp_wqe(priv, ring, stamp_index,
455 !!((ring_cons + txbbs_stamp) &
457 stamp_index = ring_index;
458 txbbs_stamp = txbbs_skipped;
460 bytes += ring->tx_info[ring_index].nr_bytes;
461 } while ((++done < budget) && (ring_index != new_index));
464 index = cons_index & size_mask;
465 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
470 * To prevent CQ overflow we first update CQ consumer and only then
473 mcq->cons_index = cons_index;
477 /* we want to dirty this cache line once */
478 ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb;
479 ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped;
481 netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
483 /* Wakeup Tx queue if this stopped, and ring is not full.
485 if (netif_tx_queue_stopped(ring->tx_queue) &&
486 !mlx4_en_is_tx_ring_full(ring)) {
487 netif_tx_wake_queue(ring->tx_queue);
490 return done < budget;
493 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
495 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
496 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
498 if (likely(priv->port_up))
499 napi_schedule_irqoff(&cq->napi);
501 mlx4_en_arm_cq(priv, cq);
504 /* TX CQ polling - called by NAPI */
505 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
507 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
508 struct net_device *dev = cq->dev;
509 struct mlx4_en_priv *priv = netdev_priv(dev);
512 clean_complete = mlx4_en_process_tx_cq(dev, cq);
517 mlx4_en_arm_cq(priv, cq);
522 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
523 struct mlx4_en_tx_ring *ring,
525 unsigned int desc_size)
527 u32 copy = (ring->size - index) * TXBB_SIZE;
530 for (i = desc_size - copy - 4; i >= 0; i -= 4) {
531 if ((i & (TXBB_SIZE - 1)) == 0)
534 *((u32 *) (ring->buf + i)) =
535 *((u32 *) (ring->bounce_buf + copy + i));
538 for (i = copy - 4; i >= 4 ; i -= 4) {
539 if ((i & (TXBB_SIZE - 1)) == 0)
542 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
543 *((u32 *) (ring->bounce_buf + i));
546 /* Return real descriptor location */
547 return ring->buf + index * TXBB_SIZE;
550 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping
552 * It seems strange we do not simply use skb_copy_bits().
553 * This would allow to inline all skbs iff skb->len <= inline_thold
555 * Note that caller already checked skb was not a gso packet
557 static bool is_inline(int inline_thold, const struct sk_buff *skb,
558 const struct skb_shared_info *shinfo,
563 if (skb->len > inline_thold || !inline_thold)
566 if (shinfo->nr_frags == 1) {
567 ptr = skb_frag_address_safe(&shinfo->frags[0]);
573 if (shinfo->nr_frags)
578 static int inline_size(const struct sk_buff *skb)
580 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
581 <= MLX4_INLINE_ALIGN)
582 return ALIGN(skb->len + CTRL_SIZE +
583 sizeof(struct mlx4_wqe_inline_seg), 16);
585 return ALIGN(skb->len + CTRL_SIZE + 2 *
586 sizeof(struct mlx4_wqe_inline_seg), 16);
589 static int get_real_size(const struct sk_buff *skb,
590 const struct skb_shared_info *shinfo,
591 struct net_device *dev,
592 int *lso_header_size,
596 struct mlx4_en_priv *priv = netdev_priv(dev);
599 if (shinfo->gso_size) {
601 if (skb->encapsulation)
602 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb);
604 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
605 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
606 ALIGN(*lso_header_size + 4, DS_SIZE);
607 if (unlikely(*lso_header_size != skb_headlen(skb))) {
608 /* We add a segment for the skb linear buffer only if
609 * it contains data */
610 if (*lso_header_size < skb_headlen(skb))
611 real_size += DS_SIZE;
613 if (netif_msg_tx_err(priv))
614 en_warn(priv, "Non-linear headers\n");
619 *lso_header_size = 0;
620 *inline_ok = is_inline(priv->prof->inline_thold, skb,
624 real_size = inline_size(skb);
626 real_size = CTRL_SIZE +
627 (shinfo->nr_frags + 1) * DS_SIZE;
633 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
634 const struct sk_buff *skb,
635 const struct skb_shared_info *shinfo,
636 int real_size, u16 *vlan_tag,
637 int tx_ind, void *fragptr)
639 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
640 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
641 unsigned int hlen = skb_headlen(skb);
643 if (skb->len <= spc) {
644 if (likely(skb->len >= MIN_PKT_LEN)) {
645 inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
647 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
648 memset(((void *)(inl + 1)) + skb->len, 0,
649 MIN_PKT_LEN - skb->len);
651 skb_copy_from_linear_data(skb, inl + 1, hlen);
652 if (shinfo->nr_frags)
653 memcpy(((void *)(inl + 1)) + hlen, fragptr,
654 skb_frag_size(&shinfo->frags[0]));
657 inl->byte_count = cpu_to_be32(1 << 31 | spc);
659 skb_copy_from_linear_data(skb, inl + 1, hlen);
661 memcpy(((void *)(inl + 1)) + hlen,
662 fragptr, spc - hlen);
663 fragptr += spc - hlen;
665 inl = (void *) (inl + 1) + spc;
666 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
668 skb_copy_from_linear_data(skb, inl + 1, spc);
669 inl = (void *) (inl + 1) + spc;
670 skb_copy_from_linear_data_offset(skb, spc, inl + 1,
672 if (shinfo->nr_frags)
673 memcpy(((void *)(inl + 1)) + hlen - spc,
675 skb_frag_size(&shinfo->frags[0]));
679 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
683 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
684 void *accel_priv, select_queue_fallback_t fallback)
686 struct mlx4_en_priv *priv = netdev_priv(dev);
687 u16 rings_p_up = priv->num_tx_rings_p_up;
691 return skb_tx_hash(dev, skb);
693 if (skb_vlan_tag_present(skb))
694 up = skb_vlan_tag_get(skb) >> VLAN_PRIO_SHIFT;
696 return fallback(dev, skb) % rings_p_up + up * rings_p_up;
699 static void mlx4_bf_copy(void __iomem *dst, const void *src,
700 unsigned int bytecnt)
702 __iowrite64_copy(dst, src, bytecnt / 8);
705 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
707 struct skb_shared_info *shinfo = skb_shinfo(skb);
708 struct mlx4_en_priv *priv = netdev_priv(dev);
709 struct device *ddev = priv->ddev;
710 struct mlx4_en_tx_ring *ring;
711 struct mlx4_en_tx_desc *tx_desc;
712 struct mlx4_wqe_data_seg *data;
713 struct mlx4_en_tx_info *tx_info;
724 void *fragptr = NULL;
734 tx_ind = skb_get_queue_mapping(skb);
735 ring = priv->tx_ring[tx_ind];
737 /* fetch ring->cons far ahead before needing it to avoid stall */
738 ring_cons = ACCESS_ONCE(ring->cons);
740 real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
741 &inline_ok, &fragptr);
742 if (unlikely(!real_size))
745 /* Align descriptor to TXBB size */
746 desc_size = ALIGN(real_size, TXBB_SIZE);
747 nr_txbb = desc_size / TXBB_SIZE;
748 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
749 if (netif_msg_tx_err(priv))
750 en_warn(priv, "Oversized header or SG list\n");
754 if (skb_vlan_tag_present(skb)) {
755 vlan_tag = skb_vlan_tag_get(skb);
756 vlan_proto = be16_to_cpu(skb->vlan_proto);
759 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
761 /* Track current inflight packets for performance analysis */
762 AVG_PERF_COUNTER(priv->pstats.inflight_avg,
763 (u32)(ring->prod - ring_cons - 1));
765 /* Packet is good - grab an index and transmit it */
766 index = ring->prod & ring->size_mask;
767 bf_index = ring->prod;
769 /* See if we have enough space for whole descriptor TXBB for setting
770 * SW ownership on next descriptor; if not, use a bounce buffer. */
771 if (likely(index + nr_txbb <= ring->size))
772 tx_desc = ring->buf + index * TXBB_SIZE;
774 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
778 /* Save skb in tx_info ring */
779 tx_info = &ring->tx_info[index];
781 tx_info->nr_txbb = nr_txbb;
783 data = &tx_desc->data;
785 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4,
788 /* valid only for none inline segments */
789 tx_info->data_offset = (void *)data - (void *)tx_desc;
791 tx_info->inl = inline_ok;
793 tx_info->linear = (lso_header_size < skb_headlen(skb) &&
796 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
797 data += tx_info->nr_maps - 1;
803 /* Map fragments if any */
804 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
805 const struct skb_frag_struct *frag;
807 frag = &shinfo->frags[i_frag];
808 byte_count = skb_frag_size(frag);
809 dma = skb_frag_dma_map(ddev, frag,
812 if (dma_mapping_error(ddev, dma))
815 data->addr = cpu_to_be64(dma);
816 data->lkey = ring->mr_key;
818 data->byte_count = cpu_to_be32(byte_count);
822 /* Map linear part if needed */
823 if (tx_info->linear) {
824 byte_count = skb_headlen(skb) - lso_header_size;
826 dma = dma_map_single(ddev, skb->data +
827 lso_header_size, byte_count,
829 if (dma_mapping_error(ddev, dma))
832 data->addr = cpu_to_be64(dma);
833 data->lkey = ring->mr_key;
835 data->byte_count = cpu_to_be32(byte_count);
837 /* tx completion can avoid cache line miss for common cases */
838 tx_info->map0_dma = dma;
839 tx_info->map0_byte_count = byte_count;
843 * For timestamping add flag to skb_shinfo and
844 * set flag for further reference
846 tx_info->ts_requested = 0;
847 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
848 shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
849 shinfo->tx_flags |= SKBTX_IN_PROGRESS;
850 tx_info->ts_requested = 1;
853 /* Prepare ctrl segement apart opcode+ownership, which depends on
854 * whether LSO is used */
855 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
856 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
857 if (!skb->encapsulation)
858 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
859 MLX4_WQE_CTRL_TCP_UDP_CSUM);
861 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
865 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
868 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
869 * so that VFs and PF can communicate with each other
871 ethh = (struct ethhdr *)skb->data;
872 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
873 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
876 /* Handle LSO (TSO) packets */
877 if (lso_header_size) {
880 /* Mark opcode as LSO */
881 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
882 ((ring->prod & ring->size) ?
883 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
885 /* Fill in the LSO prefix */
886 tx_desc->lso.mss_hdr_size = cpu_to_be32(
887 shinfo->gso_size << 16 | lso_header_size);
890 * note that we already verified that it is linear */
891 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
895 i = ((skb->len - lso_header_size) / shinfo->gso_size) +
896 !!((skb->len - lso_header_size) % shinfo->gso_size);
897 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
900 /* Normal (Non LSO) packet */
901 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
902 ((ring->prod & ring->size) ?
903 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
904 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
907 ring->bytes += tx_info->nr_bytes;
908 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
909 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
912 build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag,
915 if (skb->encapsulation) {
916 struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb);
917 if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP)
918 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
920 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
923 ring->prod += nr_txbb;
925 /* If we used a bounce buffer then copy descriptor back into place */
926 if (unlikely(bounce))
927 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
929 skb_tx_timestamp(skb);
931 /* Check available TXBBs And 2K spare for prefetch */
932 stop_queue = mlx4_en_is_tx_ring_full(ring);
933 if (unlikely(stop_queue)) {
934 netif_tx_stop_queue(ring->tx_queue);
935 ring->queue_stopped++;
937 send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue);
939 real_size = (real_size / 16) & 0x3f;
941 if (ring->bf_enabled && desc_size <= MAX_BF && !bounce &&
942 !skb_vlan_tag_present(skb) && send_doorbell) {
943 tx_desc->ctrl.bf_qpn = ring->doorbell_qpn |
944 cpu_to_be32(real_size);
946 op_own |= htonl((bf_index & 0xffff) << 8);
947 /* Ensure new descriptor hits memory
948 * before setting ownership of this descriptor to HW
951 tx_desc->ctrl.owner_opcode = op_own;
955 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
960 ring->bf.offset ^= ring->bf.buf_size;
962 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
963 if (vlan_proto == ETH_P_8021AD)
964 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN;
965 else if (vlan_proto == ETH_P_8021Q)
966 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN;
968 tx_desc->ctrl.fence_size = real_size;
970 /* Ensure new descriptor hits memory
971 * before setting ownership of this descriptor to HW
974 tx_desc->ctrl.owner_opcode = op_own;
977 /* Since there is no iowrite*_native() that writes the
978 * value as is, without byteswapping - using the one
979 * the doesn't do byteswapping in the relevant arch
982 #if defined(__LITTLE_ENDIAN)
988 ring->bf.uar->map + MLX4_SEND_DOORBELL);
994 if (unlikely(stop_queue)) {
995 /* If queue was emptied after the if (stop_queue) , and before
996 * the netif_tx_stop_queue() - need to wake the queue,
997 * or else it will remain stopped forever.
998 * Need a memory barrier to make sure ring->cons was not
999 * updated before queue was stopped.
1003 ring_cons = ACCESS_ONCE(ring->cons);
1004 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) {
1005 netif_tx_wake_queue(ring->tx_queue);
1009 return NETDEV_TX_OK;
1012 en_err(priv, "DMA mapping error\n");
1014 while (++i_frag < shinfo->nr_frags) {
1016 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr),
1017 be32_to_cpu(data->byte_count),
1022 dev_kfree_skb_any(skb);
1023 priv->stats.tx_dropped++;
1024 return NETDEV_TX_OK;