drivers/net/ethernet/mellanox/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/errno.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/io-mapping.h>
  43 #include <linux/delay.h>
  44 #include <linux/kmod.h>
  45 #include <net/devlink.h>
  46
  47 #include <linux/mlx4/device.h>
  48 #include <linux/mlx4/doorbell.h>
  49
  50 #include "mlx4.h"
  51 #include "fw.h"
  52 #include "icm.h"
  53
  54 MODULE_AUTHOR("Roland Dreier");
  55 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  56 MODULE_LICENSE("Dual BSD/GPL");
  57 MODULE_VERSION(DRV_VERSION);
  58
  59 struct workqueue_struct *mlx4_wq;
  60
  61 #ifdef CONFIG_MLX4_DEBUG
  62
  63 int mlx4_debug_level = 0;
  64 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  65 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  66
  67 #endif /* CONFIG_MLX4_DEBUG */
  68
  69 #ifdef CONFIG_PCI_MSI
  70
  71 static int msi_x = 1;
  72 module_param(msi_x, int, 0444);
  73 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  74
  75 #else /* CONFIG_PCI_MSI */
  76
  77 #define msi_x (0)
  78
  79 #endif /* CONFIG_PCI_MSI */
  80
  81 static uint8_t num_vfs[3] = {0, 0, 0};
  82 static int num_vfs_argc;
  83 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
  84 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
  85                           "num_vfs=port1,port2,port1+2");
  86
  87 static uint8_t probe_vf[3] = {0, 0, 0};
  88 static int probe_vfs_argc;
  89 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
  90 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
  91                            "probe_vf=port1,port2,port1+2");
  92
  93 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
  94 module_param_named(log_num_mgm_entry_size,
  95                         mlx4_log_num_mgm_entry_size, int, 0444);
  96 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
  97                                          " of qp per mcg, for example:"
  98                                          " 10 gives 248.range: 7 <="
  99                                          " log_num_mgm_entry_size <= 12."
 100                                          " To activate device managed"
 101                                          " flow steering when available, set to -1");
 102
 103 static bool enable_64b_cqe_eqe = true;
 104 module_param(enable_64b_cqe_eqe, bool, 0444);
 105 MODULE_PARM_DESC(enable_64b_cqe_eqe,
 106                  "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
 107
 108 #define PF_CONTEXT_BEHAVIOUR_MASK       (MLX4_FUNC_CAP_64B_EQE_CQE | \
 109                                          MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
 110                                          MLX4_FUNC_CAP_DMFS_A0_STATIC)
 111
 112 #define RESET_PERSIST_MASK_FLAGS        (MLX4_FLAG_SRIOV)
 113
 114 static char mlx4_version[] =
 115         DRV_NAME ": Mellanox ConnectX core driver v"
 116         DRV_VERSION " (" DRV_RELDATE ")\n";
 117
 118 static struct mlx4_profile default_profile = {
 119         .num_qp         = 1 << 18,
 120         .num_srq        = 1 << 16,
 121         .rdmarc_per_qp  = 1 << 4,
 122         .num_cq         = 1 << 16,
 123         .num_mcg        = 1 << 13,
 124         .num_mpt        = 1 << 19,
 125         .num_mtt        = 1 << 20, /* It is really num mtt segements */
 126 };
 127
 128 static struct mlx4_profile low_mem_profile = {
 129         .num_qp         = 1 << 17,
 130         .num_srq        = 1 << 6,
 131         .rdmarc_per_qp  = 1 << 4,
 132         .num_cq         = 1 << 8,
 133         .num_mcg        = 1 << 8,
 134         .num_mpt        = 1 << 9,
 135         .num_mtt        = 1 << 7,
 136 };
 137
 138 static int log_num_mac = 7;
 139 module_param_named(log_num_mac, log_num_mac, int, 0444);
 140 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
 141
 142 static int log_num_vlan;
 143 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
 144 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
 145 /* Log2 max number of VLANs per ETH port (0-7) */
 146 #define MLX4_LOG_NUM_VLANS 7
 147 #define MLX4_MIN_LOG_NUM_VLANS 0
 148 #define MLX4_MIN_LOG_NUM_MAC 1
 149
 150 static bool use_prio;
 151 module_param_named(use_prio, use_prio, bool, 0444);
 152 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
 153
 154 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 155 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 156 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 157
 158 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
 159 static int arr_argc = 2;
 160 module_param_array(port_type_array, int, &arr_argc, 0444);
 161 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
 162                                 "1 for IB, 2 for Ethernet");
 163
 164 struct mlx4_port_config {
 165         struct list_head list;
 166         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
 167         struct pci_dev *pdev;
 168 };
 169
 170 static atomic_t pf_loading = ATOMIC_INIT(0);
 171
 172 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
 173                                               struct mlx4_dev_cap *dev_cap)
 174 {
 175         /* The reserved_uars is calculated by system page size unit.
 176          * Therefore, adjustment is added when the uar page size is less
 177          * than the system page size
 178          */
 179         dev->caps.reserved_uars =
 180                 max_t(int,
 181                       mlx4_get_num_reserved_uar(dev),
 182                       dev_cap->reserved_uars /
 183                         (1 << (PAGE_SHIFT - dev->uar_page_shift)));
 184 }
 185
 186 int mlx4_check_port_params(struct mlx4_dev *dev,
 187                            enum mlx4_port_type *port_type)
 188 {
 189         int i;
 190
 191         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 192                 for (i = 0; i < dev->caps.num_ports - 1; i++) {
 193                         if (port_type[i] != port_type[i + 1]) {
 194                                 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
 195                                 return -EINVAL;
 196                         }
 197                 }
 198         }
 199
 200         for (i = 0; i < dev->caps.num_ports; i++) {
 201                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 202                         mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
 203                                  i + 1);
 204                         return -EINVAL;
 205                 }
 206         }
 207         return 0;
 208 }
 209
 210 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 211 {
 212         int i;
 213
 214         for (i = 1; i <= dev->caps.num_ports; ++i)
 215                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 216 }
 217
 218 enum {
 219         MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
 220 };
 221
 222 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 223 {
 224         int err = 0;
 225         struct mlx4_func func;
 226
 227         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
 228                 err = mlx4_QUERY_FUNC(dev, &func, 0);
 229                 if (err) {
 230                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 231                         return err;
 232                 }
 233                 dev_cap->max_eqs = func.max_eq;
 234                 dev_cap->reserved_eqs = func.rsvd_eqs;
 235                 dev_cap->reserved_uars = func.rsvd_uars;
 236                 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
 237         }
 238         return err;
 239 }
 240
 241 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
 242 {
 243         struct mlx4_caps *dev_cap = &dev->caps;
 244
 245         /* FW not supporting or cancelled by user */
 246         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
 247             !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
 248                 return;
 249
 250         /* Must have 64B CQE_EQE enabled by FW to use bigger stride
 251          * When FW has NCSI it may decide not to report 64B CQE/EQEs
 252          */
 253         if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
 254             !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
 255                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 256                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 257                 return;
 258         }
 259
 260         if (cache_line_size() == 128 || cache_line_size() == 256) {
 261                 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
 262                 /* Changing the real data inside CQE size to 32B */
 263                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 264                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 265
 266                 if (mlx4_is_master(dev))
 267                         dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
 268         } else {
 269                 if (cache_line_size() != 32  && cache_line_size() != 64)
 270                         mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
 271                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 272                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 273         }
 274 }
 275
 276 static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
 277                           struct mlx4_port_cap *port_cap)
 278 {
 279         dev->caps.vl_cap[port]      = port_cap->max_vl;
 280         dev->caps.ib_mtu_cap[port]          = port_cap->ib_mtu;
 281         dev->phys_caps.gid_phys_table_len[port]  = port_cap->max_gids;
 282         dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
 283         /* set gid and pkey table operating lengths by default
 284          * to non-sriov values
 285          */
 286         dev->caps.gid_table_len[port]  = port_cap->max_gids;
 287         dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
 288         dev->caps.port_width_cap[port] = port_cap->max_port_width;
 289         dev->caps.eth_mtu_cap[port]    = port_cap->eth_mtu;
 290         dev->caps.def_mac[port]        = port_cap->def_mac;
 291         dev->caps.supported_type[port] = port_cap->supported_port_types;
 292         dev->caps.suggested_type[port] = port_cap->suggested_type;
 293         dev->caps.default_sense[port] = port_cap->default_sense;
 294         dev->caps.trans_type[port]          = port_cap->trans_type;
 295         dev->caps.vendor_oui[port]     = port_cap->vendor_oui;
 296         dev->caps.wavelength[port]     = port_cap->wavelength;
 297         dev->caps.trans_code[port]     = port_cap->trans_code;
 298
 299         return 0;
 300 }
 301
 302 static int mlx4_dev_port(struct mlx4_dev *dev, int port,
 303                          struct mlx4_port_cap *port_cap)
 304 {
 305         int err = 0;
 306
 307         err = mlx4_QUERY_PORT(dev, port, port_cap);
 308
 309         if (err)
 310                 mlx4_err(dev, "QUERY_PORT command failed.\n");
 311
 312         return err;
 313 }
 314
 315 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
 316 {
 317         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
 318                 return;
 319
 320         if (mlx4_is_mfunc(dev)) {
 321                 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
 322                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
 323                 return;
 324         }
 325
 326         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
 327                 mlx4_dbg(dev,
 328                          "Keep FCS is not supported - Disabling Ignore FCS");
 329                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
 330                 return;
 331         }
 332 }
 333
 334 #define MLX4_A0_STEERING_TABLE_SIZE     256
 335 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 336 {
 337         int err;
 338         int i;
 339
 340         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 341         if (err) {
 342                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
 343                 return err;
 344         }
 345         mlx4_dev_cap_dump(dev, dev_cap);
 346
 347         if (dev_cap->min_page_sz > PAGE_SIZE) {
 348                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
 349                          dev_cap->min_page_sz, PAGE_SIZE);
 350                 return -ENODEV;
 351         }
 352         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 353                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
 354                          dev_cap->num_ports, MLX4_MAX_PORTS);
 355                 return -ENODEV;
 356         }
 357
 358         if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
 359                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
 360                          dev_cap->uar_size,
 361                          (unsigned long long)
 362                          pci_resource_len(dev->persist->pdev, 2));
 363                 return -ENODEV;
 364         }
 365
 366         dev->caps.num_ports          = dev_cap->num_ports;
 367         dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
 368         dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
 369                                       dev->caps.num_sys_eqs :
 370                                       MLX4_MAX_EQ_NUM;
 371         for (i = 1; i <= dev->caps.num_ports; ++i) {
 372                 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
 373                 if (err) {
 374                         mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
 375                         return err;
 376                 }
 377         }
 378
 379         dev->caps.uar_page_size      = PAGE_SIZE;
 380         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 381         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 382         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 383         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 384         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 385         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 386         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 387         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 388         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 389         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 390         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 391         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 392         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 393         /*
 394          * Subtract 1 from the limit because we need to allocate a
 395          * spare CQE so the HCA HW can tell the difference between an
 396          * empty CQ and a full CQ.
 397          */
 398         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 399         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 400         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 401         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
 402         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 403
 404         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 405         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 406                                         dev_cap->reserved_xrcds : 0;
 407         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 408                                         dev_cap->max_xrcds : 0;
 409         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
 410
 411         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 412         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 413         dev->caps.flags              = dev_cap->flags;
 414         dev->caps.flags2             = dev_cap->flags2;
 415         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 416         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 417         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 418         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 419         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
 420
 421         /* Save uar page shift */
 422         if (!mlx4_is_slave(dev)) {
 423                 /* Virtual PCI function needs to determine UAR page size from
 424                  * firmware. Only master PCI function can set the uar page size
 425                  */
 426                 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT;
 427                 mlx4_set_num_reserved_uars(dev, dev_cap);
 428         }
 429
 430         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
 431                 struct mlx4_init_hca_param hca_param;
 432
 433                 memset(&hca_param, 0, sizeof(hca_param));
 434                 err = mlx4_QUERY_HCA(dev, &hca_param);
 435                 /* Turn off PHV_EN flag in case phv_check_en is set.
 436                  * phv_check_en is a HW check that parse the packet and verify
 437                  * phv bit was reported correctly in the wqe. To allow QinQ
 438                  * PHV_EN flag should be set and phv_check_en must be cleared
 439                  * otherwise QinQ packets will be drop by the HW.
 440                  */
 441                 if (err || hca_param.phv_check_en)
 442                         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
 443         }
 444
 445         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
 446         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
 447                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 448         /* Don't do sense port on multifunction devices (for now at least) */
 449         if (mlx4_is_mfunc(dev))
 450                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 451
 452         if (mlx4_low_memory_profile()) {
 453                 dev->caps.log_num_macs  = MLX4_MIN_LOG_NUM_MAC;
 454                 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
 455         } else {
 456                 dev->caps.log_num_macs  = log_num_mac;
 457                 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 458         }
 459
 460         for (i = 1; i <= dev->caps.num_ports; ++i) {
 461                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
 462                 if (dev->caps.supported_type[i]) {
 463                         /* if only ETH is supported - assign ETH */
 464                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
 465                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 466                         /* if only IB is supported, assign IB */
 467                         else if (dev->caps.supported_type[i] ==
 468                                  MLX4_PORT_TYPE_IB)
 469                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 470                         else {
 471                                 /* if IB and ETH are supported, we set the port
 472                                  * type according to user selection of port type;
 473                                  * if user selected none, take the FW hint */
 474                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
 475                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
 476                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
 477                                 else
 478                                         dev->caps.port_type[i] = port_type_array[i - 1];
 479                         }
 480                 }
 481                 /*
 482                  * Link sensing is allowed on the port if 3 conditions are true:
 483                  * 1. Both protocols are supported on the port.
 484                  * 2. Different types are supported on the port
 485                  * 3. FW declared that it supports link sensing
 486                  */
 487                 mlx4_priv(dev)->sense.sense_allowed[i] =
 488                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
 489                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 490                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
 491
 492                 /*
 493                  * If "default_sense" bit is set, we move the port to "AUTO" mode
 494                  * and perform sense_port FW command to try and set the correct
 495                  * port type from beginning
 496                  */
 497                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
 498                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
 499                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
 500                         mlx4_SENSE_PORT(dev, i, &sensed_port);
 501                         if (sensed_port != MLX4_PORT_TYPE_NONE)
 502                                 dev->caps.port_type[i] = sensed_port;
 503                 } else {
 504                         dev->caps.possible_type[i] = dev->caps.port_type[i];
 505                 }
 506
 507                 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
 508                         dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
 509                         mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
 510                                   i, 1 << dev->caps.log_num_macs);
 511                 }
 512                 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
 513                         dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
 514                         mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
 515                                   i, 1 << dev->caps.log_num_vlans);
 516                 }
 517         }
 518
 519         if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
 520             (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
 521             (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
 522                 mlx4_warn(dev,
 523                           "Granular QoS per VF not supported with IB/Eth configuration\n");
 524                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
 525         }
 526
 527         dev->caps.max_counters = dev_cap->max_counters;
 528
 529         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 530         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 531                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 532                 (1 << dev->caps.log_num_macs) *
 533                 (1 << dev->caps.log_num_vlans) *
 534                 dev->caps.num_ports;
 535         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 536
 537         if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
 538             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
 539                 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
 540         else
 541                 dev->caps.dmfs_high_rate_qpn_base =
 542                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 543
 544         if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
 545             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
 546                 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
 547                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
 548                 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
 549         } else {
 550                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
 551                 dev->caps.dmfs_high_rate_qpn_base =
 552                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 553                 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
 554         }
 555
 556         dev->caps.rl_caps = dev_cap->rl_caps;
 557
 558         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
 559                 dev->caps.dmfs_high_rate_qpn_range;
 560
 561         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 562                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 563                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 564                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 565
 566         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
 567
 568         if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
 569                 if (dev_cap->flags &
 570                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
 571                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
 572                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 573                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 574                 }
 575
 576                 if (dev_cap->flags2 &
 577                     (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
 578                      MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
 579                         mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
 580                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 581                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 582                 }
 583         }
 584
 585         if ((dev->caps.flags &
 586             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
 587             mlx4_is_master(dev))
 588                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
 589
 590         if (!mlx4_is_slave(dev)) {
 591                 mlx4_enable_cqe_eqe_stride(dev);
 592                 dev->caps.alloc_res_qp_mask =
 593                         (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
 594                         MLX4_RESERVE_A0_QP;
 595
 596                 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
 597                     dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
 598                         mlx4_warn(dev, "Old device ETS support detected\n");
 599                         mlx4_warn(dev, "Consider upgrading device FW.\n");
 600                         dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
 601                 }
 602
 603         } else {
 604                 dev->caps.alloc_res_qp_mask = 0;
 605         }
 606
 607         mlx4_enable_ignore_fcs(dev);
 608
 609         return 0;
 610 }
 611
 612 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
 613                                        enum pci_bus_speed *speed,
 614                                        enum pcie_link_width *width)
 615 {
 616         u32 lnkcap1, lnkcap2;
 617         int err1, err2;
 618
 619 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
 620
 621         *speed = PCI_SPEED_UNKNOWN;
 622         *width = PCIE_LNK_WIDTH_UNKNOWN;
 623
 624         err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
 625                                           &lnkcap1);
 626         err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
 627                                           &lnkcap2);
 628         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
 629                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
 630                         *speed = PCIE_SPEED_8_0GT;
 631                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
 632                         *speed = PCIE_SPEED_5_0GT;
 633                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
 634                         *speed = PCIE_SPEED_2_5GT;
 635         }
 636         if (!err1) {
 637                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
 638                 if (!lnkcap2) { /* pre-r3.0 */
 639                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
 640                                 *speed = PCIE_SPEED_5_0GT;
 641                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
 642                                 *speed = PCIE_SPEED_2_5GT;
 643                 }
 644         }
 645
 646         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
 647                 return err1 ? err1 :
 648                         err2 ? err2 : -EINVAL;
 649         }
 650         return 0;
 651 }
 652
 653 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
 654 {
 655         enum pcie_link_width width, width_cap;
 656         enum pci_bus_speed speed, speed_cap;
 657         int err;
 658
 659 #define PCIE_SPEED_STR(speed) \
 660         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
 661          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
 662          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
 663          "Unknown")
 664
 665         err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
 666         if (err) {
 667                 mlx4_warn(dev,
 668                           "Unable to determine PCIe device BW capabilities\n");
 669                 return;
 670         }
 671
 672         err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
 673         if (err || speed == PCI_SPEED_UNKNOWN ||
 674             width == PCIE_LNK_WIDTH_UNKNOWN) {
 675                 mlx4_warn(dev,
 676                           "Unable to determine PCI device chain minimum BW\n");
 677                 return;
 678         }
 679
 680         if (width != width_cap || speed != speed_cap)
 681                 mlx4_warn(dev,
 682                           "PCIe BW is different than device's capability\n");
 683
 684         mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
 685                   PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
 686         mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
 687                   width, width_cap);
 688         return;
 689 }
 690
 691 /*The function checks if there are live vf, return the num of them*/
 692 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
 693 {
 694         struct mlx4_priv *priv = mlx4_priv(dev);
 695         struct mlx4_slave_state *s_state;
 696         int i;
 697         int ret = 0;
 698
 699         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
 700                 s_state = &priv->mfunc.master.slave_state[i];
 701                 if (s_state->active && s_state->last_cmd !=
 702                     MLX4_COMM_CMD_RESET) {
 703                         mlx4_warn(dev, "%s: slave: %d is still active\n",
 704                                   __func__, i);
 705                         ret++;
 706                 }
 707         }
 708         return ret;
 709 }
 710
 711 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
 712 {
 713         u32 qk = MLX4_RESERVED_QKEY_BASE;
 714
 715         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
 716             qpn < dev->phys_caps.base_proxy_sqpn)
 717                 return -EINVAL;
 718
 719         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
 720                 /* tunnel qp */
 721                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
 722         else
 723                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
 724         *qkey = qk;
 725         return 0;
 726 }
 727 EXPORT_SYMBOL(mlx4_get_parav_qkey);
 728
 729 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
 730 {
 731         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 732
 733         if (!mlx4_is_master(dev))
 734                 return;
 735
 736         priv->virt2phys_pkey[slave][port - 1][i] = val;
 737 }
 738 EXPORT_SYMBOL(mlx4_sync_pkey_table);
 739
 740 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
 741 {
 742         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 743
 744         if (!mlx4_is_master(dev))
 745                 return;
 746
 747         priv->slave_node_guids[slave] = guid;
 748 }
 749 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
 750
 751 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
 752 {
 753         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 754
 755         if (!mlx4_is_master(dev))
 756                 return 0;
 757
 758         return priv->slave_node_guids[slave];
 759 }
 760 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
 761
 762 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
 763 {
 764         struct mlx4_priv *priv = mlx4_priv(dev);
 765         struct mlx4_slave_state *s_slave;
 766
 767         if (!mlx4_is_master(dev))
 768                 return 0;
 769
 770         s_slave = &priv->mfunc.master.slave_state[slave];
 771         return !!s_slave->active;
 772 }
 773 EXPORT_SYMBOL(mlx4_is_slave_active);
 774
 775 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
 776                                        struct mlx4_dev_cap *dev_cap,
 777                                        struct mlx4_init_hca_param *hca_param)
 778 {
 779         dev->caps.steering_mode = hca_param->steering_mode;
 780         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
 781                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
 782                 dev->caps.fs_log_max_ucast_qp_range_size =
 783                         dev_cap->fs_log_max_ucast_qp_range_size;
 784         } else
 785                 dev->caps.num_qp_per_mgm =
 786                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
 787
 788         mlx4_dbg(dev, "Steering mode is: %s\n",
 789                  mlx4_steering_mode_str(dev->caps.steering_mode));
 790 }
 791
 792 static int mlx4_slave_cap(struct mlx4_dev *dev)
 793 {
 794         int                        err;
 795         u32                        page_size;
 796         struct mlx4_dev_cap        dev_cap;
 797         struct mlx4_func_cap       func_cap;
 798         struct mlx4_init_hca_param hca_param;
 799         u8                         i;
 800
 801         memset(&hca_param, 0, sizeof(hca_param));
 802         err = mlx4_QUERY_HCA(dev, &hca_param);
 803         if (err) {
 804                 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
 805                 return err;
 806         }
 807
 808         /* fail if the hca has an unknown global capability
 809          * at this time global_caps should be always zeroed
 810          */
 811         if (hca_param.global_caps) {
 812                 mlx4_err(dev, "Unknown hca global capabilities\n");
 813                 return -ENOSYS;
 814         }
 815
 816         mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
 817
 818         dev->caps.hca_core_clock = hca_param.hca_core_clock;
 819
 820         memset(&dev_cap, 0, sizeof(dev_cap));
 821         dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
 822         err = mlx4_dev_cap(dev, &dev_cap);
 823         if (err) {
 824                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
 825                 return err;
 826         }
 827
 828         err = mlx4_QUERY_FW(dev);
 829         if (err)
 830                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
 831
 832         page_size = ~dev->caps.page_size_cap + 1;
 833         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
 834         if (page_size > PAGE_SIZE) {
 835                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
 836                          page_size, PAGE_SIZE);
 837                 return -ENODEV;
 838         }
 839
 840         /* Set uar_page_shift for VF */
 841         dev->uar_page_shift = hca_param.uar_page_sz + 12;
 842
 843         /* Make sure the master uar page size is valid */
 844         if (dev->uar_page_shift > PAGE_SHIFT) {
 845                 mlx4_err(dev,
 846                          "Invalid configuration: uar page size is larger than system page size\n");
 847                 return  -ENODEV;
 848         }
 849
 850         /* Set reserved_uars based on the uar_page_shift */
 851         mlx4_set_num_reserved_uars(dev, &dev_cap);
 852
 853         /* Although uar page size in FW differs from system page size,
 854          * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core)
 855          * still works with assumption that uar page size == system page size
 856          */
 857         dev->caps.uar_page_size = PAGE_SIZE;
 858
 859         memset(&func_cap, 0, sizeof(func_cap));
 860         err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
 861         if (err) {
 862                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
 863                          err);
 864                 return err;
 865         }
 866
 867         if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
 868             PF_CONTEXT_BEHAVIOUR_MASK) {
 869                 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
 870                          func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
 871                 return -ENOSYS;
 872         }
 873
 874         dev->caps.num_ports             = func_cap.num_ports;
 875         dev->quotas.qp                  = func_cap.qp_quota;
 876         dev->quotas.srq                 = func_cap.srq_quota;
 877         dev->quotas.cq                  = func_cap.cq_quota;
 878         dev->quotas.mpt                 = func_cap.mpt_quota;
 879         dev->quotas.mtt                 = func_cap.mtt_quota;
 880         dev->caps.num_qps               = 1 << hca_param.log_num_qps;
 881         dev->caps.num_srqs              = 1 << hca_param.log_num_srqs;
 882         dev->caps.num_cqs               = 1 << hca_param.log_num_cqs;
 883         dev->caps.num_mpts              = 1 << hca_param.log_mpt_sz;
 884         dev->caps.num_eqs               = func_cap.max_eq;
 885         dev->caps.reserved_eqs          = func_cap.reserved_eq;
 886         dev->caps.reserved_lkey         = func_cap.reserved_lkey;
 887         dev->caps.num_pds               = MLX4_NUM_PDS;
 888         dev->caps.num_mgms              = 0;
 889         dev->caps.num_amgms             = 0;
 890
 891         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
 892                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
 893                          dev->caps.num_ports, MLX4_MAX_PORTS);
 894                 return -ENODEV;
 895         }
 896
 897         mlx4_replace_zero_macs(dev);
 898
 899         dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
 900         dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 901         dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 902         dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 903         dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 904
 905         if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
 906             !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
 907             !dev->caps.qp0_qkey) {
 908                 err = -ENOMEM;
 909                 goto err_mem;
 910         }
 911
 912         for (i = 1; i <= dev->caps.num_ports; ++i) {
 913                 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
 914                 if (err) {
 915                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
 916                                  i, err);
 917                         goto err_mem;
 918                 }
 919                 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
 920                 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
 921                 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
 922                 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
 923                 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
 924                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 925                 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
 926                 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
 927                                                       &dev->caps.gid_table_len[i],
 928                                                       &dev->caps.pkey_table_len[i]);
 929                 if (err)
 930                         goto err_mem;
 931         }
 932
 933         if (dev->caps.uar_page_size * (dev->caps.num_uars -
 934                                        dev->caps.reserved_uars) >
 935                                        pci_resource_len(dev->persist->pdev,
 936                                                         2)) {
 937                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
 938                          dev->caps.uar_page_size * dev->caps.num_uars,
 939                          (unsigned long long)
 940                          pci_resource_len(dev->persist->pdev, 2));
 941                 err = -ENOMEM;
 942                 goto err_mem;
 943         }
 944
 945         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
 946                 dev->caps.eqe_size   = 64;
 947                 dev->caps.eqe_factor = 1;
 948         } else {
 949                 dev->caps.eqe_size   = 32;
 950                 dev->caps.eqe_factor = 0;
 951         }
 952
 953         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
 954                 dev->caps.cqe_size   = 64;
 955                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
 956         } else {
 957                 dev->caps.cqe_size   = 32;
 958         }
 959
 960         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
 961                 dev->caps.eqe_size = hca_param.eqe_size;
 962                 dev->caps.eqe_factor = 0;
 963         }
 964
 965         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
 966                 dev->caps.cqe_size = hca_param.cqe_size;
 967                 /* User still need to know when CQE > 32B */
 968                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
 969         }
 970
 971         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
 972         mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
 973
 974         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
 975         mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
 976                  hca_param.rss_ip_frags ? "on" : "off");
 977
 978         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
 979             dev->caps.bf_reg_size)
 980                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
 981
 982         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
 983                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
 984
 985         return 0;
 986
 987 err_mem:
 988         kfree(dev->caps.qp0_qkey);
 989         kfree(dev->caps.qp0_tunnel);
 990         kfree(dev->caps.qp0_proxy);
 991         kfree(dev->caps.qp1_tunnel);
 992         kfree(dev->caps.qp1_proxy);
 993         dev->caps.qp0_qkey = NULL;
 994         dev->caps.qp0_tunnel = NULL;
 995         dev->caps.qp0_proxy = NULL;
 996         dev->caps.qp1_tunnel = NULL;
 997         dev->caps.qp1_proxy = NULL;
 998
 999         return err;
1000 }
1001
1002 static void mlx4_request_modules(struct mlx4_dev *dev)
1003 {
1004         int port;
1005         int has_ib_port = false;
1006         int has_eth_port = false;
1007 #define EN_DRV_NAME     "mlx4_en"
1008 #define IB_DRV_NAME     "mlx4_ib"
1009
1010         for (port = 1; port <= dev->caps.num_ports; port++) {
1011                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
1012                         has_ib_port = true;
1013                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
1014                         has_eth_port = true;
1015         }
1016
1017         if (has_eth_port)
1018                 request_module_nowait(EN_DRV_NAME);
1019         if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
1020                 request_module_nowait(IB_DRV_NAME);
1021 }
1022
1023 /*
1024  * Change the port configuration of the device.
1025  * Every user of this function must hold the port mutex.
1026  */
1027 int mlx4_change_port_types(struct mlx4_dev *dev,
1028                            enum mlx4_port_type *port_types)
1029 {
1030         int err = 0;
1031         int change = 0;
1032         int port;
1033
1034         for (port = 0; port <  dev->caps.num_ports; port++) {
1035                 /* Change the port type only if the new type is different
1036                  * from the current, and not set to Auto */
1037                 if (port_types[port] != dev->caps.port_type[port + 1])
1038                         change = 1;
1039         }
1040         if (change) {
1041                 mlx4_unregister_device(dev);
1042                 for (port = 1; port <= dev->caps.num_ports; port++) {
1043                         mlx4_CLOSE_PORT(dev, port);
1044                         dev->caps.port_type[port] = port_types[port - 1];
1045                         err = mlx4_SET_PORT(dev, port, -1);
1046                         if (err) {
1047                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
1048                                          port);
1049                                 goto out;
1050                         }
1051                 }
1052                 mlx4_set_port_mask(dev);
1053                 err = mlx4_register_device(dev);
1054                 if (err) {
1055                         mlx4_err(dev, "Failed to register device\n");
1056                         goto out;
1057                 }
1058                 mlx4_request_modules(dev);
1059         }
1060
1061 out:
1062         return err;
1063 }
1064
1065 static ssize_t show_port_type(struct device *dev,
1066                               struct device_attribute *attr,
1067                               char *buf)
1068 {
1069         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1070                                                    port_attr);
1071         struct mlx4_dev *mdev = info->dev;
1072         char type[8];
1073
1074         sprintf(type, "%s",
1075                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1076                 "ib" : "eth");
1077         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1078                 sprintf(buf, "auto (%s)\n", type);
1079         else
1080                 sprintf(buf, "%s\n", type);
1081
1082         return strlen(buf);
1083 }
1084
1085 static int __set_port_type(struct mlx4_port_info *info,
1086                            enum mlx4_port_type port_type)
1087 {
1088         struct mlx4_dev *mdev = info->dev;
1089         struct mlx4_priv *priv = mlx4_priv(mdev);
1090         enum mlx4_port_type types[MLX4_MAX_PORTS];
1091         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1092         int i;
1093         int err = 0;
1094
1095         mlx4_stop_sense(mdev);
1096         mutex_lock(&priv->port_mutex);
1097         info->tmp_type = port_type;
1098
1099         /* Possible type is always the one that was delivered */
1100         mdev->caps.possible_type[info->port] = info->tmp_type;
1101
1102         for (i = 0; i < mdev->caps.num_ports; i++) {
1103                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1104                                         mdev->caps.possible_type[i+1];
1105                 if (types[i] == MLX4_PORT_TYPE_AUTO)
1106                         types[i] = mdev->caps.port_type[i+1];
1107         }
1108
1109         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1110             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1111                 for (i = 1; i <= mdev->caps.num_ports; i++) {
1112                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1113                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1114                                 err = -EINVAL;
1115                         }
1116                 }
1117         }
1118         if (err) {
1119                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
1120                 goto out;
1121         }
1122
1123         mlx4_do_sense_ports(mdev, new_types, types);
1124
1125         err = mlx4_check_port_params(mdev, new_types);
1126         if (err)
1127                 goto out;
1128
1129         /* We are about to apply the changes after the configuration
1130          * was verified, no need to remember the temporary types
1131          * any more */
1132         for (i = 0; i < mdev->caps.num_ports; i++)
1133                 priv->port[i + 1].tmp_type = 0;
1134
1135         err = mlx4_change_port_types(mdev, new_types);
1136
1137 out:
1138         mlx4_start_sense(mdev);
1139         mutex_unlock(&priv->port_mutex);
1140
1141         return err;
1142 }
1143
1144 static ssize_t set_port_type(struct device *dev,
1145                              struct device_attribute *attr,
1146                              const char *buf, size_t count)
1147 {
1148         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1149                                                    port_attr);
1150         struct mlx4_dev *mdev = info->dev;
1151         enum mlx4_port_type port_type;
1152         static DEFINE_MUTEX(set_port_type_mutex);
1153         int err;
1154
1155         mutex_lock(&set_port_type_mutex);
1156
1157         if (!strcmp(buf, "ib\n")) {
1158                 port_type = MLX4_PORT_TYPE_IB;
1159         } else if (!strcmp(buf, "eth\n")) {
1160                 port_type = MLX4_PORT_TYPE_ETH;
1161         } else if (!strcmp(buf, "auto\n")) {
1162                 port_type = MLX4_PORT_TYPE_AUTO;
1163         } else {
1164                 mlx4_err(mdev, "%s is not supported port type\n", buf);
1165                 err = -EINVAL;
1166                 goto err_out;
1167         }
1168
1169         err = __set_port_type(info, port_type);
1170
1171 err_out:
1172         mutex_unlock(&set_port_type_mutex);
1173
1174         return err ? err : count;
1175 }
1176
1177 enum ibta_mtu {
1178         IB_MTU_256  = 1,
1179         IB_MTU_512  = 2,
1180         IB_MTU_1024 = 3,
1181         IB_MTU_2048 = 4,
1182         IB_MTU_4096 = 5
1183 };
1184
1185 static inline int int_to_ibta_mtu(int mtu)
1186 {
1187         switch (mtu) {
1188         case 256:  return IB_MTU_256;
1189         case 512:  return IB_MTU_512;
1190         case 1024: return IB_MTU_1024;
1191         case 2048: return IB_MTU_2048;
1192         case 4096: return IB_MTU_4096;
1193         default: return -1;
1194         }
1195 }
1196
1197 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1198 {
1199         switch (mtu) {
1200         case IB_MTU_256:  return  256;
1201         case IB_MTU_512:  return  512;
1202         case IB_MTU_1024: return 1024;
1203         case IB_MTU_2048: return 2048;
1204         case IB_MTU_4096: return 4096;
1205         default: return -1;
1206         }
1207 }
1208
1209 static ssize_t show_port_ib_mtu(struct device *dev,
1210                              struct device_attribute *attr,
1211                              char *buf)
1212 {
1213         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1214                                                    port_mtu_attr);
1215         struct mlx4_dev *mdev = info->dev;
1216
1217         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1218                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1219
1220         sprintf(buf, "%d\n",
1221                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1222         return strlen(buf);
1223 }
1224
1225 static ssize_t set_port_ib_mtu(struct device *dev,
1226                              struct device_attribute *attr,
1227                              const char *buf, size_t count)
1228 {
1229         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1230                                                    port_mtu_attr);
1231         struct mlx4_dev *mdev = info->dev;
1232         struct mlx4_priv *priv = mlx4_priv(mdev);
1233         int err, port, mtu, ibta_mtu = -1;
1234
1235         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1236                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1237                 return -EINVAL;
1238         }
1239
1240         err = kstrtoint(buf, 0, &mtu);
1241         if (!err)
1242                 ibta_mtu = int_to_ibta_mtu(mtu);
1243
1244         if (err || ibta_mtu < 0) {
1245                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1246                 return -EINVAL;
1247         }
1248
1249         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1250
1251         mlx4_stop_sense(mdev);
1252         mutex_lock(&priv->port_mutex);
1253         mlx4_unregister_device(mdev);
1254         for (port = 1; port <= mdev->caps.num_ports; port++) {
1255                 mlx4_CLOSE_PORT(mdev, port);
1256                 err = mlx4_SET_PORT(mdev, port, -1);
1257                 if (err) {
1258                         mlx4_err(mdev, "Failed to set port %d, aborting\n",
1259                                  port);
1260                         goto err_set_port;
1261                 }
1262         }
1263         err = mlx4_register_device(mdev);
1264 err_set_port:
1265         mutex_unlock(&priv->port_mutex);
1266         mlx4_start_sense(mdev);
1267         return err ? err : count;
1268 }
1269
1270 /* bond for multi-function device */
1271 #define MAX_MF_BOND_ALLOWED_SLAVES 63
1272 static int mlx4_mf_bond(struct mlx4_dev *dev)
1273 {
1274         int err = 0;
1275         int nvfs;
1276         struct mlx4_slaves_pport slaves_port1;
1277         struct mlx4_slaves_pport slaves_port2;
1278         DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX);
1279
1280         slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1);
1281         slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2);
1282         bitmap_and(slaves_port_1_2,
1283                    slaves_port1.slaves, slaves_port2.slaves,
1284                    dev->persist->num_vfs + 1);
1285
1286         /* only single port vfs are allowed */
1287         if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) {
1288                 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n");
1289                 return -EINVAL;
1290         }
1291
1292         /* number of virtual functions is number of total functions minus one
1293          * physical function for each port.
1294          */
1295         nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) +
1296                 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2;
1297
1298         /* limit on maximum allowed VFs */
1299         if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) {
1300                 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n",
1301                           nvfs, MAX_MF_BOND_ALLOWED_SLAVES);
1302                 return -EINVAL;
1303         }
1304
1305         if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1306                 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n");
1307                 return -EINVAL;
1308         }
1309
1310         err = mlx4_bond_mac_table(dev);
1311         if (err)
1312                 return err;
1313         err = mlx4_bond_vlan_table(dev);
1314         if (err)
1315                 goto err1;
1316         err = mlx4_bond_fs_rules(dev);
1317         if (err)
1318                 goto err2;
1319
1320         return 0;
1321 err2:
1322         (void)mlx4_unbond_vlan_table(dev);
1323 err1:
1324         (void)mlx4_unbond_mac_table(dev);
1325         return err;
1326 }
1327
1328 static int mlx4_mf_unbond(struct mlx4_dev *dev)
1329 {
1330         int ret, ret1;
1331
1332         ret = mlx4_unbond_fs_rules(dev);
1333         if (ret)
1334                 mlx4_warn(dev, "multifunction unbond for flow rules failedi (%d)\n", ret);
1335         ret1 = mlx4_unbond_mac_table(dev);
1336         if (ret1) {
1337                 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1);
1338                 ret = ret1;
1339         }
1340         ret1 = mlx4_unbond_vlan_table(dev);
1341         if (ret1) {
1342                 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1);
1343                 ret = ret1;
1344         }
1345         return ret;
1346 }
1347
1348 int mlx4_bond(struct mlx4_dev *dev)
1349 {
1350         int ret = 0;
1351         struct mlx4_priv *priv = mlx4_priv(dev);
1352
1353         mutex_lock(&priv->bond_mutex);
1354
1355         if (!mlx4_is_bonded(dev)) {
1356                 ret = mlx4_do_bond(dev, true);
1357                 if (ret)
1358                         mlx4_err(dev, "Failed to bond device: %d\n", ret);
1359                 if (!ret && mlx4_is_master(dev)) {
1360                         ret = mlx4_mf_bond(dev);
1361                         if (ret) {
1362                                 mlx4_err(dev, "bond for multifunction failed\n");
1363                                 mlx4_do_bond(dev, false);
1364                         }
1365                 }
1366         }
1367
1368         mutex_unlock(&priv->bond_mutex);
1369         if (!ret)
1370                 mlx4_dbg(dev, "Device is bonded\n");
1371
1372         return ret;
1373 }
1374 EXPORT_SYMBOL_GPL(mlx4_bond);
1375
1376 int mlx4_unbond(struct mlx4_dev *dev)
1377 {
1378         int ret = 0;
1379         struct mlx4_priv *priv = mlx4_priv(dev);
1380
1381         mutex_lock(&priv->bond_mutex);
1382
1383         if (mlx4_is_bonded(dev)) {
1384                 int ret2 = 0;
1385
1386                 ret = mlx4_do_bond(dev, false);
1387                 if (ret)
1388                         mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1389                 if (mlx4_is_master(dev))
1390                         ret2 = mlx4_mf_unbond(dev);
1391                 if (ret2) {
1392                         mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2);
1393                         ret = ret2;
1394                 }
1395         }
1396
1397         mutex_unlock(&priv->bond_mutex);
1398         if (!ret)
1399                 mlx4_dbg(dev, "Device is unbonded\n");
1400
1401         return ret;
1402 }
1403 EXPORT_SYMBOL_GPL(mlx4_unbond);
1404
1405
1406 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1407 {
1408         u8 port1 = v2p->port1;
1409         u8 port2 = v2p->port2;
1410         struct mlx4_priv *priv = mlx4_priv(dev);
1411         int err;
1412
1413         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1414                 return -ENOTSUPP;
1415
1416         mutex_lock(&priv->bond_mutex);
1417
1418         /* zero means keep current mapping for this port */
1419         if (port1 == 0)
1420                 port1 = priv->v2p.port1;
1421         if (port2 == 0)
1422                 port2 = priv->v2p.port2;
1423
1424         if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1425             (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1426             (port1 == 2 && port2 == 1)) {
1427                 /* besides boundary checks cross mapping makes
1428                  * no sense and therefore not allowed */
1429                 err = -EINVAL;
1430         } else if ((port1 == priv->v2p.port1) &&
1431                  (port2 == priv->v2p.port2)) {
1432                 err = 0;
1433         } else {
1434                 err = mlx4_virt2phy_port_map(dev, port1, port2);
1435                 if (!err) {
1436                         mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1437                                  port1, port2);
1438                         priv->v2p.port1 = port1;
1439                         priv->v2p.port2 = port2;
1440                 } else {
1441                         mlx4_err(dev, "Failed to change port mape: %d\n", err);
1442                 }
1443         }
1444
1445         mutex_unlock(&priv->bond_mutex);
1446         return err;
1447 }
1448 EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1449
1450 static int mlx4_load_fw(struct mlx4_dev *dev)
1451 {
1452         struct mlx4_priv *priv = mlx4_priv(dev);
1453         int err;
1454
1455         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1456                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
1457         if (!priv->fw.fw_icm) {
1458                 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1459                 return -ENOMEM;
1460         }
1461
1462         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1463         if (err) {
1464                 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1465                 goto err_free;
1466         }
1467
1468         err = mlx4_RUN_FW(dev);
1469         if (err) {
1470                 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1471                 goto err_unmap_fa;
1472         }
1473
1474         return 0;
1475
1476 err_unmap_fa:
1477         mlx4_UNMAP_FA(dev);
1478
1479 err_free:
1480         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1481         return err;
1482 }
1483
1484 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1485                                 int cmpt_entry_sz)
1486 {
1487         struct mlx4_priv *priv = mlx4_priv(dev);
1488         int err;
1489         int num_eqs;
1490
1491         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1492                                   cmpt_base +
1493                                   ((u64) (MLX4_CMPT_TYPE_QP *
1494                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1495                                   cmpt_entry_sz, dev->caps.num_qps,
1496                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1497                                   0, 0);
1498         if (err)
1499                 goto err;
1500
1501         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1502                                   cmpt_base +
1503                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
1504                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1505                                   cmpt_entry_sz, dev->caps.num_srqs,
1506                                   dev->caps.reserved_srqs, 0, 0);
1507         if (err)
1508                 goto err_qp;
1509
1510         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1511                                   cmpt_base +
1512                                   ((u64) (MLX4_CMPT_TYPE_CQ *
1513                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1514                                   cmpt_entry_sz, dev->caps.num_cqs,
1515                                   dev->caps.reserved_cqs, 0, 0);
1516         if (err)
1517                 goto err_srq;
1518
1519         num_eqs = dev->phys_caps.num_phys_eqs;
1520         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1521                                   cmpt_base +
1522                                   ((u64) (MLX4_CMPT_TYPE_EQ *
1523                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1524                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1525         if (err)
1526                 goto err_cq;
1527
1528         return 0;
1529
1530 err_cq:
1531         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1532
1533 err_srq:
1534         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1535
1536 err_qp:
1537         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1538
1539 err:
1540         return err;
1541 }
1542
1543 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1544                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
1545 {
1546         struct mlx4_priv *priv = mlx4_priv(dev);
1547         u64 aux_pages;
1548         int num_eqs;
1549         int err;
1550
1551         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1552         if (err) {
1553                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1554                 return err;
1555         }
1556
1557         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1558                  (unsigned long long) icm_size >> 10,
1559                  (unsigned long long) aux_pages << 2);
1560
1561         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1562                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1563         if (!priv->fw.aux_icm) {
1564                 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1565                 return -ENOMEM;
1566         }
1567
1568         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1569         if (err) {
1570                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1571                 goto err_free_aux;
1572         }
1573
1574         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1575         if (err) {
1576                 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1577                 goto err_unmap_aux;
1578         }
1579
1580
1581         num_eqs = dev->phys_caps.num_phys_eqs;
1582         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1583                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1584                                   num_eqs, num_eqs, 0, 0);
1585         if (err) {
1586                 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1587                 goto err_unmap_cmpt;
1588         }
1589
1590         /*
1591          * Reserved MTT entries must be aligned up to a cacheline
1592          * boundary, since the FW will write to them, while the driver
1593          * writes to all other MTT entries. (The variable
1594          * dev->caps.mtt_entry_sz below is really the MTT segment
1595          * size, not the raw entry size)
1596          */
1597         dev->caps.reserved_mtts =
1598                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1599                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1600
1601         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1602                                   init_hca->mtt_base,
1603                                   dev->caps.mtt_entry_sz,
1604                                   dev->caps.num_mtts,
1605                                   dev->caps.reserved_mtts, 1, 0);
1606         if (err) {
1607                 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1608                 goto err_unmap_eq;
1609         }
1610
1611         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1612                                   init_hca->dmpt_base,
1613                                   dev_cap->dmpt_entry_sz,
1614                                   dev->caps.num_mpts,
1615                                   dev->caps.reserved_mrws, 1, 1);
1616         if (err) {
1617                 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1618                 goto err_unmap_mtt;
1619         }
1620
1621         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1622                                   init_hca->qpc_base,
1623                                   dev_cap->qpc_entry_sz,
1624                                   dev->caps.num_qps,
1625                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1626                                   0, 0);
1627         if (err) {
1628                 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1629                 goto err_unmap_dmpt;
1630         }
1631
1632         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1633                                   init_hca->auxc_base,
1634                                   dev_cap->aux_entry_sz,
1635                                   dev->caps.num_qps,
1636                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1637                                   0, 0);
1638         if (err) {
1639                 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1640                 goto err_unmap_qp;
1641         }
1642
1643         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1644                                   init_hca->altc_base,
1645                                   dev_cap->altc_entry_sz,
1646                                   dev->caps.num_qps,
1647                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1648                                   0, 0);
1649         if (err) {
1650                 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1651                 goto err_unmap_auxc;
1652         }
1653
1654         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1655                                   init_hca->rdmarc_base,
1656                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1657                                   dev->caps.num_qps,
1658                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1659                                   0, 0);
1660         if (err) {
1661                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1662                 goto err_unmap_altc;
1663         }
1664
1665         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1666                                   init_hca->cqc_base,
1667                                   dev_cap->cqc_entry_sz,
1668                                   dev->caps.num_cqs,
1669                                   dev->caps.reserved_cqs, 0, 0);
1670         if (err) {
1671                 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1672                 goto err_unmap_rdmarc;
1673         }
1674
1675         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1676                                   init_hca->srqc_base,
1677                                   dev_cap->srq_entry_sz,
1678                                   dev->caps.num_srqs,
1679                                   dev->caps.reserved_srqs, 0, 0);
1680         if (err) {
1681                 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1682                 goto err_unmap_cq;
1683         }
1684
1685         /*
1686          * For flow steering device managed mode it is required to use
1687          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1688          * required, but for simplicity just map the whole multicast
1689          * group table now.  The table isn't very big and it's a lot
1690          * easier than trying to track ref counts.
1691          */
1692         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1693                                   init_hca->mc_base,
1694                                   mlx4_get_mgm_entry_size(dev),
1695                                   dev->caps.num_mgms + dev->caps.num_amgms,
1696                                   dev->caps.num_mgms + dev->caps.num_amgms,
1697                                   0, 0);
1698         if (err) {
1699                 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1700                 goto err_unmap_srq;
1701         }
1702
1703         return 0;
1704
1705 err_unmap_srq:
1706         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1707
1708 err_unmap_cq:
1709         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1710
1711 err_unmap_rdmarc:
1712         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1713
1714 err_unmap_altc:
1715         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1716
1717 err_unmap_auxc:
1718         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1719
1720 err_unmap_qp:
1721         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1722
1723 err_unmap_dmpt:
1724         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1725
1726 err_unmap_mtt:
1727         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1728
1729 err_unmap_eq:
1730         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1731
1732 err_unmap_cmpt:
1733         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1734         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1735         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1736         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1737
1738 err_unmap_aux:
1739         mlx4_UNMAP_ICM_AUX(dev);
1740
1741 err_free_aux:
1742         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1743
1744         return err;
1745 }
1746
1747 static void mlx4_free_icms(struct mlx4_dev *dev)
1748 {
1749         struct mlx4_priv *priv = mlx4_priv(dev);
1750
1751         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1752         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1753         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1754         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1755         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1756         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1757         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1758         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1759         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1760         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1761         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1762         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1763         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1764         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1765
1766         mlx4_UNMAP_ICM_AUX(dev);
1767         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1768 }
1769
1770 static void mlx4_slave_exit(struct mlx4_dev *dev)
1771 {
1772         struct mlx4_priv *priv = mlx4_priv(dev);
1773
1774         mutex_lock(&priv->cmd.slave_cmd_mutex);
1775         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1776                           MLX4_COMM_TIME))
1777                 mlx4_warn(dev, "Failed to close slave function\n");
1778         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1779 }
1780
1781 static int map_bf_area(struct mlx4_dev *dev)
1782 {
1783         struct mlx4_priv *priv = mlx4_priv(dev);
1784         resource_size_t bf_start;
1785         resource_size_t bf_len;
1786         int err = 0;
1787
1788         if (!dev->caps.bf_reg_size)
1789                 return -ENXIO;
1790
1791         bf_start = pci_resource_start(dev->persist->pdev, 2) +
1792                         (dev->caps.num_uars << PAGE_SHIFT);
1793         bf_len = pci_resource_len(dev->persist->pdev, 2) -
1794                         (dev->caps.num_uars << PAGE_SHIFT);
1795         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1796         if (!priv->bf_mapping)
1797                 err = -ENOMEM;
1798
1799         return err;
1800 }
1801
1802 static void unmap_bf_area(struct mlx4_dev *dev)
1803 {
1804         if (mlx4_priv(dev)->bf_mapping)
1805                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1806 }
1807
1808 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1809 {
1810         u32 clockhi, clocklo, clockhi1;
1811         cycle_t cycles;
1812         int i;
1813         struct mlx4_priv *priv = mlx4_priv(dev);
1814
1815         for (i = 0; i < 10; i++) {
1816                 clockhi = swab32(readl(priv->clock_mapping));
1817                 clocklo = swab32(readl(priv->clock_mapping + 4));
1818                 clockhi1 = swab32(readl(priv->clock_mapping));
1819                 if (clockhi == clockhi1)
1820                         break;
1821         }
1822
1823         cycles = (u64) clockhi << 32 | (u64) clocklo;
1824
1825         return cycles;
1826 }
1827 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1828
1829
1830 static int map_internal_clock(struct mlx4_dev *dev)
1831 {
1832         struct mlx4_priv *priv = mlx4_priv(dev);
1833
1834         priv->clock_mapping =
1835                 ioremap(pci_resource_start(dev->persist->pdev,
1836                                            priv->fw.clock_bar) +
1837                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1838
1839         if (!priv->clock_mapping)
1840                 return -ENOMEM;
1841
1842         return 0;
1843 }
1844
1845 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1846                                    struct mlx4_clock_params *params)
1847 {
1848         struct mlx4_priv *priv = mlx4_priv(dev);
1849
1850         if (mlx4_is_slave(dev))
1851                 return -ENOTSUPP;
1852
1853         if (!params)
1854                 return -EINVAL;
1855
1856         params->bar = priv->fw.clock_bar;
1857         params->offset = priv->fw.clock_offset;
1858         params->size = MLX4_CLOCK_SIZE;
1859
1860         return 0;
1861 }
1862 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1863
1864 static void unmap_internal_clock(struct mlx4_dev *dev)
1865 {
1866         struct mlx4_priv *priv = mlx4_priv(dev);
1867
1868         if (priv->clock_mapping)
1869                 iounmap(priv->clock_mapping);
1870 }
1871
1872 static void mlx4_close_hca(struct mlx4_dev *dev)
1873 {
1874         unmap_internal_clock(dev);
1875         unmap_bf_area(dev);
1876         if (mlx4_is_slave(dev))
1877                 mlx4_slave_exit(dev);
1878         else {
1879                 mlx4_CLOSE_HCA(dev, 0);
1880                 mlx4_free_icms(dev);
1881         }
1882 }
1883
1884 static void mlx4_close_fw(struct mlx4_dev *dev)
1885 {
1886         if (!mlx4_is_slave(dev)) {
1887                 mlx4_UNMAP_FA(dev);
1888                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1889         }
1890 }
1891
1892 static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1893 {
1894 #define COMM_CHAN_OFFLINE_OFFSET 0x09
1895
1896         u32 comm_flags;
1897         u32 offline_bit;
1898         unsigned long end;
1899         struct mlx4_priv *priv = mlx4_priv(dev);
1900
1901         end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1902         while (time_before(jiffies, end)) {
1903                 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1904                                           MLX4_COMM_CHAN_FLAGS));
1905                 offline_bit = (comm_flags &
1906                                (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1907                 if (!offline_bit)
1908                         return 0;
1909                 /* There are cases as part of AER/Reset flow that PF needs
1910                  * around 100 msec to load. We therefore sleep for 100 msec
1911                  * to allow other tasks to make use of that CPU during this
1912                  * time interval.
1913                  */
1914                 msleep(100);
1915         }
1916         mlx4_err(dev, "Communication channel is offline.\n");
1917         return -EIO;
1918 }
1919
1920 static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1921 {
1922 #define COMM_CHAN_RST_OFFSET 0x1e
1923
1924         struct mlx4_priv *priv = mlx4_priv(dev);
1925         u32 comm_rst;
1926         u32 comm_caps;
1927
1928         comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1929                                  MLX4_COMM_CHAN_CAPS));
1930         comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
1931
1932         if (comm_rst)
1933                 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1934 }
1935
1936 static int mlx4_init_slave(struct mlx4_dev *dev)
1937 {
1938         struct mlx4_priv *priv = mlx4_priv(dev);
1939         u64 dma = (u64) priv->mfunc.vhcr_dma;
1940         int ret_from_reset = 0;
1941         u32 slave_read;
1942         u32 cmd_channel_ver;
1943
1944         if (atomic_read(&pf_loading)) {
1945                 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
1946                 return -EPROBE_DEFER;
1947         }
1948
1949         mutex_lock(&priv->cmd.slave_cmd_mutex);
1950         priv->cmd.max_cmds = 1;
1951         if (mlx4_comm_check_offline(dev)) {
1952                 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1953                 goto err_offline;
1954         }
1955
1956         mlx4_reset_vf_support(dev);
1957         mlx4_warn(dev, "Sending reset\n");
1958         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1959                                        MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
1960         /* if we are in the middle of flr the slave will try
1961          * NUM_OF_RESET_RETRIES times before leaving.*/
1962         if (ret_from_reset) {
1963                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1964                         mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
1965                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1966                         return -EPROBE_DEFER;
1967                 } else
1968                         goto err;
1969         }
1970
1971         /* check the driver version - the slave I/F revision
1972          * must match the master's */
1973         slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1974         cmd_channel_ver = mlx4_comm_get_version();
1975
1976         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1977                 MLX4_COMM_GET_IF_REV(slave_read)) {
1978                 mlx4_err(dev, "slave driver version is not supported by the master\n");
1979                 goto err;
1980         }
1981
1982         mlx4_warn(dev, "Sending vhcr0\n");
1983         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1984                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1985                 goto err;
1986         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1987                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1988                 goto err;
1989         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1990                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1991                 goto err;
1992         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
1993                           MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1994                 goto err;
1995
1996         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1997         return 0;
1998
1999 err:
2000         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
2001 err_offline:
2002         mutex_unlock(&priv->cmd.slave_cmd_mutex);
2003         return -EIO;
2004 }
2005
2006 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
2007 {
2008         int i;
2009
2010         for (i = 1; i <= dev->caps.num_ports; i++) {
2011                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2012                         dev->caps.gid_table_len[i] =
2013                                 mlx4_get_slave_num_gids(dev, 0, i);
2014                 else
2015                         dev->caps.gid_table_len[i] = 1;
2016                 dev->caps.pkey_table_len[i] =
2017                         dev->phys_caps.pkey_phys_table_len[i] - 1;
2018         }
2019 }
2020
2021 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
2022 {
2023         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
2024
2025         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
2026               i++) {
2027                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
2028                         break;
2029         }
2030
2031         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
2032 }
2033
2034 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
2035 {
2036         switch (dmfs_high_steer_mode) {
2037         case MLX4_STEERING_DMFS_A0_DEFAULT:
2038                 return "default performance";
2039
2040         case MLX4_STEERING_DMFS_A0_DYNAMIC:
2041                 return "dynamic hybrid mode";
2042
2043         case MLX4_STEERING_DMFS_A0_STATIC:
2044                 return "performance optimized for limited rule configuration (static)";
2045
2046         case MLX4_STEERING_DMFS_A0_DISABLE:
2047                 return "disabled performance optimized steering";
2048
2049         case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
2050                 return "performance optimized steering not supported";
2051
2052         default:
2053                 return "Unrecognized mode";
2054         }
2055 }
2056
2057 #define MLX4_DMFS_A0_STEERING                   (1UL << 2)
2058
2059 static void choose_steering_mode(struct mlx4_dev *dev,
2060                                  struct mlx4_dev_cap *dev_cap)
2061 {
2062         if (mlx4_log_num_mgm_entry_size <= 0) {
2063                 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
2064                         if (dev->caps.dmfs_high_steer_mode ==
2065                             MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2066                                 mlx4_err(dev, "DMFS high rate mode not supported\n");
2067                         else
2068                                 dev->caps.dmfs_high_steer_mode =
2069                                         MLX4_STEERING_DMFS_A0_STATIC;
2070                 }
2071         }
2072
2073         if (mlx4_log_num_mgm_entry_size <= 0 &&
2074             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
2075             (!mlx4_is_mfunc(dev) ||
2076              (dev_cap->fs_max_num_qp_per_entry >=
2077              (dev->persist->num_vfs + 1))) &&
2078             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
2079                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
2080                 dev->oper_log_mgm_entry_size =
2081                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
2082                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2083                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2084                 dev->caps.fs_log_max_ucast_qp_range_size =
2085                         dev_cap->fs_log_max_ucast_qp_range_size;
2086         } else {
2087                 if (dev->caps.dmfs_high_steer_mode !=
2088                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2089                         dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
2090                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2091                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2092                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2093                 else {
2094                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2095
2096                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2097                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2098                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
2099                 }
2100                 dev->oper_log_mgm_entry_size =
2101                         mlx4_log_num_mgm_entry_size > 0 ?
2102                         mlx4_log_num_mgm_entry_size :
2103                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
2104                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2105         }
2106         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
2107                  mlx4_steering_mode_str(dev->caps.steering_mode),
2108                  dev->oper_log_mgm_entry_size,
2109                  mlx4_log_num_mgm_entry_size);
2110 }
2111
2112 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
2113                                        struct mlx4_dev_cap *dev_cap)
2114 {
2115         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2116             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
2117                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2118         else
2119                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2120
2121         mlx4_dbg(dev, "Tunneling offload mode is: %s\n",  (dev->caps.tunnel_offload_mode
2122                  == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
2123 }
2124
2125 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
2126 {
2127         int i;
2128         struct mlx4_port_cap port_cap;
2129
2130         if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2131                 return -EINVAL;
2132
2133         for (i = 1; i <= dev->caps.num_ports; i++) {
2134                 if (mlx4_dev_port(dev, i, &port_cap)) {
2135                         mlx4_err(dev,
2136                                  "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
2137                 } else if ((dev->caps.dmfs_high_steer_mode !=
2138                             MLX4_STEERING_DMFS_A0_DEFAULT) &&
2139                            (port_cap.dmfs_optimized_state ==
2140                             !!(dev->caps.dmfs_high_steer_mode ==
2141                             MLX4_STEERING_DMFS_A0_DISABLE))) {
2142                         mlx4_err(dev,
2143                                  "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2144                                  dmfs_high_rate_steering_mode_str(
2145                                         dev->caps.dmfs_high_steer_mode),
2146                                  (port_cap.dmfs_optimized_state ?
2147                                         "enabled" : "disabled"));
2148                 }
2149         }
2150
2151         return 0;
2152 }
2153
2154 static int mlx4_init_fw(struct mlx4_dev *dev)
2155 {
2156         struct mlx4_mod_stat_cfg   mlx4_cfg;
2157         int err = 0;
2158
2159         if (!mlx4_is_slave(dev)) {
2160                 err = mlx4_QUERY_FW(dev);
2161                 if (err) {
2162                         if (err == -EACCES)
2163                                 mlx4_info(dev, "non-primary physical function, skipping\n");
2164                         else
2165                                 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
2166                         return err;
2167                 }
2168
2169                 err = mlx4_load_fw(dev);
2170                 if (err) {
2171                         mlx4_err(dev, "Failed to start FW, aborting\n");
2172                         return err;
2173                 }
2174
2175                 mlx4_cfg.log_pg_sz_m = 1;
2176                 mlx4_cfg.log_pg_sz = 0;
2177                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2178                 if (err)
2179                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2180         }
2181
2182         return err;
2183 }
2184
2185 static int mlx4_init_hca(struct mlx4_dev *dev)
2186 {
2187         struct mlx4_priv          *priv = mlx4_priv(dev);
2188         struct mlx4_adapter        adapter;
2189         struct mlx4_dev_cap        dev_cap;
2190         struct mlx4_profile        profile;
2191         struct mlx4_init_hca_param init_hca;
2192         u64 icm_size;
2193         struct mlx4_config_dev_params params;
2194         int err;
2195
2196         if (!mlx4_is_slave(dev)) {
2197                 err = mlx4_dev_cap(dev, &dev_cap);
2198                 if (err) {
2199                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
2200                         return err;
2201                 }
2202
2203                 choose_steering_mode(dev, &dev_cap);
2204                 choose_tunnel_offload_mode(dev, &dev_cap);
2205
2206                 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2207                     mlx4_is_master(dev))
2208                         dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2209
2210                 err = mlx4_get_phys_port_id(dev);
2211                 if (err)
2212                         mlx4_err(dev, "Fail to get physical port id\n");
2213
2214                 if (mlx4_is_master(dev))
2215                         mlx4_parav_master_pf_caps(dev);
2216
2217                 if (mlx4_low_memory_profile()) {
2218                         mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2219                         profile = low_mem_profile;
2220                 } else {
2221                         profile = default_profile;
2222                 }
2223                 if (dev->caps.steering_mode ==
2224                     MLX4_STEERING_MODE_DEVICE_MANAGED)
2225                         profile.num_mcg = MLX4_FS_NUM_MCG;
2226
2227                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2228                                              &init_hca);
2229                 if ((long long) icm_size < 0) {
2230                         err = icm_size;
2231                         return err;
2232                 }
2233
2234                 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2235
2236                 /* Always set UAR page size 4KB, set log_uar_sz accordingly */
2237                 init_hca.log_uar_sz = ilog2(dev->caps.num_uars) +
2238                                       PAGE_SHIFT -
2239                                       DEFAULT_UAR_PAGE_SHIFT;
2240                 init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12;
2241
2242                 init_hca.mw_enabled = 0;
2243                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2244                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2245                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
2246
2247                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2248                 if (err)
2249                         return err;
2250
2251                 err = mlx4_INIT_HCA(dev, &init_hca);
2252                 if (err) {
2253                         mlx4_err(dev, "INIT_HCA command failed, aborting\n");
2254                         goto err_free_icm;
2255                 }
2256
2257                 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2258                         err = mlx4_query_func(dev, &dev_cap);
2259                         if (err < 0) {
2260                                 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
2261                                 goto err_close;
2262                         } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2263                                 dev->caps.num_eqs = dev_cap.max_eqs;
2264                                 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2265                                 dev->caps.reserved_uars = dev_cap.reserved_uars;
2266                         }
2267                 }
2268
2269                 /*
2270                  * If TS is supported by FW
2271                  * read HCA frequency by QUERY_HCA command
2272                  */
2273                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2274                         memset(&init_hca, 0, sizeof(init_hca));
2275                         err = mlx4_QUERY_HCA(dev, &init_hca);
2276                         if (err) {
2277                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
2278                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2279                         } else {
2280                                 dev->caps.hca_core_clock =
2281                                         init_hca.hca_core_clock;
2282                         }
2283
2284                         /* In case we got HCA frequency 0 - disable timestamping
2285                          * to avoid dividing by zero
2286                          */
2287                         if (!dev->caps.hca_core_clock) {
2288                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2289                                 mlx4_err(dev,
2290                                          "HCA frequency is 0 - timestamping is not supported\n");
2291                         } else if (map_internal_clock(dev)) {
2292                                 /*
2293                                  * Map internal clock,
2294                                  * in case of failure disable timestamping
2295                                  */
2296                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2297                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
2298                         }
2299                 }
2300
2301                 if (dev->caps.dmfs_high_steer_mode !=
2302                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2303                         if (mlx4_validate_optimized_steering(dev))
2304                                 mlx4_warn(dev, "Optimized steering validation failed\n");
2305
2306                         if (dev->caps.dmfs_high_steer_mode ==
2307                             MLX4_STEERING_DMFS_A0_DISABLE) {
2308                                 dev->caps.dmfs_high_rate_qpn_base =
2309                                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2310                                 dev->caps.dmfs_high_rate_qpn_range =
2311                                         MLX4_A0_STEERING_TABLE_SIZE;
2312                         }
2313
2314                         mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
2315                                  dmfs_high_rate_steering_mode_str(
2316                                         dev->caps.dmfs_high_steer_mode));
2317                 }
2318         } else {
2319                 err = mlx4_init_slave(dev);
2320                 if (err) {
2321                         if (err != -EPROBE_DEFER)
2322                                 mlx4_err(dev, "Failed to initialize slave\n");
2323                         return err;
2324                 }
2325
2326                 err = mlx4_slave_cap(dev);
2327                 if (err) {
2328                         mlx4_err(dev, "Failed to obtain slave caps\n");
2329                         goto err_close;
2330                 }
2331         }
2332
2333         if (map_bf_area(dev))
2334                 mlx4_dbg(dev, "Failed to map blue flame area\n");
2335
2336         /*Only the master set the ports, all the rest got it from it.*/
2337         if (!mlx4_is_slave(dev))
2338                 mlx4_set_port_mask(dev);
2339
2340         err = mlx4_QUERY_ADAPTER(dev, &adapter);
2341         if (err) {
2342                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
2343                 goto unmap_bf;
2344         }
2345
2346         /* Query CONFIG_DEV parameters */
2347         err = mlx4_config_dev_retrieval(dev, &params);
2348         if (err && err != -ENOTSUPP) {
2349                 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2350         } else if (!err) {
2351                 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2352                 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2353         }
2354         priv->eq_table.inta_pin = adapter.inta_pin;
2355         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
2356
2357         return 0;
2358
2359 unmap_bf:
2360         unmap_internal_clock(dev);
2361         unmap_bf_area(dev);
2362
2363         if (mlx4_is_slave(dev)) {
2364                 kfree(dev->caps.qp0_qkey);
2365                 kfree(dev->caps.qp0_tunnel);
2366                 kfree(dev->caps.qp0_proxy);
2367                 kfree(dev->caps.qp1_tunnel);
2368                 kfree(dev->caps.qp1_proxy);
2369         }
2370
2371 err_close:
2372         if (mlx4_is_slave(dev))
2373                 mlx4_slave_exit(dev);
2374         else
2375                 mlx4_CLOSE_HCA(dev, 0);
2376
2377 err_free_icm:
2378         if (!mlx4_is_slave(dev))
2379                 mlx4_free_icms(dev);
2380
2381         return err;
2382 }
2383
2384 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2385 {
2386         struct mlx4_priv *priv = mlx4_priv(dev);
2387         int nent_pow2;
2388
2389         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2390                 return -ENOENT;
2391
2392         if (!dev->caps.max_counters)
2393                 return -ENOSPC;
2394
2395         nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2396         /* reserve last counter index for sink counter */
2397         return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2398                                 nent_pow2 - 1, 0,
2399                                 nent_pow2 - dev->caps.max_counters + 1);
2400 }
2401
2402 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2403 {
2404         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2405                 return;
2406
2407         if (!dev->caps.max_counters)
2408                 return;
2409
2410         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2411 }
2412
2413 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2414 {
2415         struct mlx4_priv *priv = mlx4_priv(dev);
2416         int port;
2417
2418         for (port = 0; port < dev->caps.num_ports; port++)
2419                 if (priv->def_counter[port] != -1)
2420                         mlx4_counter_free(dev,  priv->def_counter[port]);
2421 }
2422
2423 static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2424 {
2425         struct mlx4_priv *priv = mlx4_priv(dev);
2426         int port, err = 0;
2427         u32 idx;
2428
2429         for (port = 0; port < dev->caps.num_ports; port++)
2430                 priv->def_counter[port] = -1;
2431
2432         for (port = 0; port < dev->caps.num_ports; port++) {
2433                 err = mlx4_counter_alloc(dev, &idx);
2434
2435                 if (!err || err == -ENOSPC) {
2436                         priv->def_counter[port] = idx;
2437                 } else if (err == -ENOENT) {
2438                         err = 0;
2439                         continue;
2440                 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2441                         priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2442                         mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2443                                   MLX4_SINK_COUNTER_INDEX(dev));
2444                         err = 0;
2445                 } else {
2446                         mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2447                                  __func__, port + 1, err);
2448                         mlx4_cleanup_default_counters(dev);
2449                         return err;
2450                 }
2451
2452                 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2453                          __func__, priv->def_counter[port], port + 1);
2454         }
2455
2456         return err;
2457 }
2458
2459 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2460 {
2461         struct mlx4_priv *priv = mlx4_priv(dev);
2462
2463         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2464                 return -ENOENT;
2465
2466         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2467         if (*idx == -1) {
2468                 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2469                 return -ENOSPC;
2470         }
2471
2472         return 0;
2473 }
2474
2475 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2476 {
2477         u64 out_param;
2478         int err;
2479
2480         if (mlx4_is_mfunc(dev)) {
2481                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2482                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2483                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2484                 if (!err)
2485                         *idx = get_param_l(&out_param);
2486
2487                 return err;
2488         }
2489         return __mlx4_counter_alloc(dev, idx);
2490 }
2491 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2492
2493 static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2494                                 u8 counter_index)
2495 {
2496         struct mlx4_cmd_mailbox *if_stat_mailbox;
2497         int err;
2498         u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2499
2500         if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2501         if (IS_ERR(if_stat_mailbox))
2502                 return PTR_ERR(if_stat_mailbox);
2503
2504         err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2505                            MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2506                            MLX4_CMD_NATIVE);
2507
2508         mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2509         return err;
2510 }
2511
2512 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2513 {
2514         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2515                 return;
2516
2517         if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2518                 return;
2519
2520         __mlx4_clear_if_stat(dev, idx);
2521
2522         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
2523         return;
2524 }
2525
2526 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2527 {
2528         u64 in_param = 0;
2529
2530         if (mlx4_is_mfunc(dev)) {
2531                 set_param_l(&in_param, idx);
2532                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2533                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2534                          MLX4_CMD_WRAPPED);
2535                 return;
2536         }
2537         __mlx4_counter_free(dev, idx);
2538 }
2539 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2540
2541 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2542 {
2543         struct mlx4_priv *priv = mlx4_priv(dev);
2544
2545         return priv->def_counter[port - 1];
2546 }
2547 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2548
2549 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2550 {
2551         struct mlx4_priv *priv = mlx4_priv(dev);
2552
2553         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2554 }
2555 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2556
2557 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2558 {
2559         struct mlx4_priv *priv = mlx4_priv(dev);
2560
2561         return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2562 }
2563 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2564
2565 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2566 {
2567         struct mlx4_priv *priv = mlx4_priv(dev);
2568         __be64 guid;
2569
2570         /* hw GUID */
2571         if (entry == 0)
2572                 return;
2573
2574         get_random_bytes((char *)&guid, sizeof(guid));
2575         guid &= ~(cpu_to_be64(1ULL << 56));
2576         guid |= cpu_to_be64(1ULL << 57);
2577         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2578 }
2579
2580 static int mlx4_setup_hca(struct mlx4_dev *dev)
2581 {
2582         struct mlx4_priv *priv = mlx4_priv(dev);
2583         int err;
2584         int port;
2585         __be32 ib_port_default_caps;
2586
2587         err = mlx4_init_uar_table(dev);
2588         if (err) {
2589                 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2590                  return err;
2591         }
2592
2593         err = mlx4_uar_alloc(dev, &priv->driver_uar);
2594         if (err) {
2595                 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
2596                 goto err_uar_table_free;
2597         }
2598
2599         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2600         if (!priv->kar) {
2601                 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
2602                 err = -ENOMEM;
2603                 goto err_uar_free;
2604         }
2605
2606         err = mlx4_init_pd_table(dev);
2607         if (err) {
2608                 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
2609                 goto err_kar_unmap;
2610         }
2611
2612         err = mlx4_init_xrcd_table(dev);
2613         if (err) {
2614                 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
2615                 goto err_pd_table_free;
2616         }
2617
2618         err = mlx4_init_mr_table(dev);
2619         if (err) {
2620                 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
2621                 goto err_xrcd_table_free;
2622         }
2623
2624         if (!mlx4_is_slave(dev)) {
2625                 err = mlx4_init_mcg_table(dev);
2626                 if (err) {
2627                         mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
2628                         goto err_mr_table_free;
2629                 }
2630                 err = mlx4_config_mad_demux(dev);
2631                 if (err) {
2632                         mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2633                         goto err_mcg_table_free;
2634                 }
2635         }
2636
2637         err = mlx4_init_eq_table(dev);
2638         if (err) {
2639                 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
2640                 goto err_mcg_table_free;
2641         }
2642
2643         err = mlx4_cmd_use_events(dev);
2644         if (err) {
2645                 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
2646                 goto err_eq_table_free;
2647         }
2648
2649         err = mlx4_NOP(dev);
2650         if (err) {
2651                 if (dev->flags & MLX4_FLAG_MSI_X) {
2652                         mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2653                                   priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2654                         mlx4_warn(dev, "Trying again without MSI-X\n");
2655                 } else {
2656                         mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2657                                  priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2658                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2659                 }
2660
2661                 goto err_cmd_poll;
2662         }
2663
2664         mlx4_dbg(dev, "NOP command IRQ test passed\n");
2665
2666         err = mlx4_init_cq_table(dev);
2667         if (err) {
2668                 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
2669                 goto err_cmd_poll;
2670         }
2671
2672         err = mlx4_init_srq_table(dev);
2673         if (err) {
2674                 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
2675                 goto err_cq_table_free;
2676         }
2677
2678         err = mlx4_init_qp_table(dev);
2679         if (err) {
2680                 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
2681                 goto err_srq_table_free;
2682         }
2683
2684         if (!mlx4_is_slave(dev)) {
2685                 err = mlx4_init_counters_table(dev);
2686                 if (err && err != -ENOENT) {
2687                         mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2688                         goto err_qp_table_free;
2689                 }
2690         }
2691
2692         err = mlx4_allocate_default_counters(dev);
2693         if (err) {
2694                 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2695                 goto err_counters_table_free;
2696         }
2697
2698         if (!mlx4_is_slave(dev)) {
2699                 for (port = 1; port <= dev->caps.num_ports; port++) {
2700                         ib_port_default_caps = 0;
2701                         err = mlx4_get_port_ib_caps(dev, port,
2702                                                     &ib_port_default_caps);
2703                         if (err)
2704                                 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2705                                           port, err);
2706                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2707
2708                         /* initialize per-slave default ib port capabilities */
2709                         if (mlx4_is_master(dev)) {
2710                                 int i;
2711                                 for (i = 0; i < dev->num_slaves; i++) {
2712                                         if (i == mlx4_master_func_num(dev))
2713                                                 continue;
2714                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2715                                                 ib_port_default_caps;
2716                                 }
2717                         }
2718
2719                         if (mlx4_is_mfunc(dev))
2720                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2721                         else
2722                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2723
2724                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2725                                             dev->caps.pkey_table_len[port] : -1);
2726                         if (err) {
2727                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
2728                                          port);
2729                                 goto err_default_countes_free;
2730                         }
2731                 }
2732         }
2733
2734         return 0;
2735
2736 err_default_countes_free:
2737         mlx4_cleanup_default_counters(dev);
2738
2739 err_counters_table_free:
2740         if (!mlx4_is_slave(dev))
2741                 mlx4_cleanup_counters_table(dev);
2742
2743 err_qp_table_free:
2744         mlx4_cleanup_qp_table(dev);
2745
2746 err_srq_table_free:
2747         mlx4_cleanup_srq_table(dev);
2748
2749 err_cq_table_free:
2750         mlx4_cleanup_cq_table(dev);
2751
2752 err_cmd_poll:
2753         mlx4_cmd_use_polling(dev);
2754
2755 err_eq_table_free:
2756         mlx4_cleanup_eq_table(dev);
2757
2758 err_mcg_table_free:
2759         if (!mlx4_is_slave(dev))
2760                 mlx4_cleanup_mcg_table(dev);
2761
2762 err_mr_table_free:
2763         mlx4_cleanup_mr_table(dev);
2764
2765 err_xrcd_table_free:
2766         mlx4_cleanup_xrcd_table(dev);
2767
2768 err_pd_table_free:
2769         mlx4_cleanup_pd_table(dev);
2770
2771 err_kar_unmap:
2772         iounmap(priv->kar);
2773
2774 err_uar_free:
2775         mlx4_uar_free(dev, &priv->driver_uar);
2776
2777 err_uar_table_free:
2778         mlx4_cleanup_uar_table(dev);
2779         return err;
2780 }
2781
2782 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2783 {
2784         int requested_cpu = 0;
2785         struct mlx4_priv *priv = mlx4_priv(dev);
2786         struct mlx4_eq *eq;
2787         int off = 0;
2788         int i;
2789
2790         if (eqn > dev->caps.num_comp_vectors)
2791                 return -EINVAL;
2792
2793         for (i = 1; i < port; i++)
2794                 off += mlx4_get_eqs_per_port(dev, i);
2795
2796         requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2797
2798         /* Meaning EQs are shared, and this call comes from the second port */
2799         if (requested_cpu < 0)
2800                 return 0;
2801
2802         eq = &priv->eq_table.eq[eqn];
2803
2804         if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2805                 return -ENOMEM;
2806
2807         cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2808
2809         return 0;
2810 }
2811
2812 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2813 {
2814         struct mlx4_priv *priv = mlx4_priv(dev);
2815         struct msix_entry *entries;
2816         int i;
2817         int port = 0;
2818
2819         if (msi_x) {
2820                 int nreq = dev->caps.num_ports * num_online_cpus() + 1;
2821
2822                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2823                              nreq);
2824                 if (nreq > MAX_MSIX)
2825                         nreq = MAX_MSIX;
2826
2827                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2828                 if (!entries)
2829                         goto no_msi;
2830
2831                 for (i = 0; i < nreq; ++i)
2832                         entries[i].entry = i;
2833
2834                 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2835                                              nreq);
2836
2837                 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
2838                         kfree(entries);
2839                         goto no_msi;
2840                 }
2841                 /* 1 is reserved for events (asyncrounous EQ) */
2842                 dev->caps.num_comp_vectors = nreq - 1;
2843
2844                 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2845                 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2846                             dev->caps.num_ports);
2847
2848                 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2849                         if (i == MLX4_EQ_ASYNC)
2850                                 continue;
2851
2852                         priv->eq_table.eq[i].irq =
2853                                 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2854
2855                         if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
2856                                 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2857                                             dev->caps.num_ports);
2858                                 /* We don't set affinity hint when there
2859                                  * aren't enough EQs
2860                                  */
2861                         } else {
2862                                 set_bit(port,
2863                                         priv->eq_table.eq[i].actv_ports.ports);
2864                                 if (mlx4_init_affinity_hint(dev, port + 1, i))
2865                                         mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2866                                                   i);
2867                         }
2868                         /* We divide the Eqs evenly between the two ports.
2869                          * (dev->caps.num_comp_vectors / dev->caps.num_ports)
2870                          * refers to the number of Eqs per port
2871                          * (i.e eqs_per_port). Theoretically, we would like to
2872                          * write something like (i + 1) % eqs_per_port == 0.
2873                          * However, since there's an asynchronous Eq, we have
2874                          * to skip over it by comparing this condition to
2875                          * !!((i + 1) > MLX4_EQ_ASYNC).
2876                          */
2877                         if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2878                             ((i + 1) %
2879                              (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2880                             !!((i + 1) > MLX4_EQ_ASYNC))
2881                                 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
2882                                  * everything is shared anyway.
2883                                  */
2884                                 port++;
2885                 }
2886
2887                 dev->flags |= MLX4_FLAG_MSI_X;
2888
2889                 kfree(entries);
2890                 return;
2891         }
2892
2893 no_msi:
2894         dev->caps.num_comp_vectors = 1;
2895
2896         BUG_ON(MLX4_EQ_ASYNC >= 2);
2897         for (i = 0; i < 2; ++i) {
2898                 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
2899                 if (i != MLX4_EQ_ASYNC) {
2900                         bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2901                                     dev->caps.num_ports);
2902                 }
2903         }
2904 }
2905
2906 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2907 {
2908         struct devlink *devlink = priv_to_devlink(mlx4_priv(dev));
2909         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2910         int err;
2911
2912         err = devlink_port_register(devlink, &info->devlink_port, port);
2913         if (err)
2914                 return err;
2915
2916         info->dev = dev;
2917         info->port = port;
2918         if (!mlx4_is_slave(dev)) {
2919                 mlx4_init_mac_table(dev, &info->mac_table);
2920                 mlx4_init_vlan_table(dev, &info->vlan_table);
2921                 mlx4_init_roce_gid_table(dev, &info->gid_table);
2922                 info->base_qpn = mlx4_get_base_qpn(dev, port);
2923         }
2924
2925         sprintf(info->dev_name, "mlx4_port%d", port);
2926         info->port_attr.attr.name = info->dev_name;
2927         if (mlx4_is_mfunc(dev))
2928                 info->port_attr.attr.mode = S_IRUGO;
2929         else {
2930                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2931                 info->port_attr.store     = set_port_type;
2932         }
2933         info->port_attr.show      = show_port_type;
2934         sysfs_attr_init(&info->port_attr.attr);
2935
2936         err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
2937         if (err) {
2938                 mlx4_err(dev, "Failed to create file for port %d\n", port);
2939                 devlink_port_unregister(&info->devlink_port);
2940                 info->port = -1;
2941         }
2942
2943         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2944         info->port_mtu_attr.attr.name = info->dev_mtu_name;
2945         if (mlx4_is_mfunc(dev))
2946                 info->port_mtu_attr.attr.mode = S_IRUGO;
2947         else {
2948                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2949                 info->port_mtu_attr.store     = set_port_ib_mtu;
2950         }
2951         info->port_mtu_attr.show      = show_port_ib_mtu;
2952         sysfs_attr_init(&info->port_mtu_attr.attr);
2953
2954         err = device_create_file(&dev->persist->pdev->dev,
2955                                  &info->port_mtu_attr);
2956         if (err) {
2957                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2958                 device_remove_file(&info->dev->persist->pdev->dev,
2959                                    &info->port_attr);
2960                 info->port = -1;
2961         }
2962
2963         return err;
2964 }
2965
2966 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2967 {
2968         if (info->port < 0)
2969                 return;
2970
2971         device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2972         device_remove_file(&info->dev->persist->pdev->dev,
2973                            &info->port_mtu_attr);
2974 #ifdef CONFIG_RFS_ACCEL
2975         free_irq_cpu_rmap(info->rmap);
2976         info->rmap = NULL;
2977 #endif
2978 }
2979
2980 static int mlx4_init_steering(struct mlx4_dev *dev)
2981 {
2982         struct mlx4_priv *priv = mlx4_priv(dev);
2983         int num_entries = dev->caps.num_ports;
2984         int i, j;
2985
2986         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2987         if (!priv->steer)
2988                 return -ENOMEM;
2989
2990         for (i = 0; i < num_entries; i++)
2991                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2992                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2993                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2994                 }
2995         return 0;
2996 }
2997
2998 static void mlx4_clear_steering(struct mlx4_dev *dev)
2999 {
3000         struct mlx4_priv *priv = mlx4_priv(dev);
3001         struct mlx4_steer_index *entry, *tmp_entry;
3002         struct mlx4_promisc_qp *pqp, *tmp_pqp;
3003         int num_entries = dev->caps.num_ports;
3004         int i, j;
3005
3006         for (i = 0; i < num_entries; i++) {
3007                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3008                         list_for_each_entry_safe(pqp, tmp_pqp,
3009                                                  &priv->steer[i].promisc_qps[j],
3010                                                  list) {
3011                                 list_del(&pqp->list);
3012                                 kfree(pqp);
3013                         }
3014                         list_for_each_entry_safe(entry, tmp_entry,
3015                                                  &priv->steer[i].steer_entries[j],
3016                                                  list) {
3017                                 list_del(&entry->list);
3018                                 list_for_each_entry_safe(pqp, tmp_pqp,
3019                                                          &entry->duplicates,
3020                                                          list) {
3021                                         list_del(&pqp->list);
3022                                         kfree(pqp);
3023                                 }
3024                                 kfree(entry);
3025                         }
3026                 }
3027         }
3028         kfree(priv->steer);
3029 }
3030
3031 static int extended_func_num(struct pci_dev *pdev)
3032 {
3033         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3034 }
3035
3036 #define MLX4_OWNER_BASE 0x8069c
3037 #define MLX4_OWNER_SIZE 4
3038
3039 static int mlx4_get_ownership(struct mlx4_dev *dev)
3040 {
3041         void __iomem *owner;
3042         u32 ret;
3043
3044         if (pci_channel_offline(dev->persist->pdev))
3045                 return -EIO;
3046
3047         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3048                         MLX4_OWNER_BASE,
3049                         MLX4_OWNER_SIZE);
3050         if (!owner) {
3051                 mlx4_err(dev, "Failed to obtain ownership bit\n");
3052                 return -ENOMEM;
3053         }
3054
3055         ret = readl(owner);
3056         iounmap(owner);
3057         return (int) !!ret;
3058 }
3059
3060 static void mlx4_free_ownership(struct mlx4_dev *dev)
3061 {
3062         void __iomem *owner;
3063
3064         if (pci_channel_offline(dev->persist->pdev))
3065                 return;
3066
3067         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3068                         MLX4_OWNER_BASE,
3069                         MLX4_OWNER_SIZE);
3070         if (!owner) {
3071                 mlx4_err(dev, "Failed to obtain ownership bit\n");
3072                 return;
3073         }
3074         writel(0, owner);
3075         msleep(1000);
3076         iounmap(owner);
3077 }
3078
3079 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
3080                                   !!((flags) & MLX4_FLAG_MASTER))
3081
3082 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
3083                              u8 total_vfs, int existing_vfs, int reset_flow)
3084 {
3085         u64 dev_flags = dev->flags;
3086         int err = 0;
3087         int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
3088                                         MLX4_MAX_NUM_VF);
3089
3090         if (reset_flow) {
3091                 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
3092                                        GFP_KERNEL);
3093                 if (!dev->dev_vfs)
3094                         goto free_mem;
3095                 return dev_flags;
3096         }
3097
3098         atomic_inc(&pf_loading);
3099         if (dev->flags &  MLX4_FLAG_SRIOV) {
3100                 if (existing_vfs != total_vfs) {
3101                         mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
3102                                  existing_vfs, total_vfs);
3103                         total_vfs = existing_vfs;
3104                 }
3105         }
3106
3107         dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
3108         if (NULL == dev->dev_vfs) {
3109                 mlx4_err(dev, "Failed to allocate memory for VFs\n");
3110                 goto disable_sriov;
3111         }
3112
3113         if (!(dev->flags &  MLX4_FLAG_SRIOV)) {
3114                 if (total_vfs > fw_enabled_sriov_vfs) {
3115                         mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
3116                                  total_vfs, fw_enabled_sriov_vfs);
3117                         err = -ENOMEM;
3118                         goto disable_sriov;
3119                 }
3120                 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
3121                 err = pci_enable_sriov(pdev, total_vfs);
3122         }
3123         if (err) {
3124                 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
3125                          err);
3126                 goto disable_sriov;
3127         } else {
3128                 mlx4_warn(dev, "Running in master mode\n");
3129                 dev_flags |= MLX4_FLAG_SRIOV |
3130                         MLX4_FLAG_MASTER;
3131                 dev_flags &= ~MLX4_FLAG_SLAVE;
3132                 dev->persist->num_vfs = total_vfs;
3133         }
3134         return dev_flags;
3135
3136 disable_sriov:
3137         atomic_dec(&pf_loading);
3138 free_mem:
3139         dev->persist->num_vfs = 0;
3140         kfree(dev->dev_vfs);
3141         dev->dev_vfs = NULL;
3142         return dev_flags & ~MLX4_FLAG_MASTER;
3143 }
3144
3145 enum {
3146         MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3147 };
3148
3149 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3150                               int *nvfs)
3151 {
3152         int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3153         /* Checking for 64 VFs as a limitation of CX2 */
3154         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3155             requested_vfs >= 64) {
3156                 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3157                          requested_vfs);
3158                 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3159         }
3160         return 0;
3161 }
3162
3163 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
3164                          int total_vfs, int *nvfs, struct mlx4_priv *priv,
3165                          int reset_flow)
3166 {
3167         struct mlx4_dev *dev;
3168         unsigned sum = 0;
3169         int err;
3170         int port;
3171         int i;
3172         struct mlx4_dev_cap *dev_cap = NULL;
3173         int existing_vfs = 0;
3174
3175         dev = &priv->dev;
3176
3177         INIT_LIST_HEAD(&priv->ctx_list);
3178         spin_lock_init(&priv->ctx_lock);
3179
3180         mutex_init(&priv->port_mutex);
3181         mutex_init(&priv->bond_mutex);
3182
3183         INIT_LIST_HEAD(&priv->pgdir_list);
3184         mutex_init(&priv->pgdir_mutex);
3185
3186         INIT_LIST_HEAD(&priv->bf_list);
3187         mutex_init(&priv->bf_mutex);
3188
3189         dev->rev_id = pdev->revision;
3190         dev->numa_node = dev_to_node(&pdev->dev);
3191
3192         /* Detect if this device is a virtual function */
3193         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3194                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3195                 dev->flags |= MLX4_FLAG_SLAVE;
3196         } else {
3197                 /* We reset the device and enable SRIOV only for physical
3198                  * devices.  Try to claim ownership on the device;
3199                  * if already taken, skip -- do not allow multiple PFs */
3200                 err = mlx4_get_ownership(dev);
3201                 if (err) {
3202                         if (err < 0)
3203                                 return err;
3204                         else {
3205                                 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
3206                                 return -EINVAL;
3207                         }
3208                 }
3209
3210                 atomic_set(&priv->opreq_count, 0);
3211                 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3212
3213                 /*
3214                  * Now reset the HCA before we touch the PCI capabilities or
3215                  * attempt a firmware command, since a boot ROM may have left
3216                  * the HCA in an undefined state.
3217                  */
3218                 err = mlx4_reset(dev);
3219                 if (err) {
3220                         mlx4_err(dev, "Failed to reset HCA, aborting\n");
3221                         goto err_sriov;
3222                 }
3223
3224                 if (total_vfs) {
3225                         dev->flags = MLX4_FLAG_MASTER;
3226                         existing_vfs = pci_num_vf(pdev);
3227                         if (existing_vfs)
3228                                 dev->flags |= MLX4_FLAG_SRIOV;
3229                         dev->persist->num_vfs = total_vfs;
3230                 }
3231         }
3232
3233         /* on load remove any previous indication of internal error,
3234          * device is up.
3235          */
3236         dev->persist->state = MLX4_DEVICE_STATE_UP;
3237
3238 slave_start:
3239         err = mlx4_cmd_init(dev);
3240         if (err) {
3241                 mlx4_err(dev, "Failed to init command interface, aborting\n");
3242                 goto err_sriov;
3243         }
3244
3245         /* In slave functions, the communication channel must be initialized
3246          * before posting commands. Also, init num_slaves before calling
3247          * mlx4_init_hca */
3248         if (mlx4_is_mfunc(dev)) {
3249                 if (mlx4_is_master(dev)) {
3250                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
3251
3252                 } else {
3253                         dev->num_slaves = 0;
3254                         err = mlx4_multi_func_init(dev);
3255                         if (err) {
3256                                 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
3257                                 goto err_cmd;
3258                         }
3259                 }
3260         }
3261
3262         err = mlx4_init_fw(dev);
3263         if (err) {
3264                 mlx4_err(dev, "Failed to init fw, aborting.\n");
3265                 goto err_mfunc;
3266         }
3267
3268         if (mlx4_is_master(dev)) {
3269                 /* when we hit the goto slave_start below, dev_cap already initialized */
3270                 if (!dev_cap) {
3271                         dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3272
3273                         if (!dev_cap) {
3274                                 err = -ENOMEM;
3275                                 goto err_fw;
3276                         }
3277
3278                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3279                         if (err) {
3280                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3281                                 goto err_fw;
3282                         }
3283
3284                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3285                                 goto err_fw;
3286
3287                         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3288                                 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3289                                                                   total_vfs,
3290                                                                   existing_vfs,
3291                                                                   reset_flow);
3292
3293                                 mlx4_close_fw(dev);
3294                                 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3295                                 dev->flags = dev_flags;
3296                                 if (!SRIOV_VALID_STATE(dev->flags)) {
3297                                         mlx4_err(dev, "Invalid SRIOV state\n");
3298                                         goto err_sriov;
3299                                 }
3300                                 err = mlx4_reset(dev);
3301                                 if (err) {
3302                                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3303                                         goto err_sriov;
3304                                 }
3305                                 goto slave_start;
3306                         }
3307                 } else {
3308                         /* Legacy mode FW requires SRIOV to be enabled before
3309                          * doing QUERY_DEV_CAP, since max_eq's value is different if
3310                          * SRIOV is enabled.
3311                          */
3312                         memset(dev_cap, 0, sizeof(*dev_cap));
3313                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3314                         if (err) {
3315                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3316                                 goto err_fw;
3317                         }
3318
3319                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3320                                 goto err_fw;
3321                 }
3322         }
3323
3324         err = mlx4_init_hca(dev);
3325         if (err) {
3326                 if (err == -EACCES) {
3327                         /* Not primary Physical function
3328                          * Running in slave mode */
3329                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3330                         /* We're not a PF */
3331                         if (dev->flags & MLX4_FLAG_SRIOV) {
3332                                 if (!existing_vfs)
3333                                         pci_disable_sriov(pdev);
3334                                 if (mlx4_is_master(dev) && !reset_flow)
3335                                         atomic_dec(&pf_loading);
3336                                 dev->flags &= ~MLX4_FLAG_SRIOV;
3337                         }
3338                         if (!mlx4_is_slave(dev))
3339                                 mlx4_free_ownership(dev);
3340                         dev->flags |= MLX4_FLAG_SLAVE;
3341                         dev->flags &= ~MLX4_FLAG_MASTER;
3342                         goto slave_start;
3343                 } else
3344                         goto err_fw;
3345         }
3346
3347         if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3348                 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3349                                                   existing_vfs, reset_flow);
3350
3351                 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3352                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3353                         dev->flags = dev_flags;
3354                         err = mlx4_cmd_init(dev);
3355                         if (err) {
3356                                 /* Only VHCR is cleaned up, so could still
3357                                  * send FW commands
3358                                  */
3359                                 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3360                                 goto err_close;
3361                         }
3362                 } else {
3363                         dev->flags = dev_flags;
3364                 }
3365
3366                 if (!SRIOV_VALID_STATE(dev->flags)) {
3367                         mlx4_err(dev, "Invalid SRIOV state\n");
3368                         goto err_close;
3369                 }
3370         }
3371
3372         /* check if the device is functioning at its maximum possible speed.
3373          * No return code for this call, just warn the user in case of PCI
3374          * express device capabilities are under-satisfied by the bus.
3375          */
3376         if (!mlx4_is_slave(dev))
3377                 mlx4_check_pcie_caps(dev);
3378
3379         /* In master functions, the communication channel must be initialized
3380          * after obtaining its address from fw */
3381         if (mlx4_is_master(dev)) {
3382                 if (dev->caps.num_ports < 2 &&
3383                     num_vfs_argc > 1) {
3384                         err = -EINVAL;
3385                         mlx4_err(dev,
3386                                  "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3387                                  dev->caps.num_ports);
3388                         goto err_close;
3389                 }
3390                 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
3391
3392                 for (i = 0;
3393                      i < sizeof(dev->persist->nvfs)/
3394                      sizeof(dev->persist->nvfs[0]); i++) {
3395                         unsigned j;
3396
3397                         for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
3398                                 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3399                                 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3400                                         dev->caps.num_ports;
3401                         }
3402                 }
3403
3404                 /* In master functions, the communication channel
3405                  * must be initialized after obtaining its address from fw
3406                  */
3407                 err = mlx4_multi_func_init(dev);
3408                 if (err) {
3409                         mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3410                         goto err_close;
3411                 }
3412         }
3413
3414         err = mlx4_alloc_eq_table(dev);
3415         if (err)
3416                 goto err_master_mfunc;
3417
3418         bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
3419         mutex_init(&priv->msix_ctl.pool_lock);
3420
3421         mlx4_enable_msi_x(dev);
3422         if ((mlx4_is_mfunc(dev)) &&
3423             !(dev->flags & MLX4_FLAG_MSI_X)) {
3424                 err = -ENOSYS;
3425                 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
3426                 goto err_free_eq;
3427         }
3428
3429         if (!mlx4_is_slave(dev)) {
3430                 err = mlx4_init_steering(dev);
3431                 if (err)
3432                         goto err_disable_msix;
3433         }
3434
3435         err = mlx4_setup_hca(dev);
3436         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3437             !mlx4_is_mfunc(dev)) {
3438                 dev->flags &= ~MLX4_FLAG_MSI_X;
3439                 dev->caps.num_comp_vectors = 1;
3440                 pci_disable_msix(pdev);
3441                 err = mlx4_setup_hca(dev);
3442         }
3443
3444         if (err)
3445                 goto err_steer;
3446
3447         mlx4_init_quotas(dev);
3448         /* When PF resources are ready arm its comm channel to enable
3449          * getting commands
3450          */
3451         if (mlx4_is_master(dev)) {
3452                 err = mlx4_ARM_COMM_CHANNEL(dev);
3453                 if (err) {
3454                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3455                                  err);
3456                         goto err_steer;
3457                 }
3458         }
3459
3460         for (port = 1; port <= dev->caps.num_ports; port++) {
3461                 err = mlx4_init_port_info(dev, port);
3462                 if (err)
3463                         goto err_port;
3464         }
3465
3466         priv->v2p.port1 = 1;
3467         priv->v2p.port2 = 2;
3468
3469         err = mlx4_register_device(dev);
3470         if (err)
3471                 goto err_port;
3472
3473         mlx4_request_modules(dev);
3474
3475         mlx4_sense_init(dev);
3476         mlx4_start_sense(dev);
3477
3478         priv->removed = 0;
3479
3480         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3481                 atomic_dec(&pf_loading);
3482
3483         kfree(dev_cap);
3484         return 0;
3485
3486 err_port:
3487         for (--port; port >= 1; --port)
3488                 mlx4_cleanup_port_info(&priv->port[port]);
3489
3490         mlx4_cleanup_default_counters(dev);
3491         if (!mlx4_is_slave(dev))
3492                 mlx4_cleanup_counters_table(dev);
3493         mlx4_cleanup_qp_table(dev);
3494         mlx4_cleanup_srq_table(dev);
3495         mlx4_cleanup_cq_table(dev);
3496         mlx4_cmd_use_polling(dev);
3497         mlx4_cleanup_eq_table(dev);
3498         mlx4_cleanup_mcg_table(dev);
3499         mlx4_cleanup_mr_table(dev);
3500         mlx4_cleanup_xrcd_table(dev);
3501         mlx4_cleanup_pd_table(dev);
3502         mlx4_cleanup_uar_table(dev);
3503
3504 err_steer:
3505         if (!mlx4_is_slave(dev))
3506                 mlx4_clear_steering(dev);
3507
3508 err_disable_msix:
3509         if (dev->flags & MLX4_FLAG_MSI_X)
3510                 pci_disable_msix(pdev);
3511
3512 err_free_eq:
3513         mlx4_free_eq_table(dev);
3514
3515 err_master_mfunc:
3516         if (mlx4_is_master(dev)) {
3517                 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
3518                 mlx4_multi_func_cleanup(dev);
3519         }
3520
3521         if (mlx4_is_slave(dev)) {
3522                 kfree(dev->caps.qp0_qkey);
3523                 kfree(dev->caps.qp0_tunnel);
3524                 kfree(dev->caps.qp0_proxy);
3525                 kfree(dev->caps.qp1_tunnel);
3526                 kfree(dev->caps.qp1_proxy);
3527         }
3528
3529 err_close:
3530         mlx4_close_hca(dev);
3531
3532 err_fw:
3533         mlx4_close_fw(dev);
3534
3535 err_mfunc:
3536         if (mlx4_is_slave(dev))
3537                 mlx4_multi_func_cleanup(dev);
3538
3539 err_cmd:
3540         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3541
3542 err_sriov:
3543         if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
3544                 pci_disable_sriov(pdev);
3545                 dev->flags &= ~MLX4_FLAG_SRIOV;
3546         }
3547
3548         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3549                 atomic_dec(&pf_loading);
3550
3551         kfree(priv->dev.dev_vfs);
3552
3553         if (!mlx4_is_slave(dev))
3554                 mlx4_free_ownership(dev);
3555
3556         kfree(dev_cap);
3557         return err;
3558 }
3559
3560 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3561                            struct mlx4_priv *priv)
3562 {
3563         int err;
3564         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3565         int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3566         const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3567                 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3568         unsigned total_vfs = 0;
3569         unsigned int i;
3570
3571         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3572
3573         err = pci_enable_device(pdev);
3574         if (err) {
3575                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3576                 return err;
3577         }
3578
3579         /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3580          * per port, we must limit the number of VFs to 63 (since their are
3581          * 128 MACs)
3582          */
3583         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
3584              total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3585                 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3586                 if (nvfs[i] < 0) {
3587                         dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3588                         err = -EINVAL;
3589                         goto err_disable_pdev;
3590                 }
3591         }
3592         for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
3593              i++) {
3594                 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3595                 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3596                         dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3597                         err = -EINVAL;
3598                         goto err_disable_pdev;
3599                 }
3600         }
3601         if (total_vfs > MLX4_MAX_NUM_VF) {
3602                 dev_err(&pdev->dev,
3603                         "Requested more VF's (%d) than allowed by hw (%d)\n",
3604                         total_vfs, MLX4_MAX_NUM_VF);
3605                 err = -EINVAL;
3606                 goto err_disable_pdev;
3607         }
3608
3609         for (i = 0; i < MLX4_MAX_PORTS; i++) {
3610                 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
3611                         dev_err(&pdev->dev,
3612                                 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
3613                                 nvfs[i] + nvfs[2], i + 1,
3614                                 MLX4_MAX_NUM_VF_P_PORT);
3615                         err = -EINVAL;
3616                         goto err_disable_pdev;
3617                 }
3618         }
3619
3620         /* Check for BARs. */
3621         if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3622             !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3623                 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3624                         pci_dev_data, pci_resource_flags(pdev, 0));
3625                 err = -ENODEV;
3626                 goto err_disable_pdev;
3627         }
3628         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3629                 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3630                 err = -ENODEV;
3631                 goto err_disable_pdev;
3632         }
3633
3634         err = pci_request_regions(pdev, DRV_NAME);
3635         if (err) {
3636                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3637                 goto err_disable_pdev;
3638         }
3639
3640         pci_set_master(pdev);
3641
3642         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3643         if (err) {
3644                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3645                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3646                 if (err) {
3647                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3648                         goto err_release_regions;
3649                 }
3650         }
3651         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3652         if (err) {
3653                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3654                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3655                 if (err) {
3656                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3657                         goto err_release_regions;
3658                 }
3659         }
3660
3661         /* Allow large DMA segments, up to the firmware limit of 1 GB */
3662         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3663         /* Detect if this device is a virtual function */
3664         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3665                 /* When acting as pf, we normally skip vfs unless explicitly
3666                  * requested to probe them.
3667                  */
3668                 if (total_vfs) {
3669                         unsigned vfs_offset = 0;
3670
3671                         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3672                              vfs_offset + nvfs[i] < extended_func_num(pdev);
3673                              vfs_offset += nvfs[i], i++)
3674                                 ;
3675                         if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3676                                 err = -ENODEV;
3677                                 goto err_release_regions;
3678                         }
3679                         if ((extended_func_num(pdev) - vfs_offset)
3680                             > prb_vf[i]) {
3681                                 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3682                                          extended_func_num(pdev));
3683                                 err = -ENODEV;
3684                                 goto err_release_regions;
3685                         }
3686                 }
3687         }
3688
3689         err = mlx4_catas_init(&priv->dev);
3690         if (err)
3691                 goto err_release_regions;
3692
3693         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
3694         if (err)
3695                 goto err_catas;
3696
3697         return 0;
3698
3699 err_catas:
3700         mlx4_catas_end(&priv->dev);
3701
3702 err_release_regions:
3703         pci_release_regions(pdev);
3704
3705 err_disable_pdev:
3706         pci_disable_device(pdev);
3707         pci_set_drvdata(pdev, NULL);
3708         return err;
3709 }
3710
3711 static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port,
3712                                       enum devlink_port_type port_type)
3713 {
3714         struct mlx4_port_info *info = container_of(devlink_port,
3715                                                    struct mlx4_port_info,
3716                                                    devlink_port);
3717         enum mlx4_port_type mlx4_port_type;
3718
3719         switch (port_type) {
3720         case DEVLINK_PORT_TYPE_AUTO:
3721                 mlx4_port_type = MLX4_PORT_TYPE_AUTO;
3722                 break;
3723         case DEVLINK_PORT_TYPE_ETH:
3724                 mlx4_port_type = MLX4_PORT_TYPE_ETH;
3725                 break;
3726         case DEVLINK_PORT_TYPE_IB:
3727                 mlx4_port_type = MLX4_PORT_TYPE_IB;
3728                 break;
3729         default:
3730                 return -EOPNOTSUPP;
3731         }
3732
3733         return __set_port_type(info, mlx4_port_type);
3734 }
3735
3736 static const struct devlink_ops mlx4_devlink_ops = {
3737         .port_type_set  = mlx4_devlink_port_type_set,
3738 };
3739
3740 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3741 {
3742         struct devlink *devlink;
3743         struct mlx4_priv *priv;
3744         struct mlx4_dev *dev;
3745         int ret;
3746
3747         printk_once(KERN_INFO "%s", mlx4_version);
3748
3749         devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv));
3750         if (!devlink)
3751                 return -ENOMEM;
3752         priv = devlink_priv(devlink);
3753
3754         dev       = &priv->dev;
3755         dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3756         if (!dev->persist) {
3757                 ret = -ENOMEM;
3758                 goto err_devlink_free;
3759         }
3760         dev->persist->pdev = pdev;
3761         dev->persist->dev = dev;
3762         pci_set_drvdata(pdev, dev->persist);
3763         priv->pci_dev_data = id->driver_data;
3764         mutex_init(&dev->persist->device_state_mutex);
3765         mutex_init(&dev->persist->interface_state_mutex);
3766
3767         ret = devlink_register(devlink, &pdev->dev);
3768         if (ret)
3769                 goto err_persist_free;
3770
3771         ret =  __mlx4_init_one(pdev, id->driver_data, priv);
3772         if (ret)
3773                 goto err_devlink_unregister;
3774
3775         pci_save_state(pdev);
3776         return 0;
3777
3778 err_devlink_unregister:
3779         devlink_unregister(devlink);
3780 err_persist_free:
3781         kfree(dev->persist);
3782 err_devlink_free:
3783         devlink_free(devlink);
3784         return ret;
3785 }
3786
3787 static void mlx4_clean_dev(struct mlx4_dev *dev)
3788 {
3789         struct mlx4_dev_persistent *persist = dev->persist;
3790         struct mlx4_priv *priv = mlx4_priv(dev);
3791         unsigned long   flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
3792
3793         memset(priv, 0, sizeof(*priv));
3794         priv->dev.persist = persist;
3795         priv->dev.flags = flags;
3796 }
3797
3798 static void mlx4_unload_one(struct pci_dev *pdev)
3799 {
3800         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3801         struct mlx4_dev  *dev  = persist->dev;
3802         struct mlx4_priv *priv = mlx4_priv(dev);
3803         int               pci_dev_data;
3804         int p, i;
3805
3806         if (priv->removed)
3807                 return;
3808
3809         /* saving current ports type for further use */
3810         for (i = 0; i < dev->caps.num_ports; i++) {
3811                 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3812                 dev->persist->curr_port_poss_type[i] = dev->caps.
3813                                                        possible_type[i + 1];
3814         }
3815
3816         pci_dev_data = priv->pci_dev_data;
3817
3818         mlx4_stop_sense(dev);
3819         mlx4_unregister_device(dev);
3820
3821         for (p = 1; p <= dev->caps.num_ports; p++) {
3822                 mlx4_cleanup_port_info(&priv->port[p]);
3823                 mlx4_CLOSE_PORT(dev, p);
3824         }
3825
3826         if (mlx4_is_master(dev))
3827                 mlx4_free_resource_tracker(dev,
3828                                            RES_TR_FREE_SLAVES_ONLY);
3829
3830         mlx4_cleanup_default_counters(dev);
3831         if (!mlx4_is_slave(dev))
3832                 mlx4_cleanup_counters_table(dev);
3833         mlx4_cleanup_qp_table(dev);
3834         mlx4_cleanup_srq_table(dev);
3835         mlx4_cleanup_cq_table(dev);
3836         mlx4_cmd_use_polling(dev);
3837         mlx4_cleanup_eq_table(dev);
3838         mlx4_cleanup_mcg_table(dev);
3839         mlx4_cleanup_mr_table(dev);
3840         mlx4_cleanup_xrcd_table(dev);
3841         mlx4_cleanup_pd_table(dev);
3842
3843         if (mlx4_is_master(dev))
3844                 mlx4_free_resource_tracker(dev,
3845                                            RES_TR_FREE_STRUCTS_ONLY);
3846
3847         iounmap(priv->kar);
3848         mlx4_uar_free(dev, &priv->driver_uar);
3849         mlx4_cleanup_uar_table(dev);
3850         if (!mlx4_is_slave(dev))
3851                 mlx4_clear_steering(dev);
3852         mlx4_free_eq_table(dev);
3853         if (mlx4_is_master(dev))
3854                 mlx4_multi_func_cleanup(dev);
3855         mlx4_close_hca(dev);
3856         mlx4_close_fw(dev);
3857         if (mlx4_is_slave(dev))
3858                 mlx4_multi_func_cleanup(dev);
3859         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3860
3861         if (dev->flags & MLX4_FLAG_MSI_X)
3862                 pci_disable_msix(pdev);
3863
3864         if (!mlx4_is_slave(dev))
3865                 mlx4_free_ownership(dev);
3866
3867         kfree(dev->caps.qp0_qkey);
3868         kfree(dev->caps.qp0_tunnel);
3869         kfree(dev->caps.qp0_proxy);
3870         kfree(dev->caps.qp1_tunnel);
3871         kfree(dev->caps.qp1_proxy);
3872         kfree(dev->dev_vfs);
3873
3874         mlx4_clean_dev(dev);
3875         priv->pci_dev_data = pci_dev_data;
3876         priv->removed = 1;
3877 }
3878
3879 static void mlx4_remove_one(struct pci_dev *pdev)
3880 {
3881         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3882         struct mlx4_dev  *dev  = persist->dev;
3883         struct mlx4_priv *priv = mlx4_priv(dev);
3884         struct devlink *devlink = priv_to_devlink(priv);
3885         int active_vfs = 0;
3886
3887         mutex_lock(&persist->interface_state_mutex);
3888         persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3889         mutex_unlock(&persist->interface_state_mutex);
3890
3891         /* Disabling SR-IOV is not allowed while there are active vf's */
3892         if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3893                 active_vfs = mlx4_how_many_lives_vf(dev);
3894                 if (active_vfs) {
3895                         pr_warn("Removing PF when there are active VF's !!\n");
3896                         pr_warn("Will not disable SR-IOV.\n");
3897                 }
3898         }
3899
3900         /* device marked to be under deletion running now without the lock
3901          * letting other tasks to be terminated
3902          */
3903         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3904                 mlx4_unload_one(pdev);
3905         else
3906                 mlx4_info(dev, "%s: interface is down\n", __func__);
3907         mlx4_catas_end(dev);
3908         if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3909                 mlx4_warn(dev, "Disabling SR-IOV\n");
3910                 pci_disable_sriov(pdev);
3911         }
3912
3913         pci_release_regions(pdev);
3914         pci_disable_device(pdev);
3915         devlink_unregister(devlink);
3916         kfree(dev->persist);
3917         devlink_free(devlink);
3918         pci_set_drvdata(pdev, NULL);
3919 }
3920
3921 static int restore_current_port_types(struct mlx4_dev *dev,
3922                                       enum mlx4_port_type *types,
3923                                       enum mlx4_port_type *poss_types)
3924 {
3925         struct mlx4_priv *priv = mlx4_priv(dev);
3926         int err, i;
3927
3928         mlx4_stop_sense(dev);
3929
3930         mutex_lock(&priv->port_mutex);
3931         for (i = 0; i < dev->caps.num_ports; i++)
3932                 dev->caps.possible_type[i + 1] = poss_types[i];
3933         err = mlx4_change_port_types(dev, types);
3934         mlx4_start_sense(dev);
3935         mutex_unlock(&priv->port_mutex);
3936
3937         return err;
3938 }
3939
3940 int mlx4_restart_one(struct pci_dev *pdev)
3941 {
3942         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3943         struct mlx4_dev  *dev  = persist->dev;
3944         struct mlx4_priv *priv = mlx4_priv(dev);
3945         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3946         int pci_dev_data, err, total_vfs;
3947
3948         pci_dev_data = priv->pci_dev_data;
3949         total_vfs = dev->persist->num_vfs;
3950         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
3951
3952         mlx4_unload_one(pdev);
3953         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
3954         if (err) {
3955                 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3956                          __func__, pci_name(pdev), err);
3957                 return err;
3958         }
3959
3960         err = restore_current_port_types(dev, dev->persist->curr_port_type,
3961                                          dev->persist->curr_port_poss_type);
3962         if (err)
3963                 mlx4_err(dev, "could not restore original port types (%d)\n",
3964                          err);
3965
3966         return err;
3967 }
3968
3969 static const struct pci_device_id mlx4_pci_table[] = {
3970         /* MT25408 "Hermon" SDR */
3971         { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3972         /* MT25408 "Hermon" DDR */
3973         { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3974         /* MT25408 "Hermon" QDR */
3975         { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3976         /* MT25408 "Hermon" DDR PCIe gen2 */
3977         { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3978         /* MT25408 "Hermon" QDR PCIe gen2 */
3979         { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3980         /* MT25408 "Hermon" EN 10GigE */
3981         { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3982         /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
3983         { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3984         /* MT25458 ConnectX EN 10GBASE-T 10GigE */
3985         { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3986         /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
3987         { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3988         /* MT26468 ConnectX EN 10GigE PCIe gen2*/
3989         { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3990         /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
3991         { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3992         /* MT26478 ConnectX2 40GigE PCIe gen2 */
3993         { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3994         /* MT25400 Family [ConnectX-2 Virtual Function] */
3995         { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
3996         /* MT27500 Family [ConnectX-3] */
3997         { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3998         /* MT27500 Family [ConnectX-3 Virtual Function] */
3999         { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
4000         { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
4001         { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
4002         { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
4003         { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
4004         { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
4005         { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
4006         { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
4007         { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
4008         { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
4009         { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
4010         { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
4011         { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
4012         { 0, }
4013 };
4014
4015 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
4016
4017 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
4018                                               pci_channel_state_t state)
4019 {
4020         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4021
4022         mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
4023         mlx4_enter_error_state(persist);
4024
4025         mutex_lock(&persist->interface_state_mutex);
4026         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4027                 mlx4_unload_one(pdev);
4028
4029         mutex_unlock(&persist->interface_state_mutex);
4030         if (state == pci_channel_io_perm_failure)
4031                 return PCI_ERS_RESULT_DISCONNECT;
4032
4033         pci_disable_device(pdev);
4034         return PCI_ERS_RESULT_NEED_RESET;
4035 }
4036
4037 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
4038 {
4039         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4040         struct mlx4_dev  *dev  = persist->dev;
4041         struct mlx4_priv *priv = mlx4_priv(dev);
4042         int               ret;
4043         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4044         int total_vfs;
4045
4046         mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
4047         ret = pci_enable_device(pdev);
4048         if (ret) {
4049                 mlx4_err(dev, "Can not re-enable device, ret=%d\n", ret);
4050                 return PCI_ERS_RESULT_DISCONNECT;
4051         }
4052
4053         pci_set_master(pdev);
4054         pci_restore_state(pdev);
4055         pci_save_state(pdev);
4056
4057         total_vfs = dev->persist->num_vfs;
4058         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4059
4060         mutex_lock(&persist->interface_state_mutex);
4061         if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
4062                 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
4063                                     priv, 1);
4064                 if (ret) {
4065                         mlx4_err(dev, "%s: mlx4_load_one failed, ret=%d\n",
4066                                  __func__,  ret);
4067                         goto end;
4068                 }
4069
4070                 ret = restore_current_port_types(dev, dev->persist->
4071                                                  curr_port_type, dev->persist->
4072                                                  curr_port_poss_type);
4073                 if (ret)
4074                         mlx4_err(dev, "could not restore original port types (%d)\n", ret);
4075         }
4076 end:
4077         mutex_unlock(&persist->interface_state_mutex);
4078
4079         return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
4080 }
4081
4082 static void mlx4_shutdown(struct pci_dev *pdev)
4083 {
4084         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4085
4086         mlx4_info(persist->dev, "mlx4_shutdown was called\n");
4087         mutex_lock(&persist->interface_state_mutex);
4088         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4089                 mlx4_unload_one(pdev);
4090         mutex_unlock(&persist->interface_state_mutex);
4091 }
4092
4093 static const struct pci_error_handlers mlx4_err_handler = {
4094         .error_detected = mlx4_pci_err_detected,
4095         .slot_reset     = mlx4_pci_slot_reset,
4096 };
4097
4098 static struct pci_driver mlx4_driver = {
4099         .name           = DRV_NAME,
4100         .id_table       = mlx4_pci_table,
4101         .probe          = mlx4_init_one,
4102         .shutdown       = mlx4_shutdown,
4103         .remove         = mlx4_remove_one,
4104         .err_handler    = &mlx4_err_handler,
4105 };
4106
4107 static int __init mlx4_verify_params(void)
4108 {
4109         if ((log_num_mac < 0) || (log_num_mac > 7)) {
4110                 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
4111                 return -1;
4112         }
4113
4114         if (log_num_vlan != 0)
4115                 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
4116                         MLX4_LOG_NUM_VLANS);
4117
4118         if (use_prio != 0)
4119                 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
4120
4121         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
4122                 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
4123                         log_mtts_per_seg);
4124                 return -1;
4125         }
4126
4127         /* Check if module param for ports type has legal combination */
4128         if (port_type_array[0] == false && port_type_array[1] == true) {
4129                 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
4130                 port_type_array[0] = true;
4131         }
4132
4133         if (mlx4_log_num_mgm_entry_size < -7 ||
4134             (mlx4_log_num_mgm_entry_size > 0 &&
4135              (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
4136               mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
4137                 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
4138                         mlx4_log_num_mgm_entry_size,
4139                         MLX4_MIN_MGM_LOG_ENTRY_SIZE,
4140                         MLX4_MAX_MGM_LOG_ENTRY_SIZE);
4141                 return -1;
4142         }
4143
4144         return 0;
4145 }
4146
4147 static int __init mlx4_init(void)
4148 {
4149         int ret;
4150
4151         if (mlx4_verify_params())
4152                 return -EINVAL;
4153
4154
4155         mlx4_wq = create_singlethread_workqueue("mlx4");
4156         if (!mlx4_wq)
4157                 return -ENOMEM;
4158
4159         ret = pci_register_driver(&mlx4_driver);
4160         if (ret < 0)
4161                 destroy_workqueue(mlx4_wq);
4162         return ret < 0 ? ret : 0;
4163 }
4164
4165 static void __exit mlx4_cleanup(void)
4166 {
4167         pci_unregister_driver(&mlx4_driver);
4168         destroy_workqueue(mlx4_wq);
4169 }
4170
4171 module_init(mlx4_init);
4172 module_exit(mlx4_cleanup);