2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/netdevice.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION);
58 struct workqueue_struct *mlx4_wq;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level = 0;
63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x, int, 0444);
72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
81 module_param(num_vfs, int, 0444);
82 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
85 module_param(probe_vf, int, 0644);
86 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
88 int mlx4_log_num_mgm_entry_size = 10;
89 module_param_named(log_num_mgm_entry_size,
90 mlx4_log_num_mgm_entry_size, int, 0444);
91 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
92 " of qp per mcg, for example:"
93 " 10 gives 248.range: 9<="
94 " log_num_mgm_entry_size <= 12."
95 " Not in use with device managed"
98 #define HCA_GLOBAL_CAP_MASK 0
99 #define PF_CONTEXT_BEHAVIOUR_MASK 0
101 static char mlx4_version[] __devinitdata =
102 DRV_NAME ": Mellanox ConnectX core driver v"
103 DRV_VERSION " (" DRV_RELDATE ")\n";
105 static struct mlx4_profile default_profile = {
108 .rdmarc_per_qp = 1 << 4,
112 .num_mtt = 1 << 20, /* It is really num mtt segements */
115 static int log_num_mac = 7;
116 module_param_named(log_num_mac, log_num_mac, int, 0444);
117 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
119 static int log_num_vlan;
120 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
121 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
122 /* Log2 max number of VLANs per ETH port (0-7) */
123 #define MLX4_LOG_NUM_VLANS 7
125 static bool use_prio;
126 module_param_named(use_prio, use_prio, bool, 0444);
127 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
130 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
131 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
132 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
134 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
135 static int arr_argc = 2;
136 module_param_array(port_type_array, int, &arr_argc, 0444);
137 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
138 "1 for IB, 2 for Ethernet");
140 struct mlx4_port_config {
141 struct list_head list;
142 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
143 struct pci_dev *pdev;
146 int mlx4_check_port_params(struct mlx4_dev *dev,
147 enum mlx4_port_type *port_type)
151 for (i = 0; i < dev->caps.num_ports - 1; i++) {
152 if (port_type[i] != port_type[i + 1]) {
153 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
154 mlx4_err(dev, "Only same port types supported "
155 "on this HCA, aborting.\n");
161 for (i = 0; i < dev->caps.num_ports; i++) {
162 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
163 mlx4_err(dev, "Requested port type for port %d is not "
164 "supported on this HCA\n", i + 1);
171 static void mlx4_set_port_mask(struct mlx4_dev *dev)
175 for (i = 1; i <= dev->caps.num_ports; ++i)
176 dev->caps.port_mask[i] = dev->caps.port_type[i];
179 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
184 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
186 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
190 if (dev_cap->min_page_sz > PAGE_SIZE) {
191 mlx4_err(dev, "HCA minimum page size of %d bigger than "
192 "kernel PAGE_SIZE of %ld, aborting.\n",
193 dev_cap->min_page_sz, PAGE_SIZE);
196 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
197 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
199 dev_cap->num_ports, MLX4_MAX_PORTS);
203 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
204 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
205 "PCI resource 2 size of 0x%llx, aborting.\n",
207 (unsigned long long) pci_resource_len(dev->pdev, 2));
211 dev->caps.num_ports = dev_cap->num_ports;
212 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
213 for (i = 1; i <= dev->caps.num_ports; ++i) {
214 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
215 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
216 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
217 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
218 /* set gid and pkey table operating lengths by default
219 * to non-sriov values */
220 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
221 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
222 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
223 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
224 dev->caps.def_mac[i] = dev_cap->def_mac[i];
225 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
226 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
227 dev->caps.default_sense[i] = dev_cap->default_sense[i];
228 dev->caps.trans_type[i] = dev_cap->trans_type[i];
229 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
230 dev->caps.wavelength[i] = dev_cap->wavelength[i];
231 dev->caps.trans_code[i] = dev_cap->trans_code[i];
234 dev->caps.uar_page_size = PAGE_SIZE;
235 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
236 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
237 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
238 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
239 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
240 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
241 dev->caps.max_wqes = dev_cap->max_qp_sz;
242 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
243 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
244 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
245 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
246 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
247 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
249 * Subtract 1 from the limit because we need to allocate a
250 * spare CQE so the HCA HW can tell the difference between an
251 * empty CQ and a full CQ.
253 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
254 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
255 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
256 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
257 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
259 /* The first 128 UARs are used for EQ doorbells */
260 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
261 dev->caps.reserved_pds = dev_cap->reserved_pds;
262 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
263 dev_cap->reserved_xrcds : 0;
264 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
265 dev_cap->max_xrcds : 0;
266 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
268 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
269 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
270 dev->caps.flags = dev_cap->flags;
271 dev->caps.flags2 = dev_cap->flags2;
272 dev->caps.bmme_flags = dev_cap->bmme_flags;
273 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
274 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
275 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
276 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
278 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
279 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
280 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
281 dev->caps.fs_log_max_ucast_qp_range_size =
282 dev_cap->fs_log_max_ucast_qp_range_size;
284 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
285 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) {
286 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
288 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
290 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
291 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
292 mlx4_warn(dev, "Must have UC_STEER and MC_STEER flags "
293 "set to use B0 steering. Falling back to A0 steering mode.\n");
295 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
297 mlx4_dbg(dev, "Steering mode is: %s\n",
298 mlx4_steering_mode_str(dev->caps.steering_mode));
300 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
301 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
302 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
303 /* Don't do sense port on multifunction devices (for now at least) */
304 if (mlx4_is_mfunc(dev))
305 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
307 dev->caps.log_num_macs = log_num_mac;
308 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
309 dev->caps.log_num_prios = use_prio ? 3 : 0;
311 for (i = 1; i <= dev->caps.num_ports; ++i) {
312 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
313 if (dev->caps.supported_type[i]) {
314 /* if only ETH is supported - assign ETH */
315 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
316 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
317 /* if only IB is supported, assign IB */
318 else if (dev->caps.supported_type[i] ==
320 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
322 /* if IB and ETH are supported, we set the port
323 * type according to user selection of port type;
324 * if user selected none, take the FW hint */
325 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
326 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
327 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
329 dev->caps.port_type[i] = port_type_array[i - 1];
333 * Link sensing is allowed on the port if 3 conditions are true:
334 * 1. Both protocols are supported on the port.
335 * 2. Different types are supported on the port
336 * 3. FW declared that it supports link sensing
338 mlx4_priv(dev)->sense.sense_allowed[i] =
339 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
340 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
341 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
344 * If "default_sense" bit is set, we move the port to "AUTO" mode
345 * and perform sense_port FW command to try and set the correct
346 * port type from beginning
348 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
349 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
350 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
351 mlx4_SENSE_PORT(dev, i, &sensed_port);
352 if (sensed_port != MLX4_PORT_TYPE_NONE)
353 dev->caps.port_type[i] = sensed_port;
355 dev->caps.possible_type[i] = dev->caps.port_type[i];
358 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
359 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
360 mlx4_warn(dev, "Requested number of MACs is too much "
361 "for port %d, reducing to %d.\n",
362 i, 1 << dev->caps.log_num_macs);
364 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
365 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
366 mlx4_warn(dev, "Requested number of VLANs is too much "
367 "for port %d, reducing to %d.\n",
368 i, 1 << dev->caps.log_num_vlans);
372 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
374 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
375 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
376 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
377 (1 << dev->caps.log_num_macs) *
378 (1 << dev->caps.log_num_vlans) *
379 (1 << dev->caps.log_num_prios) *
381 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
383 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
384 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
385 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
386 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
388 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
391 /*The function checks if there are live vf, return the num of them*/
392 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
394 struct mlx4_priv *priv = mlx4_priv(dev);
395 struct mlx4_slave_state *s_state;
399 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
400 s_state = &priv->mfunc.master.slave_state[i];
401 if (s_state->active && s_state->last_cmd !=
402 MLX4_COMM_CMD_RESET) {
403 mlx4_warn(dev, "%s: slave: %d is still active\n",
411 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
413 u32 qk = MLX4_RESERVED_QKEY_BASE;
415 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
416 qpn < dev->phys_caps.base_proxy_sqpn)
419 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
421 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
423 qk += qpn - dev->phys_caps.base_proxy_sqpn;
427 EXPORT_SYMBOL(mlx4_get_parav_qkey);
429 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
431 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
433 if (!mlx4_is_master(dev))
436 priv->virt2phys_pkey[slave][port - 1][i] = val;
438 EXPORT_SYMBOL(mlx4_sync_pkey_table);
440 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
442 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
444 if (!mlx4_is_master(dev))
447 priv->slave_node_guids[slave] = guid;
449 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
451 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
453 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
455 if (!mlx4_is_master(dev))
458 return priv->slave_node_guids[slave];
460 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
462 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
464 struct mlx4_priv *priv = mlx4_priv(dev);
465 struct mlx4_slave_state *s_slave;
467 if (!mlx4_is_master(dev))
470 s_slave = &priv->mfunc.master.slave_state[slave];
471 return !!s_slave->active;
473 EXPORT_SYMBOL(mlx4_is_slave_active);
475 static int mlx4_slave_cap(struct mlx4_dev *dev)
479 struct mlx4_dev_cap dev_cap;
480 struct mlx4_func_cap func_cap;
481 struct mlx4_init_hca_param hca_param;
484 memset(&hca_param, 0, sizeof(hca_param));
485 err = mlx4_QUERY_HCA(dev, &hca_param);
487 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
491 /*fail if the hca has an unknown capability */
492 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
493 HCA_GLOBAL_CAP_MASK) {
494 mlx4_err(dev, "Unknown hca global capabilities\n");
498 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
500 memset(&dev_cap, 0, sizeof(dev_cap));
501 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
502 err = mlx4_dev_cap(dev, &dev_cap);
504 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
508 err = mlx4_QUERY_FW(dev);
510 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
512 page_size = ~dev->caps.page_size_cap + 1;
513 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
514 if (page_size > PAGE_SIZE) {
515 mlx4_err(dev, "HCA minimum page size of %d bigger than "
516 "kernel PAGE_SIZE of %ld, aborting.\n",
517 page_size, PAGE_SIZE);
521 /* slave gets uar page size from QUERY_HCA fw command */
522 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
524 /* TODO: relax this assumption */
525 if (dev->caps.uar_page_size != PAGE_SIZE) {
526 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
527 dev->caps.uar_page_size, PAGE_SIZE);
531 memset(&func_cap, 0, sizeof(func_cap));
532 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
534 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
539 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
540 PF_CONTEXT_BEHAVIOUR_MASK) {
541 mlx4_err(dev, "Unknown pf context behaviour\n");
545 dev->caps.num_ports = func_cap.num_ports;
546 dev->caps.num_qps = func_cap.qp_quota;
547 dev->caps.num_srqs = func_cap.srq_quota;
548 dev->caps.num_cqs = func_cap.cq_quota;
549 dev->caps.num_eqs = func_cap.max_eq;
550 dev->caps.reserved_eqs = func_cap.reserved_eq;
551 dev->caps.num_mpts = func_cap.mpt_quota;
552 dev->caps.num_mtts = func_cap.mtt_quota;
553 dev->caps.num_pds = MLX4_NUM_PDS;
554 dev->caps.num_mgms = 0;
555 dev->caps.num_amgms = 0;
557 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
558 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
559 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
563 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
564 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
565 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
566 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
568 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
569 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
574 for (i = 1; i <= dev->caps.num_ports; ++i) {
575 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
577 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
578 " port %d, aborting (%d).\n", i, err);
581 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
582 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
583 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
584 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
585 dev->caps.port_mask[i] = dev->caps.port_type[i];
586 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
587 &dev->caps.gid_table_len[i],
588 &dev->caps.pkey_table_len[i]))
592 if (dev->caps.uar_page_size * (dev->caps.num_uars -
593 dev->caps.reserved_uars) >
594 pci_resource_len(dev->pdev, 2)) {
595 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
596 "PCI resource 2 size of 0x%llx, aborting.\n",
597 dev->caps.uar_page_size * dev->caps.num_uars,
598 (unsigned long long) pci_resource_len(dev->pdev, 2));
605 kfree(dev->caps.qp0_tunnel);
606 kfree(dev->caps.qp0_proxy);
607 kfree(dev->caps.qp1_tunnel);
608 kfree(dev->caps.qp1_proxy);
609 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
610 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
616 * Change the port configuration of the device.
617 * Every user of this function must hold the port mutex.
619 int mlx4_change_port_types(struct mlx4_dev *dev,
620 enum mlx4_port_type *port_types)
626 for (port = 0; port < dev->caps.num_ports; port++) {
627 /* Change the port type only if the new type is different
628 * from the current, and not set to Auto */
629 if (port_types[port] != dev->caps.port_type[port + 1])
633 mlx4_unregister_device(dev);
634 for (port = 1; port <= dev->caps.num_ports; port++) {
635 mlx4_CLOSE_PORT(dev, port);
636 dev->caps.port_type[port] = port_types[port - 1];
637 err = mlx4_SET_PORT(dev, port, -1);
639 mlx4_err(dev, "Failed to set port %d, "
644 mlx4_set_port_mask(dev);
645 err = mlx4_register_device(dev);
652 static ssize_t show_port_type(struct device *dev,
653 struct device_attribute *attr,
656 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
658 struct mlx4_dev *mdev = info->dev;
662 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
664 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
665 sprintf(buf, "auto (%s)\n", type);
667 sprintf(buf, "%s\n", type);
672 static ssize_t set_port_type(struct device *dev,
673 struct device_attribute *attr,
674 const char *buf, size_t count)
676 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
678 struct mlx4_dev *mdev = info->dev;
679 struct mlx4_priv *priv = mlx4_priv(mdev);
680 enum mlx4_port_type types[MLX4_MAX_PORTS];
681 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
685 if (!strcmp(buf, "ib\n"))
686 info->tmp_type = MLX4_PORT_TYPE_IB;
687 else if (!strcmp(buf, "eth\n"))
688 info->tmp_type = MLX4_PORT_TYPE_ETH;
689 else if (!strcmp(buf, "auto\n"))
690 info->tmp_type = MLX4_PORT_TYPE_AUTO;
692 mlx4_err(mdev, "%s is not supported port type\n", buf);
696 mlx4_stop_sense(mdev);
697 mutex_lock(&priv->port_mutex);
698 /* Possible type is always the one that was delivered */
699 mdev->caps.possible_type[info->port] = info->tmp_type;
701 for (i = 0; i < mdev->caps.num_ports; i++) {
702 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
703 mdev->caps.possible_type[i+1];
704 if (types[i] == MLX4_PORT_TYPE_AUTO)
705 types[i] = mdev->caps.port_type[i+1];
708 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
709 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
710 for (i = 1; i <= mdev->caps.num_ports; i++) {
711 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
712 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
718 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
719 "Set only 'eth' or 'ib' for both ports "
720 "(should be the same)\n");
724 mlx4_do_sense_ports(mdev, new_types, types);
726 err = mlx4_check_port_params(mdev, new_types);
730 /* We are about to apply the changes after the configuration
731 * was verified, no need to remember the temporary types
733 for (i = 0; i < mdev->caps.num_ports; i++)
734 priv->port[i + 1].tmp_type = 0;
736 err = mlx4_change_port_types(mdev, new_types);
739 mlx4_start_sense(mdev);
740 mutex_unlock(&priv->port_mutex);
741 return err ? err : count;
752 static inline int int_to_ibta_mtu(int mtu)
755 case 256: return IB_MTU_256;
756 case 512: return IB_MTU_512;
757 case 1024: return IB_MTU_1024;
758 case 2048: return IB_MTU_2048;
759 case 4096: return IB_MTU_4096;
764 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
767 case IB_MTU_256: return 256;
768 case IB_MTU_512: return 512;
769 case IB_MTU_1024: return 1024;
770 case IB_MTU_2048: return 2048;
771 case IB_MTU_4096: return 4096;
776 static ssize_t show_port_ib_mtu(struct device *dev,
777 struct device_attribute *attr,
780 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
782 struct mlx4_dev *mdev = info->dev;
784 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
785 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
788 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
792 static ssize_t set_port_ib_mtu(struct device *dev,
793 struct device_attribute *attr,
794 const char *buf, size_t count)
796 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
798 struct mlx4_dev *mdev = info->dev;
799 struct mlx4_priv *priv = mlx4_priv(mdev);
800 int err, port, mtu, ibta_mtu = -1;
802 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
803 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
807 err = sscanf(buf, "%d", &mtu);
809 ibta_mtu = int_to_ibta_mtu(mtu);
811 if (err <= 0 || ibta_mtu < 0) {
812 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
816 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
818 mlx4_stop_sense(mdev);
819 mutex_lock(&priv->port_mutex);
820 mlx4_unregister_device(mdev);
821 for (port = 1; port <= mdev->caps.num_ports; port++) {
822 mlx4_CLOSE_PORT(mdev, port);
823 err = mlx4_SET_PORT(mdev, port, -1);
825 mlx4_err(mdev, "Failed to set port %d, "
830 err = mlx4_register_device(mdev);
832 mutex_unlock(&priv->port_mutex);
833 mlx4_start_sense(mdev);
834 return err ? err : count;
837 static int mlx4_load_fw(struct mlx4_dev *dev)
839 struct mlx4_priv *priv = mlx4_priv(dev);
842 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
843 GFP_HIGHUSER | __GFP_NOWARN, 0);
844 if (!priv->fw.fw_icm) {
845 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
849 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
851 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
855 err = mlx4_RUN_FW(dev);
857 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
867 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
871 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
874 struct mlx4_priv *priv = mlx4_priv(dev);
878 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
880 ((u64) (MLX4_CMPT_TYPE_QP *
881 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
882 cmpt_entry_sz, dev->caps.num_qps,
883 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
888 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
890 ((u64) (MLX4_CMPT_TYPE_SRQ *
891 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
892 cmpt_entry_sz, dev->caps.num_srqs,
893 dev->caps.reserved_srqs, 0, 0);
897 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
899 ((u64) (MLX4_CMPT_TYPE_CQ *
900 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
901 cmpt_entry_sz, dev->caps.num_cqs,
902 dev->caps.reserved_cqs, 0, 0);
906 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
908 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
910 ((u64) (MLX4_CMPT_TYPE_EQ *
911 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
912 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
919 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
922 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
925 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
931 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
932 struct mlx4_init_hca_param *init_hca, u64 icm_size)
934 struct mlx4_priv *priv = mlx4_priv(dev);
939 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
941 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
945 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
946 (unsigned long long) icm_size >> 10,
947 (unsigned long long) aux_pages << 2);
949 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
950 GFP_HIGHUSER | __GFP_NOWARN, 0);
951 if (!priv->fw.aux_icm) {
952 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
956 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
958 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
962 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
964 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
969 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
971 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
972 init_hca->eqc_base, dev_cap->eqc_entry_sz,
973 num_eqs, num_eqs, 0, 0);
975 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
980 * Reserved MTT entries must be aligned up to a cacheline
981 * boundary, since the FW will write to them, while the driver
982 * writes to all other MTT entries. (The variable
983 * dev->caps.mtt_entry_sz below is really the MTT segment
984 * size, not the raw entry size)
986 dev->caps.reserved_mtts =
987 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
988 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
990 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
992 dev->caps.mtt_entry_sz,
994 dev->caps.reserved_mtts, 1, 0);
996 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1000 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1001 init_hca->dmpt_base,
1002 dev_cap->dmpt_entry_sz,
1004 dev->caps.reserved_mrws, 1, 1);
1006 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1010 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1012 dev_cap->qpc_entry_sz,
1014 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1017 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1018 goto err_unmap_dmpt;
1021 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1022 init_hca->auxc_base,
1023 dev_cap->aux_entry_sz,
1025 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1028 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1032 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1033 init_hca->altc_base,
1034 dev_cap->altc_entry_sz,
1036 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1039 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1040 goto err_unmap_auxc;
1043 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1044 init_hca->rdmarc_base,
1045 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1047 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1050 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1051 goto err_unmap_altc;
1054 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1056 dev_cap->cqc_entry_sz,
1058 dev->caps.reserved_cqs, 0, 0);
1060 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1061 goto err_unmap_rdmarc;
1064 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1065 init_hca->srqc_base,
1066 dev_cap->srq_entry_sz,
1068 dev->caps.reserved_srqs, 0, 0);
1070 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1075 * For flow steering device managed mode it is required to use
1076 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1077 * required, but for simplicity just map the whole multicast
1078 * group table now. The table isn't very big and it's a lot
1079 * easier than trying to track ref counts.
1081 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1083 mlx4_get_mgm_entry_size(dev),
1084 dev->caps.num_mgms + dev->caps.num_amgms,
1085 dev->caps.num_mgms + dev->caps.num_amgms,
1088 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1095 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1098 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1101 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1104 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1107 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1110 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1113 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1116 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1119 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1122 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1123 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1124 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1125 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1128 mlx4_UNMAP_ICM_AUX(dev);
1131 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1136 static void mlx4_free_icms(struct mlx4_dev *dev)
1138 struct mlx4_priv *priv = mlx4_priv(dev);
1140 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1141 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1142 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1143 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1144 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1145 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1146 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1147 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1148 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1149 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1150 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1151 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1152 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1153 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1155 mlx4_UNMAP_ICM_AUX(dev);
1156 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1159 static void mlx4_slave_exit(struct mlx4_dev *dev)
1161 struct mlx4_priv *priv = mlx4_priv(dev);
1163 mutex_lock(&priv->cmd.slave_cmd_mutex);
1164 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1165 mlx4_warn(dev, "Failed to close slave function.\n");
1166 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1169 static int map_bf_area(struct mlx4_dev *dev)
1171 struct mlx4_priv *priv = mlx4_priv(dev);
1172 resource_size_t bf_start;
1173 resource_size_t bf_len;
1176 if (!dev->caps.bf_reg_size)
1179 bf_start = pci_resource_start(dev->pdev, 2) +
1180 (dev->caps.num_uars << PAGE_SHIFT);
1181 bf_len = pci_resource_len(dev->pdev, 2) -
1182 (dev->caps.num_uars << PAGE_SHIFT);
1183 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1184 if (!priv->bf_mapping)
1190 static void unmap_bf_area(struct mlx4_dev *dev)
1192 if (mlx4_priv(dev)->bf_mapping)
1193 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1196 static void mlx4_close_hca(struct mlx4_dev *dev)
1199 if (mlx4_is_slave(dev))
1200 mlx4_slave_exit(dev);
1202 mlx4_CLOSE_HCA(dev, 0);
1203 mlx4_free_icms(dev);
1205 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1209 static int mlx4_init_slave(struct mlx4_dev *dev)
1211 struct mlx4_priv *priv = mlx4_priv(dev);
1212 u64 dma = (u64) priv->mfunc.vhcr_dma;
1213 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1214 int ret_from_reset = 0;
1216 u32 cmd_channel_ver;
1218 mutex_lock(&priv->cmd.slave_cmd_mutex);
1219 priv->cmd.max_cmds = 1;
1220 mlx4_warn(dev, "Sending reset\n");
1221 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1223 /* if we are in the middle of flr the slave will try
1224 * NUM_OF_RESET_RETRIES times before leaving.*/
1225 if (ret_from_reset) {
1226 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1227 msleep(SLEEP_TIME_IN_RESET);
1228 while (ret_from_reset && num_of_reset_retries) {
1229 mlx4_warn(dev, "slave is currently in the"
1230 "middle of FLR. retrying..."
1232 (NUM_OF_RESET_RETRIES -
1233 num_of_reset_retries + 1));
1235 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1237 num_of_reset_retries = num_of_reset_retries - 1;
1243 /* check the driver version - the slave I/F revision
1244 * must match the master's */
1245 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1246 cmd_channel_ver = mlx4_comm_get_version();
1248 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1249 MLX4_COMM_GET_IF_REV(slave_read)) {
1250 mlx4_err(dev, "slave driver version is not supported"
1251 " by the master\n");
1255 mlx4_warn(dev, "Sending vhcr0\n");
1256 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1259 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1262 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1265 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1268 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1272 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1273 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1277 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1281 for (i = 1; i <= dev->caps.num_ports; i++) {
1282 dev->caps.gid_table_len[i] = 1;
1283 dev->caps.pkey_table_len[i] =
1284 dev->phys_caps.pkey_phys_table_len[i] - 1;
1288 static int mlx4_init_hca(struct mlx4_dev *dev)
1290 struct mlx4_priv *priv = mlx4_priv(dev);
1291 struct mlx4_adapter adapter;
1292 struct mlx4_dev_cap dev_cap;
1293 struct mlx4_mod_stat_cfg mlx4_cfg;
1294 struct mlx4_profile profile;
1295 struct mlx4_init_hca_param init_hca;
1299 if (!mlx4_is_slave(dev)) {
1300 err = mlx4_QUERY_FW(dev);
1303 mlx4_info(dev, "non-primary physical function, skipping.\n");
1305 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1309 err = mlx4_load_fw(dev);
1311 mlx4_err(dev, "Failed to start FW, aborting.\n");
1315 mlx4_cfg.log_pg_sz_m = 1;
1316 mlx4_cfg.log_pg_sz = 0;
1317 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1319 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1321 err = mlx4_dev_cap(dev, &dev_cap);
1323 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1327 if (mlx4_is_master(dev))
1328 mlx4_parav_master_pf_caps(dev);
1330 priv->fs_hash_mode = MLX4_FS_L2_HASH;
1332 switch (priv->fs_hash_mode) {
1333 case MLX4_FS_L2_HASH:
1334 init_hca.fs_hash_enable_bits = 0;
1337 case MLX4_FS_L2_L3_L4_HASH:
1338 /* Enable flow steering with
1339 * udp unicast and tcp unicast
1341 init_hca.fs_hash_enable_bits =
1342 MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN;
1346 profile = default_profile;
1347 if (dev->caps.steering_mode ==
1348 MLX4_STEERING_MODE_DEVICE_MANAGED)
1349 profile.num_mcg = MLX4_FS_NUM_MCG;
1351 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1353 if ((long long) icm_size < 0) {
1358 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1360 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1361 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1363 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1367 err = mlx4_INIT_HCA(dev, &init_hca);
1369 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1373 err = mlx4_init_slave(dev);
1375 mlx4_err(dev, "Failed to initialize slave\n");
1379 err = mlx4_slave_cap(dev);
1381 mlx4_err(dev, "Failed to obtain slave caps\n");
1386 if (map_bf_area(dev))
1387 mlx4_dbg(dev, "Failed to map blue flame area\n");
1389 /*Only the master set the ports, all the rest got it from it.*/
1390 if (!mlx4_is_slave(dev))
1391 mlx4_set_port_mask(dev);
1393 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1395 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1399 priv->eq_table.inta_pin = adapter.inta_pin;
1400 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1408 mlx4_close_hca(dev);
1411 if (!mlx4_is_slave(dev))
1412 mlx4_free_icms(dev);
1415 if (!mlx4_is_slave(dev)) {
1417 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1422 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1424 struct mlx4_priv *priv = mlx4_priv(dev);
1427 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1430 nent = dev->caps.max_counters;
1431 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1434 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1436 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1439 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1441 struct mlx4_priv *priv = mlx4_priv(dev);
1443 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1446 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1453 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1458 if (mlx4_is_mfunc(dev)) {
1459 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1460 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1461 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1463 *idx = get_param_l(&out_param);
1467 return __mlx4_counter_alloc(dev, idx);
1469 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1471 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1473 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1477 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1481 if (mlx4_is_mfunc(dev)) {
1482 set_param_l(&in_param, idx);
1483 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1484 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1488 __mlx4_counter_free(dev, idx);
1490 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1492 static int mlx4_setup_hca(struct mlx4_dev *dev)
1494 struct mlx4_priv *priv = mlx4_priv(dev);
1497 __be32 ib_port_default_caps;
1499 err = mlx4_init_uar_table(dev);
1501 mlx4_err(dev, "Failed to initialize "
1502 "user access region table, aborting.\n");
1506 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1508 mlx4_err(dev, "Failed to allocate driver access region, "
1510 goto err_uar_table_free;
1513 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1515 mlx4_err(dev, "Couldn't map kernel access region, "
1521 err = mlx4_init_pd_table(dev);
1523 mlx4_err(dev, "Failed to initialize "
1524 "protection domain table, aborting.\n");
1528 err = mlx4_init_xrcd_table(dev);
1530 mlx4_err(dev, "Failed to initialize "
1531 "reliable connection domain table, aborting.\n");
1532 goto err_pd_table_free;
1535 err = mlx4_init_mr_table(dev);
1537 mlx4_err(dev, "Failed to initialize "
1538 "memory region table, aborting.\n");
1539 goto err_xrcd_table_free;
1542 err = mlx4_init_eq_table(dev);
1544 mlx4_err(dev, "Failed to initialize "
1545 "event queue table, aborting.\n");
1546 goto err_mr_table_free;
1549 err = mlx4_cmd_use_events(dev);
1551 mlx4_err(dev, "Failed to switch to event-driven "
1552 "firmware commands, aborting.\n");
1553 goto err_eq_table_free;
1556 err = mlx4_NOP(dev);
1558 if (dev->flags & MLX4_FLAG_MSI_X) {
1559 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1560 "interrupt IRQ %d).\n",
1561 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1562 mlx4_warn(dev, "Trying again without MSI-X.\n");
1564 mlx4_err(dev, "NOP command failed to generate interrupt "
1565 "(IRQ %d), aborting.\n",
1566 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1567 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1573 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1575 err = mlx4_init_cq_table(dev);
1577 mlx4_err(dev, "Failed to initialize "
1578 "completion queue table, aborting.\n");
1582 err = mlx4_init_srq_table(dev);
1584 mlx4_err(dev, "Failed to initialize "
1585 "shared receive queue table, aborting.\n");
1586 goto err_cq_table_free;
1589 err = mlx4_init_qp_table(dev);
1591 mlx4_err(dev, "Failed to initialize "
1592 "queue pair table, aborting.\n");
1593 goto err_srq_table_free;
1596 if (!mlx4_is_slave(dev)) {
1597 err = mlx4_init_mcg_table(dev);
1599 mlx4_err(dev, "Failed to initialize "
1600 "multicast group table, aborting.\n");
1601 goto err_qp_table_free;
1605 err = mlx4_init_counters_table(dev);
1606 if (err && err != -ENOENT) {
1607 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1608 goto err_mcg_table_free;
1611 if (!mlx4_is_slave(dev)) {
1612 for (port = 1; port <= dev->caps.num_ports; port++) {
1613 ib_port_default_caps = 0;
1614 err = mlx4_get_port_ib_caps(dev, port,
1615 &ib_port_default_caps);
1617 mlx4_warn(dev, "failed to get port %d default "
1618 "ib capabilities (%d). Continuing "
1619 "with caps = 0\n", port, err);
1620 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1622 /* initialize per-slave default ib port capabilities */
1623 if (mlx4_is_master(dev)) {
1625 for (i = 0; i < dev->num_slaves; i++) {
1626 if (i == mlx4_master_func_num(dev))
1628 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1629 ib_port_default_caps;
1633 if (mlx4_is_mfunc(dev))
1634 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1636 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1638 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1639 dev->caps.pkey_table_len[port] : -1);
1641 mlx4_err(dev, "Failed to set port %d, aborting\n",
1643 goto err_counters_table_free;
1650 err_counters_table_free:
1651 mlx4_cleanup_counters_table(dev);
1654 mlx4_cleanup_mcg_table(dev);
1657 mlx4_cleanup_qp_table(dev);
1660 mlx4_cleanup_srq_table(dev);
1663 mlx4_cleanup_cq_table(dev);
1666 mlx4_cmd_use_polling(dev);
1669 mlx4_cleanup_eq_table(dev);
1672 mlx4_cleanup_mr_table(dev);
1674 err_xrcd_table_free:
1675 mlx4_cleanup_xrcd_table(dev);
1678 mlx4_cleanup_pd_table(dev);
1684 mlx4_uar_free(dev, &priv->driver_uar);
1687 mlx4_cleanup_uar_table(dev);
1691 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1693 struct mlx4_priv *priv = mlx4_priv(dev);
1694 struct msix_entry *entries;
1695 int nreq = min_t(int, dev->caps.num_ports *
1696 min_t(int, netif_get_num_default_rss_queues() + 1,
1697 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
1702 /* In multifunction mode each function gets 2 msi-X vectors
1703 * one for data path completions anf the other for asynch events
1704 * or command completions */
1705 if (mlx4_is_mfunc(dev)) {
1708 nreq = min_t(int, dev->caps.num_eqs -
1709 dev->caps.reserved_eqs, nreq);
1712 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1716 for (i = 0; i < nreq; ++i)
1717 entries[i].entry = i;
1720 err = pci_enable_msix(dev->pdev, entries, nreq);
1722 /* Try again if at least 2 vectors are available */
1724 mlx4_info(dev, "Requested %d vectors, "
1725 "but only %d MSI-X vectors available, "
1726 "trying again\n", nreq, err);
1735 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1736 /*Working in legacy mode , all EQ's shared*/
1737 dev->caps.comp_pool = 0;
1738 dev->caps.num_comp_vectors = nreq - 1;
1740 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1741 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1743 for (i = 0; i < nreq; ++i)
1744 priv->eq_table.eq[i].irq = entries[i].vector;
1746 dev->flags |= MLX4_FLAG_MSI_X;
1753 dev->caps.num_comp_vectors = 1;
1754 dev->caps.comp_pool = 0;
1756 for (i = 0; i < 2; ++i)
1757 priv->eq_table.eq[i].irq = dev->pdev->irq;
1760 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1762 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1767 if (!mlx4_is_slave(dev)) {
1768 INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL);
1769 mlx4_init_mac_table(dev, &info->mac_table);
1770 mlx4_init_vlan_table(dev, &info->vlan_table);
1772 dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
1773 (port - 1) * (1 << log_num_mac);
1776 sprintf(info->dev_name, "mlx4_port%d", port);
1777 info->port_attr.attr.name = info->dev_name;
1778 if (mlx4_is_mfunc(dev))
1779 info->port_attr.attr.mode = S_IRUGO;
1781 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1782 info->port_attr.store = set_port_type;
1784 info->port_attr.show = show_port_type;
1785 sysfs_attr_init(&info->port_attr.attr);
1787 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1789 mlx4_err(dev, "Failed to create file for port %d\n", port);
1793 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
1794 info->port_mtu_attr.attr.name = info->dev_mtu_name;
1795 if (mlx4_is_mfunc(dev))
1796 info->port_mtu_attr.attr.mode = S_IRUGO;
1798 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
1799 info->port_mtu_attr.store = set_port_ib_mtu;
1801 info->port_mtu_attr.show = show_port_ib_mtu;
1802 sysfs_attr_init(&info->port_mtu_attr.attr);
1804 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
1806 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
1807 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1814 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1819 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1820 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
1823 static int mlx4_init_steering(struct mlx4_dev *dev)
1825 struct mlx4_priv *priv = mlx4_priv(dev);
1826 int num_entries = dev->caps.num_ports;
1829 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1833 for (i = 0; i < num_entries; i++)
1834 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1835 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1836 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1841 static void mlx4_clear_steering(struct mlx4_dev *dev)
1843 struct mlx4_priv *priv = mlx4_priv(dev);
1844 struct mlx4_steer_index *entry, *tmp_entry;
1845 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1846 int num_entries = dev->caps.num_ports;
1849 for (i = 0; i < num_entries; i++) {
1850 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1851 list_for_each_entry_safe(pqp, tmp_pqp,
1852 &priv->steer[i].promisc_qps[j],
1854 list_del(&pqp->list);
1857 list_for_each_entry_safe(entry, tmp_entry,
1858 &priv->steer[i].steer_entries[j],
1860 list_del(&entry->list);
1861 list_for_each_entry_safe(pqp, tmp_pqp,
1864 list_del(&pqp->list);
1874 static int extended_func_num(struct pci_dev *pdev)
1876 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
1879 #define MLX4_OWNER_BASE 0x8069c
1880 #define MLX4_OWNER_SIZE 4
1882 static int mlx4_get_ownership(struct mlx4_dev *dev)
1884 void __iomem *owner;
1887 if (pci_channel_offline(dev->pdev))
1890 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1893 mlx4_err(dev, "Failed to obtain ownership bit\n");
1902 static void mlx4_free_ownership(struct mlx4_dev *dev)
1904 void __iomem *owner;
1906 if (pci_channel_offline(dev->pdev))
1909 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1912 mlx4_err(dev, "Failed to obtain ownership bit\n");
1920 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
1922 struct mlx4_priv *priv;
1923 struct mlx4_dev *dev;
1927 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
1929 err = pci_enable_device(pdev);
1931 dev_err(&pdev->dev, "Cannot enable PCI device, "
1935 if (num_vfs > MLX4_MAX_NUM_VF) {
1936 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
1937 num_vfs, MLX4_MAX_NUM_VF);
1943 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
1944 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1945 dev_err(&pdev->dev, "Missing DCS, aborting."
1946 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
1947 pci_dev_data, pci_resource_flags(pdev, 0));
1949 goto err_disable_pdev;
1951 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1952 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1954 goto err_disable_pdev;
1957 err = pci_request_regions(pdev, DRV_NAME);
1959 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
1960 goto err_disable_pdev;
1963 pci_set_master(pdev);
1965 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1967 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1968 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1970 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1971 goto err_release_regions;
1974 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1976 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1977 "consistent PCI DMA mask.\n");
1978 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1980 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1982 goto err_release_regions;
1986 /* Allow large DMA segments, up to the firmware limit of 1 GB */
1987 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
1989 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1991 dev_err(&pdev->dev, "Device struct alloc failed, "
1994 goto err_release_regions;
1999 INIT_LIST_HEAD(&priv->ctx_list);
2000 spin_lock_init(&priv->ctx_lock);
2002 mutex_init(&priv->port_mutex);
2004 INIT_LIST_HEAD(&priv->pgdir_list);
2005 mutex_init(&priv->pgdir_mutex);
2007 INIT_LIST_HEAD(&priv->bf_list);
2008 mutex_init(&priv->bf_mutex);
2010 dev->rev_id = pdev->revision;
2011 /* Detect if this device is a virtual function */
2012 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2013 /* When acting as pf, we normally skip vfs unless explicitly
2014 * requested to probe them. */
2015 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2016 mlx4_warn(dev, "Skipping virtual function:%d\n",
2017 extended_func_num(pdev));
2021 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2022 dev->flags |= MLX4_FLAG_SLAVE;
2024 /* We reset the device and enable SRIOV only for physical
2025 * devices. Try to claim ownership on the device;
2026 * if already taken, skip -- do not allow multiple PFs */
2027 err = mlx4_get_ownership(dev);
2032 mlx4_warn(dev, "Multiple PFs not yet supported."
2040 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs);
2041 err = pci_enable_sriov(pdev, num_vfs);
2043 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2047 mlx4_warn(dev, "Running in master mode\n");
2048 dev->flags |= MLX4_FLAG_SRIOV |
2050 dev->num_vfs = num_vfs;
2055 * Now reset the HCA before we touch the PCI capabilities or
2056 * attempt a firmware command, since a boot ROM may have left
2057 * the HCA in an undefined state.
2059 err = mlx4_reset(dev);
2061 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2067 err = mlx4_cmd_init(dev);
2069 mlx4_err(dev, "Failed to init command interface, aborting.\n");
2073 /* In slave functions, the communication channel must be initialized
2074 * before posting commands. Also, init num_slaves before calling
2076 if (mlx4_is_mfunc(dev)) {
2077 if (mlx4_is_master(dev))
2078 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2080 dev->num_slaves = 0;
2081 if (mlx4_multi_func_init(dev)) {
2082 mlx4_err(dev, "Failed to init slave mfunc"
2083 " interface, aborting.\n");
2089 err = mlx4_init_hca(dev);
2091 if (err == -EACCES) {
2092 /* Not primary Physical function
2093 * Running in slave mode */
2094 mlx4_cmd_cleanup(dev);
2095 dev->flags |= MLX4_FLAG_SLAVE;
2096 dev->flags &= ~MLX4_FLAG_MASTER;
2102 /* In master functions, the communication channel must be initialized
2103 * after obtaining its address from fw */
2104 if (mlx4_is_master(dev)) {
2105 if (mlx4_multi_func_init(dev)) {
2106 mlx4_err(dev, "Failed to init master mfunc"
2107 "interface, aborting.\n");
2112 err = mlx4_alloc_eq_table(dev);
2114 goto err_master_mfunc;
2116 priv->msix_ctl.pool_bm = 0;
2117 mutex_init(&priv->msix_ctl.pool_lock);
2119 mlx4_enable_msi_x(dev);
2120 if ((mlx4_is_mfunc(dev)) &&
2121 !(dev->flags & MLX4_FLAG_MSI_X)) {
2122 mlx4_err(dev, "INTx is not supported in multi-function mode."
2127 if (!mlx4_is_slave(dev)) {
2128 err = mlx4_init_steering(dev);
2133 err = mlx4_setup_hca(dev);
2134 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2135 !mlx4_is_mfunc(dev)) {
2136 dev->flags &= ~MLX4_FLAG_MSI_X;
2137 dev->caps.num_comp_vectors = 1;
2138 dev->caps.comp_pool = 0;
2139 pci_disable_msix(pdev);
2140 err = mlx4_setup_hca(dev);
2146 for (port = 1; port <= dev->caps.num_ports; port++) {
2147 err = mlx4_init_port_info(dev, port);
2152 err = mlx4_register_device(dev);
2156 mlx4_sense_init(dev);
2157 mlx4_start_sense(dev);
2159 priv->pci_dev_data = pci_dev_data;
2160 pci_set_drvdata(pdev, dev);
2165 for (--port; port >= 1; --port)
2166 mlx4_cleanup_port_info(&priv->port[port]);
2168 mlx4_cleanup_counters_table(dev);
2169 mlx4_cleanup_mcg_table(dev);
2170 mlx4_cleanup_qp_table(dev);
2171 mlx4_cleanup_srq_table(dev);
2172 mlx4_cleanup_cq_table(dev);
2173 mlx4_cmd_use_polling(dev);
2174 mlx4_cleanup_eq_table(dev);
2175 mlx4_cleanup_mr_table(dev);
2176 mlx4_cleanup_xrcd_table(dev);
2177 mlx4_cleanup_pd_table(dev);
2178 mlx4_cleanup_uar_table(dev);
2181 if (!mlx4_is_slave(dev))
2182 mlx4_clear_steering(dev);
2185 mlx4_free_eq_table(dev);
2188 if (mlx4_is_master(dev))
2189 mlx4_multi_func_cleanup(dev);
2192 if (dev->flags & MLX4_FLAG_MSI_X)
2193 pci_disable_msix(pdev);
2195 mlx4_close_hca(dev);
2198 if (mlx4_is_slave(dev))
2199 mlx4_multi_func_cleanup(dev);
2202 mlx4_cmd_cleanup(dev);
2205 if (dev->flags & MLX4_FLAG_SRIOV)
2206 pci_disable_sriov(pdev);
2209 if (!mlx4_is_slave(dev))
2210 mlx4_free_ownership(dev);
2215 err_release_regions:
2216 pci_release_regions(pdev);
2219 pci_disable_device(pdev);
2220 pci_set_drvdata(pdev, NULL);
2224 static int __devinit mlx4_init_one(struct pci_dev *pdev,
2225 const struct pci_device_id *id)
2227 printk_once(KERN_INFO "%s", mlx4_version);
2229 return __mlx4_init_one(pdev, id->driver_data);
2232 static void mlx4_remove_one(struct pci_dev *pdev)
2234 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2235 struct mlx4_priv *priv = mlx4_priv(dev);
2239 /* in SRIOV it is not allowed to unload the pf's
2240 * driver while there are alive vf's */
2241 if (mlx4_is_master(dev)) {
2242 if (mlx4_how_many_lives_vf(dev))
2243 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2245 mlx4_stop_sense(dev);
2246 mlx4_unregister_device(dev);
2248 for (p = 1; p <= dev->caps.num_ports; p++) {
2249 mlx4_cleanup_port_info(&priv->port[p]);
2250 mlx4_CLOSE_PORT(dev, p);
2253 if (mlx4_is_master(dev))
2254 mlx4_free_resource_tracker(dev,
2255 RES_TR_FREE_SLAVES_ONLY);
2257 mlx4_cleanup_counters_table(dev);
2258 mlx4_cleanup_mcg_table(dev);
2259 mlx4_cleanup_qp_table(dev);
2260 mlx4_cleanup_srq_table(dev);
2261 mlx4_cleanup_cq_table(dev);
2262 mlx4_cmd_use_polling(dev);
2263 mlx4_cleanup_eq_table(dev);
2264 mlx4_cleanup_mr_table(dev);
2265 mlx4_cleanup_xrcd_table(dev);
2266 mlx4_cleanup_pd_table(dev);
2268 if (mlx4_is_master(dev))
2269 mlx4_free_resource_tracker(dev,
2270 RES_TR_FREE_STRUCTS_ONLY);
2273 mlx4_uar_free(dev, &priv->driver_uar);
2274 mlx4_cleanup_uar_table(dev);
2275 if (!mlx4_is_slave(dev))
2276 mlx4_clear_steering(dev);
2277 mlx4_free_eq_table(dev);
2278 if (mlx4_is_master(dev))
2279 mlx4_multi_func_cleanup(dev);
2280 mlx4_close_hca(dev);
2281 if (mlx4_is_slave(dev))
2282 mlx4_multi_func_cleanup(dev);
2283 mlx4_cmd_cleanup(dev);
2285 if (dev->flags & MLX4_FLAG_MSI_X)
2286 pci_disable_msix(pdev);
2287 if (dev->flags & MLX4_FLAG_SRIOV) {
2288 mlx4_warn(dev, "Disabling SR-IOV\n");
2289 pci_disable_sriov(pdev);
2292 if (!mlx4_is_slave(dev))
2293 mlx4_free_ownership(dev);
2295 kfree(dev->caps.qp0_tunnel);
2296 kfree(dev->caps.qp0_proxy);
2297 kfree(dev->caps.qp1_tunnel);
2298 kfree(dev->caps.qp1_proxy);
2301 pci_release_regions(pdev);
2302 pci_disable_device(pdev);
2303 pci_set_drvdata(pdev, NULL);
2307 int mlx4_restart_one(struct pci_dev *pdev)
2309 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2310 struct mlx4_priv *priv = mlx4_priv(dev);
2313 pci_dev_data = priv->pci_dev_data;
2314 mlx4_remove_one(pdev);
2315 return __mlx4_init_one(pdev, pci_dev_data);
2318 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
2319 /* MT25408 "Hermon" SDR */
2320 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2321 /* MT25408 "Hermon" DDR */
2322 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2323 /* MT25408 "Hermon" QDR */
2324 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2325 /* MT25408 "Hermon" DDR PCIe gen2 */
2326 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2327 /* MT25408 "Hermon" QDR PCIe gen2 */
2328 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2329 /* MT25408 "Hermon" EN 10GigE */
2330 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2331 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2332 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2333 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2334 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2335 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2336 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2337 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2338 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2339 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2340 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2341 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2342 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2343 /* MT25400 Family [ConnectX-2 Virtual Function] */
2344 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
2345 /* MT27500 Family [ConnectX-3] */
2346 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2347 /* MT27500 Family [ConnectX-3 Virtual Function] */
2348 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
2349 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2350 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2351 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2352 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2353 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2354 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2355 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2356 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2357 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2358 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2359 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2360 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2364 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2366 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2367 pci_channel_state_t state)
2369 mlx4_remove_one(pdev);
2371 return state == pci_channel_io_perm_failure ?
2372 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2375 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2377 int ret = __mlx4_init_one(pdev, 0);
2379 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2382 static struct pci_error_handlers mlx4_err_handler = {
2383 .error_detected = mlx4_pci_err_detected,
2384 .slot_reset = mlx4_pci_slot_reset,
2387 static struct pci_driver mlx4_driver = {
2389 .id_table = mlx4_pci_table,
2390 .probe = mlx4_init_one,
2391 .remove = __devexit_p(mlx4_remove_one),
2392 .err_handler = &mlx4_err_handler,
2395 static int __init mlx4_verify_params(void)
2397 if ((log_num_mac < 0) || (log_num_mac > 7)) {
2398 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
2402 if (log_num_vlan != 0)
2403 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2404 MLX4_LOG_NUM_VLANS);
2406 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2407 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
2411 /* Check if module param for ports type has legal combination */
2412 if (port_type_array[0] == false && port_type_array[1] == true) {
2413 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2414 port_type_array[0] = true;
2420 static int __init mlx4_init(void)
2424 if (mlx4_verify_params())
2429 mlx4_wq = create_singlethread_workqueue("mlx4");
2433 ret = pci_register_driver(&mlx4_driver);
2434 return ret < 0 ? ret : 0;
2437 static void __exit mlx4_cleanup(void)
2439 pci_unregister_driver(&mlx4_driver);
2440 destroy_workqueue(mlx4_wq);
2443 module_init(mlx4_init);
2444 module_exit(mlx4_cleanup);