drivers/net/ethernet/mellanox/mlx4/mcg.c

   1 /*
   2  * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/string.h>
  35 #include <linux/etherdevice.h>
  36
  37 #include <linux/mlx4/cmd.h>
  38 #include <linux/export.h>
  39
  40 #include "mlx4.h"
  41
  42 static const u8 zero_gid[16];   /* automatically initialized to 0 */
  43
  44 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev)
  45 {
  46         return 1 << dev->oper_log_mgm_entry_size;
  47 }
  48
  49 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev)
  50 {
  51         return 4 * (mlx4_get_mgm_entry_size(dev) / 16 - 2);
  52 }
  53
  54 static int mlx4_QP_FLOW_STEERING_ATTACH(struct mlx4_dev *dev,
  55                                         struct mlx4_cmd_mailbox *mailbox,
  56                                         u32 size,
  57                                         u64 *reg_id)
  58 {
  59         u64 imm;
  60         int err = 0;
  61
  62         err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0,
  63                            MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  64                            MLX4_CMD_NATIVE);
  65         if (err)
  66                 return err;
  67         *reg_id = imm;
  68
  69         return err;
  70 }
  71
  72 static int mlx4_QP_FLOW_STEERING_DETACH(struct mlx4_dev *dev, u64 regid)
  73 {
  74         int err = 0;
  75
  76         err = mlx4_cmd(dev, regid, 0, 0,
  77                        MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  78                        MLX4_CMD_NATIVE);
  79
  80         return err;
  81 }
  82
  83 static int mlx4_READ_ENTRY(struct mlx4_dev *dev, int index,
  84                            struct mlx4_cmd_mailbox *mailbox)
  85 {
  86         return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG,
  87                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  88 }
  89
  90 static int mlx4_WRITE_ENTRY(struct mlx4_dev *dev, int index,
  91                             struct mlx4_cmd_mailbox *mailbox)
  92 {
  93         return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG,
  94                         MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  95 }
  96
  97 static int mlx4_WRITE_PROMISC(struct mlx4_dev *dev, u8 port, u8 steer,
  98                               struct mlx4_cmd_mailbox *mailbox)
  99 {
 100         u32 in_mod;
 101
 102         in_mod = (u32) port << 16 | steer << 1;
 103         return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1,
 104                         MLX4_CMD_WRITE_MCG, MLX4_CMD_TIME_CLASS_A,
 105                         MLX4_CMD_NATIVE);
 106 }
 107
 108 static int mlx4_GID_HASH(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
 109                          u16 *hash, u8 op_mod)
 110 {
 111         u64 imm;
 112         int err;
 113
 114         err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod,
 115                            MLX4_CMD_MGID_HASH, MLX4_CMD_TIME_CLASS_A,
 116                            MLX4_CMD_NATIVE);
 117
 118         if (!err)
 119                 *hash = imm;
 120
 121         return err;
 122 }
 123
 124 static struct mlx4_promisc_qp *get_promisc_qp(struct mlx4_dev *dev, u8 port,
 125                                               enum mlx4_steer_type steer,
 126                                               u32 qpn)
 127 {
 128         struct mlx4_steer *s_steer;
 129         struct mlx4_promisc_qp *pqp;
 130
 131         if (port < 1 || port > dev->caps.num_ports)
 132                 return NULL;
 133
 134         s_steer = &mlx4_priv(dev)->steer[port - 1];
 135
 136         list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
 137                 if (pqp->qpn == qpn)
 138                         return pqp;
 139         }
 140         /* not found */
 141         return NULL;
 142 }
 143
 144 /*
 145  * Add new entry to steering data structure.
 146  * All promisc QPs should be added as well
 147  */
 148 static int new_steering_entry(struct mlx4_dev *dev, u8 port,
 149                               enum mlx4_steer_type steer,
 150                               unsigned int index, u32 qpn)
 151 {
 152         struct mlx4_steer *s_steer;
 153         struct mlx4_cmd_mailbox *mailbox;
 154         struct mlx4_mgm *mgm;
 155         u32 members_count;
 156         struct mlx4_steer_index *new_entry;
 157         struct mlx4_promisc_qp *pqp;
 158         struct mlx4_promisc_qp *dqp = NULL;
 159         u32 prot;
 160         int err;
 161
 162         if (port < 1 || port > dev->caps.num_ports)
 163                 return -EINVAL;
 164
 165         s_steer = &mlx4_priv(dev)->steer[port - 1];
 166         new_entry = kzalloc(sizeof *new_entry, GFP_KERNEL);
 167         if (!new_entry)
 168                 return -ENOMEM;
 169
 170         INIT_LIST_HEAD(&new_entry->duplicates);
 171         new_entry->index = index;
 172         list_add_tail(&new_entry->list, &s_steer->steer_entries[steer]);
 173
 174         /* If the given qpn is also a promisc qp,
 175          * it should be inserted to duplicates list
 176          */
 177         pqp = get_promisc_qp(dev, port, steer, qpn);
 178         if (pqp) {
 179                 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
 180                 if (!dqp) {
 181                         err = -ENOMEM;
 182                         goto out_alloc;
 183                 }
 184                 dqp->qpn = qpn;
 185                 list_add_tail(&dqp->list, &new_entry->duplicates);
 186         }
 187
 188         /* if no promisc qps for this vep, we are done */
 189         if (list_empty(&s_steer->promisc_qps[steer]))
 190                 return 0;
 191
 192         /* now need to add all the promisc qps to the new
 193          * steering entry, as they should also receive the packets
 194          * destined to this address */
 195         mailbox = mlx4_alloc_cmd_mailbox(dev);
 196         if (IS_ERR(mailbox)) {
 197                 err = -ENOMEM;
 198                 goto out_alloc;
 199         }
 200         mgm = mailbox->buf;
 201
 202         err = mlx4_READ_ENTRY(dev, index, mailbox);
 203         if (err)
 204                 goto out_mailbox;
 205
 206         members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
 207         prot = be32_to_cpu(mgm->members_count) >> 30;
 208         list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
 209                 /* don't add already existing qpn */
 210                 if (pqp->qpn == qpn)
 211                         continue;
 212                 if (members_count == dev->caps.num_qp_per_mgm) {
 213                         /* out of space */
 214                         err = -ENOMEM;
 215                         goto out_mailbox;
 216                 }
 217
 218                 /* add the qpn */
 219                 mgm->qp[members_count++] = cpu_to_be32(pqp->qpn & MGM_QPN_MASK);
 220         }
 221         /* update the qps count and update the entry with all the promisc qps*/
 222         mgm->members_count = cpu_to_be32(members_count | (prot << 30));
 223         err = mlx4_WRITE_ENTRY(dev, index, mailbox);
 224
 225 out_mailbox:
 226         mlx4_free_cmd_mailbox(dev, mailbox);
 227         if (!err)
 228                 return 0;
 229 out_alloc:
 230         if (dqp) {
 231                 list_del(&dqp->list);
 232                 kfree(dqp);
 233         }
 234         list_del(&new_entry->list);
 235         kfree(new_entry);
 236         return err;
 237 }
 238
 239 /* update the data structures with existing steering entry */
 240 static int existing_steering_entry(struct mlx4_dev *dev, u8 port,
 241                                    enum mlx4_steer_type steer,
 242                                    unsigned int index, u32 qpn)
 243 {
 244         struct mlx4_steer *s_steer;
 245         struct mlx4_steer_index *tmp_entry, *entry = NULL;
 246         struct mlx4_promisc_qp *pqp;
 247         struct mlx4_promisc_qp *dqp;
 248
 249         if (port < 1 || port > dev->caps.num_ports)
 250                 return -EINVAL;
 251
 252         s_steer = &mlx4_priv(dev)->steer[port - 1];
 253
 254         pqp = get_promisc_qp(dev, port, steer, qpn);
 255         if (!pqp)
 256                 return 0; /* nothing to do */
 257
 258         list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
 259                 if (tmp_entry->index == index) {
 260                         entry = tmp_entry;
 261                         break;
 262                 }
 263         }
 264         if (unlikely(!entry)) {
 265                 mlx4_warn(dev, "Steering entry at index %x is not registered\n", index);
 266                 return -EINVAL;
 267         }
 268
 269         /* the given qpn is listed as a promisc qpn
 270          * we need to add it as a duplicate to this entry
 271          * for future references */
 272         list_for_each_entry(dqp, &entry->duplicates, list) {
 273                 if (qpn == pqp->qpn)
 274                         return 0; /* qp is already duplicated */
 275         }
 276
 277         /* add the qp as a duplicate on this index */
 278         dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
 279         if (!dqp)
 280                 return -ENOMEM;
 281         dqp->qpn = qpn;
 282         list_add_tail(&dqp->list, &entry->duplicates);
 283
 284         return 0;
 285 }
 286
 287 /* Check whether a qpn is a duplicate on steering entry
 288  * If so, it should not be removed from mgm */
 289 static bool check_duplicate_entry(struct mlx4_dev *dev, u8 port,
 290                                   enum mlx4_steer_type steer,
 291                                   unsigned int index, u32 qpn)
 292 {
 293         struct mlx4_steer *s_steer;
 294         struct mlx4_steer_index *tmp_entry, *entry = NULL;
 295         struct mlx4_promisc_qp *dqp, *tmp_dqp;
 296
 297         if (port < 1 || port > dev->caps.num_ports)
 298                 return NULL;
 299
 300         s_steer = &mlx4_priv(dev)->steer[port - 1];
 301
 302         /* if qp is not promisc, it cannot be duplicated */
 303         if (!get_promisc_qp(dev, port, steer, qpn))
 304                 return false;
 305
 306         /* The qp is promisc qp so it is a duplicate on this index
 307          * Find the index entry, and remove the duplicate */
 308         list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
 309                 if (tmp_entry->index == index) {
 310                         entry = tmp_entry;
 311                         break;
 312                 }
 313         }
 314         if (unlikely(!entry)) {
 315                 mlx4_warn(dev, "Steering entry for index %x is not registered\n", index);
 316                 return false;
 317         }
 318         list_for_each_entry_safe(dqp, tmp_dqp, &entry->duplicates, list) {
 319                 if (dqp->qpn == qpn) {
 320                         list_del(&dqp->list);
 321                         kfree(dqp);
 322                 }
 323         }
 324         return true;
 325 }
 326
 327 /* I a steering entry contains only promisc QPs, it can be removed. */
 328 static bool can_remove_steering_entry(struct mlx4_dev *dev, u8 port,
 329                                       enum mlx4_steer_type steer,
 330                                       unsigned int index, u32 tqpn)
 331 {
 332         struct mlx4_steer *s_steer;
 333         struct mlx4_cmd_mailbox *mailbox;
 334         struct mlx4_mgm *mgm;
 335         struct mlx4_steer_index *entry = NULL, *tmp_entry;
 336         u32 qpn;
 337         u32 members_count;
 338         bool ret = false;
 339         int i;
 340
 341         if (port < 1 || port > dev->caps.num_ports)
 342                 return NULL;
 343
 344         s_steer = &mlx4_priv(dev)->steer[port - 1];
 345
 346         mailbox = mlx4_alloc_cmd_mailbox(dev);
 347         if (IS_ERR(mailbox))
 348                 return false;
 349         mgm = mailbox->buf;
 350
 351         if (mlx4_READ_ENTRY(dev, index, mailbox))
 352                 goto out;
 353         members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
 354         for (i = 0;  i < members_count; i++) {
 355                 qpn = be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK;
 356                 if (!get_promisc_qp(dev, port, steer, qpn) && qpn != tqpn) {
 357                         /* the qp is not promisc, the entry can't be removed */
 358                         goto out;
 359                 }
 360         }
 361          /* All the qps currently registered for this entry are promiscuous,
 362           * Checking for duplicates */
 363         ret = true;
 364         list_for_each_entry_safe(entry, tmp_entry, &s_steer->steer_entries[steer], list) {
 365                 if (entry->index == index) {
 366                         if (list_empty(&entry->duplicates) ||
 367                             members_count == 1) {
 368                                 struct mlx4_promisc_qp *pqp, *tmp_pqp;
 369                                 /* If there is only 1 entry in duplicates then
 370                                  * this is the QP we want to delete, going over
 371                                  * the list and deleting the entry.
 372                                  */
 373                                 list_del(&entry->list);
 374                                 list_for_each_entry_safe(pqp, tmp_pqp,
 375                                                          &entry->duplicates,
 376                                                          list) {
 377                                         list_del(&pqp->list);
 378                                         kfree(pqp);
 379                                 }
 380                                 kfree(entry);
 381                         } else {
 382                                 /* This entry contains duplicates so it shouldn't be removed */
 383                                 ret = false;
 384                                 goto out;
 385                         }
 386                 }
 387         }
 388
 389 out:
 390         mlx4_free_cmd_mailbox(dev, mailbox);
 391         return ret;
 392 }
 393
 394 static int add_promisc_qp(struct mlx4_dev *dev, u8 port,
 395                           enum mlx4_steer_type steer, u32 qpn)
 396 {
 397         struct mlx4_steer *s_steer;
 398         struct mlx4_cmd_mailbox *mailbox;
 399         struct mlx4_mgm *mgm;
 400         struct mlx4_steer_index *entry;
 401         struct mlx4_promisc_qp *pqp;
 402         struct mlx4_promisc_qp *dqp;
 403         u32 members_count;
 404         u32 prot;
 405         int i;
 406         bool found;
 407         int err;
 408         struct mlx4_priv *priv = mlx4_priv(dev);
 409
 410         if (port < 1 || port > dev->caps.num_ports)
 411                 return -EINVAL;
 412
 413         s_steer = &mlx4_priv(dev)->steer[port - 1];
 414
 415         mutex_lock(&priv->mcg_table.mutex);
 416
 417         if (get_promisc_qp(dev, port, steer, qpn)) {
 418                 err = 0;  /* Noting to do, already exists */
 419                 goto out_mutex;
 420         }
 421
 422         pqp = kmalloc(sizeof *pqp, GFP_KERNEL);
 423         if (!pqp) {
 424                 err = -ENOMEM;
 425                 goto out_mutex;
 426         }
 427         pqp->qpn = qpn;
 428
 429         mailbox = mlx4_alloc_cmd_mailbox(dev);
 430         if (IS_ERR(mailbox)) {
 431                 err = -ENOMEM;
 432                 goto out_alloc;
 433         }
 434         mgm = mailbox->buf;
 435
 436         /* the promisc qp needs to be added for each one of the steering
 437          * entries, if it already exists, needs to be added as a duplicate
 438          * for this entry */
 439         list_for_each_entry(entry, &s_steer->steer_entries[steer], list) {
 440                 err = mlx4_READ_ENTRY(dev, entry->index, mailbox);
 441                 if (err)
 442                         goto out_mailbox;
 443
 444                 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
 445                 prot = be32_to_cpu(mgm->members_count) >> 30;
 446                 found = false;
 447                 for (i = 0; i < members_count; i++) {
 448                         if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qpn) {
 449                                 /* Entry already exists, add to duplicates */
 450                                 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
 451                                 if (!dqp) {
 452                                         err = -ENOMEM;
 453                                         goto out_mailbox;
 454                                 }
 455                                 dqp->qpn = qpn;
 456                                 list_add_tail(&dqp->list, &entry->duplicates);
 457                                 found = true;
 458                         }
 459                 }
 460                 if (!found) {
 461                         /* Need to add the qpn to mgm */
 462                         if (members_count == dev->caps.num_qp_per_mgm) {
 463                                 /* entry is full */
 464                                 err = -ENOMEM;
 465                                 goto out_mailbox;
 466                         }
 467                         mgm->qp[members_count++] = cpu_to_be32(qpn & MGM_QPN_MASK);
 468                         mgm->members_count = cpu_to_be32(members_count | (prot << 30));
 469                         err = mlx4_WRITE_ENTRY(dev, entry->index, mailbox);
 470                         if (err)
 471                                 goto out_mailbox;
 472                 }
 473         }
 474
 475         /* add the new qpn to list of promisc qps */
 476         list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
 477         /* now need to add all the promisc qps to default entry */
 478         memset(mgm, 0, sizeof *mgm);
 479         members_count = 0;
 480         list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list) {
 481                 if (members_count == dev->caps.num_qp_per_mgm) {
 482                         /* entry is full */
 483                         err = -ENOMEM;
 484                         goto out_list;
 485                 }
 486                 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
 487         }
 488         mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
 489
 490         err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
 491         if (err)
 492                 goto out_list;
 493
 494         mlx4_free_cmd_mailbox(dev, mailbox);
 495         mutex_unlock(&priv->mcg_table.mutex);
 496         return 0;
 497
 498 out_list:
 499         list_del(&pqp->list);
 500 out_mailbox:
 501         mlx4_free_cmd_mailbox(dev, mailbox);
 502 out_alloc:
 503         kfree(pqp);
 504 out_mutex:
 505         mutex_unlock(&priv->mcg_table.mutex);
 506         return err;
 507 }
 508
 509 static int remove_promisc_qp(struct mlx4_dev *dev, u8 port,
 510                              enum mlx4_steer_type steer, u32 qpn)
 511 {
 512         struct mlx4_priv *priv = mlx4_priv(dev);
 513         struct mlx4_steer *s_steer;
 514         struct mlx4_cmd_mailbox *mailbox;
 515         struct mlx4_mgm *mgm;
 516         struct mlx4_steer_index *entry;
 517         struct mlx4_promisc_qp *pqp;
 518         struct mlx4_promisc_qp *dqp;
 519         u32 members_count;
 520         bool found;
 521         bool back_to_list = false;
 522         int i;
 523         int err;
 524
 525         if (port < 1 || port > dev->caps.num_ports)
 526                 return -EINVAL;
 527
 528         s_steer = &mlx4_priv(dev)->steer[port - 1];
 529         mutex_lock(&priv->mcg_table.mutex);
 530
 531         pqp = get_promisc_qp(dev, port, steer, qpn);
 532         if (unlikely(!pqp)) {
 533                 mlx4_warn(dev, "QP %x is not promiscuous QP\n", qpn);
 534                 /* nothing to do */
 535                 err = 0;
 536                 goto out_mutex;
 537         }
 538
 539         /*remove from list of promisc qps */
 540         list_del(&pqp->list);
 541
 542         /* set the default entry not to include the removed one */
 543         mailbox = mlx4_alloc_cmd_mailbox(dev);
 544         if (IS_ERR(mailbox)) {
 545                 err = -ENOMEM;
 546                 back_to_list = true;
 547                 goto out_list;
 548         }
 549         mgm = mailbox->buf;
 550         members_count = 0;
 551         list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list)
 552                 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
 553         mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
 554
 555         err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
 556         if (err)
 557                 goto out_mailbox;
 558
 559         /* remove the qp from all the steering entries*/
 560         list_for_each_entry(entry, &s_steer->steer_entries[steer], list) {
 561                 found = false;
 562                 list_for_each_entry(dqp, &entry->duplicates, list) {
 563                         if (dqp->qpn == qpn) {
 564                                 found = true;
 565                                 break;
 566                         }
 567                 }
 568                 if (found) {
 569                         /* a duplicate, no need to change the mgm,
 570                          * only update the duplicates list */
 571                         list_del(&dqp->list);
 572                         kfree(dqp);
 573                 } else {
 574                         int loc = -1;
 575                         err = mlx4_READ_ENTRY(dev, entry->index, mailbox);
 576                                 if (err)
 577                                         goto out_mailbox;
 578                         members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
 579                         for (i = 0; i < members_count; ++i)
 580                                 if ((be32_to_cpu(mgm->qp[i]) &
 581                                      MGM_QPN_MASK) == qpn) {
 582                                         loc = i;
 583                                         break;
 584                                 }
 585
 586                         if (loc < 0) {
 587                                 mlx4_err(dev, "QP %06x wasn't found in entry %d\n",
 588                                          qpn, entry->index);
 589                                 err = -EINVAL;
 590                                 goto out_mailbox;
 591                         }
 592
 593                         /* copy the last QP in this MGM over removed QP */
 594                         mgm->qp[loc] = mgm->qp[members_count - 1];
 595                         mgm->qp[members_count - 1] = 0;
 596                         mgm->members_count = cpu_to_be32(--members_count |
 597                                                          (MLX4_PROT_ETH << 30));
 598
 599                         err = mlx4_WRITE_ENTRY(dev, entry->index, mailbox);
 600                                 if (err)
 601                                         goto out_mailbox;
 602                 }
 603
 604         }
 605
 606 out_mailbox:
 607         mlx4_free_cmd_mailbox(dev, mailbox);
 608 out_list:
 609         if (back_to_list)
 610                 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
 611         else
 612                 kfree(pqp);
 613 out_mutex:
 614         mutex_unlock(&priv->mcg_table.mutex);
 615         return err;
 616 }
 617
 618 /*
 619  * Caller must hold MCG table semaphore.  gid and mgm parameters must
 620  * be properly aligned for command interface.
 621  *
 622  *  Returns 0 unless a firmware command error occurs.
 623  *
 624  * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1
 625  * and *mgm holds MGM entry.
 626  *
 627  * if GID is found in AMGM, *index = index in AMGM, *prev = index of
 628  * previous entry in hash chain and *mgm holds AMGM entry.
 629  *
 630  * If no AMGM exists for given gid, *index = -1, *prev = index of last
 631  * entry in hash chain and *mgm holds end of hash chain.
 632  */
 633 static int find_entry(struct mlx4_dev *dev, u8 port,
 634                       u8 *gid, enum mlx4_protocol prot,
 635                       struct mlx4_cmd_mailbox *mgm_mailbox,
 636                       int *prev, int *index)
 637 {
 638         struct mlx4_cmd_mailbox *mailbox;
 639         struct mlx4_mgm *mgm = mgm_mailbox->buf;
 640         u8 *mgid;
 641         int err;
 642         u16 hash;
 643         u8 op_mod = (prot == MLX4_PROT_ETH) ?
 644                 !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) : 0;
 645
 646         mailbox = mlx4_alloc_cmd_mailbox(dev);
 647         if (IS_ERR(mailbox))
 648                 return -ENOMEM;
 649         mgid = mailbox->buf;
 650
 651         memcpy(mgid, gid, 16);
 652
 653         err = mlx4_GID_HASH(dev, mailbox, &hash, op_mod);
 654         mlx4_free_cmd_mailbox(dev, mailbox);
 655         if (err)
 656                 return err;
 657
 658         if (0)
 659                 mlx4_dbg(dev, "Hash for %pI6 is %04x\n", gid, hash);
 660
 661         *index = hash;
 662         *prev  = -1;
 663
 664         do {
 665                 err = mlx4_READ_ENTRY(dev, *index, mgm_mailbox);
 666                 if (err)
 667                         return err;
 668
 669                 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
 670                         if (*index != hash) {
 671                                 mlx4_err(dev, "Found zero MGID in AMGM\n");
 672                                 err = -EINVAL;
 673                         }
 674                         return err;
 675                 }
 676
 677                 if (!memcmp(mgm->gid, gid, 16) &&
 678                     be32_to_cpu(mgm->members_count) >> 30 == prot)
 679                         return err;
 680
 681                 *prev = *index;
 682                 *index = be32_to_cpu(mgm->next_gid_index) >> 6;
 683         } while (*index);
 684
 685         *index = -1;
 686         return err;
 687 }
 688
 689 static const u8 __promisc_mode[] = {
 690         [MLX4_FS_REGULAR]   = 0x0,
 691         [MLX4_FS_ALL_DEFAULT] = 0x1,
 692         [MLX4_FS_MC_DEFAULT] = 0x3,
 693         [MLX4_FS_UC_SNIFFER] = 0x4,
 694         [MLX4_FS_MC_SNIFFER] = 0x5,
 695 };
 696
 697 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
 698                                     enum mlx4_net_trans_promisc_mode flow_type)
 699 {
 700         if (flow_type >= MLX4_FS_MODE_NUM) {
 701                 mlx4_err(dev, "Invalid flow type. type = %d\n", flow_type);
 702                 return -EINVAL;
 703         }
 704         return __promisc_mode[flow_type];
 705 }
 706 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_mode);
 707
 708 static void trans_rule_ctrl_to_hw(struct mlx4_net_trans_rule *ctrl,
 709                                   struct mlx4_net_trans_rule_hw_ctrl *hw)
 710 {
 711         u8 flags = 0;
 712
 713         flags = ctrl->queue_mode == MLX4_NET_TRANS_Q_LIFO ? 1 : 0;
 714         flags |= ctrl->exclusive ? (1 << 2) : 0;
 715         flags |= ctrl->allow_loopback ? (1 << 3) : 0;
 716
 717         hw->flags = flags;
 718         hw->type = __promisc_mode[ctrl->promisc_mode];
 719         hw->prio = cpu_to_be16(ctrl->priority);
 720         hw->port = ctrl->port;
 721         hw->qpn = cpu_to_be32(ctrl->qpn);
 722 }
 723
 724 const u16 __sw_id_hw[] = {
 725         [MLX4_NET_TRANS_RULE_ID_ETH]     = 0xE001,
 726         [MLX4_NET_TRANS_RULE_ID_IB]      = 0xE005,
 727         [MLX4_NET_TRANS_RULE_ID_IPV6]    = 0xE003,
 728         [MLX4_NET_TRANS_RULE_ID_IPV4]    = 0xE002,
 729         [MLX4_NET_TRANS_RULE_ID_TCP]     = 0xE004,
 730         [MLX4_NET_TRANS_RULE_ID_UDP]     = 0xE006,
 731         [MLX4_NET_TRANS_RULE_ID_VXLAN]   = 0xE008
 732 };
 733
 734 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
 735                                   enum mlx4_net_trans_rule_id id)
 736 {
 737         if (id >= MLX4_NET_TRANS_RULE_NUM) {
 738                 mlx4_err(dev, "Invalid network rule id. id = %d\n", id);
 739                 return -EINVAL;
 740         }
 741         return __sw_id_hw[id];
 742 }
 743 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_id);
 744
 745 static const int __rule_hw_sz[] = {
 746         [MLX4_NET_TRANS_RULE_ID_ETH] =
 747                 sizeof(struct mlx4_net_trans_rule_hw_eth),
 748         [MLX4_NET_TRANS_RULE_ID_IB] =
 749                 sizeof(struct mlx4_net_trans_rule_hw_ib),
 750         [MLX4_NET_TRANS_RULE_ID_IPV6] = 0,
 751         [MLX4_NET_TRANS_RULE_ID_IPV4] =
 752                 sizeof(struct mlx4_net_trans_rule_hw_ipv4),
 753         [MLX4_NET_TRANS_RULE_ID_TCP] =
 754                 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp),
 755         [MLX4_NET_TRANS_RULE_ID_UDP] =
 756                 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp),
 757         [MLX4_NET_TRANS_RULE_ID_VXLAN] =
 758                 sizeof(struct mlx4_net_trans_rule_hw_vxlan)
 759 };
 760
 761 int mlx4_hw_rule_sz(struct mlx4_dev *dev,
 762                enum mlx4_net_trans_rule_id id)
 763 {
 764         if (id >= MLX4_NET_TRANS_RULE_NUM) {
 765                 mlx4_err(dev, "Invalid network rule id. id = %d\n", id);
 766                 return -EINVAL;
 767         }
 768
 769         return __rule_hw_sz[id];
 770 }
 771 EXPORT_SYMBOL_GPL(mlx4_hw_rule_sz);
 772
 773 static int parse_trans_rule(struct mlx4_dev *dev, struct mlx4_spec_list *spec,
 774                             struct _rule_hw *rule_hw)
 775 {
 776         if (mlx4_hw_rule_sz(dev, spec->id) < 0)
 777                 return -EINVAL;
 778         memset(rule_hw, 0, mlx4_hw_rule_sz(dev, spec->id));
 779         rule_hw->id = cpu_to_be16(__sw_id_hw[spec->id]);
 780         rule_hw->size = mlx4_hw_rule_sz(dev, spec->id) >> 2;
 781
 782         switch (spec->id) {
 783         case MLX4_NET_TRANS_RULE_ID_ETH:
 784                 memcpy(rule_hw->eth.dst_mac, spec->eth.dst_mac, ETH_ALEN);
 785                 memcpy(rule_hw->eth.dst_mac_msk, spec->eth.dst_mac_msk,
 786                        ETH_ALEN);
 787                 memcpy(rule_hw->eth.src_mac, spec->eth.src_mac, ETH_ALEN);
 788                 memcpy(rule_hw->eth.src_mac_msk, spec->eth.src_mac_msk,
 789                        ETH_ALEN);
 790                 if (spec->eth.ether_type_enable) {
 791                         rule_hw->eth.ether_type_enable = 1;
 792                         rule_hw->eth.ether_type = spec->eth.ether_type;
 793                 }
 794                 rule_hw->eth.vlan_tag = spec->eth.vlan_id;
 795                 rule_hw->eth.vlan_tag_msk = spec->eth.vlan_id_msk;
 796                 break;
 797
 798         case MLX4_NET_TRANS_RULE_ID_IB:
 799                 rule_hw->ib.l3_qpn = spec->ib.l3_qpn;
 800                 rule_hw->ib.qpn_mask = spec->ib.qpn_msk;
 801                 memcpy(&rule_hw->ib.dst_gid, &spec->ib.dst_gid, 16);
 802                 memcpy(&rule_hw->ib.dst_gid_msk, &spec->ib.dst_gid_msk, 16);
 803                 break;
 804
 805         case MLX4_NET_TRANS_RULE_ID_IPV6:
 806                 return -EOPNOTSUPP;
 807
 808         case MLX4_NET_TRANS_RULE_ID_IPV4:
 809                 rule_hw->ipv4.src_ip = spec->ipv4.src_ip;
 810                 rule_hw->ipv4.src_ip_msk = spec->ipv4.src_ip_msk;
 811                 rule_hw->ipv4.dst_ip = spec->ipv4.dst_ip;
 812                 rule_hw->ipv4.dst_ip_msk = spec->ipv4.dst_ip_msk;
 813                 break;
 814
 815         case MLX4_NET_TRANS_RULE_ID_TCP:
 816         case MLX4_NET_TRANS_RULE_ID_UDP:
 817                 rule_hw->tcp_udp.dst_port = spec->tcp_udp.dst_port;
 818                 rule_hw->tcp_udp.dst_port_msk = spec->tcp_udp.dst_port_msk;
 819                 rule_hw->tcp_udp.src_port = spec->tcp_udp.src_port;
 820                 rule_hw->tcp_udp.src_port_msk = spec->tcp_udp.src_port_msk;
 821                 break;
 822
 823         case MLX4_NET_TRANS_RULE_ID_VXLAN:
 824                 rule_hw->vxlan.vni =
 825                         cpu_to_be32(be32_to_cpu(spec->vxlan.vni) << 8);
 826                 rule_hw->vxlan.vni_mask =
 827                         cpu_to_be32(be32_to_cpu(spec->vxlan.vni_mask) << 8);
 828                 break;
 829
 830         default:
 831                 return -EINVAL;
 832         }
 833
 834         return __rule_hw_sz[spec->id];
 835 }
 836
 837 static void mlx4_err_rule(struct mlx4_dev *dev, char *str,
 838                           struct mlx4_net_trans_rule *rule)
 839 {
 840 #define BUF_SIZE 256
 841         struct mlx4_spec_list *cur;
 842         char buf[BUF_SIZE];
 843         int len = 0;
 844
 845         mlx4_err(dev, "%s", str);
 846         len += snprintf(buf + len, BUF_SIZE - len,
 847                         "port = %d prio = 0x%x qp = 0x%x ",
 848                         rule->port, rule->priority, rule->qpn);
 849
 850         list_for_each_entry(cur, &rule->list, list) {
 851                 switch (cur->id) {
 852                 case MLX4_NET_TRANS_RULE_ID_ETH:
 853                         len += snprintf(buf + len, BUF_SIZE - len,
 854                                         "dmac = %pM ", &cur->eth.dst_mac);
 855                         if (cur->eth.ether_type)
 856                                 len += snprintf(buf + len, BUF_SIZE - len,
 857                                                 "ethertype = 0x%x ",
 858                                                 be16_to_cpu(cur->eth.ether_type));
 859                         if (cur->eth.vlan_id)
 860                                 len += snprintf(buf + len, BUF_SIZE - len,
 861                                                 "vlan-id = %d ",
 862                                                 be16_to_cpu(cur->eth.vlan_id));
 863                         break;
 864
 865                 case MLX4_NET_TRANS_RULE_ID_IPV4:
 866                         if (cur->ipv4.src_ip)
 867                                 len += snprintf(buf + len, BUF_SIZE - len,
 868                                                 "src-ip = %pI4 ",
 869                                                 &cur->ipv4.src_ip);
 870                         if (cur->ipv4.dst_ip)
 871                                 len += snprintf(buf + len, BUF_SIZE - len,
 872                                                 "dst-ip = %pI4 ",
 873                                                 &cur->ipv4.dst_ip);
 874                         break;
 875
 876                 case MLX4_NET_TRANS_RULE_ID_TCP:
 877                 case MLX4_NET_TRANS_RULE_ID_UDP:
 878                         if (cur->tcp_udp.src_port)
 879                                 len += snprintf(buf + len, BUF_SIZE - len,
 880                                                 "src-port = %d ",
 881                                                 be16_to_cpu(cur->tcp_udp.src_port));
 882                         if (cur->tcp_udp.dst_port)
 883                                 len += snprintf(buf + len, BUF_SIZE - len,
 884                                                 "dst-port = %d ",
 885                                                 be16_to_cpu(cur->tcp_udp.dst_port));
 886                         break;
 887
 888                 case MLX4_NET_TRANS_RULE_ID_IB:
 889                         len += snprintf(buf + len, BUF_SIZE - len,
 890                                         "dst-gid = %pI6\n", cur->ib.dst_gid);
 891                         len += snprintf(buf + len, BUF_SIZE - len,
 892                                         "dst-gid-mask = %pI6\n",
 893                                         cur->ib.dst_gid_msk);
 894                         break;
 895
 896                 case MLX4_NET_TRANS_RULE_ID_IPV6:
 897                         break;
 898
 899                 default:
 900                         break;
 901                 }
 902         }
 903         len += snprintf(buf + len, BUF_SIZE - len, "\n");
 904         mlx4_err(dev, "%s", buf);
 905
 906         if (len >= BUF_SIZE)
 907                 mlx4_err(dev, "Network rule error message was truncated, print buffer is too small\n");
 908 }
 909
 910 int mlx4_flow_attach(struct mlx4_dev *dev,
 911                      struct mlx4_net_trans_rule *rule, u64 *reg_id)
 912 {
 913         struct mlx4_cmd_mailbox *mailbox;
 914         struct mlx4_spec_list *cur;
 915         u32 size = 0;
 916         int ret;
 917
 918         mailbox = mlx4_alloc_cmd_mailbox(dev);
 919         if (IS_ERR(mailbox))
 920                 return PTR_ERR(mailbox);
 921
 922         trans_rule_ctrl_to_hw(rule, mailbox->buf);
 923
 924         size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
 925
 926         list_for_each_entry(cur, &rule->list, list) {
 927                 ret = parse_trans_rule(dev, cur, mailbox->buf + size);
 928                 if (ret < 0) {
 929                         mlx4_free_cmd_mailbox(dev, mailbox);
 930                         return ret;
 931                 }
 932                 size += ret;
 933         }
 934
 935         ret = mlx4_QP_FLOW_STEERING_ATTACH(dev, mailbox, size >> 2, reg_id);
 936         if (ret == -ENOMEM)
 937                 mlx4_err_rule(dev,
 938                               "mcg table is full. Fail to register network rule\n",
 939                               rule);
 940         else if (ret)
 941                 mlx4_err_rule(dev, "Fail to register network rule\n", rule);
 942
 943         mlx4_free_cmd_mailbox(dev, mailbox);
 944
 945         return ret;
 946 }
 947 EXPORT_SYMBOL_GPL(mlx4_flow_attach);
 948
 949 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id)
 950 {
 951         int err;
 952
 953         err = mlx4_QP_FLOW_STEERING_DETACH(dev, reg_id);
 954         if (err)
 955                 mlx4_err(dev, "Fail to detach network rule. registration id = 0x%llx\n",
 956                          reg_id);
 957         return err;
 958 }
 959 EXPORT_SYMBOL_GPL(mlx4_flow_detach);
 960
 961 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
 962                                       u32 max_range_qpn)
 963 {
 964         int err;
 965         u64 in_param;
 966
 967         in_param = ((u64) min_range_qpn) << 32;
 968         in_param |= ((u64) max_range_qpn) & 0xFFFFFFFF;
 969
 970         err = mlx4_cmd(dev, in_param, 0, 0,
 971                         MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
 972                         MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 973
 974         return err;
 975 }
 976 EXPORT_SYMBOL_GPL(mlx4_FLOW_STEERING_IB_UC_QP_RANGE);
 977
 978 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
 979                           int block_mcast_loopback, enum mlx4_protocol prot,
 980                           enum mlx4_steer_type steer)
 981 {
 982         struct mlx4_priv *priv = mlx4_priv(dev);
 983         struct mlx4_cmd_mailbox *mailbox;
 984         struct mlx4_mgm *mgm;
 985         u32 members_count;
 986         int index, prev;
 987         int link = 0;
 988         int i;
 989         int err;
 990         u8 port = gid[5];
 991         u8 new_entry = 0;
 992
 993         mailbox = mlx4_alloc_cmd_mailbox(dev);
 994         if (IS_ERR(mailbox))
 995                 return PTR_ERR(mailbox);
 996         mgm = mailbox->buf;
 997
 998         mutex_lock(&priv->mcg_table.mutex);
 999         err = find_entry(dev, port, gid, prot,
1000                          mailbox, &prev, &index);
1001         if (err)
1002                 goto out;
1003
1004         if (index != -1) {
1005                 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
1006                         new_entry = 1;
1007                         memcpy(mgm->gid, gid, 16);
1008                 }
1009         } else {
1010                 link = 1;
1011
1012                 index = mlx4_bitmap_alloc(&priv->mcg_table.bitmap);
1013                 if (index == -1) {
1014                         mlx4_err(dev, "No AMGM entries left\n");
1015                         err = -ENOMEM;
1016                         goto out;
1017                 }
1018                 index += dev->caps.num_mgms;
1019
1020                 new_entry = 1;
1021                 memset(mgm, 0, sizeof *mgm);
1022                 memcpy(mgm->gid, gid, 16);
1023         }
1024
1025         members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
1026         if (members_count == dev->caps.num_qp_per_mgm) {
1027                 mlx4_err(dev, "MGM at index %x is full\n", index);
1028                 err = -ENOMEM;
1029                 goto out;
1030         }
1031
1032         for (i = 0; i < members_count; ++i)
1033                 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) {
1034                         mlx4_dbg(dev, "QP %06x already a member of MGM\n", qp->qpn);
1035                         err = 0;
1036                         goto out;
1037                 }
1038
1039         if (block_mcast_loopback)
1040                 mgm->qp[members_count++] = cpu_to_be32((qp->qpn & MGM_QPN_MASK) |
1041                                                        (1U << MGM_BLCK_LB_BIT));
1042         else
1043                 mgm->qp[members_count++] = cpu_to_be32(qp->qpn & MGM_QPN_MASK);
1044
1045         mgm->members_count = cpu_to_be32(members_count | (u32) prot << 30);
1046
1047         err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1048         if (err)
1049                 goto out;
1050
1051         if (!link)
1052                 goto out;
1053
1054         err = mlx4_READ_ENTRY(dev, prev, mailbox);
1055         if (err)
1056                 goto out;
1057
1058         mgm->next_gid_index = cpu_to_be32(index << 6);
1059
1060         err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
1061         if (err)
1062                 goto out;
1063
1064 out:
1065         if (prot == MLX4_PROT_ETH) {
1066                 /* manage the steering entry for promisc mode */
1067                 if (new_entry)
1068                         new_steering_entry(dev, port, steer, index, qp->qpn);
1069                 else
1070                         existing_steering_entry(dev, port, steer,
1071                                                 index, qp->qpn);
1072         }
1073         if (err && link && index != -1) {
1074                 if (index < dev->caps.num_mgms)
1075                         mlx4_warn(dev, "Got AMGM index %d < %d\n",
1076                                   index, dev->caps.num_mgms);
1077                 else
1078                         mlx4_bitmap_free(&priv->mcg_table.bitmap,
1079                                          index - dev->caps.num_mgms, MLX4_USE_RR);
1080         }
1081         mutex_unlock(&priv->mcg_table.mutex);
1082
1083         mlx4_free_cmd_mailbox(dev, mailbox);
1084         return err;
1085 }
1086
1087 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1088                           enum mlx4_protocol prot, enum mlx4_steer_type steer)
1089 {
1090         struct mlx4_priv *priv = mlx4_priv(dev);
1091         struct mlx4_cmd_mailbox *mailbox;
1092         struct mlx4_mgm *mgm;
1093         u32 members_count;
1094         int prev, index;
1095         int i, loc = -1;
1096         int err;
1097         u8 port = gid[5];
1098         bool removed_entry = false;
1099
1100         mailbox = mlx4_alloc_cmd_mailbox(dev);
1101         if (IS_ERR(mailbox))
1102                 return PTR_ERR(mailbox);
1103         mgm = mailbox->buf;
1104
1105         mutex_lock(&priv->mcg_table.mutex);
1106
1107         err = find_entry(dev, port, gid, prot,
1108                          mailbox, &prev, &index);
1109         if (err)
1110                 goto out;
1111
1112         if (index == -1) {
1113                 mlx4_err(dev, "MGID %pI6 not found\n", gid);
1114                 err = -EINVAL;
1115                 goto out;
1116         }
1117
1118         /* if this pq is also a promisc qp, it shouldn't be removed */
1119         if (prot == MLX4_PROT_ETH &&
1120             check_duplicate_entry(dev, port, steer, index, qp->qpn))
1121                 goto out;
1122
1123         members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
1124         for (i = 0; i < members_count; ++i)
1125                 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) {
1126                         loc = i;
1127                         break;
1128                 }
1129
1130         if (loc == -1) {
1131                 mlx4_err(dev, "QP %06x not found in MGM\n", qp->qpn);
1132                 err = -EINVAL;
1133                 goto out;
1134         }
1135
1136         /* copy the last QP in this MGM over removed QP */
1137         mgm->qp[loc] = mgm->qp[members_count - 1];
1138         mgm->qp[members_count - 1] = 0;
1139         mgm->members_count = cpu_to_be32(--members_count | (u32) prot << 30);
1140
1141         if (prot == MLX4_PROT_ETH)
1142                 removed_entry = can_remove_steering_entry(dev, port, steer,
1143                                                                 index, qp->qpn);
1144         if (members_count && (prot != MLX4_PROT_ETH || !removed_entry)) {
1145                 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1146                 goto out;
1147         }
1148
1149         /* We are going to delete the entry, members count should be 0 */
1150         mgm->members_count = cpu_to_be32((u32) prot << 30);
1151
1152         if (prev == -1) {
1153                 /* Remove entry from MGM */
1154                 int amgm_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1155                 if (amgm_index) {
1156                         err = mlx4_READ_ENTRY(dev, amgm_index, mailbox);
1157                         if (err)
1158                                 goto out;
1159                 } else
1160                         memset(mgm->gid, 0, 16);
1161
1162                 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1163                 if (err)
1164                         goto out;
1165
1166                 if (amgm_index) {
1167                         if (amgm_index < dev->caps.num_mgms)
1168                                 mlx4_warn(dev, "MGM entry %d had AMGM index %d < %d\n",
1169                                           index, amgm_index, dev->caps.num_mgms);
1170                         else
1171                                 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1172                                                  amgm_index - dev->caps.num_mgms, MLX4_USE_RR);
1173                 }
1174         } else {
1175                 /* Remove entry from AMGM */
1176                 int cur_next_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1177                 err = mlx4_READ_ENTRY(dev, prev, mailbox);
1178                 if (err)
1179                         goto out;
1180
1181                 mgm->next_gid_index = cpu_to_be32(cur_next_index << 6);
1182
1183                 err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
1184                 if (err)
1185                         goto out;
1186
1187                 if (index < dev->caps.num_mgms)
1188                         mlx4_warn(dev, "entry %d had next AMGM index %d < %d\n",
1189                                   prev, index, dev->caps.num_mgms);
1190                 else
1191                         mlx4_bitmap_free(&priv->mcg_table.bitmap,
1192                                          index - dev->caps.num_mgms, MLX4_USE_RR);
1193         }
1194
1195 out:
1196         mutex_unlock(&priv->mcg_table.mutex);
1197
1198         mlx4_free_cmd_mailbox(dev, mailbox);
1199         return err;
1200 }
1201
1202 static int mlx4_QP_ATTACH(struct mlx4_dev *dev, struct mlx4_qp *qp,
1203                           u8 gid[16], u8 attach, u8 block_loopback,
1204                           enum mlx4_protocol prot)
1205 {
1206         struct mlx4_cmd_mailbox *mailbox;
1207         int err = 0;
1208         int qpn;
1209
1210         if (!mlx4_is_mfunc(dev))
1211                 return -EBADF;
1212
1213         mailbox = mlx4_alloc_cmd_mailbox(dev);
1214         if (IS_ERR(mailbox))
1215                 return PTR_ERR(mailbox);
1216
1217         memcpy(mailbox->buf, gid, 16);
1218         qpn = qp->qpn;
1219         qpn |= (prot << 28);
1220         if (attach && block_loopback)
1221                 qpn |= (1 << 31);
1222
1223         err = mlx4_cmd(dev, mailbox->dma, qpn, attach,
1224                        MLX4_CMD_QP_ATTACH, MLX4_CMD_TIME_CLASS_A,
1225                        MLX4_CMD_WRAPPED);
1226
1227         mlx4_free_cmd_mailbox(dev, mailbox);
1228         return err;
1229 }
1230
1231 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1232                               u8 gid[16], u8 port,
1233                               int block_mcast_loopback,
1234                               enum mlx4_protocol prot, u64 *reg_id)
1235 {
1236                 struct mlx4_spec_list spec = { {NULL} };
1237                 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
1238
1239                 struct mlx4_net_trans_rule rule = {
1240                         .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1241                         .exclusive = 0,
1242                         .promisc_mode = MLX4_FS_REGULAR,
1243                         .priority = MLX4_DOMAIN_NIC,
1244                 };
1245
1246                 rule.allow_loopback = !block_mcast_loopback;
1247                 rule.port = port;
1248                 rule.qpn = qp->qpn;
1249                 INIT_LIST_HEAD(&rule.list);
1250
1251                 switch (prot) {
1252                 case MLX4_PROT_ETH:
1253                         spec.id = MLX4_NET_TRANS_RULE_ID_ETH;
1254                         memcpy(spec.eth.dst_mac, &gid[10], ETH_ALEN);
1255                         memcpy(spec.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
1256                         break;
1257
1258                 case MLX4_PROT_IB_IPV6:
1259                         spec.id = MLX4_NET_TRANS_RULE_ID_IB;
1260                         memcpy(spec.ib.dst_gid, gid, 16);
1261                         memset(&spec.ib.dst_gid_msk, 0xff, 16);
1262                         break;
1263                 default:
1264                         return -EINVAL;
1265                 }
1266                 list_add_tail(&spec.list, &rule.list);
1267
1268                 return mlx4_flow_attach(dev, &rule, reg_id);
1269 }
1270
1271 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1272                           u8 port, int block_mcast_loopback,
1273                           enum mlx4_protocol prot, u64 *reg_id)
1274 {
1275         switch (dev->caps.steering_mode) {
1276         case MLX4_STEERING_MODE_A0:
1277                 if (prot == MLX4_PROT_ETH)
1278                         return 0;
1279
1280         case MLX4_STEERING_MODE_B0:
1281                 if (prot == MLX4_PROT_ETH)
1282                         gid[7] |= (MLX4_MC_STEER << 1);
1283
1284                 if (mlx4_is_mfunc(dev))
1285                         return mlx4_QP_ATTACH(dev, qp, gid, 1,
1286                                               block_mcast_loopback, prot);
1287                 return mlx4_qp_attach_common(dev, qp, gid,
1288                                              block_mcast_loopback, prot,
1289                                              MLX4_MC_STEER);
1290
1291         case MLX4_STEERING_MODE_DEVICE_MANAGED:
1292                 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
1293                                                  block_mcast_loopback,
1294                                                  prot, reg_id);
1295         default:
1296                 return -EINVAL;
1297         }
1298 }
1299 EXPORT_SYMBOL_GPL(mlx4_multicast_attach);
1300
1301 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1302                           enum mlx4_protocol prot, u64 reg_id)
1303 {
1304         switch (dev->caps.steering_mode) {
1305         case MLX4_STEERING_MODE_A0:
1306                 if (prot == MLX4_PROT_ETH)
1307                         return 0;
1308
1309         case MLX4_STEERING_MODE_B0:
1310                 if (prot == MLX4_PROT_ETH)
1311                         gid[7] |= (MLX4_MC_STEER << 1);
1312
1313                 if (mlx4_is_mfunc(dev))
1314                         return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1315
1316                 return mlx4_qp_detach_common(dev, qp, gid, prot,
1317                                              MLX4_MC_STEER);
1318
1319         case MLX4_STEERING_MODE_DEVICE_MANAGED:
1320                 return mlx4_flow_detach(dev, reg_id);
1321
1322         default:
1323                 return -EINVAL;
1324         }
1325 }
1326 EXPORT_SYMBOL_GPL(mlx4_multicast_detach);
1327
1328 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port,
1329                                 u32 qpn, enum mlx4_net_trans_promisc_mode mode)
1330 {
1331         struct mlx4_net_trans_rule rule;
1332         u64 *regid_p;
1333
1334         switch (mode) {
1335         case MLX4_FS_ALL_DEFAULT:
1336                 regid_p = &dev->regid_promisc_array[port];
1337                 break;
1338         case MLX4_FS_MC_DEFAULT:
1339                 regid_p = &dev->regid_allmulti_array[port];
1340                 break;
1341         default:
1342                 return -1;
1343         }
1344
1345         if (*regid_p != 0)
1346                 return -1;
1347
1348         rule.promisc_mode = mode;
1349         rule.port = port;
1350         rule.qpn = qpn;
1351         INIT_LIST_HEAD(&rule.list);
1352         mlx4_err(dev, "going promisc on %x\n", port);
1353
1354         return  mlx4_flow_attach(dev, &rule, regid_p);
1355 }
1356 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_add);
1357
1358 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1359                                    enum mlx4_net_trans_promisc_mode mode)
1360 {
1361         int ret;
1362         u64 *regid_p;
1363
1364         switch (mode) {
1365         case MLX4_FS_ALL_DEFAULT:
1366                 regid_p = &dev->regid_promisc_array[port];
1367                 break;
1368         case MLX4_FS_MC_DEFAULT:
1369                 regid_p = &dev->regid_allmulti_array[port];
1370                 break;
1371         default:
1372                 return -1;
1373         }
1374
1375         if (*regid_p == 0)
1376                 return -1;
1377
1378         ret =  mlx4_flow_detach(dev, *regid_p);
1379         if (ret == 0)
1380                 *regid_p = 0;
1381
1382         return ret;
1383 }
1384 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_remove);
1385
1386 int mlx4_unicast_attach(struct mlx4_dev *dev,
1387                         struct mlx4_qp *qp, u8 gid[16],
1388                         int block_mcast_loopback, enum mlx4_protocol prot)
1389 {
1390         if (prot == MLX4_PROT_ETH)
1391                 gid[7] |= (MLX4_UC_STEER << 1);
1392
1393         if (mlx4_is_mfunc(dev))
1394                 return mlx4_QP_ATTACH(dev, qp, gid, 1,
1395                                         block_mcast_loopback, prot);
1396
1397         return mlx4_qp_attach_common(dev, qp, gid, block_mcast_loopback,
1398                                         prot, MLX4_UC_STEER);
1399 }
1400 EXPORT_SYMBOL_GPL(mlx4_unicast_attach);
1401
1402 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1403                                u8 gid[16], enum mlx4_protocol prot)
1404 {
1405         if (prot == MLX4_PROT_ETH)
1406                 gid[7] |= (MLX4_UC_STEER << 1);
1407
1408         if (mlx4_is_mfunc(dev))
1409                 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1410
1411         return mlx4_qp_detach_common(dev, qp, gid, prot, MLX4_UC_STEER);
1412 }
1413 EXPORT_SYMBOL_GPL(mlx4_unicast_detach);
1414
1415 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1416                          struct mlx4_vhcr *vhcr,
1417                          struct mlx4_cmd_mailbox *inbox,
1418                          struct mlx4_cmd_mailbox *outbox,
1419                          struct mlx4_cmd_info *cmd)
1420 {
1421         u32 qpn = (u32) vhcr->in_param & 0xffffffff;
1422         int port = mlx4_slave_convert_port(dev, slave, vhcr->in_param >> 62);
1423         enum mlx4_steer_type steer = vhcr->in_modifier;
1424
1425         if (port < 0)
1426                 return -EINVAL;
1427
1428         /* Promiscuous unicast is not allowed in mfunc */
1429         if (mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)
1430                 return 0;
1431
1432         if (vhcr->op_modifier)
1433                 return add_promisc_qp(dev, port, steer, qpn);
1434         else
1435                 return remove_promisc_qp(dev, port, steer, qpn);
1436 }
1437
1438 static int mlx4_PROMISC(struct mlx4_dev *dev, u32 qpn,
1439                         enum mlx4_steer_type steer, u8 add, u8 port)
1440 {
1441         return mlx4_cmd(dev, (u64) qpn | (u64) port << 62, (u32) steer, add,
1442                         MLX4_CMD_PROMISC, MLX4_CMD_TIME_CLASS_A,
1443                         MLX4_CMD_WRAPPED);
1444 }
1445
1446 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1447 {
1448         if (mlx4_is_mfunc(dev))
1449                 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 1, port);
1450
1451         return add_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1452 }
1453 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_add);
1454
1455 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1456 {
1457         if (mlx4_is_mfunc(dev))
1458                 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 0, port);
1459
1460         return remove_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1461 }
1462 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_remove);
1463
1464 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1465 {
1466         if (mlx4_is_mfunc(dev))
1467                 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 1, port);
1468
1469         return add_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1470 }
1471 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_add);
1472
1473 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1474 {
1475         if (mlx4_is_mfunc(dev))
1476                 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 0, port);
1477
1478         return remove_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1479 }
1480 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_remove);
1481
1482 int mlx4_init_mcg_table(struct mlx4_dev *dev)
1483 {
1484         struct mlx4_priv *priv = mlx4_priv(dev);
1485         int err;
1486
1487         /* No need for mcg_table when fw managed the mcg table*/
1488         if (dev->caps.steering_mode ==
1489             MLX4_STEERING_MODE_DEVICE_MANAGED)
1490                 return 0;
1491         err = mlx4_bitmap_init(&priv->mcg_table.bitmap, dev->caps.num_amgms,
1492                                dev->caps.num_amgms - 1, 0, 0);
1493         if (err)
1494                 return err;
1495
1496         mutex_init(&priv->mcg_table.mutex);
1497
1498         return 0;
1499 }
1500
1501 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev)
1502 {
1503         if (dev->caps.steering_mode !=
1504             MLX4_STEERING_MODE_DEVICE_MANAGED)
1505                 mlx4_bitmap_cleanup(&mlx4_priv(dev)->mcg_table.bitmap);
1506 }