2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/string.h>
35 #include <linux/etherdevice.h>
37 #include <linux/mlx4/cmd.h>
38 #include <linux/export.h>
42 static const u8 zero_gid[16]; /* automatically initialized to 0 */
44 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev)
46 return 1 << dev->oper_log_mgm_entry_size;
49 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev)
51 return 4 * (mlx4_get_mgm_entry_size(dev) / 16 - 2);
54 static int mlx4_QP_FLOW_STEERING_ATTACH(struct mlx4_dev *dev,
55 struct mlx4_cmd_mailbox *mailbox,
62 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0,
63 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
72 static int mlx4_QP_FLOW_STEERING_DETACH(struct mlx4_dev *dev, u64 regid)
76 err = mlx4_cmd(dev, regid, 0, 0,
77 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
83 static int mlx4_READ_ENTRY(struct mlx4_dev *dev, int index,
84 struct mlx4_cmd_mailbox *mailbox)
86 return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG,
87 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
90 static int mlx4_WRITE_ENTRY(struct mlx4_dev *dev, int index,
91 struct mlx4_cmd_mailbox *mailbox)
93 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG,
94 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
97 static int mlx4_WRITE_PROMISC(struct mlx4_dev *dev, u8 port, u8 steer,
98 struct mlx4_cmd_mailbox *mailbox)
102 in_mod = (u32) port << 16 | steer << 1;
103 return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1,
104 MLX4_CMD_WRITE_MCG, MLX4_CMD_TIME_CLASS_A,
108 static int mlx4_GID_HASH(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
109 u16 *hash, u8 op_mod)
114 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod,
115 MLX4_CMD_MGID_HASH, MLX4_CMD_TIME_CLASS_A,
124 static struct mlx4_promisc_qp *get_promisc_qp(struct mlx4_dev *dev, u8 port,
125 enum mlx4_steer_type steer,
128 struct mlx4_steer *s_steer = &mlx4_priv(dev)->steer[port - 1];
129 struct mlx4_promisc_qp *pqp;
131 list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
140 * Add new entry to steering data structure.
141 * All promisc QPs should be added as well
143 static int new_steering_entry(struct mlx4_dev *dev, u8 port,
144 enum mlx4_steer_type steer,
145 unsigned int index, u32 qpn)
147 struct mlx4_steer *s_steer;
148 struct mlx4_cmd_mailbox *mailbox;
149 struct mlx4_mgm *mgm;
151 struct mlx4_steer_index *new_entry;
152 struct mlx4_promisc_qp *pqp;
153 struct mlx4_promisc_qp *dqp = NULL;
157 s_steer = &mlx4_priv(dev)->steer[port - 1];
158 new_entry = kzalloc(sizeof *new_entry, GFP_KERNEL);
162 INIT_LIST_HEAD(&new_entry->duplicates);
163 new_entry->index = index;
164 list_add_tail(&new_entry->list, &s_steer->steer_entries[steer]);
166 /* If the given qpn is also a promisc qp,
167 * it should be inserted to duplicates list
169 pqp = get_promisc_qp(dev, port, steer, qpn);
171 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
177 list_add_tail(&dqp->list, &new_entry->duplicates);
180 /* if no promisc qps for this vep, we are done */
181 if (list_empty(&s_steer->promisc_qps[steer]))
184 /* now need to add all the promisc qps to the new
185 * steering entry, as they should also receive the packets
186 * destined to this address */
187 mailbox = mlx4_alloc_cmd_mailbox(dev);
188 if (IS_ERR(mailbox)) {
194 err = mlx4_READ_ENTRY(dev, index, mailbox);
198 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
199 prot = be32_to_cpu(mgm->members_count) >> 30;
200 list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
201 /* don't add already existing qpn */
204 if (members_count == dev->caps.num_qp_per_mgm) {
211 mgm->qp[members_count++] = cpu_to_be32(pqp->qpn & MGM_QPN_MASK);
213 /* update the qps count and update the entry with all the promisc qps*/
214 mgm->members_count = cpu_to_be32(members_count | (prot << 30));
215 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
218 mlx4_free_cmd_mailbox(dev, mailbox);
223 list_del(&dqp->list);
226 list_del(&new_entry->list);
231 /* update the data structures with existing steering entry */
232 static int existing_steering_entry(struct mlx4_dev *dev, u8 port,
233 enum mlx4_steer_type steer,
234 unsigned int index, u32 qpn)
236 struct mlx4_steer *s_steer;
237 struct mlx4_steer_index *tmp_entry, *entry = NULL;
238 struct mlx4_promisc_qp *pqp;
239 struct mlx4_promisc_qp *dqp;
241 s_steer = &mlx4_priv(dev)->steer[port - 1];
243 pqp = get_promisc_qp(dev, port, steer, qpn);
245 return 0; /* nothing to do */
247 list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
248 if (tmp_entry->index == index) {
253 if (unlikely(!entry)) {
254 mlx4_warn(dev, "Steering entry at index %x is not registered\n", index);
258 /* the given qpn is listed as a promisc qpn
259 * we need to add it as a duplicate to this entry
260 * for future references */
261 list_for_each_entry(dqp, &entry->duplicates, list) {
263 return 0; /* qp is already duplicated */
266 /* add the qp as a duplicate on this index */
267 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
271 list_add_tail(&dqp->list, &entry->duplicates);
276 /* Check whether a qpn is a duplicate on steering entry
277 * If so, it should not be removed from mgm */
278 static bool check_duplicate_entry(struct mlx4_dev *dev, u8 port,
279 enum mlx4_steer_type steer,
280 unsigned int index, u32 qpn)
282 struct mlx4_steer *s_steer;
283 struct mlx4_steer_index *tmp_entry, *entry = NULL;
284 struct mlx4_promisc_qp *dqp, *tmp_dqp;
286 s_steer = &mlx4_priv(dev)->steer[port - 1];
288 /* if qp is not promisc, it cannot be duplicated */
289 if (!get_promisc_qp(dev, port, steer, qpn))
292 /* The qp is promisc qp so it is a duplicate on this index
293 * Find the index entry, and remove the duplicate */
294 list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
295 if (tmp_entry->index == index) {
300 if (unlikely(!entry)) {
301 mlx4_warn(dev, "Steering entry for index %x is not registered\n", index);
304 list_for_each_entry_safe(dqp, tmp_dqp, &entry->duplicates, list) {
305 if (dqp->qpn == qpn) {
306 list_del(&dqp->list);
313 /* I a steering entry contains only promisc QPs, it can be removed. */
314 static bool can_remove_steering_entry(struct mlx4_dev *dev, u8 port,
315 enum mlx4_steer_type steer,
316 unsigned int index, u32 tqpn)
318 struct mlx4_steer *s_steer;
319 struct mlx4_cmd_mailbox *mailbox;
320 struct mlx4_mgm *mgm;
321 struct mlx4_steer_index *entry = NULL, *tmp_entry;
327 s_steer = &mlx4_priv(dev)->steer[port - 1];
329 mailbox = mlx4_alloc_cmd_mailbox(dev);
334 if (mlx4_READ_ENTRY(dev, index, mailbox))
336 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
337 for (i = 0; i < members_count; i++) {
338 qpn = be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK;
339 if (!get_promisc_qp(dev, port, steer, qpn) && qpn != tqpn) {
340 /* the qp is not promisc, the entry can't be removed */
344 /* All the qps currently registered for this entry are promiscuous,
345 * Checking for duplicates */
347 list_for_each_entry_safe(entry, tmp_entry, &s_steer->steer_entries[steer], list) {
348 if (entry->index == index) {
349 if (list_empty(&entry->duplicates)) {
350 list_del(&entry->list);
353 /* This entry contains duplicates so it shouldn't be removed */
361 mlx4_free_cmd_mailbox(dev, mailbox);
365 static int add_promisc_qp(struct mlx4_dev *dev, u8 port,
366 enum mlx4_steer_type steer, u32 qpn)
368 struct mlx4_steer *s_steer;
369 struct mlx4_cmd_mailbox *mailbox;
370 struct mlx4_mgm *mgm;
371 struct mlx4_steer_index *entry;
372 struct mlx4_promisc_qp *pqp;
373 struct mlx4_promisc_qp *dqp;
379 struct mlx4_priv *priv = mlx4_priv(dev);
381 s_steer = &mlx4_priv(dev)->steer[port - 1];
383 mutex_lock(&priv->mcg_table.mutex);
385 if (get_promisc_qp(dev, port, steer, qpn)) {
386 err = 0; /* Noting to do, already exists */
390 pqp = kmalloc(sizeof *pqp, GFP_KERNEL);
397 mailbox = mlx4_alloc_cmd_mailbox(dev);
398 if (IS_ERR(mailbox)) {
404 /* the promisc qp needs to be added for each one of the steering
405 * entries, if it already exists, needs to be added as a duplicate
407 list_for_each_entry(entry, &s_steer->steer_entries[steer], list) {
408 err = mlx4_READ_ENTRY(dev, entry->index, mailbox);
412 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
413 prot = be32_to_cpu(mgm->members_count) >> 30;
415 for (i = 0; i < members_count; i++) {
416 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qpn) {
417 /* Entry already exists, add to duplicates */
418 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
424 list_add_tail(&dqp->list, &entry->duplicates);
429 /* Need to add the qpn to mgm */
430 if (members_count == dev->caps.num_qp_per_mgm) {
435 mgm->qp[members_count++] = cpu_to_be32(qpn & MGM_QPN_MASK);
436 mgm->members_count = cpu_to_be32(members_count | (prot << 30));
437 err = mlx4_WRITE_ENTRY(dev, entry->index, mailbox);
443 /* add the new qpn to list of promisc qps */
444 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
445 /* now need to add all the promisc qps to default entry */
446 memset(mgm, 0, sizeof *mgm);
448 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list)
449 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
450 mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
452 err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
456 mlx4_free_cmd_mailbox(dev, mailbox);
457 mutex_unlock(&priv->mcg_table.mutex);
461 list_del(&pqp->list);
463 mlx4_free_cmd_mailbox(dev, mailbox);
467 mutex_unlock(&priv->mcg_table.mutex);
471 static int remove_promisc_qp(struct mlx4_dev *dev, u8 port,
472 enum mlx4_steer_type steer, u32 qpn)
474 struct mlx4_priv *priv = mlx4_priv(dev);
475 struct mlx4_steer *s_steer;
476 struct mlx4_cmd_mailbox *mailbox;
477 struct mlx4_mgm *mgm;
478 struct mlx4_steer_index *entry;
479 struct mlx4_promisc_qp *pqp;
480 struct mlx4_promisc_qp *dqp;
483 bool back_to_list = false;
487 s_steer = &mlx4_priv(dev)->steer[port - 1];
488 mutex_lock(&priv->mcg_table.mutex);
490 pqp = get_promisc_qp(dev, port, steer, qpn);
491 if (unlikely(!pqp)) {
492 mlx4_warn(dev, "QP %x is not promiscuous QP\n", qpn);
498 /*remove from list of promisc qps */
499 list_del(&pqp->list);
501 /* set the default entry not to include the removed one */
502 mailbox = mlx4_alloc_cmd_mailbox(dev);
503 if (IS_ERR(mailbox)) {
509 memset(mgm, 0, sizeof *mgm);
511 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list)
512 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
513 mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
515 err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
519 /* remove the qp from all the steering entries*/
520 list_for_each_entry(entry, &s_steer->steer_entries[steer], list) {
522 list_for_each_entry(dqp, &entry->duplicates, list) {
523 if (dqp->qpn == qpn) {
529 /* a duplicate, no need to change the mgm,
530 * only update the duplicates list */
531 list_del(&dqp->list);
534 err = mlx4_READ_ENTRY(dev, entry->index, mailbox);
537 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
538 for (loc = -1, i = 0; i < members_count; ++i)
539 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qpn)
542 mgm->members_count = cpu_to_be32(--members_count |
543 (MLX4_PROT_ETH << 30));
544 mgm->qp[loc] = mgm->qp[i - 1];
547 err = mlx4_WRITE_ENTRY(dev, entry->index, mailbox);
555 mlx4_free_cmd_mailbox(dev, mailbox);
558 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
562 mutex_unlock(&priv->mcg_table.mutex);
567 * Caller must hold MCG table semaphore. gid and mgm parameters must
568 * be properly aligned for command interface.
570 * Returns 0 unless a firmware command error occurs.
572 * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1
573 * and *mgm holds MGM entry.
575 * if GID is found in AMGM, *index = index in AMGM, *prev = index of
576 * previous entry in hash chain and *mgm holds AMGM entry.
578 * If no AMGM exists for given gid, *index = -1, *prev = index of last
579 * entry in hash chain and *mgm holds end of hash chain.
581 static int find_entry(struct mlx4_dev *dev, u8 port,
582 u8 *gid, enum mlx4_protocol prot,
583 struct mlx4_cmd_mailbox *mgm_mailbox,
584 int *prev, int *index)
586 struct mlx4_cmd_mailbox *mailbox;
587 struct mlx4_mgm *mgm = mgm_mailbox->buf;
591 u8 op_mod = (prot == MLX4_PROT_ETH) ?
592 !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) : 0;
594 mailbox = mlx4_alloc_cmd_mailbox(dev);
599 memcpy(mgid, gid, 16);
601 err = mlx4_GID_HASH(dev, mailbox, &hash, op_mod);
602 mlx4_free_cmd_mailbox(dev, mailbox);
607 mlx4_dbg(dev, "Hash for %pI6 is %04x\n", gid, hash);
613 err = mlx4_READ_ENTRY(dev, *index, mgm_mailbox);
617 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
618 if (*index != hash) {
619 mlx4_err(dev, "Found zero MGID in AMGM.\n");
625 if (!memcmp(mgm->gid, gid, 16) &&
626 be32_to_cpu(mgm->members_count) >> 30 == prot)
630 *index = be32_to_cpu(mgm->next_gid_index) >> 6;
637 static const u8 __promisc_mode[] = {
638 [MLX4_FS_REGULAR] = 0x0,
639 [MLX4_FS_ALL_DEFAULT] = 0x1,
640 [MLX4_FS_MC_DEFAULT] = 0x3,
641 [MLX4_FS_UC_SNIFFER] = 0x4,
642 [MLX4_FS_MC_SNIFFER] = 0x5,
645 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
646 enum mlx4_net_trans_promisc_mode flow_type)
648 if (flow_type >= MLX4_FS_MODE_NUM) {
649 mlx4_err(dev, "Invalid flow type. type = %d\n", flow_type);
652 return __promisc_mode[flow_type];
654 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_mode);
656 static void trans_rule_ctrl_to_hw(struct mlx4_net_trans_rule *ctrl,
657 struct mlx4_net_trans_rule_hw_ctrl *hw)
661 flags = ctrl->queue_mode == MLX4_NET_TRANS_Q_LIFO ? 1 : 0;
662 flags |= ctrl->exclusive ? (1 << 2) : 0;
663 flags |= ctrl->allow_loopback ? (1 << 3) : 0;
666 hw->type = __promisc_mode[ctrl->promisc_mode];
667 hw->prio = cpu_to_be16(ctrl->priority);
668 hw->port = ctrl->port;
669 hw->qpn = cpu_to_be32(ctrl->qpn);
672 const u16 __sw_id_hw[] = {
673 [MLX4_NET_TRANS_RULE_ID_ETH] = 0xE001,
674 [MLX4_NET_TRANS_RULE_ID_IB] = 0xE005,
675 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0xE003,
676 [MLX4_NET_TRANS_RULE_ID_IPV4] = 0xE002,
677 [MLX4_NET_TRANS_RULE_ID_TCP] = 0xE004,
678 [MLX4_NET_TRANS_RULE_ID_UDP] = 0xE006
681 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
682 enum mlx4_net_trans_rule_id id)
684 if (id >= MLX4_NET_TRANS_RULE_NUM) {
685 mlx4_err(dev, "Invalid network rule id. id = %d\n", id);
688 return __sw_id_hw[id];
690 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_id);
692 static const int __rule_hw_sz[] = {
693 [MLX4_NET_TRANS_RULE_ID_ETH] =
694 sizeof(struct mlx4_net_trans_rule_hw_eth),
695 [MLX4_NET_TRANS_RULE_ID_IB] =
696 sizeof(struct mlx4_net_trans_rule_hw_ib),
697 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0,
698 [MLX4_NET_TRANS_RULE_ID_IPV4] =
699 sizeof(struct mlx4_net_trans_rule_hw_ipv4),
700 [MLX4_NET_TRANS_RULE_ID_TCP] =
701 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp),
702 [MLX4_NET_TRANS_RULE_ID_UDP] =
703 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp)
706 int mlx4_hw_rule_sz(struct mlx4_dev *dev,
707 enum mlx4_net_trans_rule_id id)
709 if (id >= MLX4_NET_TRANS_RULE_NUM) {
710 mlx4_err(dev, "Invalid network rule id. id = %d\n", id);
714 return __rule_hw_sz[id];
716 EXPORT_SYMBOL_GPL(mlx4_hw_rule_sz);
718 static int parse_trans_rule(struct mlx4_dev *dev, struct mlx4_spec_list *spec,
719 struct _rule_hw *rule_hw)
721 if (mlx4_hw_rule_sz(dev, spec->id) < 0)
723 memset(rule_hw, 0, mlx4_hw_rule_sz(dev, spec->id));
724 rule_hw->id = cpu_to_be16(__sw_id_hw[spec->id]);
725 rule_hw->size = mlx4_hw_rule_sz(dev, spec->id) >> 2;
728 case MLX4_NET_TRANS_RULE_ID_ETH:
729 memcpy(rule_hw->eth.dst_mac, spec->eth.dst_mac, ETH_ALEN);
730 memcpy(rule_hw->eth.dst_mac_msk, spec->eth.dst_mac_msk,
732 memcpy(rule_hw->eth.src_mac, spec->eth.src_mac, ETH_ALEN);
733 memcpy(rule_hw->eth.src_mac_msk, spec->eth.src_mac_msk,
735 if (spec->eth.ether_type_enable) {
736 rule_hw->eth.ether_type_enable = 1;
737 rule_hw->eth.ether_type = spec->eth.ether_type;
739 rule_hw->eth.vlan_tag = spec->eth.vlan_id;
740 rule_hw->eth.vlan_tag_msk = spec->eth.vlan_id_msk;
743 case MLX4_NET_TRANS_RULE_ID_IB:
744 rule_hw->ib.l3_qpn = spec->ib.l3_qpn;
745 rule_hw->ib.qpn_mask = spec->ib.qpn_msk;
746 memcpy(&rule_hw->ib.dst_gid, &spec->ib.dst_gid, 16);
747 memcpy(&rule_hw->ib.dst_gid_msk, &spec->ib.dst_gid_msk, 16);
750 case MLX4_NET_TRANS_RULE_ID_IPV6:
753 case MLX4_NET_TRANS_RULE_ID_IPV4:
754 rule_hw->ipv4.src_ip = spec->ipv4.src_ip;
755 rule_hw->ipv4.src_ip_msk = spec->ipv4.src_ip_msk;
756 rule_hw->ipv4.dst_ip = spec->ipv4.dst_ip;
757 rule_hw->ipv4.dst_ip_msk = spec->ipv4.dst_ip_msk;
760 case MLX4_NET_TRANS_RULE_ID_TCP:
761 case MLX4_NET_TRANS_RULE_ID_UDP:
762 rule_hw->tcp_udp.dst_port = spec->tcp_udp.dst_port;
763 rule_hw->tcp_udp.dst_port_msk = spec->tcp_udp.dst_port_msk;
764 rule_hw->tcp_udp.src_port = spec->tcp_udp.src_port;
765 rule_hw->tcp_udp.src_port_msk = spec->tcp_udp.src_port_msk;
772 return __rule_hw_sz[spec->id];
775 static void mlx4_err_rule(struct mlx4_dev *dev, char *str,
776 struct mlx4_net_trans_rule *rule)
779 struct mlx4_spec_list *cur;
783 mlx4_err(dev, "%s", str);
784 len += snprintf(buf + len, BUF_SIZE - len,
785 "port = %d prio = 0x%x qp = 0x%x ",
786 rule->port, rule->priority, rule->qpn);
788 list_for_each_entry(cur, &rule->list, list) {
790 case MLX4_NET_TRANS_RULE_ID_ETH:
791 len += snprintf(buf + len, BUF_SIZE - len,
792 "dmac = %pM ", &cur->eth.dst_mac);
793 if (cur->eth.ether_type)
794 len += snprintf(buf + len, BUF_SIZE - len,
796 be16_to_cpu(cur->eth.ether_type));
797 if (cur->eth.vlan_id)
798 len += snprintf(buf + len, BUF_SIZE - len,
800 be16_to_cpu(cur->eth.vlan_id));
803 case MLX4_NET_TRANS_RULE_ID_IPV4:
804 if (cur->ipv4.src_ip)
805 len += snprintf(buf + len, BUF_SIZE - len,
808 if (cur->ipv4.dst_ip)
809 len += snprintf(buf + len, BUF_SIZE - len,
814 case MLX4_NET_TRANS_RULE_ID_TCP:
815 case MLX4_NET_TRANS_RULE_ID_UDP:
816 if (cur->tcp_udp.src_port)
817 len += snprintf(buf + len, BUF_SIZE - len,
819 be16_to_cpu(cur->tcp_udp.src_port));
820 if (cur->tcp_udp.dst_port)
821 len += snprintf(buf + len, BUF_SIZE - len,
823 be16_to_cpu(cur->tcp_udp.dst_port));
826 case MLX4_NET_TRANS_RULE_ID_IB:
827 len += snprintf(buf + len, BUF_SIZE - len,
828 "dst-gid = %pI6\n", cur->ib.dst_gid);
829 len += snprintf(buf + len, BUF_SIZE - len,
830 "dst-gid-mask = %pI6\n",
831 cur->ib.dst_gid_msk);
834 case MLX4_NET_TRANS_RULE_ID_IPV6:
841 len += snprintf(buf + len, BUF_SIZE - len, "\n");
842 mlx4_err(dev, "%s", buf);
845 mlx4_err(dev, "Network rule error message was truncated, print buffer is too small.\n");
848 int mlx4_flow_attach(struct mlx4_dev *dev,
849 struct mlx4_net_trans_rule *rule, u64 *reg_id)
851 struct mlx4_cmd_mailbox *mailbox;
852 struct mlx4_spec_list *cur;
856 mailbox = mlx4_alloc_cmd_mailbox(dev);
858 return PTR_ERR(mailbox);
860 memset(mailbox->buf, 0, sizeof(struct mlx4_net_trans_rule_hw_ctrl));
861 trans_rule_ctrl_to_hw(rule, mailbox->buf);
863 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
865 list_for_each_entry(cur, &rule->list, list) {
866 ret = parse_trans_rule(dev, cur, mailbox->buf + size);
868 mlx4_free_cmd_mailbox(dev, mailbox);
874 ret = mlx4_QP_FLOW_STEERING_ATTACH(dev, mailbox, size >> 2, reg_id);
877 "mcg table is full. Fail to register network rule.\n",
880 mlx4_err_rule(dev, "Fail to register network rule.\n", rule);
882 mlx4_free_cmd_mailbox(dev, mailbox);
886 EXPORT_SYMBOL_GPL(mlx4_flow_attach);
888 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id)
892 err = mlx4_QP_FLOW_STEERING_DETACH(dev, reg_id);
894 mlx4_err(dev, "Fail to detach network rule. registration id = 0x%llx\n",
898 EXPORT_SYMBOL_GPL(mlx4_flow_detach);
900 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
901 int block_mcast_loopback, enum mlx4_protocol prot,
902 enum mlx4_steer_type steer)
904 struct mlx4_priv *priv = mlx4_priv(dev);
905 struct mlx4_cmd_mailbox *mailbox;
906 struct mlx4_mgm *mgm;
915 mailbox = mlx4_alloc_cmd_mailbox(dev);
917 return PTR_ERR(mailbox);
920 mutex_lock(&priv->mcg_table.mutex);
921 err = find_entry(dev, port, gid, prot,
922 mailbox, &prev, &index);
927 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
929 memcpy(mgm->gid, gid, 16);
934 index = mlx4_bitmap_alloc(&priv->mcg_table.bitmap);
936 mlx4_err(dev, "No AMGM entries left\n");
940 index += dev->caps.num_mgms;
943 memset(mgm, 0, sizeof *mgm);
944 memcpy(mgm->gid, gid, 16);
947 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
948 if (members_count == dev->caps.num_qp_per_mgm) {
949 mlx4_err(dev, "MGM at index %x is full.\n", index);
954 for (i = 0; i < members_count; ++i)
955 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) {
956 mlx4_dbg(dev, "QP %06x already a member of MGM\n", qp->qpn);
961 if (block_mcast_loopback)
962 mgm->qp[members_count++] = cpu_to_be32((qp->qpn & MGM_QPN_MASK) |
963 (1U << MGM_BLCK_LB_BIT));
965 mgm->qp[members_count++] = cpu_to_be32(qp->qpn & MGM_QPN_MASK);
967 mgm->members_count = cpu_to_be32(members_count | (u32) prot << 30);
969 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
976 err = mlx4_READ_ENTRY(dev, prev, mailbox);
980 mgm->next_gid_index = cpu_to_be32(index << 6);
982 err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
987 if (prot == MLX4_PROT_ETH) {
988 /* manage the steering entry for promisc mode */
990 new_steering_entry(dev, port, steer, index, qp->qpn);
992 existing_steering_entry(dev, port, steer,
995 if (err && link && index != -1) {
996 if (index < dev->caps.num_mgms)
997 mlx4_warn(dev, "Got AMGM index %d < %d",
998 index, dev->caps.num_mgms);
1000 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1001 index - dev->caps.num_mgms);
1003 mutex_unlock(&priv->mcg_table.mutex);
1005 mlx4_free_cmd_mailbox(dev, mailbox);
1009 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1010 enum mlx4_protocol prot, enum mlx4_steer_type steer)
1012 struct mlx4_priv *priv = mlx4_priv(dev);
1013 struct mlx4_cmd_mailbox *mailbox;
1014 struct mlx4_mgm *mgm;
1020 bool removed_entry = false;
1022 mailbox = mlx4_alloc_cmd_mailbox(dev);
1023 if (IS_ERR(mailbox))
1024 return PTR_ERR(mailbox);
1027 mutex_lock(&priv->mcg_table.mutex);
1029 err = find_entry(dev, port, gid, prot,
1030 mailbox, &prev, &index);
1035 mlx4_err(dev, "MGID %pI6 not found\n", gid);
1040 /* if this pq is also a promisc qp, it shouldn't be removed */
1041 if (prot == MLX4_PROT_ETH &&
1042 check_duplicate_entry(dev, port, steer, index, qp->qpn))
1045 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
1046 for (loc = -1, i = 0; i < members_count; ++i)
1047 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn)
1051 mlx4_err(dev, "QP %06x not found in MGM\n", qp->qpn);
1057 mgm->members_count = cpu_to_be32(--members_count | (u32) prot << 30);
1058 mgm->qp[loc] = mgm->qp[i - 1];
1061 if (prot == MLX4_PROT_ETH)
1062 removed_entry = can_remove_steering_entry(dev, port, steer,
1064 if (i != 1 && (prot != MLX4_PROT_ETH || !removed_entry)) {
1065 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1069 /* We are going to delete the entry, members count should be 0 */
1070 mgm->members_count = cpu_to_be32((u32) prot << 30);
1073 /* Remove entry from MGM */
1074 int amgm_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1076 err = mlx4_READ_ENTRY(dev, amgm_index, mailbox);
1080 memset(mgm->gid, 0, 16);
1082 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1087 if (amgm_index < dev->caps.num_mgms)
1088 mlx4_warn(dev, "MGM entry %d had AMGM index %d < %d",
1089 index, amgm_index, dev->caps.num_mgms);
1091 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1092 amgm_index - dev->caps.num_mgms);
1095 /* Remove entry from AMGM */
1096 int cur_next_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1097 err = mlx4_READ_ENTRY(dev, prev, mailbox);
1101 mgm->next_gid_index = cpu_to_be32(cur_next_index << 6);
1103 err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
1107 if (index < dev->caps.num_mgms)
1108 mlx4_warn(dev, "entry %d had next AMGM index %d < %d",
1109 prev, index, dev->caps.num_mgms);
1111 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1112 index - dev->caps.num_mgms);
1116 mutex_unlock(&priv->mcg_table.mutex);
1118 mlx4_free_cmd_mailbox(dev, mailbox);
1122 static int mlx4_QP_ATTACH(struct mlx4_dev *dev, struct mlx4_qp *qp,
1123 u8 gid[16], u8 attach, u8 block_loopback,
1124 enum mlx4_protocol prot)
1126 struct mlx4_cmd_mailbox *mailbox;
1130 if (!mlx4_is_mfunc(dev))
1133 mailbox = mlx4_alloc_cmd_mailbox(dev);
1134 if (IS_ERR(mailbox))
1135 return PTR_ERR(mailbox);
1137 memcpy(mailbox->buf, gid, 16);
1139 qpn |= (prot << 28);
1140 if (attach && block_loopback)
1143 err = mlx4_cmd(dev, mailbox->dma, qpn, attach,
1144 MLX4_CMD_QP_ATTACH, MLX4_CMD_TIME_CLASS_A,
1147 mlx4_free_cmd_mailbox(dev, mailbox);
1151 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1152 u8 gid[16], u8 port,
1153 int block_mcast_loopback,
1154 enum mlx4_protocol prot, u64 *reg_id)
1156 struct mlx4_spec_list spec = { {NULL} };
1157 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
1159 struct mlx4_net_trans_rule rule = {
1160 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1162 .promisc_mode = MLX4_FS_REGULAR,
1163 .priority = MLX4_DOMAIN_NIC,
1166 rule.allow_loopback = !block_mcast_loopback;
1169 INIT_LIST_HEAD(&rule.list);
1173 spec.id = MLX4_NET_TRANS_RULE_ID_ETH;
1174 memcpy(spec.eth.dst_mac, &gid[10], ETH_ALEN);
1175 memcpy(spec.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
1178 case MLX4_PROT_IB_IPV6:
1179 spec.id = MLX4_NET_TRANS_RULE_ID_IB;
1180 memcpy(spec.ib.dst_gid, gid, 16);
1181 memset(&spec.ib.dst_gid_msk, 0xff, 16);
1186 list_add_tail(&spec.list, &rule.list);
1188 return mlx4_flow_attach(dev, &rule, reg_id);
1191 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1192 u8 port, int block_mcast_loopback,
1193 enum mlx4_protocol prot, u64 *reg_id)
1195 switch (dev->caps.steering_mode) {
1196 case MLX4_STEERING_MODE_A0:
1197 if (prot == MLX4_PROT_ETH)
1200 case MLX4_STEERING_MODE_B0:
1201 if (prot == MLX4_PROT_ETH)
1202 gid[7] |= (MLX4_MC_STEER << 1);
1204 if (mlx4_is_mfunc(dev))
1205 return mlx4_QP_ATTACH(dev, qp, gid, 1,
1206 block_mcast_loopback, prot);
1207 return mlx4_qp_attach_common(dev, qp, gid,
1208 block_mcast_loopback, prot,
1211 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1212 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
1213 block_mcast_loopback,
1219 EXPORT_SYMBOL_GPL(mlx4_multicast_attach);
1221 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1222 enum mlx4_protocol prot, u64 reg_id)
1224 switch (dev->caps.steering_mode) {
1225 case MLX4_STEERING_MODE_A0:
1226 if (prot == MLX4_PROT_ETH)
1229 case MLX4_STEERING_MODE_B0:
1230 if (prot == MLX4_PROT_ETH)
1231 gid[7] |= (MLX4_MC_STEER << 1);
1233 if (mlx4_is_mfunc(dev))
1234 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1236 return mlx4_qp_detach_common(dev, qp, gid, prot,
1239 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1240 return mlx4_flow_detach(dev, reg_id);
1246 EXPORT_SYMBOL_GPL(mlx4_multicast_detach);
1248 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port,
1249 u32 qpn, enum mlx4_net_trans_promisc_mode mode)
1251 struct mlx4_net_trans_rule rule;
1255 case MLX4_FS_ALL_DEFAULT:
1256 regid_p = &dev->regid_promisc_array[port];
1258 case MLX4_FS_MC_DEFAULT:
1259 regid_p = &dev->regid_allmulti_array[port];
1268 rule.promisc_mode = mode;
1271 INIT_LIST_HEAD(&rule.list);
1272 mlx4_err(dev, "going promisc on %x\n", port);
1274 return mlx4_flow_attach(dev, &rule, regid_p);
1276 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_add);
1278 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1279 enum mlx4_net_trans_promisc_mode mode)
1285 case MLX4_FS_ALL_DEFAULT:
1286 regid_p = &dev->regid_promisc_array[port];
1288 case MLX4_FS_MC_DEFAULT:
1289 regid_p = &dev->regid_allmulti_array[port];
1298 ret = mlx4_flow_detach(dev, *regid_p);
1304 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_remove);
1306 int mlx4_unicast_attach(struct mlx4_dev *dev,
1307 struct mlx4_qp *qp, u8 gid[16],
1308 int block_mcast_loopback, enum mlx4_protocol prot)
1310 if (prot == MLX4_PROT_ETH)
1311 gid[7] |= (MLX4_UC_STEER << 1);
1313 if (mlx4_is_mfunc(dev))
1314 return mlx4_QP_ATTACH(dev, qp, gid, 1,
1315 block_mcast_loopback, prot);
1317 return mlx4_qp_attach_common(dev, qp, gid, block_mcast_loopback,
1318 prot, MLX4_UC_STEER);
1320 EXPORT_SYMBOL_GPL(mlx4_unicast_attach);
1322 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1323 u8 gid[16], enum mlx4_protocol prot)
1325 if (prot == MLX4_PROT_ETH)
1326 gid[7] |= (MLX4_UC_STEER << 1);
1328 if (mlx4_is_mfunc(dev))
1329 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1331 return mlx4_qp_detach_common(dev, qp, gid, prot, MLX4_UC_STEER);
1333 EXPORT_SYMBOL_GPL(mlx4_unicast_detach);
1335 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1336 struct mlx4_vhcr *vhcr,
1337 struct mlx4_cmd_mailbox *inbox,
1338 struct mlx4_cmd_mailbox *outbox,
1339 struct mlx4_cmd_info *cmd)
1341 u32 qpn = (u32) vhcr->in_param & 0xffffffff;
1342 u8 port = vhcr->in_param >> 62;
1343 enum mlx4_steer_type steer = vhcr->in_modifier;
1345 /* Promiscuous unicast is not allowed in mfunc */
1346 if (mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)
1349 if (vhcr->op_modifier)
1350 return add_promisc_qp(dev, port, steer, qpn);
1352 return remove_promisc_qp(dev, port, steer, qpn);
1355 static int mlx4_PROMISC(struct mlx4_dev *dev, u32 qpn,
1356 enum mlx4_steer_type steer, u8 add, u8 port)
1358 return mlx4_cmd(dev, (u64) qpn | (u64) port << 62, (u32) steer, add,
1359 MLX4_CMD_PROMISC, MLX4_CMD_TIME_CLASS_A,
1363 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1365 if (mlx4_is_mfunc(dev))
1366 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 1, port);
1368 return add_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1370 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_add);
1372 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1374 if (mlx4_is_mfunc(dev))
1375 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 0, port);
1377 return remove_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1379 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_remove);
1381 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1383 if (mlx4_is_mfunc(dev))
1384 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 1, port);
1386 return add_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1388 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_add);
1390 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1392 if (mlx4_is_mfunc(dev))
1393 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 0, port);
1395 return remove_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1397 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_remove);
1399 int mlx4_init_mcg_table(struct mlx4_dev *dev)
1401 struct mlx4_priv *priv = mlx4_priv(dev);
1404 /* No need for mcg_table when fw managed the mcg table*/
1405 if (dev->caps.steering_mode ==
1406 MLX4_STEERING_MODE_DEVICE_MANAGED)
1408 err = mlx4_bitmap_init(&priv->mcg_table.bitmap, dev->caps.num_amgms,
1409 dev->caps.num_amgms - 1, 0, 0);
1413 mutex_init(&priv->mcg_table.mutex);
1418 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev)
1420 if (dev->caps.steering_mode !=
1421 MLX4_STEERING_MODE_DEVICE_MANAGED)
1422 mlx4_bitmap_cleanup(&mlx4_priv(dev)->mcg_table.bitmap);