2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/timer.h>
43 #include <linux/semaphore.h>
44 #include <linux/workqueue.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/driver.h>
48 #include <linux/mlx4/doorbell.h>
49 #include <linux/mlx4/cmd.h>
51 #define DRV_NAME "mlx4_core"
52 #define DRV_VERSION "1.0"
53 #define DRV_RELDATE "July 14, 2011"
56 MLX4_HCR_BASE = 0x80680,
57 MLX4_HCR_SIZE = 0x0001c,
58 MLX4_CLR_INT_SIZE = 0x00008,
59 MLX4_SLAVE_COMM_BASE = 0x0,
60 MLX4_COMM_PAGESIZE = 0x1000
64 MLX4_MGM_ENTRY_SIZE = 0x100,
65 MLX4_QP_PER_MGM = 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
66 MLX4_MTT_ENTRY_PER_SEG = 8
70 MLX4_NUM_PDS = 1 << 15
74 MLX4_CMPT_TYPE_QP = 0,
75 MLX4_CMPT_TYPE_SRQ = 1,
76 MLX4_CMPT_TYPE_CQ = 2,
77 MLX4_CMPT_TYPE_EQ = 3,
83 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
92 #define MLX4_COMM_TIME 10000
98 MLX4_COMM_CMD_VHCR_EN,
99 MLX4_COMM_CMD_VHCR_POST,
100 MLX4_COMM_CMD_FLR = 254
103 /*The flag indicates that the slave should delay the RESET cmd*/
104 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
105 /*indicates how many retries will be done if we are in the middle of FLR*/
106 #define NUM_OF_RESET_RETRIES 10
107 #define SLEEP_TIME_IN_RESET (2 * 1000)
119 MLX4_NUM_OF_RESOURCE_TYPE
122 enum mlx4_alloc_mode {
124 RES_OP_RESERVE_AND_MAP,
130 *Virtual HCR structures.
131 * mlx4_vhcr is the sw representation, in machine endianess
133 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
134 * to FW to go through communication channel.
135 * It is big endian, and has the same structure as the physical HCR
136 * used by command interface
149 struct mlx4_vhcr_cmd {
160 struct mlx4_cmd_info {
165 bool encode_slave_id;
166 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
167 struct mlx4_cmd_mailbox *inbox);
168 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
169 struct mlx4_cmd_mailbox *inbox,
170 struct mlx4_cmd_mailbox *outbox,
171 struct mlx4_cmd_info *cmd);
174 #ifdef CONFIG_MLX4_DEBUG
175 extern int mlx4_debug_level;
176 #else /* CONFIG_MLX4_DEBUG */
177 #define mlx4_debug_level (0)
178 #endif /* CONFIG_MLX4_DEBUG */
180 #define mlx4_dbg(mdev, format, arg...) \
182 if (mlx4_debug_level) \
183 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
186 #define mlx4_err(mdev, format, arg...) \
187 dev_err(&mdev->pdev->dev, format, ##arg)
188 #define mlx4_info(mdev, format, arg...) \
189 dev_info(&mdev->pdev->dev, format, ##arg)
190 #define mlx4_warn(mdev, format, arg...) \
191 dev_warn(&mdev->pdev->dev, format, ##arg)
193 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
194 #define ALL_SLAVES 0xff
204 unsigned long *table;
208 unsigned long **bits;
209 unsigned int *num_free;
216 struct mlx4_icm_table {
224 struct mlx4_icm **icm;
260 } __packed port_change;
262 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
264 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
265 } __packed comm_channel_arm;
270 } __packed mac_update;
276 } __packed flr_event;
284 struct mlx4_dev *dev;
285 void __iomem *doorbell;
291 struct mlx4_buf_list *page_list;
295 struct mlx4_slave_eqe {
301 struct mlx4_slave_event_eq_info {
307 struct mlx4_profile {
321 struct mlx4_icm *fw_icm;
322 struct mlx4_icm *aux_icm;
335 #define MGM_QPN_MASK 0x00FFFFFF
336 #define MGM_BLCK_LB_BIT 30
338 #define VLAN_FLTR_SIZE 128
340 struct mlx4_vlan_fltr {
341 __be32 entry[VLAN_FLTR_SIZE];
344 struct mlx4_promisc_qp {
345 struct list_head list;
349 struct mlx4_steer_index {
350 struct list_head list;
352 struct list_head duplicates;
356 __be32 next_gid_index;
357 __be32 members_count;
360 __be32 qp[MLX4_QP_PER_MGM];
363 struct mlx4_slave_state {
370 u16 mtu[MLX4_MAX_PORTS + 1];
371 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
372 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
373 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
374 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
375 struct mlx4_slave_event_eq_info event_eq;
379 /*initialized via the kzalloc*/
380 u8 is_slave_going_down;
386 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
389 struct mlx4_resource_tracker {
391 /* tree for each resources */
392 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
393 /* num_of_slave's lists, one per slave */
394 struct slave_list *slave_list;
397 #define SLAVE_EVENT_EQ_SIZE 128
398 struct mlx4_slave_event_eq {
402 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
405 struct mlx4_master_qp0_state {
406 int proxy_qp0_active;
411 struct mlx4_mfunc_master_ctx {
412 struct mlx4_slave_state *slave_state;
413 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
414 int init_port_ref[MLX4_MAX_PORTS + 1];
415 u16 max_mtu[MLX4_MAX_PORTS + 1];
416 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
417 struct mlx4_resource_tracker res_tracker;
418 struct workqueue_struct *comm_wq;
419 struct work_struct comm_work;
420 struct work_struct slave_event_work;
421 struct work_struct slave_flr_event_work;
422 spinlock_t slave_state_lock;
423 __be32 comm_arm_bit_vector[4];
424 struct mlx4_eqe cmd_eqe;
425 struct mlx4_slave_event_eq slave_eq;
426 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
430 struct mlx4_comm __iomem *comm;
431 struct mlx4_vhcr_cmd *vhcr;
434 struct mlx4_mfunc_master_ctx master;
438 struct pci_pool *pool;
440 struct mutex hcr_mutex;
441 struct semaphore poll_sem;
442 struct semaphore event_sem;
443 struct semaphore slave_sem;
445 spinlock_t context_lock;
447 struct mlx4_cmd_context *context;
454 struct mlx4_uar_table {
455 struct mlx4_bitmap bitmap;
458 struct mlx4_mr_table {
459 struct mlx4_bitmap mpt_bitmap;
460 struct mlx4_buddy mtt_buddy;
463 struct mlx4_icm_table mtt_table;
464 struct mlx4_icm_table dmpt_table;
467 struct mlx4_cq_table {
468 struct mlx4_bitmap bitmap;
470 struct radix_tree_root tree;
471 struct mlx4_icm_table table;
472 struct mlx4_icm_table cmpt_table;
475 struct mlx4_eq_table {
476 struct mlx4_bitmap bitmap;
478 void __iomem *clr_int;
479 void __iomem **uar_map;
482 struct mlx4_icm_table table;
483 struct mlx4_icm_table cmpt_table;
488 struct mlx4_srq_table {
489 struct mlx4_bitmap bitmap;
491 struct radix_tree_root tree;
492 struct mlx4_icm_table table;
493 struct mlx4_icm_table cmpt_table;
496 struct mlx4_qp_table {
497 struct mlx4_bitmap bitmap;
501 struct mlx4_icm_table qp_table;
502 struct mlx4_icm_table auxc_table;
503 struct mlx4_icm_table altc_table;
504 struct mlx4_icm_table rdmarc_table;
505 struct mlx4_icm_table cmpt_table;
508 struct mlx4_mcg_table {
510 struct mlx4_bitmap bitmap;
511 struct mlx4_icm_table table;
514 struct mlx4_catas_err {
516 struct timer_list timer;
517 struct list_head list;
520 #define MLX4_MAX_MAC_NUM 128
521 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
523 struct mlx4_mac_table {
524 __be64 entries[MLX4_MAX_MAC_NUM];
525 int refs[MLX4_MAX_MAC_NUM];
531 #define MLX4_MAX_VLAN_NUM 128
532 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
534 struct mlx4_vlan_table {
535 __be32 entries[MLX4_MAX_VLAN_NUM];
536 int refs[MLX4_MAX_VLAN_NUM];
542 struct mlx4_mac_entry {
546 struct mlx4_port_info {
547 struct mlx4_dev *dev;
550 struct device_attribute port_attr;
551 enum mlx4_port_type tmp_type;
552 struct mlx4_mac_table mac_table;
553 struct radix_tree_root mac_tree;
554 struct mlx4_vlan_table vlan_table;
559 struct mlx4_dev *dev;
560 u8 do_sense_port[MLX4_MAX_PORTS + 1];
561 u8 sense_allowed[MLX4_MAX_PORTS + 1];
562 struct delayed_work sense_poll;
565 struct mlx4_msix_ctl {
567 spinlock_t pool_lock;
571 struct list_head promisc_qps[MLX4_NUM_STEERS];
572 struct list_head steer_entries[MLX4_NUM_STEERS];
573 struct list_head high_prios;
579 struct list_head dev_list;
580 struct list_head ctx_list;
583 struct list_head pgdir_list;
584 struct mutex pgdir_mutex;
588 struct mlx4_mfunc mfunc;
590 struct mlx4_bitmap pd_bitmap;
591 struct mlx4_bitmap xrcd_bitmap;
592 struct mlx4_uar_table uar_table;
593 struct mlx4_mr_table mr_table;
594 struct mlx4_cq_table cq_table;
595 struct mlx4_eq_table eq_table;
596 struct mlx4_srq_table srq_table;
597 struct mlx4_qp_table qp_table;
598 struct mlx4_mcg_table mcg_table;
599 struct mlx4_bitmap counters_bitmap;
601 struct mlx4_catas_err catas_err;
603 void __iomem *clr_base;
605 struct mlx4_uar driver_uar;
607 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
608 struct mlx4_sense sense;
609 struct mutex port_mutex;
610 struct mlx4_msix_ctl msix_ctl;
611 struct mlx4_steer *steer;
612 struct list_head bf_list;
613 struct mutex bf_mutex;
614 struct io_mapping *bf_mapping;
617 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
619 return container_of(dev, struct mlx4_priv, dev);
622 #define MLX4_SENSE_RANGE (HZ * 3)
624 extern struct workqueue_struct *mlx4_wq;
626 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
627 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
628 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
629 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
630 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
631 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
632 u32 reserved_bot, u32 resetrved_top);
633 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
635 int mlx4_reset(struct mlx4_dev *dev);
637 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
638 void mlx4_free_eq_table(struct mlx4_dev *dev);
640 int mlx4_init_pd_table(struct mlx4_dev *dev);
641 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
642 int mlx4_init_uar_table(struct mlx4_dev *dev);
643 int mlx4_init_mr_table(struct mlx4_dev *dev);
644 int mlx4_init_eq_table(struct mlx4_dev *dev);
645 int mlx4_init_cq_table(struct mlx4_dev *dev);
646 int mlx4_init_qp_table(struct mlx4_dev *dev);
647 int mlx4_init_srq_table(struct mlx4_dev *dev);
648 int mlx4_init_mcg_table(struct mlx4_dev *dev);
650 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
651 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
652 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
653 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
654 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
655 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
656 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
657 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
658 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
660 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
661 struct mlx4_vhcr *vhcr,
662 struct mlx4_cmd_mailbox *inbox,
663 struct mlx4_cmd_mailbox *outbox,
664 struct mlx4_cmd_info *cmd);
665 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
666 struct mlx4_vhcr *vhcr,
667 struct mlx4_cmd_mailbox *inbox,
668 struct mlx4_cmd_mailbox *outbox,
669 struct mlx4_cmd_info *cmd);
670 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
671 struct mlx4_vhcr *vhcr,
672 struct mlx4_cmd_mailbox *inbox,
673 struct mlx4_cmd_mailbox *outbox,
674 struct mlx4_cmd_info *cmd);
675 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
676 struct mlx4_vhcr *vhcr,
677 struct mlx4_cmd_mailbox *inbox,
678 struct mlx4_cmd_mailbox *outbox,
679 struct mlx4_cmd_info *cmd);
680 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
681 struct mlx4_vhcr *vhcr,
682 struct mlx4_cmd_mailbox *inbox,
683 struct mlx4_cmd_mailbox *outbox,
684 struct mlx4_cmd_info *cmd);
685 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
686 struct mlx4_vhcr *vhcr,
687 struct mlx4_cmd_mailbox *inbox,
688 struct mlx4_cmd_mailbox *outbox,
689 struct mlx4_cmd_info *cmd);
690 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
691 struct mlx4_vhcr *vhcr,
692 struct mlx4_cmd_mailbox *inbox,
693 struct mlx4_cmd_mailbox *outbox,
694 struct mlx4_cmd_info *cmd);
696 void mlx4_start_catas_poll(struct mlx4_dev *dev);
697 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
698 void mlx4_catas_init(void);
699 int mlx4_restart_one(struct pci_dev *pdev);
700 int mlx4_register_device(struct mlx4_dev *dev);
701 void mlx4_unregister_device(struct mlx4_dev *dev);
702 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
705 struct mlx4_init_hca_param;
707 u64 mlx4_make_profile(struct mlx4_dev *dev,
708 struct mlx4_profile *request,
709 struct mlx4_dev_cap *dev_cap,
710 struct mlx4_init_hca_param *init_hca);
711 void mlx4_master_comm_channel(struct work_struct *work);
712 void mlx4_gen_slave_eqe(struct work_struct *work);
713 void mlx4_master_handle_slave_flr(struct work_struct *work);
715 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
716 struct mlx4_vhcr *vhcr,
717 struct mlx4_cmd_mailbox *inbox,
718 struct mlx4_cmd_mailbox *outbox,
719 struct mlx4_cmd_info *cmd);
720 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
721 struct mlx4_vhcr *vhcr,
722 struct mlx4_cmd_mailbox *inbox,
723 struct mlx4_cmd_mailbox *outbox,
724 struct mlx4_cmd_info *cmd);
725 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
726 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
727 struct mlx4_cmd_mailbox *outbox,
728 struct mlx4_cmd_info *cmd);
729 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
730 struct mlx4_vhcr *vhcr,
731 struct mlx4_cmd_mailbox *inbox,
732 struct mlx4_cmd_mailbox *outbox,
733 struct mlx4_cmd_info *cmd);
734 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
735 struct mlx4_vhcr *vhcr,
736 struct mlx4_cmd_mailbox *inbox,
737 struct mlx4_cmd_mailbox *outbox,
738 struct mlx4_cmd_info *cmd);
739 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
740 struct mlx4_vhcr *vhcr,
741 struct mlx4_cmd_mailbox *inbox,
742 struct mlx4_cmd_mailbox *outbox,
743 struct mlx4_cmd_info *cmd);
744 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
745 struct mlx4_vhcr *vhcr,
746 struct mlx4_cmd_mailbox *inbox,
747 struct mlx4_cmd_mailbox *outbox,
748 struct mlx4_cmd_info *cmd);
749 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
750 struct mlx4_vhcr *vhcr,
751 struct mlx4_cmd_mailbox *inbox,
752 struct mlx4_cmd_mailbox *outbox,
753 struct mlx4_cmd_info *cmd);
754 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
755 struct mlx4_vhcr *vhcr,
756 struct mlx4_cmd_mailbox *inbox,
757 struct mlx4_cmd_mailbox *outbox,
758 struct mlx4_cmd_info *cmd);
759 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
760 struct mlx4_vhcr *vhcr,
761 struct mlx4_cmd_mailbox *inbox,
762 struct mlx4_cmd_mailbox *outbox,
763 struct mlx4_cmd_info *cmd);
764 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
765 struct mlx4_vhcr *vhcr,
766 struct mlx4_cmd_mailbox *inbox,
767 struct mlx4_cmd_mailbox *outbox,
768 struct mlx4_cmd_info *cmd);
769 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
770 struct mlx4_vhcr *vhcr,
771 struct mlx4_cmd_mailbox *inbox,
772 struct mlx4_cmd_mailbox *outbox,
773 struct mlx4_cmd_info *cmd);
774 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
775 struct mlx4_vhcr *vhcr,
776 struct mlx4_cmd_mailbox *inbox,
777 struct mlx4_cmd_mailbox *outbox,
778 struct mlx4_cmd_info *cmd);
779 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
780 struct mlx4_vhcr *vhcr,
781 struct mlx4_cmd_mailbox *inbox,
782 struct mlx4_cmd_mailbox *outbox,
783 struct mlx4_cmd_info *cmd);
784 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
785 struct mlx4_vhcr *vhcr,
786 struct mlx4_cmd_mailbox *inbox,
787 struct mlx4_cmd_mailbox *outbox,
788 struct mlx4_cmd_info *cmd);
789 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
790 struct mlx4_vhcr *vhcr,
791 struct mlx4_cmd_mailbox *inbox,
792 struct mlx4_cmd_mailbox *outbox,
793 struct mlx4_cmd_info *cmd);
794 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
795 struct mlx4_vhcr *vhcr,
796 struct mlx4_cmd_mailbox *inbox,
797 struct mlx4_cmd_mailbox *outbox,
798 struct mlx4_cmd_info *cmd);
799 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
800 struct mlx4_vhcr *vhcr,
801 struct mlx4_cmd_mailbox *inbox,
802 struct mlx4_cmd_mailbox *outbox,
803 struct mlx4_cmd_info *cmd);
805 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
807 int mlx4_cmd_init(struct mlx4_dev *dev);
808 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
809 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
810 int mlx4_cmd_use_events(struct mlx4_dev *dev);
811 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
813 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
814 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
816 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
818 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
820 void mlx4_handle_catas_err(struct mlx4_dev *dev);
822 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
823 enum mlx4_port_type *type);
824 void mlx4_do_sense_ports(struct mlx4_dev *dev,
825 enum mlx4_port_type *stype,
826 enum mlx4_port_type *defaults);
827 void mlx4_start_sense(struct mlx4_dev *dev);
828 void mlx4_stop_sense(struct mlx4_dev *dev);
829 void mlx4_sense_init(struct mlx4_dev *dev);
830 int mlx4_check_port_params(struct mlx4_dev *dev,
831 enum mlx4_port_type *port_type);
832 int mlx4_change_port_types(struct mlx4_dev *dev,
833 enum mlx4_port_type *port_types);
835 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
836 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
838 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
839 /* resource tracker functions*/
840 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
841 enum mlx4_resource resource_type,
842 int resource_id, int *slave);
843 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
844 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
846 void mlx4_free_resource_tracker(struct mlx4_dev *dev);
848 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
849 struct mlx4_vhcr *vhcr,
850 struct mlx4_cmd_mailbox *inbox,
851 struct mlx4_cmd_mailbox *outbox,
852 struct mlx4_cmd_info *cmd);
853 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
854 struct mlx4_vhcr *vhcr,
855 struct mlx4_cmd_mailbox *inbox,
856 struct mlx4_cmd_mailbox *outbox,
857 struct mlx4_cmd_info *cmd);
858 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
859 struct mlx4_vhcr *vhcr,
860 struct mlx4_cmd_mailbox *inbox,
861 struct mlx4_cmd_mailbox *outbox,
862 struct mlx4_cmd_info *cmd);
863 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
864 struct mlx4_vhcr *vhcr,
865 struct mlx4_cmd_mailbox *inbox,
866 struct mlx4_cmd_mailbox *outbox,
867 struct mlx4_cmd_info *cmd);
868 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
869 int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port);
872 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
873 struct mlx4_vhcr *vhcr,
874 struct mlx4_cmd_mailbox *inbox,
875 struct mlx4_cmd_mailbox *outbox,
876 struct mlx4_cmd_info *cmd);
878 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
879 struct mlx4_vhcr *vhcr,
880 struct mlx4_cmd_mailbox *inbox,
881 struct mlx4_cmd_mailbox *outbox,
882 struct mlx4_cmd_info *cmd);
883 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
884 enum mlx4_protocol prot, enum mlx4_steer_type steer);
885 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
886 int block_mcast_loopback, enum mlx4_protocol prot,
887 enum mlx4_steer_type steer);
888 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
889 struct mlx4_vhcr *vhcr,
890 struct mlx4_cmd_mailbox *inbox,
891 struct mlx4_cmd_mailbox *outbox,
892 struct mlx4_cmd_info *cmd);
893 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
894 struct mlx4_vhcr *vhcr,
895 struct mlx4_cmd_mailbox *inbox,
896 struct mlx4_cmd_mailbox *outbox,
897 struct mlx4_cmd_info *cmd);
898 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
899 int port, void *buf);
900 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
901 struct mlx4_cmd_mailbox *outbox);
902 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
903 struct mlx4_vhcr *vhcr,
904 struct mlx4_cmd_mailbox *inbox,
905 struct mlx4_cmd_mailbox *outbox,
906 struct mlx4_cmd_info *cmd);
907 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
908 struct mlx4_vhcr *vhcr,
909 struct mlx4_cmd_mailbox *inbox,
910 struct mlx4_cmd_mailbox *outbox,
911 struct mlx4_cmd_info *cmd);
912 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
913 struct mlx4_vhcr *vhcr,
914 struct mlx4_cmd_mailbox *inbox,
915 struct mlx4_cmd_mailbox *outbox,
916 struct mlx4_cmd_info *cmd);
918 static inline void set_param_l(u64 *arg, u32 val)
923 static inline void set_param_h(u64 *arg, u32 val)
925 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
928 static inline u32 get_param_l(u64 *arg)
930 return (u32) (*arg & 0xffffffff);
933 static inline u32 get_param_h(u64 *arg)
935 return (u32)(*arg >> 32);
938 #define NOT_MASKED_PD_BITS 17