2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/export.h>
38 #include <linux/slab.h>
39 #include <linux/kernel.h>
41 #include <linux/mlx4/cmd.h>
47 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
49 struct mlx4_mpt_entry {
63 __be32 first_byte_offset;
66 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
67 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
68 #define MLX4_MPT_FLAG_MIO (1 << 17)
69 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
70 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
71 #define MLX4_MPT_FLAG_REGION (1 << 8)
73 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
74 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
75 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
77 #define MLX4_MPT_STATUS_SW 0xF0
78 #define MLX4_MPT_STATUS_HW 0x00
80 static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
86 spin_lock(&buddy->lock);
88 for (o = order; o <= buddy->max_order; ++o)
89 if (buddy->num_free[o]) {
90 m = 1 << (buddy->max_order - o);
91 seg = find_first_bit(buddy->bits[o], m);
96 spin_unlock(&buddy->lock);
100 clear_bit(seg, buddy->bits[o]);
101 --buddy->num_free[o];
106 set_bit(seg ^ 1, buddy->bits[o]);
107 ++buddy->num_free[o];
110 spin_unlock(&buddy->lock);
117 static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
121 spin_lock(&buddy->lock);
123 while (test_bit(seg ^ 1, buddy->bits[order])) {
124 clear_bit(seg ^ 1, buddy->bits[order]);
125 --buddy->num_free[order];
130 set_bit(seg, buddy->bits[order]);
131 ++buddy->num_free[order];
133 spin_unlock(&buddy->lock);
136 static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
140 buddy->max_order = max_order;
141 spin_lock_init(&buddy->lock);
143 buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
145 buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free,
147 if (!buddy->bits || !buddy->num_free)
150 for (i = 0; i <= buddy->max_order; ++i) {
151 s = BITS_TO_LONGS(1 << (buddy->max_order - i));
152 buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
155 bitmap_zero(buddy->bits[i], 1 << (buddy->max_order - i));
158 set_bit(0, buddy->bits[buddy->max_order]);
159 buddy->num_free[buddy->max_order] = 1;
164 for (i = 0; i <= buddy->max_order; ++i)
165 kfree(buddy->bits[i]);
169 kfree(buddy->num_free);
174 static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
178 for (i = 0; i <= buddy->max_order; ++i)
179 kfree(buddy->bits[i]);
182 kfree(buddy->num_free);
185 static u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
187 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
190 seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, order);
194 if (mlx4_table_get_range(dev, &mr_table->mtt_table, seg,
195 seg + (1 << order) - 1)) {
196 mlx4_buddy_free(&mr_table->mtt_buddy, seg, order);
203 static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
209 if (mlx4_is_mfunc(dev)) {
210 set_param_l(&in_param, order);
211 err = mlx4_cmd_imm(dev, in_param, &out_param, RES_MTT,
212 RES_OP_RESERVE_AND_MAP,
214 MLX4_CMD_TIME_CLASS_A,
218 return get_param_l(&out_param);
220 return __mlx4_alloc_mtt_range(dev, order);
223 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
224 struct mlx4_mtt *mtt)
230 mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
233 mtt->page_shift = page_shift;
235 for (mtt->order = 0, i = dev->caps.mtts_per_seg; i < npages; i <<= 1)
238 mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order);
239 if (mtt->first_seg == -1)
244 EXPORT_SYMBOL_GPL(mlx4_mtt_init);
246 static void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg,
249 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
251 mlx4_buddy_free(&mr_table->mtt_buddy, first_seg, order);
252 mlx4_table_put_range(dev, &mr_table->mtt_table, first_seg,
253 first_seg + (1 << order) - 1);
256 static void mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order)
261 if (mlx4_is_mfunc(dev)) {
262 set_param_l(&in_param, first_seg);
263 set_param_h(&in_param, order);
264 err = mlx4_cmd(dev, in_param, RES_MTT, RES_OP_RESERVE_AND_MAP,
266 MLX4_CMD_TIME_CLASS_A,
269 mlx4_warn(dev, "Failed to free mtt range at:%d"
270 " order:%d\n", first_seg, order);
273 __mlx4_free_mtt_range(dev, first_seg, order);
276 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
281 mlx4_free_mtt_range(dev, mtt->first_seg, mtt->order);
283 EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);
285 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
287 return (u64) mtt->first_seg * dev->caps.mtt_entry_sz;
289 EXPORT_SYMBOL_GPL(mlx4_mtt_addr);
291 static u32 hw_index_to_key(u32 ind)
293 return (ind >> 24) | (ind << 8);
296 static u32 key_to_hw_index(u32 key)
298 return (key << 24) | (key >> 8);
301 static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
304 return mlx4_cmd(dev, mailbox->dma | dev->caps.function , mpt_index,
305 0, MLX4_CMD_SW2HW_MPT, MLX4_CMD_TIME_CLASS_B,
309 static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
312 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
313 !mailbox, MLX4_CMD_HW2SW_MPT,
314 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
317 static int mlx4_mr_reserve_range(struct mlx4_dev *dev, int cnt, int align,
320 struct mlx4_priv *priv = mlx4_priv(dev);
323 mridx = mlx4_bitmap_alloc_range(&priv->mr_table.mpt_bitmap, cnt, align);
331 EXPORT_SYMBOL_GPL(mlx4_mr_reserve_range);
333 static void mlx4_mr_release_range(struct mlx4_dev *dev, u32 base_mridx, int cnt)
335 struct mlx4_priv *priv = mlx4_priv(dev);
336 mlx4_bitmap_free_range(&priv->mr_table.mpt_bitmap, base_mridx, cnt);
338 EXPORT_SYMBOL_GPL(mlx4_mr_release_range);
340 static int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
341 u64 iova, u64 size, u32 access, int npages,
342 int page_shift, struct mlx4_mr *mr)
348 mr->enabled = MLX4_MR_DISABLED;
349 mr->key = hw_index_to_key(mridx);
351 return mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
353 EXPORT_SYMBOL_GPL(mlx4_mr_alloc_reserved);
355 static int mlx4_WRITE_MTT(struct mlx4_dev *dev,
356 struct mlx4_cmd_mailbox *mailbox,
359 return mlx4_cmd(dev, mailbox->dma, num_entries, 0, MLX4_CMD_WRITE_MTT,
360 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
363 static int __mlx4_mr_reserve(struct mlx4_dev *dev)
365 struct mlx4_priv *priv = mlx4_priv(dev);
367 return mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
370 static int mlx4_mr_reserve(struct mlx4_dev *dev)
374 if (mlx4_is_mfunc(dev)) {
375 if (mlx4_cmd_imm(dev, 0, &out_param, RES_MPT, RES_OP_RESERVE,
377 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
379 return get_param_l(&out_param);
381 return __mlx4_mr_reserve(dev);
384 static void __mlx4_mr_release(struct mlx4_dev *dev, u32 index)
386 struct mlx4_priv *priv = mlx4_priv(dev);
388 mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index);
391 static void mlx4_mr_release(struct mlx4_dev *dev, u32 index)
395 if (mlx4_is_mfunc(dev)) {
396 set_param_l(&in_param, index);
397 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_RESERVE,
399 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
400 mlx4_warn(dev, "Failed to release mr index:%d\n",
404 __mlx4_mr_release(dev, index);
407 static int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index)
409 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
411 return mlx4_table_get(dev, &mr_table->dmpt_table, index);
414 static int mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index)
418 if (mlx4_is_mfunc(dev)) {
419 set_param_l(¶m, index);
420 return mlx4_cmd_imm(dev, param, ¶m, RES_MPT, RES_OP_MAP_ICM,
422 MLX4_CMD_TIME_CLASS_A,
425 return __mlx4_mr_alloc_icm(dev, index);
428 static void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index)
430 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
432 mlx4_table_put(dev, &mr_table->dmpt_table, index);
435 static void mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index)
439 if (mlx4_is_mfunc(dev)) {
440 set_param_l(&in_param, index);
441 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_MAP_ICM,
442 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
444 mlx4_warn(dev, "Failed to free icm of mr index:%d\n",
448 return __mlx4_mr_free_icm(dev, index);
451 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
452 int npages, int page_shift, struct mlx4_mr *mr)
457 index = mlx4_mr_reserve(dev);
461 err = mlx4_mr_alloc_reserved(dev, index, pd, iova, size,
462 access, npages, page_shift, mr);
464 mlx4_mr_release(dev, index);
468 EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
470 static void mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr)
474 if (mr->enabled == MLX4_MR_EN_HW) {
475 err = mlx4_HW2SW_MPT(dev, NULL,
476 key_to_hw_index(mr->key) &
477 (dev->caps.num_mpts - 1));
479 mlx4_warn(dev, "xxx HW2SW_MPT failed (%d)\n", err);
481 mr->enabled = MLX4_MR_EN_SW;
483 mlx4_mtt_cleanup(dev, &mr->mtt);
485 EXPORT_SYMBOL_GPL(mlx4_mr_free_reserved);
487 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr)
489 mlx4_mr_free_reserved(dev, mr);
491 mlx4_mr_free_icm(dev, key_to_hw_index(mr->key));
492 mlx4_mr_release(dev, key_to_hw_index(mr->key));
494 EXPORT_SYMBOL_GPL(mlx4_mr_free);
496 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
498 struct mlx4_cmd_mailbox *mailbox;
499 struct mlx4_mpt_entry *mpt_entry;
502 err = mlx4_mr_alloc_icm(dev, key_to_hw_index(mr->key));
506 mailbox = mlx4_alloc_cmd_mailbox(dev);
507 if (IS_ERR(mailbox)) {
508 err = PTR_ERR(mailbox);
511 mpt_entry = mailbox->buf;
513 memset(mpt_entry, 0, sizeof *mpt_entry);
515 mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO |
516 MLX4_MPT_FLAG_REGION |
519 mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
520 mpt_entry->pd_flags = cpu_to_be32(mr->pd | MLX4_MPT_PD_FLAG_EN_INV);
521 mpt_entry->start = cpu_to_be64(mr->iova);
522 mpt_entry->length = cpu_to_be64(mr->size);
523 mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
525 if (mr->mtt.order < 0) {
526 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
527 mpt_entry->mtt_seg = 0;
529 mpt_entry->mtt_seg = cpu_to_be64(mlx4_mtt_addr(dev, &mr->mtt));
532 if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
533 /* fast register MR in free state */
534 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
535 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG |
536 MLX4_MPT_PD_FLAG_RAE);
537 mpt_entry->mtt_sz = cpu_to_be32((1 << mr->mtt.order) *
538 dev->caps.mtts_per_seg);
540 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
543 err = mlx4_SW2HW_MPT(dev, mailbox,
544 key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
546 mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
549 mr->enabled = MLX4_MR_EN_HW;
551 mlx4_free_cmd_mailbox(dev, mailbox);
556 mlx4_free_cmd_mailbox(dev, mailbox);
559 mlx4_mr_free_icm(dev, key_to_hw_index(mr->key));
562 EXPORT_SYMBOL_GPL(mlx4_mr_enable);
564 static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
565 int start_index, int npages, u64 *page_list)
567 struct mlx4_priv *priv = mlx4_priv(dev);
569 dma_addr_t dma_handle;
571 int s = start_index * sizeof (u64);
573 /* All MTTs must fit in the same page */
574 if (start_index / (PAGE_SIZE / sizeof (u64)) !=
575 (start_index + npages - 1) / (PAGE_SIZE / sizeof (u64)))
578 if (start_index & (dev->caps.mtts_per_seg - 1))
581 mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->first_seg +
582 s / dev->caps.mtt_entry_sz, &dma_handle);
586 dma_sync_single_for_cpu(&dev->pdev->dev, dma_handle,
587 npages * sizeof (u64), DMA_TO_DEVICE);
589 for (i = 0; i < npages; ++i)
590 mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
592 dma_sync_single_for_device(&dev->pdev->dev, dma_handle,
593 npages * sizeof (u64), DMA_TO_DEVICE);
598 static int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
599 int start_index, int npages, u64 *page_list)
605 chunk = min_t(int, PAGE_SIZE / sizeof(u64), npages);
606 err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list);
610 start_index += chunk;
616 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
617 int start_index, int npages, u64 *page_list)
619 struct mlx4_cmd_mailbox *mailbox = NULL;
620 __be64 *inbox = NULL;
628 if (mlx4_is_mfunc(dev)) {
629 mailbox = mlx4_alloc_cmd_mailbox(dev);
631 return PTR_ERR(mailbox);
632 inbox = mailbox->buf;
635 int s = mtt->first_seg * dev->caps.mtts_per_seg +
637 chunk = min_t(int, MLX4_MAILBOX_SIZE / sizeof(u64) -
638 dev->caps.mtts_per_seg, npages);
639 if (s / (PAGE_SIZE / sizeof(u64)) !=
640 (s + chunk - 1) / (PAGE_SIZE / sizeof(u64)))
641 chunk = PAGE_SIZE / sizeof(u64) -
642 (s % (PAGE_SIZE / sizeof(u64)));
644 inbox[0] = cpu_to_be64(mtt->first_seg *
645 dev->caps.mtts_per_seg +
648 for (i = 0; i < chunk; ++i)
649 inbox[i + 2] = cpu_to_be64(page_list[i] |
650 MLX4_MTT_FLAG_PRESENT);
651 err = mlx4_WRITE_MTT(dev, mailbox, chunk);
653 mlx4_free_cmd_mailbox(dev, mailbox);
658 start_index += chunk;
661 mlx4_free_cmd_mailbox(dev, mailbox);
665 return __mlx4_write_mtt(dev, mtt, start_index, npages, page_list);
667 EXPORT_SYMBOL_GPL(mlx4_write_mtt);
669 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
670 struct mlx4_buf *buf)
676 page_list = kmalloc(buf->npages * sizeof *page_list, GFP_KERNEL);
680 for (i = 0; i < buf->npages; ++i)
682 page_list[i] = buf->direct.map + (i << buf->page_shift);
684 page_list[i] = buf->page_list[i].map;
686 err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
691 EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);
693 int mlx4_init_mr_table(struct mlx4_dev *dev)
695 struct mlx4_priv *priv = mlx4_priv(dev);
696 struct mlx4_mr_table *mr_table = &priv->mr_table;
699 if (!is_power_of_2(dev->caps.num_mpts))
702 /* Nothing to do for slaves - all MR handling is forwarded
704 if (mlx4_is_slave(dev))
707 err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
708 ~0, dev->caps.reserved_mrws, 0);
712 err = mlx4_buddy_init(&mr_table->mtt_buddy,
713 ilog2(dev->caps.num_mtt_segs));
717 if (dev->caps.reserved_mtts) {
718 priv->reserved_mtts =
719 mlx4_alloc_mtt_range(dev,
720 fls(dev->caps.reserved_mtts - 1));
721 if (priv->reserved_mtts < 0) {
722 mlx4_warn(dev, "MTT table of order %d is too small.\n",
723 mr_table->mtt_buddy.max_order);
725 goto err_reserve_mtts;
732 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
735 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
740 void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
742 struct mlx4_priv *priv = mlx4_priv(dev);
743 struct mlx4_mr_table *mr_table = &priv->mr_table;
745 if (mlx4_is_slave(dev))
747 if (priv->reserved_mtts >= 0)
748 mlx4_free_mtt_range(dev, priv->reserved_mtts,
749 fls(dev->caps.reserved_mtts - 1));
750 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
751 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
754 static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list,
755 int npages, u64 iova)
759 if (npages > fmr->max_pages)
762 page_mask = (1 << fmr->page_shift) - 1;
764 /* We are getting page lists, so va must be page aligned. */
765 if (iova & page_mask)
768 /* Trust the user not to pass misaligned data in page_list */
770 for (i = 0; i < npages; ++i) {
771 if (page_list[i] & ~page_mask)
775 if (fmr->maps >= fmr->max_maps)
781 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
782 int npages, u64 iova, u32 *lkey, u32 *rkey)
787 err = mlx4_check_fmr(fmr, page_list, npages, iova);
793 key = key_to_hw_index(fmr->mr.key);
794 key += dev->caps.num_mpts;
795 *lkey = *rkey = fmr->mr.key = hw_index_to_key(key);
797 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
799 /* Make sure MPT status is visible before writing MTT entries */
802 dma_sync_single_for_cpu(&dev->pdev->dev, fmr->dma_handle,
803 npages * sizeof(u64), DMA_TO_DEVICE);
805 for (i = 0; i < npages; ++i)
806 fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
808 dma_sync_single_for_device(&dev->pdev->dev, fmr->dma_handle,
809 npages * sizeof(u64), DMA_TO_DEVICE);
811 fmr->mpt->key = cpu_to_be32(key);
812 fmr->mpt->lkey = cpu_to_be32(key);
813 fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift));
814 fmr->mpt->start = cpu_to_be64(iova);
816 /* Make MTT entries are visible before setting MPT status */
819 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW;
821 /* Make sure MPT status is visible before consumer can use FMR */
826 EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr);
828 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
829 int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
831 struct mlx4_priv *priv = mlx4_priv(dev);
835 if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
838 /* All MTTs must fit in the same page */
839 if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
842 fmr->page_shift = page_shift;
843 fmr->max_pages = max_pages;
844 fmr->max_maps = max_maps;
847 err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages,
848 page_shift, &fmr->mr);
852 mtt_seg = fmr->mr.mtt.first_seg * dev->caps.mtt_entry_sz;
854 fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
855 fmr->mr.mtt.first_seg,
865 mlx4_mr_free(dev, &fmr->mr);
868 EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);
870 static int mlx4_fmr_alloc_reserved(struct mlx4_dev *dev, u32 mridx,
871 u32 pd, u32 access, int max_pages,
872 int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
874 struct mlx4_priv *priv = mlx4_priv(dev);
877 if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
880 /* All MTTs must fit in the same page */
881 if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
884 fmr->page_shift = page_shift;
885 fmr->max_pages = max_pages;
886 fmr->max_maps = max_maps;
889 err = mlx4_mr_alloc_reserved(dev, mridx, pd, 0, 0, access, max_pages,
890 page_shift, &fmr->mr);
894 fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
895 fmr->mr.mtt.first_seg,
905 mlx4_mr_free_reserved(dev, &fmr->mr);
908 EXPORT_SYMBOL_GPL(mlx4_fmr_alloc_reserved);
910 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
912 struct mlx4_priv *priv = mlx4_priv(dev);
915 err = mlx4_mr_enable(dev, &fmr->mr);
919 fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table,
920 key_to_hw_index(fmr->mr.key), NULL);
926 EXPORT_SYMBOL_GPL(mlx4_fmr_enable);
928 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
929 u32 *lkey, u32 *rkey)
931 struct mlx4_cmd_mailbox *mailbox;
939 mailbox = mlx4_alloc_cmd_mailbox(dev);
940 if (IS_ERR(mailbox)) {
941 err = PTR_ERR(mailbox);
942 printk(KERN_WARNING "mlx4_ib: mlx4_alloc_cmd_mailbox"
943 " failed (%d)\n", err);
947 err = mlx4_HW2SW_MPT(dev, NULL,
948 key_to_hw_index(fmr->mr.key) &
949 (dev->caps.num_mpts - 1));
950 mlx4_free_cmd_mailbox(dev, mailbox);
952 printk(KERN_WARNING "mlx4_ib: mlx4_HW2SW_MPT failed (%d)\n",
956 fmr->mr.enabled = MLX4_MR_EN_SW;
958 EXPORT_SYMBOL_GPL(mlx4_fmr_unmap);
960 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
965 mlx4_mr_free(dev, &fmr->mr);
966 fmr->mr.enabled = MLX4_MR_DISABLED;
970 EXPORT_SYMBOL_GPL(mlx4_fmr_free);
972 static int mlx4_fmr_free_reserved(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
977 mlx4_mr_free_reserved(dev, &fmr->mr);
978 fmr->mr.enabled = MLX4_MR_DISABLED;
982 EXPORT_SYMBOL_GPL(mlx4_fmr_free_reserved);
984 int mlx4_SYNC_TPT(struct mlx4_dev *dev)
986 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000,
989 EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT);