2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
45 #include "mlx5_core.h"
57 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
58 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
59 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
60 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
61 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
62 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
63 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
64 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
65 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
66 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
67 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
71 struct mlx5_cmd_msg *in,
72 struct mlx5_cmd_msg *out,
73 void *uout, int uout_size,
75 void *context, int page_queue)
77 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
78 struct mlx5_cmd_work_ent *ent;
80 ent = kzalloc(sizeof(*ent), alloc_flags);
82 return ERR_PTR(-ENOMEM);
87 ent->uout_size = uout_size;
89 ent->context = context;
91 ent->page_queue = page_queue;
96 static u8 alloc_token(struct mlx5_cmd *cmd)
100 spin_lock(&cmd->token_lock);
105 spin_unlock(&cmd->token_lock);
110 static int alloc_ent(struct mlx5_cmd *cmd)
115 spin_lock_irqsave(&cmd->alloc_lock, flags);
116 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
117 if (ret < cmd->max_reg_cmds)
118 clear_bit(ret, &cmd->bitmask);
119 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
121 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
124 static void free_ent(struct mlx5_cmd *cmd, int idx)
128 spin_lock_irqsave(&cmd->alloc_lock, flags);
129 set_bit(idx, &cmd->bitmask);
130 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
135 return cmd->cmd_buf + (idx << cmd->log_stride);
138 static u8 xor8_buf(void *buf, size_t offset, int len)
143 int end = len + offset;
145 for (i = offset; i < end; i++)
151 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
153 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
154 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
156 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
159 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
165 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
167 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
168 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
170 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
171 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
174 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
176 struct mlx5_cmd_mailbox *next = msg->next;
178 int blen = size - min_t(int, sizeof(msg->first.data), size);
179 int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
180 / MLX5_CMD_DATA_BLOCK_SIZE;
183 for (i = 0; i < n && next; i++) {
184 calc_block_sig(next->buf);
189 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
191 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
193 calc_chain_sig(ent->in);
194 calc_chain_sig(ent->out);
198 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
200 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
204 own = ent->lay->status_own;
205 if (!(own & CMD_OWNER_HW)) {
209 usleep_range(5000, 10000);
210 } while (time_before(jiffies, poll_end));
212 ent->ret = -ETIMEDOUT;
215 static void free_cmd(struct mlx5_cmd_work_ent *ent)
221 static int verify_signature(struct mlx5_cmd_work_ent *ent)
223 struct mlx5_cmd_mailbox *next = ent->out->next;
226 int size = ent->out->len;
227 int blen = size - min_t(int, sizeof(ent->out->first.data), size);
228 int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
229 / MLX5_CMD_DATA_BLOCK_SIZE;
232 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
236 for (i = 0; i < n && next; i++) {
237 err = verify_block_sig(next->buf);
247 static void dump_buf(void *buf, int size, int data_only, int offset)
252 for (i = 0; i < size; i += 16) {
253 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
254 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
263 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
264 u32 *synd, u8 *status)
270 case MLX5_CMD_OP_TEARDOWN_HCA:
271 case MLX5_CMD_OP_DISABLE_HCA:
272 case MLX5_CMD_OP_MANAGE_PAGES:
273 case MLX5_CMD_OP_DESTROY_MKEY:
274 case MLX5_CMD_OP_DESTROY_EQ:
275 case MLX5_CMD_OP_DESTROY_CQ:
276 case MLX5_CMD_OP_DESTROY_QP:
277 case MLX5_CMD_OP_DESTROY_PSV:
278 case MLX5_CMD_OP_DESTROY_SRQ:
279 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
280 case MLX5_CMD_OP_DESTROY_DCT:
281 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
282 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
283 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
284 case MLX5_CMD_OP_DEALLOC_PD:
285 case MLX5_CMD_OP_DEALLOC_UAR:
286 case MLX5_CMD_OP_DETACH_FROM_MCG:
287 case MLX5_CMD_OP_DEALLOC_XRCD:
288 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
289 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
290 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
291 case MLX5_CMD_OP_DESTROY_LAG:
292 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
293 case MLX5_CMD_OP_DESTROY_TIR:
294 case MLX5_CMD_OP_DESTROY_SQ:
295 case MLX5_CMD_OP_DESTROY_RQ:
296 case MLX5_CMD_OP_DESTROY_RMP:
297 case MLX5_CMD_OP_DESTROY_TIS:
298 case MLX5_CMD_OP_DESTROY_RQT:
299 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
300 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
301 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
302 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
303 case MLX5_CMD_OP_2ERR_QP:
304 case MLX5_CMD_OP_2RST_QP:
305 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
306 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
307 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
308 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
309 case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
310 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
311 return MLX5_CMD_STAT_OK;
313 case MLX5_CMD_OP_QUERY_HCA_CAP:
314 case MLX5_CMD_OP_QUERY_ADAPTER:
315 case MLX5_CMD_OP_INIT_HCA:
316 case MLX5_CMD_OP_ENABLE_HCA:
317 case MLX5_CMD_OP_QUERY_PAGES:
318 case MLX5_CMD_OP_SET_HCA_CAP:
319 case MLX5_CMD_OP_QUERY_ISSI:
320 case MLX5_CMD_OP_SET_ISSI:
321 case MLX5_CMD_OP_CREATE_MKEY:
322 case MLX5_CMD_OP_QUERY_MKEY:
323 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
324 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
325 case MLX5_CMD_OP_CREATE_EQ:
326 case MLX5_CMD_OP_QUERY_EQ:
327 case MLX5_CMD_OP_GEN_EQE:
328 case MLX5_CMD_OP_CREATE_CQ:
329 case MLX5_CMD_OP_QUERY_CQ:
330 case MLX5_CMD_OP_MODIFY_CQ:
331 case MLX5_CMD_OP_CREATE_QP:
332 case MLX5_CMD_OP_RST2INIT_QP:
333 case MLX5_CMD_OP_INIT2RTR_QP:
334 case MLX5_CMD_OP_RTR2RTS_QP:
335 case MLX5_CMD_OP_RTS2RTS_QP:
336 case MLX5_CMD_OP_SQERR2RTS_QP:
337 case MLX5_CMD_OP_QUERY_QP:
338 case MLX5_CMD_OP_SQD_RTS_QP:
339 case MLX5_CMD_OP_INIT2INIT_QP:
340 case MLX5_CMD_OP_CREATE_PSV:
341 case MLX5_CMD_OP_CREATE_SRQ:
342 case MLX5_CMD_OP_QUERY_SRQ:
343 case MLX5_CMD_OP_ARM_RQ:
344 case MLX5_CMD_OP_CREATE_XRC_SRQ:
345 case MLX5_CMD_OP_QUERY_XRC_SRQ:
346 case MLX5_CMD_OP_ARM_XRC_SRQ:
347 case MLX5_CMD_OP_CREATE_DCT:
348 case MLX5_CMD_OP_DRAIN_DCT:
349 case MLX5_CMD_OP_QUERY_DCT:
350 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
351 case MLX5_CMD_OP_QUERY_VPORT_STATE:
352 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
353 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
354 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
355 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
356 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
357 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
358 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
359 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
360 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
361 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
362 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
363 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
364 case MLX5_CMD_OP_QUERY_Q_COUNTER:
365 case MLX5_CMD_OP_SET_RATE_LIMIT:
366 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
367 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
368 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
369 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
370 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
371 case MLX5_CMD_OP_ALLOC_PD:
372 case MLX5_CMD_OP_ALLOC_UAR:
373 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
374 case MLX5_CMD_OP_ACCESS_REG:
375 case MLX5_CMD_OP_ATTACH_TO_MCG:
376 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
377 case MLX5_CMD_OP_MAD_IFC:
378 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
379 case MLX5_CMD_OP_SET_MAD_DEMUX:
380 case MLX5_CMD_OP_NOP:
381 case MLX5_CMD_OP_ALLOC_XRCD:
382 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
383 case MLX5_CMD_OP_QUERY_CONG_STATUS:
384 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
385 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
386 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
387 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
388 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
389 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
390 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
391 case MLX5_CMD_OP_CREATE_LAG:
392 case MLX5_CMD_OP_MODIFY_LAG:
393 case MLX5_CMD_OP_QUERY_LAG:
394 case MLX5_CMD_OP_CREATE_VPORT_LAG:
395 case MLX5_CMD_OP_CREATE_TIR:
396 case MLX5_CMD_OP_MODIFY_TIR:
397 case MLX5_CMD_OP_QUERY_TIR:
398 case MLX5_CMD_OP_CREATE_SQ:
399 case MLX5_CMD_OP_MODIFY_SQ:
400 case MLX5_CMD_OP_QUERY_SQ:
401 case MLX5_CMD_OP_CREATE_RQ:
402 case MLX5_CMD_OP_MODIFY_RQ:
403 case MLX5_CMD_OP_QUERY_RQ:
404 case MLX5_CMD_OP_CREATE_RMP:
405 case MLX5_CMD_OP_MODIFY_RMP:
406 case MLX5_CMD_OP_QUERY_RMP:
407 case MLX5_CMD_OP_CREATE_TIS:
408 case MLX5_CMD_OP_MODIFY_TIS:
409 case MLX5_CMD_OP_QUERY_TIS:
410 case MLX5_CMD_OP_CREATE_RQT:
411 case MLX5_CMD_OP_MODIFY_RQT:
412 case MLX5_CMD_OP_QUERY_RQT:
414 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
415 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
416 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
417 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
418 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
419 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
420 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
421 case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
422 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
423 *status = MLX5_DRIVER_STATUS_ABORTED;
424 *synd = MLX5_DRIVER_SYND;
427 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
432 const char *mlx5_command_str(int command)
434 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
437 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
438 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
439 MLX5_COMMAND_STR_CASE(INIT_HCA);
440 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
441 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
442 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
443 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
444 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
445 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
446 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
447 MLX5_COMMAND_STR_CASE(SET_ISSI);
448 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
449 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
450 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
451 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
452 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
453 MLX5_COMMAND_STR_CASE(CREATE_EQ);
454 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
455 MLX5_COMMAND_STR_CASE(QUERY_EQ);
456 MLX5_COMMAND_STR_CASE(GEN_EQE);
457 MLX5_COMMAND_STR_CASE(CREATE_CQ);
458 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
459 MLX5_COMMAND_STR_CASE(QUERY_CQ);
460 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
461 MLX5_COMMAND_STR_CASE(CREATE_QP);
462 MLX5_COMMAND_STR_CASE(DESTROY_QP);
463 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
464 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
465 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
466 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
467 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
468 MLX5_COMMAND_STR_CASE(2ERR_QP);
469 MLX5_COMMAND_STR_CASE(2RST_QP);
470 MLX5_COMMAND_STR_CASE(QUERY_QP);
471 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
472 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
473 MLX5_COMMAND_STR_CASE(CREATE_PSV);
474 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
475 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
476 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
477 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
478 MLX5_COMMAND_STR_CASE(ARM_RQ);
479 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
480 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
481 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
482 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
483 MLX5_COMMAND_STR_CASE(CREATE_DCT);
484 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
485 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
486 MLX5_COMMAND_STR_CASE(QUERY_DCT);
487 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
488 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
489 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
490 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
491 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
492 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
493 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
494 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
495 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
496 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
497 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
498 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
499 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
500 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
501 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
502 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
503 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
504 MLX5_COMMAND_STR_CASE(SET_RATE_LIMIT);
505 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
506 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
507 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
508 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
509 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
510 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
511 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
512 MLX5_COMMAND_STR_CASE(ALLOC_PD);
513 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
514 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
515 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
516 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
517 MLX5_COMMAND_STR_CASE(ACCESS_REG);
518 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
519 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
520 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
521 MLX5_COMMAND_STR_CASE(MAD_IFC);
522 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
523 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
524 MLX5_COMMAND_STR_CASE(NOP);
525 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
526 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
527 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
528 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
529 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
530 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
531 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
532 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
533 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
534 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
535 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
536 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
537 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
538 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
539 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
540 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
541 MLX5_COMMAND_STR_CASE(CREATE_LAG);
542 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
543 MLX5_COMMAND_STR_CASE(QUERY_LAG);
544 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
545 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
546 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
547 MLX5_COMMAND_STR_CASE(CREATE_TIR);
548 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
549 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
550 MLX5_COMMAND_STR_CASE(QUERY_TIR);
551 MLX5_COMMAND_STR_CASE(CREATE_SQ);
552 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
553 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
554 MLX5_COMMAND_STR_CASE(QUERY_SQ);
555 MLX5_COMMAND_STR_CASE(CREATE_RQ);
556 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
557 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
558 MLX5_COMMAND_STR_CASE(QUERY_RQ);
559 MLX5_COMMAND_STR_CASE(CREATE_RMP);
560 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
561 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
562 MLX5_COMMAND_STR_CASE(QUERY_RMP);
563 MLX5_COMMAND_STR_CASE(CREATE_TIS);
564 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
565 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
566 MLX5_COMMAND_STR_CASE(QUERY_TIS);
567 MLX5_COMMAND_STR_CASE(CREATE_RQT);
568 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
569 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
570 MLX5_COMMAND_STR_CASE(QUERY_RQT);
571 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
572 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
573 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
574 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
575 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
576 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
577 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
578 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
579 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
580 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
581 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
582 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
583 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
584 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
585 MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
586 MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
587 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
588 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
589 default: return "unknown command opcode";
593 static const char *cmd_status_str(u8 status)
596 case MLX5_CMD_STAT_OK:
598 case MLX5_CMD_STAT_INT_ERR:
599 return "internal error";
600 case MLX5_CMD_STAT_BAD_OP_ERR:
601 return "bad operation";
602 case MLX5_CMD_STAT_BAD_PARAM_ERR:
603 return "bad parameter";
604 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
605 return "bad system state";
606 case MLX5_CMD_STAT_BAD_RES_ERR:
607 return "bad resource";
608 case MLX5_CMD_STAT_RES_BUSY:
609 return "resource busy";
610 case MLX5_CMD_STAT_LIM_ERR:
611 return "limits exceeded";
612 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
613 return "bad resource state";
614 case MLX5_CMD_STAT_IX_ERR:
616 case MLX5_CMD_STAT_NO_RES_ERR:
617 return "no resources";
618 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
619 return "bad input length";
620 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
621 return "bad output length";
622 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
623 return "bad QP state";
624 case MLX5_CMD_STAT_BAD_PKT_ERR:
625 return "bad packet (discarded)";
626 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
627 return "bad size too many outstanding CQEs";
629 return "unknown status";
633 static int cmd_status_to_err(u8 status)
636 case MLX5_CMD_STAT_OK: return 0;
637 case MLX5_CMD_STAT_INT_ERR: return -EIO;
638 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
639 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
640 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
641 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
642 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
643 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
644 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
645 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
646 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
647 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
648 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
649 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
650 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
651 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
652 default: return -EIO;
656 struct mlx5_ifc_mbox_out_bits {
658 u8 reserved_at_8[0x18];
662 u8 reserved_at_40[0x40];
665 struct mlx5_ifc_mbox_in_bits {
667 u8 reserved_at_10[0x10];
669 u8 reserved_at_20[0x10];
672 u8 reserved_at_40[0x40];
675 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
677 *status = MLX5_GET(mbox_out, out, status);
678 *syndrome = MLX5_GET(mbox_out, out, syndrome);
681 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
688 mlx5_cmd_mbox_status(out, &status, &syndrome);
692 opcode = MLX5_GET(mbox_in, in, opcode);
693 op_mod = MLX5_GET(mbox_in, in, op_mod);
696 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
697 mlx5_command_str(opcode),
699 cmd_status_str(status),
703 return cmd_status_to_err(status);
706 static void dump_command(struct mlx5_core_dev *dev,
707 struct mlx5_cmd_work_ent *ent, int input)
709 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
710 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
711 struct mlx5_cmd_mailbox *next = msg->next;
716 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
719 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
720 "dump command data %s(0x%x) %s\n",
721 mlx5_command_str(op), op,
722 input ? "INPUT" : "OUTPUT");
724 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
725 mlx5_command_str(op), op,
726 input ? "INPUT" : "OUTPUT");
730 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
731 offset += sizeof(ent->lay->in);
733 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
734 offset += sizeof(ent->lay->out);
737 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
738 offset += sizeof(*ent->lay);
741 while (next && offset < msg->len) {
743 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
744 dump_buf(next->buf, dump_len, 1, offset);
745 offset += MLX5_CMD_DATA_BLOCK_SIZE;
747 mlx5_core_dbg(dev, "command block:\n");
748 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
749 offset += sizeof(struct mlx5_cmd_prot_block);
758 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
760 return MLX5_GET(mbox_in, in->first.data, opcode);
763 static void cb_timeout_handler(struct work_struct *work)
765 struct delayed_work *dwork = container_of(work, struct delayed_work,
767 struct mlx5_cmd_work_ent *ent = container_of(dwork,
768 struct mlx5_cmd_work_ent,
770 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
773 ent->ret = -ETIMEDOUT;
774 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
775 mlx5_command_str(msg_to_opcode(ent->in)),
776 msg_to_opcode(ent->in));
777 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
780 static void cmd_work_handler(struct work_struct *work)
782 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
783 struct mlx5_cmd *cmd = ent->cmd;
784 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
785 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
786 struct mlx5_cmd_layout *lay;
787 struct semaphore *sem;
790 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
792 if (!ent->page_queue) {
793 ent->idx = alloc_ent(cmd);
795 mlx5_core_err(dev, "failed to allocate command entry\n");
800 ent->idx = cmd->max_reg_cmds;
801 spin_lock_irqsave(&cmd->alloc_lock, flags);
802 clear_bit(ent->idx, &cmd->bitmask);
803 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
806 cmd->ent_arr[ent->idx] = ent;
807 lay = get_inst(cmd, ent->idx);
809 memset(lay, 0, sizeof(*lay));
810 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
811 ent->op = be32_to_cpu(lay->in[0]) >> 16;
813 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
814 lay->inlen = cpu_to_be32(ent->in->len);
816 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
817 lay->outlen = cpu_to_be32(ent->out->len);
818 lay->type = MLX5_PCI_CMD_XPORT;
819 lay->token = ent->token;
820 lay->status_own = CMD_OWNER_HW;
821 set_signature(ent, !cmd->checksum_disabled);
822 dump_command(dev, ent, 1);
823 ent->ts1 = ktime_get_ns();
826 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
828 /* ring doorbell after the descriptor is valid */
829 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
831 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
833 /* if not in polling don't use ent after this point */
834 if (cmd->mode == CMD_MODE_POLLING) {
836 /* make sure we read the descriptor after ownership is SW */
838 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
842 static const char *deliv_status_to_str(u8 status)
845 case MLX5_CMD_DELIVERY_STAT_OK:
847 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
848 return "signature error";
849 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
850 return "token error";
851 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
852 return "bad block number";
853 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
854 return "output pointer not aligned to block size";
855 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
856 return "input pointer not aligned to block size";
857 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
858 return "firmware internal error";
859 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
860 return "command input length error";
861 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
862 return "command ouput length error";
863 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
864 return "reserved fields not cleared";
865 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
866 return "bad command descriptor type";
868 return "unknown status code";
872 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
874 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
875 struct mlx5_cmd *cmd = &dev->cmd;
878 if (cmd->mode == CMD_MODE_POLLING) {
879 wait_for_completion(&ent->done);
880 } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
881 ent->ret = -ETIMEDOUT;
882 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
887 if (err == -ETIMEDOUT) {
888 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
889 mlx5_command_str(msg_to_opcode(ent->in)),
890 msg_to_opcode(ent->in));
892 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
893 err, deliv_status_to_str(ent->status), ent->status);
899 * 1. Callback functions may not sleep
900 * 2. page queue commands do not support asynchrous completion
902 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
903 struct mlx5_cmd_msg *out, void *uout, int uout_size,
904 mlx5_cmd_cbk_t callback,
905 void *context, int page_queue, u8 *status,
908 struct mlx5_cmd *cmd = &dev->cmd;
909 struct mlx5_cmd_work_ent *ent;
910 struct mlx5_cmd_stats *stats;
915 if (callback && page_queue)
918 ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
926 init_completion(&ent->done);
928 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
929 INIT_WORK(&ent->work, cmd_work_handler);
931 cmd_work_handler(&ent->work);
932 } else if (!queue_work(cmd->wq, &ent->work)) {
933 mlx5_core_warn(dev, "failed to queue work\n");
941 err = wait_func(dev, ent);
942 if (err == -ETIMEDOUT)
945 ds = ent->ts2 - ent->ts1;
946 op = MLX5_GET(mbox_in, in->first.data, opcode);
947 if (op < ARRAY_SIZE(cmd->stats)) {
948 stats = &cmd->stats[op];
949 spin_lock_irq(&stats->lock);
952 spin_unlock_irq(&stats->lock);
954 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
955 "fw exec time for %s is %lld nsec\n",
956 mlx5_command_str(op), ds);
957 *status = ent->status;
965 static ssize_t dbg_write(struct file *filp, const char __user *buf,
966 size_t count, loff_t *pos)
968 struct mlx5_core_dev *dev = filp->private_data;
969 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
973 if (!dbg->in_msg || !dbg->out_msg)
976 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
979 lbuf[sizeof(lbuf) - 1] = 0;
981 if (strcmp(lbuf, "go"))
984 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
986 return err ? err : count;
990 static const struct file_operations fops = {
991 .owner = THIS_MODULE,
996 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
999 struct mlx5_cmd_prot_block *block;
1000 struct mlx5_cmd_mailbox *next;
1006 copy = min_t(int, size, sizeof(to->first.data));
1007 memcpy(to->first.data, from, copy);
1018 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1020 memcpy(block->data, from, copy);
1023 block->token = token;
1030 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1032 struct mlx5_cmd_prot_block *block;
1033 struct mlx5_cmd_mailbox *next;
1039 copy = min_t(int, size, sizeof(from->first.data));
1040 memcpy(to, from->first.data, copy);
1051 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1054 memcpy(to, block->data, copy);
1063 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1066 struct mlx5_cmd_mailbox *mailbox;
1068 mailbox = kmalloc(sizeof(*mailbox), flags);
1070 return ERR_PTR(-ENOMEM);
1072 mailbox->buf = pci_pool_zalloc(dev->cmd.pool, flags,
1074 if (!mailbox->buf) {
1075 mlx5_core_dbg(dev, "failed allocation\n");
1077 return ERR_PTR(-ENOMEM);
1079 mailbox->next = NULL;
1084 static void free_cmd_box(struct mlx5_core_dev *dev,
1085 struct mlx5_cmd_mailbox *mailbox)
1087 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1091 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1092 gfp_t flags, int size,
1095 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1096 struct mlx5_cmd_prot_block *block;
1097 struct mlx5_cmd_msg *msg;
1103 msg = kzalloc(sizeof(*msg), flags);
1105 return ERR_PTR(-ENOMEM);
1107 blen = size - min_t(int, sizeof(msg->first.data), size);
1108 n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
1110 for (i = 0; i < n; i++) {
1111 tmp = alloc_cmd_box(dev, flags);
1113 mlx5_core_warn(dev, "failed allocating block\n");
1120 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1121 block->block_num = cpu_to_be32(n - i - 1);
1122 block->token = token;
1132 free_cmd_box(dev, head);
1137 return ERR_PTR(err);
1140 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1141 struct mlx5_cmd_msg *msg)
1143 struct mlx5_cmd_mailbox *head = msg->next;
1144 struct mlx5_cmd_mailbox *next;
1148 free_cmd_box(dev, head);
1154 static ssize_t data_write(struct file *filp, const char __user *buf,
1155 size_t count, loff_t *pos)
1157 struct mlx5_core_dev *dev = filp->private_data;
1158 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1167 ptr = memdup_user(buf, count);
1169 return PTR_ERR(ptr);
1178 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1181 struct mlx5_core_dev *dev = filp->private_data;
1182 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1191 copy = min_t(int, count, dbg->outlen);
1192 if (copy_to_user(buf, dbg->out_msg, copy))
1200 static const struct file_operations dfops = {
1201 .owner = THIS_MODULE,
1202 .open = simple_open,
1203 .write = data_write,
1207 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1210 struct mlx5_core_dev *dev = filp->private_data;
1211 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1218 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1222 if (copy_to_user(buf, &outlen, err))
1230 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1231 size_t count, loff_t *pos)
1233 struct mlx5_core_dev *dev = filp->private_data;
1234 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1240 if (*pos != 0 || count > 6)
1243 kfree(dbg->out_msg);
1244 dbg->out_msg = NULL;
1247 if (copy_from_user(outlen_str, buf, count))
1252 err = sscanf(outlen_str, "%d", &outlen);
1256 ptr = kzalloc(outlen, GFP_KERNEL);
1261 dbg->outlen = outlen;
1268 static const struct file_operations olfops = {
1269 .owner = THIS_MODULE,
1270 .open = simple_open,
1271 .write = outlen_write,
1272 .read = outlen_read,
1275 static void set_wqname(struct mlx5_core_dev *dev)
1277 struct mlx5_cmd *cmd = &dev->cmd;
1279 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1280 dev_name(&dev->pdev->dev));
1283 static void clean_debug_files(struct mlx5_core_dev *dev)
1285 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1287 if (!mlx5_debugfs_root)
1290 mlx5_cmdif_debugfs_cleanup(dev);
1291 debugfs_remove_recursive(dbg->dbg_root);
1294 static int create_debugfs_files(struct mlx5_core_dev *dev)
1296 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1299 if (!mlx5_debugfs_root)
1302 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1306 dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1311 dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1316 dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1318 if (!dbg->dbg_outlen)
1321 dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1323 if (!dbg->dbg_status)
1326 dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1330 mlx5_cmdif_debugfs_init(dev);
1335 clean_debug_files(dev);
1339 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1341 struct mlx5_cmd *cmd = &dev->cmd;
1344 for (i = 0; i < cmd->max_reg_cmds; i++)
1346 down(&cmd->pages_sem);
1350 up(&cmd->pages_sem);
1351 for (i = 0; i < cmd->max_reg_cmds; i++)
1355 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1357 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1360 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1362 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1365 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1367 unsigned long flags;
1370 spin_lock_irqsave(&msg->parent->lock, flags);
1371 list_add_tail(&msg->list, &msg->parent->head);
1372 spin_unlock_irqrestore(&msg->parent->lock, flags);
1374 mlx5_free_cmd_msg(dev, msg);
1378 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
1380 struct mlx5_cmd *cmd = &dev->cmd;
1381 struct mlx5_cmd_work_ent *ent;
1382 mlx5_cmd_cbk_t callback;
1387 struct mlx5_cmd_stats *stats;
1388 unsigned long flags;
1389 unsigned long vector;
1391 /* there can be at most 32 command queues */
1392 vector = vec & 0xffffffff;
1393 for (i = 0; i < (1 << cmd->log_sz); i++) {
1394 if (test_bit(i, &vector)) {
1395 struct semaphore *sem;
1397 ent = cmd->ent_arr[i];
1399 cancel_delayed_work(&ent->cb_timeout_work);
1400 if (ent->page_queue)
1401 sem = &cmd->pages_sem;
1404 ent->ts2 = ktime_get_ns();
1405 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1406 dump_command(dev, ent, 0);
1408 if (!cmd->checksum_disabled)
1409 ent->ret = verify_signature(ent);
1412 if (vec & MLX5_TRIGGERED_CMD_COMP)
1413 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1415 ent->status = ent->lay->status_own >> 1;
1417 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1418 ent->ret, deliv_status_to_str(ent->status), ent->status);
1420 free_ent(cmd, ent->idx);
1422 if (ent->callback) {
1423 ds = ent->ts2 - ent->ts1;
1424 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1425 stats = &cmd->stats[ent->op];
1426 spin_lock_irqsave(&stats->lock, flags);
1429 spin_unlock_irqrestore(&stats->lock, flags);
1432 callback = ent->callback;
1433 context = ent->context;
1436 err = mlx5_copy_from_msg(ent->uout,
1440 err = err ? err : mlx5_cmd_check(dev,
1441 ent->in->first.data,
1445 mlx5_free_cmd_msg(dev, ent->out);
1446 free_msg(dev, ent->in);
1448 err = err ? err : ent->status;
1450 callback(err, context);
1452 complete(&ent->done);
1458 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1460 static int status_to_err(u8 status)
1462 return status ? -1 : 0; /* TBD more meaningful codes */
1465 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1468 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1469 struct cmd_msg_cache *ch = NULL;
1470 struct mlx5_cmd *cmd = &dev->cmd;
1476 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1477 ch = &cmd->cache[i];
1478 if (in_size > ch->max_inbox_size)
1480 spin_lock_irq(&ch->lock);
1481 if (list_empty(&ch->head)) {
1482 spin_unlock_irq(&ch->lock);
1485 msg = list_entry(ch->head.next, typeof(*msg), list);
1486 /* For cached lists, we must explicitly state what is
1490 list_del(&msg->list);
1491 spin_unlock_irq(&ch->lock);
1499 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1503 static int is_manage_pages(void *in)
1505 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1508 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1509 int out_size, mlx5_cmd_cbk_t callback, void *context)
1511 struct mlx5_cmd_msg *inb;
1512 struct mlx5_cmd_msg *outb;
1520 if (pci_channel_offline(dev->pdev) ||
1521 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1522 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1524 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1525 MLX5_SET(mbox_out, out, status, status);
1526 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1530 pages_queue = is_manage_pages(in);
1531 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1533 inb = alloc_msg(dev, in_size, gfp);
1539 token = alloc_token(&dev->cmd);
1541 err = mlx5_copy_to_msg(inb, in, in_size, token);
1543 mlx5_core_warn(dev, "err %d\n", err);
1547 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1549 err = PTR_ERR(outb);
1553 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1554 pages_queue, &status, token);
1558 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1560 err = status_to_err(status);
1565 err = mlx5_copy_from_msg(out, outb, out_size);
1569 mlx5_free_cmd_msg(dev, outb);
1577 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1582 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1583 return err ? : mlx5_cmd_check(dev, in, out);
1585 EXPORT_SYMBOL(mlx5_cmd_exec);
1587 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1588 void *out, int out_size, mlx5_cmd_cbk_t callback,
1591 return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1593 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1595 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1597 struct cmd_msg_cache *ch;
1598 struct mlx5_cmd_msg *msg;
1599 struct mlx5_cmd_msg *n;
1602 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1603 ch = &dev->cmd.cache[i];
1604 list_for_each_entry_safe(msg, n, &ch->head, list) {
1605 list_del(&msg->list);
1606 mlx5_free_cmd_msg(dev, msg);
1611 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1615 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1616 16 + MLX5_CMD_DATA_BLOCK_SIZE,
1617 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1618 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1619 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1620 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1623 static void create_msg_cache(struct mlx5_core_dev *dev)
1625 struct mlx5_cmd *cmd = &dev->cmd;
1626 struct cmd_msg_cache *ch;
1627 struct mlx5_cmd_msg *msg;
1631 /* Initialize and fill the caches with initial entries */
1632 for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1633 ch = &cmd->cache[k];
1634 spin_lock_init(&ch->lock);
1635 INIT_LIST_HEAD(&ch->head);
1636 ch->num_ent = cmd_cache_num_ent[k];
1637 ch->max_inbox_size = cmd_cache_ent_size[k];
1638 for (i = 0; i < ch->num_ent; i++) {
1639 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1640 ch->max_inbox_size, 0);
1644 list_add_tail(&msg->list, &ch->head);
1649 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1651 struct device *ddev = &dev->pdev->dev;
1653 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1654 &cmd->alloc_dma, GFP_KERNEL);
1655 if (!cmd->cmd_alloc_buf)
1658 /* make sure it is aligned to 4K */
1659 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1660 cmd->cmd_buf = cmd->cmd_alloc_buf;
1661 cmd->dma = cmd->alloc_dma;
1662 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1666 dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1668 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1669 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1670 &cmd->alloc_dma, GFP_KERNEL);
1671 if (!cmd->cmd_alloc_buf)
1674 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1675 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1676 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1680 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1682 struct device *ddev = &dev->pdev->dev;
1684 dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1688 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1690 int size = sizeof(struct mlx5_cmd_prot_block);
1691 int align = roundup_pow_of_two(size);
1692 struct mlx5_cmd *cmd = &dev->cmd;
1698 memset(cmd, 0, sizeof(*cmd));
1699 cmd_if_rev = cmdif_rev(dev);
1700 if (cmd_if_rev != CMD_IF_REV) {
1701 dev_err(&dev->pdev->dev,
1702 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1703 CMD_IF_REV, cmd_if_rev);
1707 cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1711 err = alloc_cmd_page(dev, cmd);
1715 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1716 cmd->log_sz = cmd_l >> 4 & 0xf;
1717 cmd->log_stride = cmd_l & 0xf;
1718 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1719 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1725 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1726 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1731 cmd->checksum_disabled = 1;
1732 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1733 cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1735 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1736 if (cmd->cmdif_rev > CMD_IF_REV) {
1737 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1738 CMD_IF_REV, cmd->cmdif_rev);
1743 spin_lock_init(&cmd->alloc_lock);
1744 spin_lock_init(&cmd->token_lock);
1745 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1746 spin_lock_init(&cmd->stats[i].lock);
1748 sema_init(&cmd->sem, cmd->max_reg_cmds);
1749 sema_init(&cmd->pages_sem, 1);
1751 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1752 cmd_l = (u32)(cmd->dma);
1753 if (cmd_l & 0xfff) {
1754 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1759 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1760 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1762 /* Make sure firmware sees the complete address before we proceed */
1765 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1767 cmd->mode = CMD_MODE_POLLING;
1769 create_msg_cache(dev);
1772 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1774 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1779 err = create_debugfs_files(dev);
1788 destroy_workqueue(cmd->wq);
1791 destroy_msg_cache(dev);
1794 free_cmd_page(dev, cmd);
1797 pci_pool_destroy(cmd->pool);
1801 EXPORT_SYMBOL(mlx5_cmd_init);
1803 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1805 struct mlx5_cmd *cmd = &dev->cmd;
1807 clean_debug_files(dev);
1808 destroy_workqueue(cmd->wq);
1809 destroy_msg_cache(dev);
1810 free_cmd_page(dev, cmd);
1811 pci_pool_destroy(cmd->pool);
1813 EXPORT_SYMBOL(mlx5_cmd_cleanup);