2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
47 #include <net/switchdev.h>
49 #include "mlx5_core.h"
52 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
54 #define MLX5E_HW2SW_MTU(hwmtu) ((hwmtu) - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
55 #define MLX5E_SW2HW_MTU(swmtu) ((swmtu) + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
57 #define MLX5E_MAX_NUM_TC 8
59 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
60 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
61 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
67 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
68 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3
69 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
71 #define MLX5_RX_HEADROOM NET_SKB_PAD
73 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
74 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */
75 #define MLX5_MPWRQ_LOG_WQE_SZ 18
76 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
77 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
78 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
79 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
80 MLX5_MPWRQ_WQE_PAGE_ORDER)
82 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
83 #define MLX5E_REQUIRED_MTTS(wqes) \
84 (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
85 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
87 #define MLX5_UMR_ALIGN (2048)
88 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
90 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
91 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
92 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
94 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
95 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
96 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
97 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
98 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
99 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
100 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
102 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
103 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
104 #define MLX5E_MIN_NUM_CHANNELS 0x1
105 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
106 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
107 #define MLX5E_TX_CQ_POLL_BUDGET 128
108 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
109 #define MLX5E_SQ_BF_BUDGET 16
111 #define MLX5E_ICOSQ_MAX_WQEBBS \
112 (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
114 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
115 #define MLX5E_XDP_IHS_DS_COUNT \
116 DIV_ROUND_UP(MLX5E_XDP_MIN_INLINE - 2, MLX5_SEND_WQE_DS)
117 #define MLX5E_XDP_TX_DS_COUNT \
118 (MLX5E_XDP_IHS_DS_COUNT + \
119 (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
120 #define MLX5E_XDP_TX_WQEBBS \
121 DIV_ROUND_UP(MLX5E_XDP_TX_DS_COUNT, MLX5_SEND_WQEBB_NUM_DS)
123 #define MLX5E_NUM_MAIN_GROUPS 9
125 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
128 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
129 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
132 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
137 static inline int mlx5_min_log_rq_size(int wq_type)
140 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
141 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
143 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
147 static inline int mlx5_max_log_rq_size(int wq_type)
150 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
151 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
153 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
157 struct mlx5e_tx_wqe {
158 struct mlx5_wqe_ctrl_seg ctrl;
159 struct mlx5_wqe_eth_seg eth;
162 struct mlx5e_rx_wqe {
163 struct mlx5_wqe_srq_next_seg next;
164 struct mlx5_wqe_data_seg data;
167 struct mlx5e_umr_wqe {
168 struct mlx5_wqe_ctrl_seg ctrl;
169 struct mlx5_wqe_umr_ctrl_seg uctrl;
170 struct mlx5_mkey_seg mkc;
171 struct mlx5_wqe_data_seg data;
174 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
176 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
181 enum mlx5e_priv_flag {
182 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
183 MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),
186 #define MLX5E_SET_PFLAG(priv, pflag, enable) \
189 (priv)->params.pflags |= (pflag); \
191 (priv)->params.pflags &= ~(pflag); \
194 #define MLX5E_GET_PFLAG(priv, pflag) (!!((priv)->params.pflags & (pflag)))
196 #ifdef CONFIG_MLX5_CORE_EN_DCB
197 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
200 struct mlx5e_cq_moder {
205 struct mlx5e_params {
208 u8 mpwqe_log_stride_sz;
209 u8 mpwqe_log_num_strides;
213 u8 rx_cq_period_mode;
214 bool rx_cqe_compress_def;
215 struct mlx5e_cq_moder rx_cq_moderation;
216 struct mlx5e_cq_moder tx_cq_moderation;
221 u8 tx_min_inline_mode;
223 u8 toeplitz_hash_key[40];
224 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
225 bool vlan_strip_disable;
231 #ifdef CONFIG_MLX5_CORE_EN_DCB
232 struct mlx5e_cee_config {
233 /* bw pct for priority group */
234 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
235 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
236 bool pfc_setting[CEE_DCBX_MAX_PRIO];
243 MLX5_DCB_CHG_NO_RESET,
247 enum mlx5_dcbx_oper_mode mode;
248 struct mlx5e_cee_config cee_cfg; /* pending configuration */
250 /* The only setting that cannot be read from FW */
251 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
255 struct mlx5e_tstamp {
257 struct cyclecounter cycles;
258 struct timecounter clock;
259 struct hwtstamp_config hwtstamp_config;
261 unsigned long overflow_period;
262 struct delayed_work overflow_work;
263 struct mlx5_core_dev *mdev;
264 struct ptp_clock *ptp;
265 struct ptp_clock_info ptp_info;
270 MLX5E_RQ_STATE_ENABLED,
271 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
276 /* data path - accessed per cqe */
279 /* data path - accessed per napi poll */
281 struct napi_struct *napi;
282 struct mlx5_core_cq mcq;
283 struct mlx5e_channel *channel;
284 struct mlx5e_priv *priv;
286 /* cqe decompression */
287 struct mlx5_cqe64 title;
288 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
291 u16 decmprs_wqe_counter;
294 struct mlx5_frag_wq_ctrl wq_ctrl;
295 } ____cacheline_aligned_in_smp;
298 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
299 struct mlx5_cqe64 *cqe);
300 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
303 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix);
305 struct mlx5e_dma_info {
310 struct mlx5e_rx_am_stats {
311 int ppms; /* packets per msec */
312 int epms; /* events per msec */
315 struct mlx5e_rx_am_sample {
317 unsigned int pkt_ctr;
321 struct mlx5e_rx_am { /* Adaptive Moderation */
323 struct mlx5e_rx_am_stats prev_stats;
324 struct mlx5e_rx_am_sample start_sample;
325 struct work_struct work;
334 /* a single cache unit is capable to serve one napi call (for non-striding rq)
335 * or a MPWQE (for striding rq).
337 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
338 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
339 #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
340 struct mlx5e_page_cache {
343 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
348 struct mlx5_wq_ll wq;
351 struct mlx5e_dma_info *dma_info;
353 struct mlx5e_mpw_info *info;
359 u32 wqe_sz; /* wqe data buffer size */
360 u8 map_dir; /* dma map direction */
365 struct net_device *netdev;
366 struct mlx5e_tstamp *tstamp;
367 struct mlx5e_rq_stats stats;
369 struct mlx5e_page_cache page_cache;
371 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
372 mlx5e_fp_alloc_wqe alloc_wqe;
373 mlx5e_fp_dealloc_wqe dealloc_wqe;
379 struct mlx5e_rx_am am; /* Adaptive Moderation */
380 struct bpf_prog *xdp_prog;
383 struct mlx5_wq_ctrl wq_ctrl;
386 u32 mpwqe_num_strides;
388 struct mlx5e_channel *channel;
389 struct mlx5e_priv *priv;
390 struct mlx5_core_mkey umr_mkey;
391 } ____cacheline_aligned_in_smp;
393 struct mlx5e_umr_dma_info {
396 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
397 struct mlx5e_umr_wqe wqe;
400 struct mlx5e_mpw_info {
401 struct mlx5e_umr_dma_info umr;
402 u16 consumed_strides;
403 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
406 struct mlx5e_tx_wqe_info {
412 enum mlx5e_dma_map_type {
413 MLX5E_DMA_MAP_SINGLE,
417 struct mlx5e_sq_dma {
420 enum mlx5e_dma_map_type type;
424 MLX5E_SQ_STATE_ENABLED,
425 MLX5E_SQ_STATE_BF_ENABLE,
428 struct mlx5e_sq_wqe_info {
442 /* dirtied @completion */
447 u16 pc ____cacheline_aligned_in_smp;
452 struct mlx5e_sq_stats stats;
456 /* pointers to per tx element info: write@xmit, read@completion */
459 struct sk_buff **skb;
460 struct mlx5e_sq_dma *dma_fifo;
461 struct mlx5e_tx_wqe_info *wqe_info;
463 struct mlx5e_sq_wqe_info *ico_wqe;
465 struct mlx5e_sq_wqe_info *wqe_info;
466 struct mlx5e_dma_info *di;
472 struct mlx5_wq_cyc wq;
474 struct netdev_queue *txq;
481 struct mlx5e_tstamp *tstamp;
486 struct mlx5_wq_ctrl wq_ctrl;
487 struct mlx5_sq_bfreg bfreg;
488 struct mlx5e_channel *channel;
492 } ____cacheline_aligned_in_smp;
494 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
496 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
501 MLX5E_CHANNEL_NAPI_SCHED = 1,
504 struct mlx5e_channel {
507 struct mlx5e_sq xdp_sq;
508 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
509 struct mlx5e_sq icosq; /* internal control operations */
511 struct napi_struct napi;
513 struct net_device *netdev;
519 struct mlx5e_priv *priv;
524 enum mlx5e_traffic_types {
529 MLX5E_TT_IPV4_IPSEC_AH,
530 MLX5E_TT_IPV6_IPSEC_AH,
531 MLX5E_TT_IPV4_IPSEC_ESP,
532 MLX5E_TT_IPV6_IPSEC_ESP,
537 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
541 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
543 MLX5E_STATE_DESTROYING,
546 struct mlx5e_vxlan_db {
547 spinlock_t lock; /* protect vxlan table */
548 struct radix_tree_root tree;
551 struct mlx5e_l2_rule {
552 u8 addr[ETH_ALEN + 2];
553 struct mlx5_flow_handle *rule;
556 struct mlx5e_flow_table {
558 struct mlx5_flow_table *t;
559 struct mlx5_flow_group **g;
562 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
564 struct mlx5e_tc_table {
565 struct mlx5_flow_table *t;
567 struct rhashtable_params ht_params;
568 struct rhashtable ht;
571 struct mlx5e_vlan_table {
572 struct mlx5e_flow_table ft;
573 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
574 struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID];
575 struct mlx5_flow_handle *untagged_rule;
576 struct mlx5_flow_handle *any_cvlan_rule;
577 struct mlx5_flow_handle *any_svlan_rule;
578 bool filter_disabled;
581 struct mlx5e_l2_table {
582 struct mlx5e_flow_table ft;
583 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
584 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
585 struct mlx5e_l2_rule broadcast;
586 struct mlx5e_l2_rule allmulti;
587 struct mlx5e_l2_rule promisc;
588 bool broadcast_enabled;
589 bool allmulti_enabled;
590 bool promisc_enabled;
593 /* L3/L4 traffic type classifier */
594 struct mlx5e_ttc_table {
595 struct mlx5e_flow_table ft;
596 struct mlx5_flow_handle *rules[MLX5E_NUM_TT];
599 #define ARFS_HASH_SHIFT BITS_PER_BYTE
600 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
602 struct mlx5e_flow_table ft;
603 struct mlx5_flow_handle *default_rule;
604 struct hlist_head rules_hash[ARFS_HASH_SIZE];
615 struct mlx5e_arfs_tables {
616 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
617 /* Protect aRFS rules list */
618 spinlock_t arfs_lock;
619 struct list_head rules;
621 struct workqueue_struct *wq;
626 MLX5E_VLAN_FT_LEVEL = 0,
632 struct mlx5e_ethtool_table {
633 struct mlx5_flow_table *ft;
637 #define ETHTOOL_NUM_L3_L4_FTS 7
638 #define ETHTOOL_NUM_L2_FTS 4
640 struct mlx5e_ethtool_steering {
641 struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
642 struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS];
643 struct list_head rules;
647 struct mlx5e_flow_steering {
648 struct mlx5_flow_namespace *ns;
649 struct mlx5e_ethtool_steering ethtool;
650 struct mlx5e_tc_table tc;
651 struct mlx5e_vlan_table vlan;
652 struct mlx5e_l2_table l2;
653 struct mlx5e_ttc_table ttc;
654 struct mlx5e_arfs_tables arfs;
664 struct mlx5e_rqt rqt;
665 struct list_head list;
673 struct mlx5e_profile {
674 void (*init)(struct mlx5_core_dev *mdev,
675 struct net_device *netdev,
676 const struct mlx5e_profile *profile, void *ppriv);
677 void (*cleanup)(struct mlx5e_priv *priv);
678 int (*init_rx)(struct mlx5e_priv *priv);
679 void (*cleanup_rx)(struct mlx5e_priv *priv);
680 int (*init_tx)(struct mlx5e_priv *priv);
681 void (*cleanup_tx)(struct mlx5e_priv *priv);
682 void (*enable)(struct mlx5e_priv *priv);
683 void (*disable)(struct mlx5e_priv *priv);
684 void (*update_stats)(struct mlx5e_priv *priv);
685 int (*max_nch)(struct mlx5_core_dev *mdev);
690 /* priv data path fields - start */
691 struct mlx5e_sq **txq_to_sq_map;
692 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
693 struct bpf_prog *xdp_prog;
694 /* priv data path fields - end */
697 struct mutex state_lock; /* Protects Interface state */
698 struct mlx5e_rq drop_rq;
700 struct mlx5e_channel **channel;
701 u32 tisn[MLX5E_MAX_NUM_TC];
702 struct mlx5e_rqt indir_rqt;
703 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
704 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
705 u32 tx_rates[MLX5E_MAX_NUM_SQS];
707 struct mlx5e_flow_steering fs;
708 struct mlx5e_vxlan_db vxlan;
710 struct mlx5e_params params;
711 struct workqueue_struct *wq;
712 struct work_struct update_carrier_work;
713 struct work_struct set_rx_mode_work;
714 struct work_struct tx_timeout_work;
715 struct delayed_work update_stats_work;
717 struct mlx5_core_dev *mdev;
718 struct net_device *netdev;
719 struct mlx5e_stats stats;
720 struct mlx5e_tstamp tstamp;
722 #ifdef CONFIG_MLX5_CORE_EN_DCB
723 struct mlx5e_dcbx dcbx;
726 const struct mlx5e_profile *profile;
730 void mlx5e_build_ptys2ethtool_map(void);
732 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
733 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
734 void *accel_priv, select_queue_fallback_t fallback);
735 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
737 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
738 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
739 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
740 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
741 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
742 void mlx5e_free_sq_descs(struct mlx5e_sq *sq);
744 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
746 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
747 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
748 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
749 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
750 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
751 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
752 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
753 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
754 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
755 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
757 void mlx5e_rx_am(struct mlx5e_rq *rq);
758 void mlx5e_rx_am_work(struct work_struct *work);
759 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
761 void mlx5e_update_stats(struct mlx5e_priv *priv);
763 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
764 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
765 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
766 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
767 int mlx5e_self_test_num(struct mlx5e_priv *priv);
768 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
770 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
772 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
773 struct ethtool_rxnfc *info, u32 *rule_locs);
774 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
775 struct ethtool_rx_flow_spec *fs);
776 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
778 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
779 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
780 void mlx5e_set_rx_mode_work(struct work_struct *work);
782 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
783 struct skb_shared_hwtstamps *hwts);
784 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
785 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
786 void mlx5e_pps_event_handler(struct mlx5e_priv *priv,
787 struct ptp_clock_event *event);
788 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
789 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
790 void mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
792 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
794 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
796 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
797 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
799 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
801 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
802 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc,
803 enum mlx5e_traffic_types tt);
805 int mlx5e_open_locked(struct net_device *netdev);
806 int mlx5e_close_locked(struct net_device *netdev);
807 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
808 u32 *indirection_rqt, int len,
810 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
812 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
815 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
816 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
818 u16 ofst = sq->bf_offset;
820 /* ensure wqe is visible to device before updating doorbell record */
823 *sq->wq.db = cpu_to_be32(sq->pc);
825 /* ensure doorbell record is visible to device before ringing the
830 __iowrite64_copy(sq->bfreg.map + ofst, ctrl, bf_sz);
832 mlx5_write64((__be32 *)ctrl, sq->bfreg.map + ofst, NULL);
833 /* flush the write-combining mapped buffer */
836 sq->bf_offset ^= sq->bf_buf_size;
839 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
841 struct mlx5_core_cq *mcq;
844 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
847 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
849 return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
852 extern const struct ethtool_ops mlx5e_ethtool_ops;
853 #ifdef CONFIG_MLX5_CORE_EN_DCB
854 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
855 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
856 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
859 #ifndef CONFIG_RFS_ACCEL
860 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
865 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
867 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
872 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
877 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
878 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
879 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
880 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
881 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
882 u16 rxq_index, u32 flow_id);
885 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
886 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
887 struct mlx5e_tir *tir, u32 *in, int inlen);
888 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
889 struct mlx5e_tir *tir);
890 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
891 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
892 int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev,
895 struct mlx5_eswitch_rep;
896 int mlx5e_vport_rep_load(struct mlx5_eswitch *esw,
897 struct mlx5_eswitch_rep *rep);
898 void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw,
899 struct mlx5_eswitch_rep *rep);
900 int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep);
901 void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw,
902 struct mlx5_eswitch_rep *rep);
903 int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv);
904 void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv);
905 int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr);
906 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
907 void mlx5e_update_hw_rep_counters(struct mlx5e_priv *priv);
909 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
910 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
911 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
912 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
913 int mlx5e_create_tises(struct mlx5e_priv *priv);
914 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
915 int mlx5e_close(struct net_device *netdev);
916 int mlx5e_open(struct net_device *netdev);
917 void mlx5e_update_stats_work(struct work_struct *work);
918 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
919 const struct mlx5e_profile *profile,
921 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv);
922 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
923 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
924 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
925 void mlx5e_add_vxlan_port(struct net_device *netdev,
926 struct udp_tunnel_info *ti);
927 void mlx5e_del_vxlan_port(struct net_device *netdev,
928 struct udp_tunnel_info *ti);
930 int mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
932 bool mlx5e_has_offload_stats(const struct net_device *dev, int attr_id);
934 bool mlx5e_is_uplink_rep(struct mlx5e_priv *priv);
935 bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv);
936 #endif /* __MLX5_EN_H__ */