2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/rhashtable.h>
48 #include <net/switchdev.h>
50 #include "mlx5_core.h"
53 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
55 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
57 #define MLX5E_HW2SW_MTU(priv, hwmtu) ((hwmtu) - ((priv)->hard_mtu))
58 #define MLX5E_SW2HW_MTU(priv, swmtu) ((swmtu) + ((priv)->hard_mtu))
60 #define MLX5E_MAX_NUM_TC 8
62 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
63 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
64 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
66 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
67 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
68 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
70 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
71 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3
72 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
74 #define MLX5_RX_HEADROOM NET_SKB_PAD
75 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
76 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
78 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
79 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
80 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
81 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
82 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
83 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
85 #define MLX5_MPWRQ_LOG_WQE_SZ 18
86 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
87 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
88 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
89 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
90 MLX5_MPWRQ_WQE_PAGE_ORDER)
92 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
93 #define MLX5E_REQUIRED_MTTS(wqes) \
94 (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
95 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
97 #define MLX5_UMR_ALIGN (2048)
98 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (256)
100 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
101 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
102 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
104 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
105 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
106 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
107 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
108 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
109 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
110 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
112 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
113 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
114 #define MLX5E_MIN_NUM_CHANNELS 0x1
115 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
116 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
117 #define MLX5E_TX_CQ_POLL_BUDGET 128
118 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
120 #define MLX5E_ICOSQ_MAX_WQEBBS \
121 (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
123 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
124 #define MLX5E_XDP_TX_DS_COUNT \
125 ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
127 #define MLX5E_NUM_MAIN_GROUPS 9
129 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
132 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
133 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
136 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
141 static inline int mlx5_min_log_rq_size(int wq_type)
144 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
145 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
147 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
151 static inline int mlx5_max_log_rq_size(int wq_type)
154 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
155 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
157 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
161 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
163 return is_kdump_kernel() ?
164 MLX5E_MIN_NUM_CHANNELS :
165 min_t(int, mdev->priv.eq_table.num_comp_vectors,
166 MLX5E_MAX_NUM_CHANNELS);
169 struct mlx5e_tx_wqe {
170 struct mlx5_wqe_ctrl_seg ctrl;
171 struct mlx5_wqe_eth_seg eth;
174 struct mlx5e_rx_wqe {
175 struct mlx5_wqe_srq_next_seg next;
176 struct mlx5_wqe_data_seg data;
179 struct mlx5e_umr_wqe {
180 struct mlx5_wqe_ctrl_seg ctrl;
181 struct mlx5_wqe_umr_ctrl_seg uctrl;
182 struct mlx5_mkey_seg mkc;
183 struct mlx5_wqe_data_seg data;
186 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
188 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
193 enum mlx5e_priv_flag {
194 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
195 MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),
198 #define MLX5E_SET_PFLAG(params, pflag, enable) \
201 (params)->pflags |= (pflag); \
203 (params)->pflags &= ~(pflag); \
206 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag)))
208 #ifdef CONFIG_MLX5_CORE_EN_DCB
209 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
212 struct mlx5e_cq_moder {
217 struct mlx5e_params {
221 u8 mpwqe_log_stride_sz;
222 u8 mpwqe_log_num_strides;
226 u8 rx_cq_period_mode;
227 bool rx_cqe_compress_def;
228 struct mlx5e_cq_moder rx_cq_moderation;
229 struct mlx5e_cq_moder tx_cq_moderation;
233 u8 tx_min_inline_mode;
235 u8 toeplitz_hash_key[40];
236 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
237 bool vlan_strip_disable;
242 struct bpf_prog *xdp_prog;
245 #ifdef CONFIG_MLX5_CORE_EN_DCB
246 struct mlx5e_cee_config {
247 /* bw pct for priority group */
248 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
249 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
250 bool pfc_setting[CEE_DCBX_MAX_PRIO];
257 MLX5_DCB_CHG_NO_RESET,
261 enum mlx5_dcbx_oper_mode mode;
262 struct mlx5e_cee_config cee_cfg; /* pending configuration */
264 /* The only setting that cannot be read from FW */
265 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
269 struct mlx5e_tstamp {
271 struct cyclecounter cycles;
272 struct timecounter clock;
273 struct hwtstamp_config hwtstamp_config;
275 unsigned long overflow_period;
276 struct delayed_work overflow_work;
277 struct mlx5_core_dev *mdev;
278 struct ptp_clock *ptp;
279 struct ptp_clock_info ptp_info;
284 MLX5E_RQ_STATE_ENABLED,
285 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
290 /* data path - accessed per cqe */
293 /* data path - accessed per napi poll */
295 struct napi_struct *napi;
296 struct mlx5_core_cq mcq;
297 struct mlx5e_channel *channel;
299 /* cqe decompression */
300 struct mlx5_cqe64 title;
301 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
304 u16 decmprs_wqe_counter;
307 struct mlx5_core_dev *mdev;
308 struct mlx5_frag_wq_ctrl wq_ctrl;
309 } ____cacheline_aligned_in_smp;
311 struct mlx5e_tx_wqe_info {
318 enum mlx5e_dma_map_type {
319 MLX5E_DMA_MAP_SINGLE,
323 struct mlx5e_sq_dma {
326 enum mlx5e_dma_map_type type;
330 MLX5E_SQ_STATE_ENABLED,
331 MLX5E_SQ_STATE_IPSEC,
334 struct mlx5e_sq_wqe_info {
342 /* dirtied @completion */
347 u16 pc ____cacheline_aligned_in_smp;
349 struct mlx5e_sq_stats stats;
353 /* write@xmit, read@completion */
355 struct mlx5e_sq_dma *dma_fifo;
356 struct mlx5e_tx_wqe_info *wqe_info;
360 struct mlx5_wq_cyc wq;
362 void __iomem *uar_map;
363 struct netdev_queue *txq;
369 struct mlx5e_tstamp *tstamp;
374 struct mlx5_wq_ctrl wq_ctrl;
375 struct mlx5e_channel *channel;
378 } ____cacheline_aligned_in_smp;
383 /* dirtied @rx completion */
389 /* write@xmit, read@completion */
391 struct mlx5e_dma_info *di;
396 struct mlx5_wq_cyc wq;
397 void __iomem *uar_map;
405 struct mlx5_wq_ctrl wq_ctrl;
406 struct mlx5e_channel *channel;
407 } ____cacheline_aligned_in_smp;
412 /* dirtied @completion */
416 u16 pc ____cacheline_aligned_in_smp;
422 /* write@xmit, read@completion */
424 struct mlx5e_sq_wqe_info *ico_wqe;
428 struct mlx5_wq_cyc wq;
429 void __iomem *uar_map;
437 struct mlx5_wq_ctrl wq_ctrl;
438 struct mlx5e_channel *channel;
439 } ____cacheline_aligned_in_smp;
442 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
444 return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc));
447 struct mlx5e_dma_info {
452 struct mlx5e_wqe_frag_info {
453 struct mlx5e_dma_info di;
457 struct mlx5e_umr_dma_info {
460 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
461 struct mlx5e_umr_wqe wqe;
464 struct mlx5e_mpw_info {
465 struct mlx5e_umr_dma_info umr;
466 u16 consumed_strides;
467 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
470 struct mlx5e_rx_am_stats {
471 int ppms; /* packets per msec */
472 int bpms; /* bytes per msec */
473 int epms; /* events per msec */
476 struct mlx5e_rx_am_sample {
483 struct mlx5e_rx_am { /* Adaptive Moderation */
485 struct mlx5e_rx_am_stats prev_stats;
486 struct mlx5e_rx_am_sample start_sample;
487 struct work_struct work;
496 /* a single cache unit is capable to serve one napi call (for non-striding rq)
497 * or a MPWQE (for striding rq).
499 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
500 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
501 #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
502 struct mlx5e_page_cache {
505 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
509 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
510 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq*, struct mlx5e_rx_wqe*, u16);
511 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
515 struct mlx5_wq_ll wq;
519 struct mlx5e_wqe_frag_info *frag_info;
520 u32 frag_sz; /* max possible skb frag_sz */
525 struct mlx5e_mpw_info *info;
531 u32 wqe_sz; /* wqe data buffer size */
532 u8 map_dir; /* dma map direction */
537 struct net_device *netdev;
538 struct mlx5e_tstamp *tstamp;
539 struct mlx5e_rq_stats stats;
541 struct mlx5e_page_cache page_cache;
543 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
544 mlx5e_fp_alloc_wqe alloc_wqe;
545 mlx5e_fp_dealloc_wqe dealloc_wqe;
551 struct mlx5e_rx_am am; /* Adaptive Moderation */
554 struct bpf_prog *xdp_prog;
555 struct mlx5e_xdpsq xdpsq;
558 struct mlx5_wq_ctrl wq_ctrl;
561 u32 mpwqe_num_strides;
563 struct mlx5e_channel *channel;
564 struct mlx5_core_dev *mdev;
565 struct mlx5_core_mkey umr_mkey;
566 } ____cacheline_aligned_in_smp;
569 MLX5E_CHANNEL_NAPI_SCHED = 1,
572 struct mlx5e_channel {
575 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
576 struct mlx5e_icosq icosq; /* internal control operations */
578 struct napi_struct napi;
580 struct net_device *netdev;
586 struct mlx5e_priv *priv;
587 struct mlx5_core_dev *mdev;
588 struct mlx5e_tstamp *tstamp;
593 struct mlx5e_channels {
594 struct mlx5e_channel **c;
596 struct mlx5e_params params;
599 enum mlx5e_traffic_types {
604 MLX5E_TT_IPV4_IPSEC_AH,
605 MLX5E_TT_IPV6_IPSEC_AH,
606 MLX5E_TT_IPV4_IPSEC_ESP,
607 MLX5E_TT_IPV6_IPSEC_ESP,
612 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
616 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
618 MLX5E_STATE_DESTROYING,
621 struct mlx5e_vxlan_db {
622 spinlock_t lock; /* protect vxlan table */
623 struct radix_tree_root tree;
626 struct mlx5e_l2_rule {
627 u8 addr[ETH_ALEN + 2];
628 struct mlx5_flow_handle *rule;
631 struct mlx5e_flow_table {
633 struct mlx5_flow_table *t;
634 struct mlx5_flow_group **g;
637 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
639 struct mlx5e_tc_table {
640 struct mlx5_flow_table *t;
642 struct rhashtable_params ht_params;
643 struct rhashtable ht;
645 DECLARE_HASHTABLE(mod_hdr_tbl, 8);
648 struct mlx5e_vlan_table {
649 struct mlx5e_flow_table ft;
650 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
651 struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID];
652 struct mlx5_flow_handle *untagged_rule;
653 struct mlx5_flow_handle *any_cvlan_rule;
654 struct mlx5_flow_handle *any_svlan_rule;
655 bool filter_disabled;
658 struct mlx5e_l2_table {
659 struct mlx5e_flow_table ft;
660 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
661 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
662 struct mlx5e_l2_rule broadcast;
663 struct mlx5e_l2_rule allmulti;
664 struct mlx5e_l2_rule promisc;
665 bool broadcast_enabled;
666 bool allmulti_enabled;
667 bool promisc_enabled;
670 /* L3/L4 traffic type classifier */
671 struct mlx5e_ttc_table {
672 struct mlx5e_flow_table ft;
673 struct mlx5_flow_handle *rules[MLX5E_NUM_TT];
676 #define ARFS_HASH_SHIFT BITS_PER_BYTE
677 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
679 struct mlx5e_flow_table ft;
680 struct mlx5_flow_handle *default_rule;
681 struct hlist_head rules_hash[ARFS_HASH_SIZE];
692 struct mlx5e_arfs_tables {
693 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
694 /* Protect aRFS rules list */
695 spinlock_t arfs_lock;
696 struct list_head rules;
698 struct workqueue_struct *wq;
703 MLX5E_VLAN_FT_LEVEL = 0,
709 struct mlx5e_ethtool_table {
710 struct mlx5_flow_table *ft;
714 #define ETHTOOL_NUM_L3_L4_FTS 7
715 #define ETHTOOL_NUM_L2_FTS 4
717 struct mlx5e_ethtool_steering {
718 struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
719 struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS];
720 struct list_head rules;
724 struct mlx5e_flow_steering {
725 struct mlx5_flow_namespace *ns;
726 struct mlx5e_ethtool_steering ethtool;
727 struct mlx5e_tc_table tc;
728 struct mlx5e_vlan_table vlan;
729 struct mlx5e_l2_table l2;
730 struct mlx5e_ttc_table ttc;
731 struct mlx5e_arfs_tables arfs;
741 struct mlx5e_rqt rqt;
742 struct list_head list;
751 /* priv data path fields - start */
752 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
753 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
754 /* priv data path fields - end */
757 struct mutex state_lock; /* Protects Interface state */
758 struct mlx5e_rq drop_rq;
760 struct mlx5e_channels channels;
761 u32 tisn[MLX5E_MAX_NUM_TC];
762 struct mlx5e_rqt indir_rqt;
763 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
764 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
765 u32 tx_rates[MLX5E_MAX_NUM_SQS];
768 struct mlx5e_flow_steering fs;
769 struct mlx5e_vxlan_db vxlan;
771 struct workqueue_struct *wq;
772 struct work_struct update_carrier_work;
773 struct work_struct set_rx_mode_work;
774 struct work_struct tx_timeout_work;
775 struct delayed_work update_stats_work;
777 struct mlx5_core_dev *mdev;
778 struct net_device *netdev;
779 struct mlx5e_stats stats;
780 struct mlx5e_tstamp tstamp;
782 #ifdef CONFIG_MLX5_CORE_EN_DCB
783 struct mlx5e_dcbx dcbx;
786 const struct mlx5e_profile *profile;
788 #ifdef CONFIG_MLX5_EN_IPSEC
789 struct mlx5e_ipsec *ipsec;
793 struct mlx5e_profile {
794 void (*init)(struct mlx5_core_dev *mdev,
795 struct net_device *netdev,
796 const struct mlx5e_profile *profile, void *ppriv);
797 void (*cleanup)(struct mlx5e_priv *priv);
798 int (*init_rx)(struct mlx5e_priv *priv);
799 void (*cleanup_rx)(struct mlx5e_priv *priv);
800 int (*init_tx)(struct mlx5e_priv *priv);
801 void (*cleanup_tx)(struct mlx5e_priv *priv);
802 void (*enable)(struct mlx5e_priv *priv);
803 void (*disable)(struct mlx5e_priv *priv);
804 void (*update_stats)(struct mlx5e_priv *priv);
805 void (*update_carrier)(struct mlx5e_priv *priv);
806 int (*max_nch)(struct mlx5_core_dev *mdev);
808 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
809 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
814 void mlx5e_build_ptys2ethtool_map(void);
816 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
817 void *accel_priv, select_queue_fallback_t fallback);
818 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
820 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
821 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
822 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
823 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
824 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
825 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq);
826 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
827 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq);
829 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
831 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
832 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
833 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
834 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
835 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
836 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
837 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
838 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
839 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
841 void mlx5e_rx_am(struct mlx5e_rq *rq);
842 void mlx5e_rx_am_work(struct work_struct *work);
843 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
845 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full);
847 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
848 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
849 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
850 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
851 int mlx5e_self_test_num(struct mlx5e_priv *priv);
852 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
854 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
856 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
857 struct ethtool_rxnfc *info, u32 *rule_locs);
858 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
859 struct ethtool_rx_flow_spec *fs);
860 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
862 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
863 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
864 void mlx5e_set_rx_mode_work(struct work_struct *work);
866 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
867 struct skb_shared_hwtstamps *hwts);
868 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
869 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
870 void mlx5e_pps_event_handler(struct mlx5e_priv *priv,
871 struct ptp_clock_event *event);
872 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
873 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
874 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
876 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
878 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
880 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
881 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
883 struct mlx5e_redirect_rqt_param {
886 u32 rqn; /* Direct RQN (Non-RSS) */
889 struct mlx5e_channels *channels;
890 } rss; /* RSS data */
894 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
895 struct mlx5e_redirect_rqt_param rrp);
896 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
897 enum mlx5e_traffic_types tt,
900 int mlx5e_open_locked(struct net_device *netdev);
901 int mlx5e_close_locked(struct net_device *netdev);
903 int mlx5e_open_channels(struct mlx5e_priv *priv,
904 struct mlx5e_channels *chs);
905 void mlx5e_close_channels(struct mlx5e_channels *chs);
907 /* Function pointer to be used to modify WH settings while
910 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
911 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
912 struct mlx5e_channels *new_chs,
913 mlx5e_fp_hw_modify hw_modify);
914 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
915 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
917 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
918 u32 *indirection_rqt, int len,
920 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
922 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
924 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
925 struct mlx5e_params *params, u8 rq_type);
928 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
930 u16 pi = *pc & wq->sz_m1;
931 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
932 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
934 memset(cseg, 0, sizeof(*cseg));
936 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
937 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
945 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
946 void __iomem *uar_map,
947 struct mlx5_wqe_ctrl_seg *ctrl)
949 ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
950 /* ensure wqe is visible to device before updating doorbell record */
953 *wq->db = cpu_to_be32(pc);
955 /* ensure doorbell record is visible to device before ringing the
960 mlx5_write64((__be32 *)ctrl, uar_map, NULL);
963 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
965 struct mlx5_core_cq *mcq;
968 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
971 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
973 return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
976 extern const struct ethtool_ops mlx5e_ethtool_ops;
977 #ifdef CONFIG_MLX5_CORE_EN_DCB
978 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
979 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
980 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
983 #ifndef CONFIG_RFS_ACCEL
984 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
989 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
991 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
996 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
1001 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
1002 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
1003 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
1004 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
1005 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1006 u16 rxq_index, u32 flow_id);
1009 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
1010 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
1011 struct mlx5e_tir *tir, u32 *in, int inlen);
1012 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1013 struct mlx5e_tir *tir);
1014 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1015 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1016 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
1018 /* common netdev helpers */
1019 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1021 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv);
1022 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
1024 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
1025 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv);
1026 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
1027 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
1028 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1030 int mlx5e_create_ttc_table(struct mlx5e_priv *priv);
1031 void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv);
1033 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
1034 u32 underlay_qpn, u32 *tisn);
1035 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1037 int mlx5e_create_tises(struct mlx5e_priv *priv);
1038 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
1039 int mlx5e_close(struct net_device *netdev);
1040 int mlx5e_open(struct net_device *netdev);
1041 void mlx5e_update_stats_work(struct work_struct *work);
1042 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
1044 /* ethtool helpers */
1045 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1046 struct ethtool_drvinfo *drvinfo);
1047 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1048 uint32_t stringset, uint8_t *data);
1049 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1050 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1051 struct ethtool_stats *stats, u64 *data);
1052 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1053 struct ethtool_ringparam *param);
1054 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1055 struct ethtool_ringparam *param);
1056 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1057 struct ethtool_channels *ch);
1058 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1059 struct ethtool_channels *ch);
1060 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1061 struct ethtool_coalesce *coal);
1062 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1063 struct ethtool_coalesce *coal);
1064 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1065 struct ethtool_ts_info *info);
1066 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1067 struct ethtool_flash *flash);
1069 /* mlx5e generic netdev management API */
1071 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1073 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1074 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1075 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1076 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1077 struct mlx5e_params *params,
1080 #endif /* __MLX5_EN_H__ */