2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/if_vlan.h>
34 #include <linux/etherdevice.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/qp.h>
37 #include <linux/mlx5/cq.h>
38 #include <linux/mlx5/vport.h>
41 #include "mlx5_core.h"
43 #define MLX5E_MAX_NUM_TC 8
45 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7
46 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
47 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
49 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7
50 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
51 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
53 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (16 * 1024)
54 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
55 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
56 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
57 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
58 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
59 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7
61 #define MLX5E_TX_CQ_POLL_BUDGET 128
62 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
64 static const char vport_strings[][ETH_GSTRING_LEN] = {
65 /* vport statistics */
78 "rx_multicast_packets",
80 "tx_multicast_packets",
82 "rx_broadcast_packets",
84 "tx_broadcast_packets",
101 struct mlx5e_vport_stats {
107 u64 rx_error_packets;
109 u64 tx_error_packets;
111 u64 rx_unicast_packets;
112 u64 rx_unicast_bytes;
113 u64 tx_unicast_packets;
114 u64 tx_unicast_bytes;
115 u64 rx_multicast_packets;
116 u64 rx_multicast_bytes;
117 u64 tx_multicast_packets;
118 u64 tx_multicast_bytes;
119 u64 rx_broadcast_packets;
120 u64 rx_broadcast_bytes;
121 u64 tx_broadcast_packets;
122 u64 tx_broadcast_bytes;
132 u64 tx_queue_stopped;
134 u64 tx_queue_dropped;
137 #define NUM_VPORT_COUNTERS 31
140 static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
148 struct mlx5e_rq_stats {
154 #define NUM_RQ_STATS 5
157 static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
168 struct mlx5e_sq_stats {
172 u64 csum_offload_none;
177 #define NUM_SQ_STATS 8
181 struct mlx5e_vport_stats vport;
184 struct mlx5e_params {
188 u8 default_vlan_prio;
190 u16 rx_cq_moderation_usec;
191 u16 rx_cq_moderation_pkts;
192 u16 tx_cq_moderation_usec;
193 u16 tx_cq_moderation_pkts;
195 u16 rx_hash_log_tbl_sz;
201 MLX5E_RQ_STATE_POST_WQES_ENABLE,
205 MLX5E_CQ_HAS_CQES = 1,
209 /* data path - accessed per cqe */
213 /* data path - accessed per napi poll */
214 struct napi_struct *napi;
215 struct mlx5_core_cq mcq;
216 struct mlx5e_channel *channel;
219 struct mlx5_wq_ctrl wq_ctrl;
220 } ____cacheline_aligned_in_smp;
224 struct mlx5_wq_ll wq;
226 struct sk_buff **skb;
229 struct net_device *netdev;
230 struct mlx5e_rq_stats stats;
237 struct mlx5_wq_ctrl wq_ctrl;
239 struct mlx5e_channel *channel;
240 } ____cacheline_aligned_in_smp;
242 struct mlx5e_tx_skb_cb {
248 #define MLX5E_TX_SKB_CB(__skb) ((struct mlx5e_tx_skb_cb *)__skb->cb)
250 struct mlx5e_sq_dma {
256 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
262 /* dirtied @completion */
267 u16 pc ____cacheline_aligned_in_smp;
270 struct mlx5e_sq_stats stats;
274 /* pointers to per packet info: write@xmit, read@completion */
275 struct sk_buff **skb;
276 struct mlx5e_sq_dma *dma_fifo;
279 struct mlx5_wq_cyc wq;
281 void __iomem *uar_map;
282 struct netdev_queue *txq;
292 struct mlx5_wq_ctrl wq_ctrl;
294 struct mlx5e_channel *channel;
296 } ____cacheline_aligned_in_smp;
298 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
300 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
305 MLX5E_CHANNEL_NAPI_SCHED = 1,
308 struct mlx5e_channel {
311 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
312 struct napi_struct napi;
314 struct net_device *netdev;
318 int tc_to_txq_map[MLX5E_MAX_NUM_TC];
321 struct mlx5e_priv *priv;
326 enum mlx5e_traffic_types {
327 MLX5E_TT_IPV4_TCP = 0,
328 MLX5E_TT_IPV6_TCP = 1,
329 MLX5E_TT_IPV4_UDP = 2,
330 MLX5E_TT_IPV6_UDP = 3,
338 MLX5E_RQT_SPREADING = 0,
339 MLX5E_RQT_DEFAULT_RQ = 1,
343 struct mlx5e_eth_addr_info {
344 u8 addr[ETH_ALEN + 2];
346 u32 ft_ix[MLX5E_NUM_TT]; /* flow table index per traffic type */
349 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
351 struct mlx5e_eth_addr_db {
352 struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
353 struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
354 struct mlx5e_eth_addr_info broadcast;
355 struct mlx5e_eth_addr_info allmulti;
356 struct mlx5e_eth_addr_info promisc;
357 bool broadcast_enabled;
358 bool allmulti_enabled;
359 bool promisc_enabled;
363 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
367 struct mlx5e_vlan_db {
368 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
369 u32 active_vlans_ft_ix[VLAN_N_VID];
370 u32 untagged_rule_ft_ix;
371 u32 any_vlan_rule_ft_ix;
372 bool filter_disabled;
375 struct mlx5e_flow_table {
381 /* priv data path fields - start */
383 int default_vlan_prio;
384 struct mlx5e_sq **txq_to_sq_map;
385 /* priv data path fields - end */
388 struct mutex state_lock; /* Protects Interface state */
389 struct mlx5_uar cq_uar;
392 struct mlx5_core_mr mr;
394 struct mlx5e_channel **channel;
395 u32 tisn[MLX5E_MAX_NUM_TC];
397 u32 tirn[MLX5E_NUM_TT];
399 struct mlx5e_flow_table ft;
400 struct mlx5e_eth_addr_db eth_addr;
401 struct mlx5e_vlan_db vlan;
403 struct mlx5e_params params;
404 spinlock_t async_events_spinlock; /* sync hw events */
405 struct work_struct update_carrier_work;
406 struct work_struct set_rx_mode_work;
407 struct delayed_work update_stats_work;
409 struct mlx5_core_dev *mdev;
410 struct net_device *netdev;
411 struct mlx5e_stats stats;
414 #define MLX5E_NET_IP_ALIGN 2
416 struct mlx5e_tx_wqe {
417 struct mlx5_wqe_ctrl_seg ctrl;
418 struct mlx5_wqe_eth_seg eth;
421 struct mlx5e_rx_wqe {
422 struct mlx5_wqe_srq_next_seg next;
423 struct mlx5_wqe_data_seg data;
426 enum mlx5e_link_mode {
427 MLX5E_1000BASE_CX_SGMII = 0,
428 MLX5E_1000BASE_KX = 1,
429 MLX5E_10GBASE_CX4 = 2,
430 MLX5E_10GBASE_KX4 = 3,
431 MLX5E_10GBASE_KR = 4,
432 MLX5E_20GBASE_KR2 = 5,
433 MLX5E_40GBASE_CR4 = 6,
434 MLX5E_40GBASE_KR4 = 7,
435 MLX5E_56GBASE_R4 = 8,
436 MLX5E_10GBASE_CR = 12,
437 MLX5E_10GBASE_SR = 13,
438 MLX5E_10GBASE_ER = 14,
439 MLX5E_40GBASE_SR4 = 15,
440 MLX5E_40GBASE_LR4 = 16,
441 MLX5E_100GBASE_CR4 = 20,
442 MLX5E_100GBASE_SR4 = 21,
443 MLX5E_100GBASE_KR4 = 22,
444 MLX5E_100GBASE_LR4 = 23,
445 MLX5E_100BASE_TX = 24,
446 MLX5E_100BASE_T = 25,
447 MLX5E_10GBASE_T = 26,
448 MLX5E_25GBASE_CR = 27,
449 MLX5E_25GBASE_KR = 28,
450 MLX5E_25GBASE_SR = 29,
451 MLX5E_50GBASE_CR2 = 30,
452 MLX5E_50GBASE_KR2 = 31,
453 MLX5E_LINK_MODES_NUMBER,
456 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
458 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
459 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
460 void *accel_priv, select_queue_fallback_t fallback);
461 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
463 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
464 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
465 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
466 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq);
467 bool mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
468 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
469 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
471 void mlx5e_update_stats(struct mlx5e_priv *priv);
473 int mlx5e_open_flow_table(struct mlx5e_priv *priv);
474 void mlx5e_close_flow_table(struct mlx5e_priv *priv);
475 void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
476 void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv);
477 void mlx5e_set_rx_mode_work(struct work_struct *work);
479 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
481 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
483 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
484 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
485 int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv);
486 void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv);
488 int mlx5e_open_locked(struct net_device *netdev);
489 int mlx5e_close_locked(struct net_device *netdev);
490 int mlx5e_update_priv_params(struct mlx5e_priv *priv,
491 struct mlx5e_params *new_params);
493 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
494 struct mlx5e_tx_wqe *wqe)
496 /* ensure wqe is visible to device before updating doorbell record */
499 *sq->wq.db = cpu_to_be32(sq->pc);
501 /* ensure doorbell record is visible to device before ringing the
506 mlx5_write64((__be32 *)&wqe->ctrl,
507 sq->uar_map + MLX5_BF_OFFSET + sq->bf_offset,
510 sq->bf_offset ^= sq->bf_buf_size;
513 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
515 struct mlx5_core_cq *mcq;
518 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
521 extern const struct ethtool_ops mlx5e_ethtool_ops;