2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/if_vlan.h>
34 #include <linux/etherdevice.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/qp.h>
37 #include <linux/mlx5/cq.h>
38 #include <linux/mlx5/vport.h>
41 #include "mlx5_core.h"
43 #define MLX5E_MAX_NUM_TC 8
45 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
46 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
47 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
49 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
50 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
51 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
53 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
54 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
55 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
56 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
57 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
58 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
60 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
61 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
62 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
63 #define MLX5E_TX_CQ_POLL_BUDGET 128
64 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
65 #define MLX5E_SQ_BF_BUDGET 16
67 static const char vport_strings[][ETH_GSTRING_LEN] = {
68 /* vport statistics */
81 "rx_multicast_packets",
83 "tx_multicast_packets",
85 "rx_broadcast_packets",
87 "tx_broadcast_packets",
105 struct mlx5e_vport_stats {
111 u64 rx_error_packets;
113 u64 tx_error_packets;
115 u64 rx_unicast_packets;
116 u64 rx_unicast_bytes;
117 u64 tx_unicast_packets;
118 u64 tx_unicast_bytes;
119 u64 rx_multicast_packets;
120 u64 rx_multicast_bytes;
121 u64 tx_multicast_packets;
122 u64 tx_multicast_bytes;
123 u64 rx_broadcast_packets;
124 u64 rx_broadcast_bytes;
125 u64 tx_broadcast_packets;
126 u64 tx_broadcast_bytes;
137 u64 tx_queue_stopped;
139 u64 tx_queue_dropped;
142 #define NUM_VPORT_COUNTERS 32
145 static const char pport_strings[][ETH_GSTRING_LEN] = {
146 /* IEEE802.3 counters */
157 "in_range_len_errors",
167 /* RFC2863 counters */
179 "out_multicast_pkts",
180 "out_broadcast_pkts",
182 /* RFC2819 counters */
203 "p8192to10239octets",
206 #define NUM_IEEE_802_3_COUNTERS 19
207 #define NUM_RFC_2863_COUNTERS 13
208 #define NUM_RFC_2819_COUNTERS 21
209 #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \
210 NUM_RFC_2863_COUNTERS + \
211 NUM_RFC_2819_COUNTERS)
213 struct mlx5e_pport_stats {
214 __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS];
215 __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS];
216 __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS];
219 static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
228 struct mlx5e_rq_stats {
235 #define NUM_RQ_STATS 6
238 static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
249 struct mlx5e_sq_stats {
253 u64 csum_offload_none;
258 #define NUM_SQ_STATS 8
262 struct mlx5e_vport_stats vport;
263 struct mlx5e_pport_stats pport;
266 struct mlx5e_params {
270 u8 default_vlan_prio;
272 u16 rx_cq_moderation_usec;
273 u16 rx_cq_moderation_pkts;
274 u16 tx_cq_moderation_usec;
275 u16 tx_cq_moderation_pkts;
281 u8 toeplitz_hash_key[40];
282 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
286 MLX5E_RQ_STATE_POST_WQES_ENABLE,
290 MLX5E_CQ_HAS_CQES = 1,
294 /* data path - accessed per cqe */
298 /* data path - accessed per napi poll */
299 struct napi_struct *napi;
300 struct mlx5_core_cq mcq;
301 struct mlx5e_channel *channel;
302 struct mlx5e_priv *priv;
305 struct mlx5_wq_ctrl wq_ctrl;
306 } ____cacheline_aligned_in_smp;
310 struct mlx5_wq_ll wq;
312 struct sk_buff **skb;
315 struct net_device *netdev;
316 struct mlx5e_rq_stats stats;
323 struct mlx5_wq_ctrl wq_ctrl;
325 struct mlx5e_channel *channel;
326 struct mlx5e_priv *priv;
327 } ____cacheline_aligned_in_smp;
329 struct mlx5e_tx_skb_cb {
335 #define MLX5E_TX_SKB_CB(__skb) ((struct mlx5e_tx_skb_cb *)__skb->cb)
337 struct mlx5e_sq_dma {
343 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
349 /* dirtied @completion */
354 u16 pc ____cacheline_aligned_in_smp;
359 struct mlx5e_sq_stats stats;
363 /* pointers to per packet info: write@xmit, read@completion */
364 struct sk_buff **skb;
365 struct mlx5e_sq_dma *dma_fifo;
368 struct mlx5_wq_cyc wq;
370 void __iomem *uar_map;
371 void __iomem *uar_bf_map;
372 struct netdev_queue *txq;
382 struct mlx5_wq_ctrl wq_ctrl;
384 struct mlx5e_channel *channel;
386 } ____cacheline_aligned_in_smp;
388 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
390 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
395 MLX5E_CHANNEL_NAPI_SCHED = 1,
398 struct mlx5e_channel {
401 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
402 struct napi_struct napi;
404 struct net_device *netdev;
410 struct mlx5e_priv *priv;
415 enum mlx5e_traffic_types {
420 MLX5E_TT_IPV4_IPSEC_AH,
421 MLX5E_TT_IPV6_IPSEC_AH,
422 MLX5E_TT_IPV4_IPSEC_ESP,
423 MLX5E_TT_IPV6_IPSEC_ESP,
431 MLX5E_INDIRECTION_RQT,
436 struct mlx5e_eth_addr_info {
437 u8 addr[ETH_ALEN + 2];
439 u32 ft_ix[MLX5E_NUM_TT]; /* flow table index per traffic type */
442 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
444 struct mlx5e_eth_addr_db {
445 struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
446 struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
447 struct mlx5e_eth_addr_info broadcast;
448 struct mlx5e_eth_addr_info allmulti;
449 struct mlx5e_eth_addr_info promisc;
450 bool broadcast_enabled;
451 bool allmulti_enabled;
452 bool promisc_enabled;
456 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
458 MLX5E_STATE_DESTROYING,
461 struct mlx5e_vlan_db {
462 u32 active_vlans_ft_ix[VLAN_N_VID];
463 u32 untagged_rule_ft_ix;
464 u32 any_vlan_rule_ft_ix;
465 bool filter_disabled;
468 struct mlx5e_flow_table {
474 /* priv data path fields - start */
475 int default_vlan_prio;
476 struct mlx5e_sq **txq_to_sq_map;
477 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
478 /* priv data path fields - end */
481 struct mutex state_lock; /* Protects Interface state */
482 struct mlx5_uar cq_uar;
485 struct mlx5_core_mr mr;
486 struct mlx5e_rq drop_rq;
488 struct mlx5e_channel **channel;
489 u32 tisn[MLX5E_MAX_NUM_TC];
490 u32 rqtn[MLX5E_NUM_RQT];
491 u32 tirn[MLX5E_NUM_TT];
493 struct mlx5e_flow_table ft;
494 struct mlx5e_eth_addr_db eth_addr;
495 struct mlx5e_vlan_db vlan;
497 struct mlx5e_params params;
498 spinlock_t async_events_spinlock; /* sync hw events */
499 struct work_struct update_carrier_work;
500 struct work_struct set_rx_mode_work;
501 struct delayed_work update_stats_work;
503 struct mlx5_core_dev *mdev;
504 struct net_device *netdev;
505 struct mlx5e_stats stats;
508 #define MLX5E_NET_IP_ALIGN 2
510 struct mlx5e_tx_wqe {
511 struct mlx5_wqe_ctrl_seg ctrl;
512 struct mlx5_wqe_eth_seg eth;
515 struct mlx5e_rx_wqe {
516 struct mlx5_wqe_srq_next_seg next;
517 struct mlx5_wqe_data_seg data;
520 enum mlx5e_link_mode {
521 MLX5E_1000BASE_CX_SGMII = 0,
522 MLX5E_1000BASE_KX = 1,
523 MLX5E_10GBASE_CX4 = 2,
524 MLX5E_10GBASE_KX4 = 3,
525 MLX5E_10GBASE_KR = 4,
526 MLX5E_20GBASE_KR2 = 5,
527 MLX5E_40GBASE_CR4 = 6,
528 MLX5E_40GBASE_KR4 = 7,
529 MLX5E_56GBASE_R4 = 8,
530 MLX5E_10GBASE_CR = 12,
531 MLX5E_10GBASE_SR = 13,
532 MLX5E_10GBASE_ER = 14,
533 MLX5E_40GBASE_SR4 = 15,
534 MLX5E_40GBASE_LR4 = 16,
535 MLX5E_100GBASE_CR4 = 20,
536 MLX5E_100GBASE_SR4 = 21,
537 MLX5E_100GBASE_KR4 = 22,
538 MLX5E_100GBASE_LR4 = 23,
539 MLX5E_100BASE_TX = 24,
540 MLX5E_100BASE_T = 25,
541 MLX5E_10GBASE_T = 26,
542 MLX5E_25GBASE_CR = 27,
543 MLX5E_25GBASE_KR = 28,
544 MLX5E_25GBASE_SR = 29,
545 MLX5E_50GBASE_CR2 = 30,
546 MLX5E_50GBASE_KR2 = 31,
547 MLX5E_LINK_MODES_NUMBER,
550 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
552 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
553 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
554 void *accel_priv, select_queue_fallback_t fallback);
555 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
557 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
558 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
559 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
560 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq);
561 bool mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
562 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
563 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
565 void mlx5e_update_stats(struct mlx5e_priv *priv);
567 int mlx5e_create_flow_tables(struct mlx5e_priv *priv);
568 void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv);
569 void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
570 void mlx5e_set_rx_mode_work(struct work_struct *work);
572 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
574 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
576 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
577 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
579 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix);
581 int mlx5e_open_locked(struct net_device *netdev);
582 int mlx5e_close_locked(struct net_device *netdev);
584 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
585 struct mlx5e_tx_wqe *wqe, int bf_sz)
587 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
589 /* ensure wqe is visible to device before updating doorbell record */
592 *sq->wq.db = cpu_to_be32(sq->pc);
594 /* ensure doorbell record is visible to device before ringing the
600 __iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz);
602 /* flush the write-combining mapped buffer */
606 mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL);
609 sq->bf_offset ^= sq->bf_buf_size;
612 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
614 struct mlx5_core_cq *mcq;
617 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
620 extern const struct ethtool_ops mlx5e_ethtool_ops;
621 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);